Display device and method of manufacturing the same

Abstract

The display device includes: a substrate layer including a display area and a non-display area; and a plurality of pixels arranged in the display area, each having a plurality of sub-pixels. According to one embodiment of the present disclosure, each sub-pixel may include: a display element layer including a pixel circuit unit, an emission area for emitting light, and a non-emission area arranged around the emission area. The display element layer may include: a partition wall arranged in the emission area of ​​each sub-pixel; a dam arranged in the non-emission area of ​​each sub-pixel and located on the same surface as the partition wall; a first electrode and a second electrode arranged on the partition wall and spaced apart from each other; and at least one light-emitting element arranged between the first electrode and the second electrode in the emission area of ​​each sub-pixel and emitting light.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a display device, and more particularly, to a display device including an ultra-small light emitting element and a method of manufacturing the display device. Background Art

[0002] A light emitting diode can have relatively satisfactory durability even under severe environmental conditions and has excellent performance in terms of life span and brightness. Recently, research on a technology for applying such a light emitting diode to various display devices has become significantly more active.

[0003] As part of such research, technology is being developed to manufacture a light-emitting diode having an ultra-small size corresponding to a micrometer or nanometer level using an inorganic crystal structure (for example, a structure obtained by growing a nitride-based semiconductor).

[0004] The light emitting diode can be manufactured in a sufficiently small size to form a pixel of a display device, etc. The light emitting diode can be grown individually and independently on a substrate, and the grown light emitting diode can be separated from the substrate and used to manufacture a display panel. In the case where the light emitting diode is used as a light source of a display panel, a plurality of light emitting diodes can be arranged in each pixel of the display panel. Here, if a plurality of light emitting diodes are arranged in close contact with each other, an undesirable short circuit may be caused between adjacent light emitting diodes, thereby damaging the light emitting diodes. As a result, defects of the light emitting diodes may occur. Summary of the invention

[0005] Technical issues

[0006] Various embodiments of the present disclosure are directed to a display device formed through a simple manufacturing process using a reduced number of masks and a method of manufacturing the display device.

[0007] Technical Solution

[0008] A display device according to an embodiment of the present disclosure may include: a substrate layer including a display area and a non-display area; and a plurality of pixels arranged in the display area, and each of the plurality of pixels includes a plurality of sub-pixels. Each of the plurality of sub-pixels may include a pixel circuit layer and a display element layer, and the display element layer includes an emission area that emits light and a non-emission area arranged around the periphery of the emission area. The display element layer may include: a partition wall arranged in the emission area of ​​each sub-pixel; a dam arranged in the non-emission area of ​​each sub-pixel, the dam and the partition wall being arranged on the same surface; a first electrode and a second electrode arranged on the partition wall and spaced apart from each other; and at least one light-emitting element emitting light, the light-emitting element being between the first electrode and the second electrode in the emission area of ​​each sub-pixel.

[0009] In an embodiment of the present disclosure, the partition wall and the bank may include the same material and may be integral with each other.

[0010] In an embodiment of the present disclosure, the light emitting element includes a first end and a second end opposite to the first end. The display element layer may further include: a first contact electrode electrically connecting the first electrode to one of the first end and the second end of the light emitting element; and a second contact electrode electrically connecting the second electrode to the other end of the opposite end of the first end or the second end of the light emitting element.

[0011] In an embodiment of the present disclosure, the display element layer may further include: a first insulating layer disposed between the light emitting element and the pixel circuit layer; and a second insulating layer disposed on a portion of an upper surface of the light emitting element.

[0012] In an embodiment of the present disclosure, the first contact electrode and the second contact electrode may be disposed on the same layer, and be spaced apart from and electrically insulated from each other on the second insulating layer.

[0013] In an embodiment of the present disclosure, the pixel circuit layer may include: at least one transistor disposed on the base layer; and a passivation layer disposed on the transistor.

[0014] In an embodiment of the present disclosure, the passivation layer may be on the same surface as the partition wall and the bank.

[0015] In an embodiment of the present disclosure, the passivation layer may be integral with the partition wall and the bank, and may include the same material as that of the partition wall and the bank.

[0016] In an embodiment of the present disclosure, the display device may further include: a conductive pattern disposed between the base layer and the transistor.

[0017] In an embodiment of the present disclosure, the conductive pattern may include a light shielding pattern that blocks light from entering the rear surface of the base layer.

[0018] In an embodiment of the present disclosure, the display device may further include: a color conversion layer disposed on the display element layer, the color conversion layer including color conversion particles for converting light into light having a set color; and a substrate disposed on the color conversion layer.

[0019] In an embodiment of the present disclosure, the display device may further include: a substrate disposed on the display element layer; and an intermediate layer disposed between the display element layer and the substrate.

[0020] In an embodiment of the present disclosure, the intermediate layer may include: an adhesive material for bonding the display element layer to the substrate.

[0021] In an embodiment of the present disclosure, the first electrode and the second electrode may be electrically separated from each other, and one of the first electrode and the second electrode may surround the remaining one of the first electrode and the second electrode.

[0022] In the embodiments of the present disclosure, the light emitting element may include: an ultra-small light emitting diode in the shape of a cylinder or a polygonal prism, and the ultra-small light emitting diode is in the size of a micrometer or a nanometer.

[0023] According to an embodiment of the present disclosure, a method for manufacturing a display device may include: providing a base layer on which a pixel circuit layer of a plurality of sub-pixels is formed, each of the plurality of sub-pixels including an emission region and a non-emission region; and forming a display element layer on the pixel circuit layer that emits light from the emission region of each of the plurality of sub-pixels. Forming the display element layer may include: forming a partition wall in the emission region of each of the plurality of sub-pixels, and at the same time, forming a dam in the non-emission region of each sub-pixel; forming a first electrode and a second electrode spaced apart from each other on the partition wall; forming a first insulating layer that exposes a portion of the upper surface of each electrode corresponding to the first electrode and the second electrode; aligning a plurality of light-emitting elements between the first electrode and the second electrode by applying corresponding alignment voltages to the first electrode and the second electrode, respectively; forming a second insulating layer on the plurality of light-emitting elements that exposes the opposite ends of each of the plurality of light-emitting elements; and forming a first contact electrode and a second contact electrode on the second insulating layer.

[0024] In an embodiment of the present disclosure, the first contact electrode and the second contact electrode may be disposed on the same layer, spaced apart from each other and electrically insulated from each other on the second insulating layer.

[0025] In an embodiment of the present disclosure, forming a pixel circuit layer may include: forming at least one transistor on the base layer; and forming a passivation layer on the transistor. The passivation layer may be integral with the partition wall and the bank, and the passivation layer, the partition wall and the bank include the same material.

[0026] In an embodiment of the present disclosure, the first electrode and the second electrode may be electrically separated from each other, and one of the first electrode and the second electrode may surround the remaining one of the first electrode and the second electrode.

[0027] Beneficial Effects

[0028] Various embodiments of the present disclosure may provide a display device formed through a relatively simple manufacturing process using a reduced number of masks and a method of manufacturing the display device.

[0029] The effects of the present disclosure are not limited to the foregoing, and other various effects are expected here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1a and Figure 1b is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure.

[0031] Figure 2 The display device according to the embodiment of the present disclosure is shown, specifically, the display device using Figure 1a Schematic plan view of a display device in which the light-emitting element shown is used as a light source.

[0032] Figures 3a to 3d is a diagram showing various embodiments Figure 2 A circuit diagram of an example of a unit light emitting area of ​​a display device.

[0033] Figure 4 It is schematically shown that the Figure 2 1 is a plan view of first to third sub-pixels in one of the pixels shown in FIG.

[0034] Figure 5 It is along Figure 4 A cross-sectional view taken along line II'.

[0035] Figure 6 It is shown Figure 4 Schematic plan view of another embodiment of a first sub-pixel in a pixel.

[0036] Figure 7 It is shown Figure 4 Schematic plan view of another embodiment of a first sub-pixel in a pixel.

[0037] Figure 8a to Figure 8h The manufacturing sequence is shown in Figure 5 A cross-sectional view of a method of displaying a device.

[0038] Fig. 9 A display device according to an embodiment of the present disclosure is shown, and a color conversion layer is combined with Figure 5 A schematic cross-sectional view of the structure of a display device.

[0039] Fig.10 The display device according to the embodiment of the present disclosure is schematically shown. Figure 4 The cross-sectional view corresponding to the line II'.

[0040] Figures 11a to 11g The manufacturing sequence is shown in Fig.10 A cross-sectional view of a method of displaying a device.

[0041] Fig.12 A display device according to an embodiment of the present disclosure is shown, and a substrate is bonded to Fig.10A schematic cross-sectional view of the structure of a display device. DETAILED DESCRIPTION

[0042] Since the present disclosure allows various changes and many embodiments, specific embodiments will be shown in the drawings and will be described in detail in the written description. However, this is not intended to limit the present disclosure to the specific manner of practice, and it will be understood that all changes, equivalents and substitutes that do not depart from the spirit and technical scope of the present disclosure are included in the present disclosure.

[0043] Throughout the disclosure, the same reference numerals always indicate the same parts (components) in the various figures and embodiments of the present disclosure. For clear illustration, the size of the elements in the drawings may be exaggerated. It will be understood that, although the terms "first", "second", etc. may be used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element. In the present disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0044] It will also be understood that when the terms "comprise", "include", "have", etc. are used in this specification, it indicates the presence of the stated features, integers, steps, operations, elements, components and / or combinations thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof. In addition, when a first component such as a layer, film, region or plate is disposed on a second component, the first component may not only be directly on the second component, but a third component may be placed between them. In addition, when it is stated that a first component such as a layer, film, region or plate is formed on a second component, the surface of the second component on which the first component is formed is not limited to the upper surface of the second component, but may include other surfaces of the second component such as a side surface or a lower surface. Similarly, when a first component such as a layer, film, region or plate is below a second component, the first component may not only be directly below the second component, but a third component may be placed between them.

[0045] The embodiments and required details of the present disclosure are described with reference to the accompanying drawings to describe the present disclosure in detail so that a person skilled in the art with ordinary knowledge in the technical field to which the present disclosure belongs can easily practice the present disclosure. In addition, as long as a certain component is not specifically mentioned as one or single in a sentence, the component can be multiple.

[0046] Figure 1a and Figure 1b 2 is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure. Figure 1a and Figure 1b A cylindrical light emitting element is shown, but the present disclosure is not limited thereto.

[0047] Reference Figure 1a and Figure 1b , the light emitting element LD according to an embodiment of the present disclosure may include a first semiconductor layer (or a first conductive semiconductor layer) 11, a second semiconductor layer (or a second conductive semiconductor layer) 13, and an active layer 12 disposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. For example, the light emitting element LD may be implemented as a stacked body formed by sequentially stacking the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13.

[0048] In an embodiment of the present disclosure, the light emitting element LD may be formed in a rod-like shape extending in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end and a second end in the extending direction. One of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on the first end, and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on the second end.

[0049] Although the light emitting element LD may be provided in the form of a cylinder, the present disclosure is not limited thereto. The light emitting element LD may include a rod-like shape or a strip-like shape extending in the longitudinal direction (i.e., to have an aspect ratio greater than 1). For example, the length L of the light emitting element LD in the longitudinal direction may be greater than its diameter. The light emitting element LD may include a light emitting diode manufactured in an ultra-small size having a diameter and / or length corresponding to, for example, a micrometer-scale size or a nanometer-scale size.

[0050] However, the size of the light emitting element LD is not limited thereto, and the size of the light emitting element LD may be changed to meet requirements of a lighting device or a self-emitting display device to which the light emitting element LD is applied.

[0051] The first conductive semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include a semiconductor layer including any one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a first conductive dopant such as Si, Ge, or Sn. The material forming the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of various other materials.

[0052] The active layer 12 may be formed on the first conductive semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. In an embodiment of the present disclosure, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In addition, the active layer 12 may be formed of a material such as AlGaN or AlInGaN.

[0053] If an electric field having a predetermined voltage or more is applied to opposite ends of the light emitting element LD, the light emitting element LD emits light by bonding of electron-hole pairs in the active layer 12 .

[0054] The second conductive semiconductor layer 13 may be disposed on the active layer 12, and may include a semiconductor layer of a type different from that of the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include a semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductive dopant such as Mg. The material forming the second conductive semiconductor layer 13 is not limited thereto, and the second conductive semiconductor layer 13 may be formed of various other materials.

[0055] In the embodiments of the present disclosure, Figure 1a As shown in FIG. 1 , the light emitting element LD may include, in addition to the first conductive semiconductor layer 11, the active layer 12 and the second conductive semiconductor layer 13, an electrode layer 15 disposed on the second conductive semiconductor layer 13. Figure 1b As shown in , the light emitting element LD may further include another electrode layer 16 disposed on one end of the first conductive semiconductor layer 11 in addition to the electrode layer 15 .

[0056] Although each of the electrode layers 15 and 16 may be formed by an ohmic contact electrode, the present disclosure is not limited thereto. In addition, each of the electrode layers 15 and 16 may include a metal or a metal oxide. For example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni) and oxides or alloys thereof, and ITO may be used alone or in combination with one another. However, the present disclosure is not limited thereto.

[0057] The materials included in the respective electrode layers 15 and 16 may be the same as or different from each other. The electrode layers 15 and 16 may be substantially transparent or translucent. Therefore, light generated from the light emitting element LD may pass through the electrode layers 15 and 16 and then be emitted to the outside of the light emitting element LD.

[0058] In the embodiment of the present disclosure, the light emitting element LD may further include an insulating film 14. However, in some embodiments of the present disclosure, the insulating film 14 may be omitted or provided to cover only some of the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13.

[0059] like Figure 1a As shown in , the insulating film 14 may be provided on a portion of the light emitting element LD except for one of the opposite ends of the light emitting element LD. In this case, the insulating film 14 may expose only one electrode layer 15 provided on one end of the second conductive semiconductor layer 13 of the light emitting element LD, and surround the entire side surface of the component except the electrode layer 15. Here, the insulating film 14 may allow at least the opposite end of the light emitting element LD to be exposed to the outside. For example, the insulating film 14 may allow not only the electrode layer 15 provided on one end of the second conductive semiconductor layer 13 to be exposed to the outside, but also one end of the first conductive semiconductor layer 11 to be exposed to the outside.

[0060] In an embodiment, Figure 1b As shown in FIG. 1 , in the case where the electrode layers 15 and 16 are provided on respective opposite ends of the light emitting element LD, the insulating film 14 may allow at least a portion of each of the electrode layers 15 and 16 to be exposed to the outside. Alternatively, in an embodiment, the insulating film 14 may not be provided.

[0061] In an embodiment of the present disclosure, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include a material selected from SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 At least one insulating material in the group consisting of, but not limited to this. In other words, various materials with insulating properties can be used.

[0062] If the insulating film 14 is provided on the light emitting element LD, the active layer 12 can be prevented from being short-circuited with the first electrode and / or the second electrode not shown. Due to the insulating film 14, the occurrence of defects on the surface of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. In the case where a plurality of light emitting elements LD are provided in close contact with each other, the insulating film 14 can prevent an undesirable short circuit from occurring between the light emitting elements LD.

[0063] The light emitting element LD may be used as a light source for various display devices. The light emitting element LD may be manufactured through a surface treatment process.

[0064] Figure 2 The display device according to the embodiment of the present disclosure is shown, specifically, the display device using Figure 1a Schematic plan view of a display device in which the light-emitting element shown is used as a light source.

[0065] For illustration purposes, Figure 2 Focusing on the display area in which an image is displayed, the structure of the display device is schematically shown. In some embodiments, although not shown, at least one driving circuit (eg, a scan driver and a data driver) and / or a plurality of lines may be further provided in the display device.

[0066] Reference Figure 1a and Figure 2 According to an embodiment of the present disclosure, a display device may include a base layer BSL, pixels PXL disposed on the base layer BSL and each including at least one light emitting element LD, a driver (not shown) disposed on the base layer BSL and configured to drive the pixels PXL, and a line component (not shown) disposed to connect the pixels PXL to the driver.

[0067] The display device may be classified into a passive matrix display device and an active matrix display device according to a driving method. For example, in the case where the display device according to the embodiment is implemented as an active matrix display device, each of the pixels PXL may include a driving transistor configured to control the amount of current to be supplied to the light emitting element LD and a switching transistor configured to transmit a data signal to the driving transistor.

[0068] Recently, considering resolution, contrast and operating speed, an active matrix display device capable of selectively turning on each pixel PXL has become mainstream. However, the present disclosure is not limited thereto. For example, a passive matrix display device in which the pixels PXL can be turned on in groups may also employ components (e.g., a first electrode and a second electrode) for driving the light emitting element LD.

[0069] The base layer BSL may include a display area DA and a non-display area NDA.

[0070] In an embodiment, the display area DA may be disposed in the central portion of the display device, and the non-display area NDA may be disposed in the peripheral portion of the display device in such a manner as to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed.

[0071] The display area DA may be an area in which pixels PXL for displaying an image are disposed. The non-display area NDA may be an area in which a driver for driving the pixels PXL and some of the line units for coupling the pixels PXL to the driver are disposed.

[0072] The display area DA may have various shapes. For example, the display area DA may be provided in various forms such as a closed polygon including sides formed by straight lines, a circle or an ellipse including sides formed by curved lines, and a semicircle or a semiellipse including sides formed by straight lines and curved lines.

[0073] The non-display area NDA may be disposed on at least one side of the display area DA. In an embodiment of the present disclosure, the non-display area NDA may surround the display area DA.

[0074] The base layer BSL may be a rigid substrate or a flexible substrate, and its material or properties are not particularly limited. For example, the base layer BSL may be a rigid substrate made of glass or reinforced glass, or a flexible substrate formed of a thin film made of plastic or metal. In addition, the base layer BSL may be a transparent substrate, but is not limited thereto. For example, the base layer BSL may be a translucent substrate, an opaque substrate, or a reflective substrate.

[0075] The pixels PXL may be disposed in the display area DA on the base layer BSL. Each of the pixels PXL refers to a minimum unit for displaying an image, and a plurality of pixels may be provided.

[0076] Each of the pixels PXL may include a light emitting element LD configured to be driven in response to a corresponding scan signal and a corresponding data signal. The light emitting element LD may have a small size corresponding to a nanometer level or a micrometer level and be connected in parallel with a light emitting element disposed adjacent thereto. The light emitting element LD may form a light source of the corresponding pixel PXL.

[0077] In addition, each of the pixels PXL may include a plurality of sub-pixels. For example, each pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. In an embodiment, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may emit light of different colors. For example, the first sub-pixel SP1 may be a red sub-pixel for emitting red light, the second sub-pixel SP2 may be a green sub-pixel for emitting green light, and the third sub-pixel SP3 may be a blue sub-pixel for emitting blue light. However, there is no specific limitation on the color, type, and / or number of sub-pixels forming each pixel PXL. For example, the color of light emitted from each sub-pixel may be changed in various ways. Although in Figure 2 2 shows an embodiment in which the pixels PXL are arranged in a stripe shape in the display area DA, but the present disclosure is not limited thereto. For example, the display area DA may have various well-known pixel arrangement shapes.

[0078] The driver may provide a signal to each pixel PXL through the line assembly, thereby controlling the operation of the pixel PXL. Figure 2In the figure, the wire components are omitted for the purpose of convenience of illustration.

[0079] The driver may include a scan driver configured to provide a scan signal to the pixel PXL through a scan line, an emission driver configured to provide an emission control signal to the pixel PXL through an emission control line, a data driver configured to provide a data signal to the pixel PXL through a data line, and a timing controller. The timing controller may control the scan driver, the emission driver, and the data driver.

[0080] Figures 3a to 3d is a diagram showing various embodiments Figure 2 A circuit diagram of an example of a unit light emitting area of ​​a display device.

[0081] Reference Figures 3a to 3d , each of the first to third sub-pixels may be constructed by an active pixel. However, the type, structure and / or driving method of each of the first to third sub-pixels are not specifically limited. For example, each of the first to third sub-pixels may be constructed by a pixel of a passive display device or an active display device that may have various known structures.

[0082] In addition, refer to Figures 3a to 3d , the first to third sub-pixels may have substantially the same structure or similar structures. Hereinafter, for the purpose of convenience, as a representative example, the first sub-pixel among the first to third sub-pixels will be described.

[0083] Reference Figure 1a , Figure 2 and Figure 3a , the first subpixel SP1 may include an emission circuit (or emission region) EMC configured to generate light having brightness corresponding to a data signal and a pixel driving circuit 144 configured to drive the emission circuit EMC.

[0084] In an embodiment, the emission circuit EMC may include a plurality of light emitting elements LD connected in parallel to each other between a first driving power supply VDD and a second driving power supply (or referred to as a second driving power) VSS. The first driving power supply VDD and the second driving power supply VSS may have different potentials. For example, the first driving power supply VDD may be set to a high potential power supply, and the second driving power supply VSS may be set to a low potential power supply. Here, during the emission period of the first sub-pixel SP1, the potential difference between the first driving power supply VDD and the second driving power supply VSS may be set to a threshold voltage of the light emitting element LD or greater. The first electrode (e.g., anode electrode) of each of the light emitting elements LD may be electrically connected to the first driving power supply VDD via the pixel driving circuit 144. The second electrode (e.g., cathode electrode) of each of the light emitting elements LD may be electrically connected to the second driving power supply VSS.

[0085] Each of the light emitting elements LD may emit light with brightness corresponding to a driving current controlled by the pixel driving circuit 144 .

[0086] Although Figures 3a to 3d An embodiment in which the light emitting elements LD are connected in parallel to each other in the same direction (e.g., forward direction) between the first driving power supply VDD and the second driving power supply VSS is shown, but the present disclosure is not limited thereto. For example, in an embodiment, some of the light emitting elements LD may be connected to each other in the forward direction between the first driving power supply VDD and the second driving power supply VSS, while other light emitting elements LD may be connected to each other in the reverse direction. One of the first driving power supply VDD and the second driving power supply VSS may be supplied in the form of an AC voltage. In this case, the light emitting element LD connected in the forward direction and the light emitting element LD connected in the reverse direction may emit light alternately. As another embodiment, in an embodiment, the first sub-pixel SP1 may include only a single light emitting element LD.

[0087] In an embodiment of the present disclosure, the pixel driving circuit 144 may include a first transistor T1, a second transistor T2 and a storage capacitor Cst. The structure of the pixel driving circuit 144 is not limited to Figure 3a The structure of the embodiment shown in FIG.

[0088] The first electrode of the first transistor (switching transistor) T1 is electrically connected to the data line Dj, and the second electrode of the first transistor T1 is electrically connected to the first node N1. Here, the first electrode and the second electrode of the first transistor T1 can be different electrodes. For example, if the first electrode is a source electrode, the second electrode is a drain electrode. The gate electrode of the first transistor T1 is connected to the scan line Si.

[0089] When a scan signal having a voltage (e.g., a low level voltage) capable of turning on the first transistor T1 is supplied from the scan line Si, the first transistor T1 is turned on to electrically connect the data line Dj to the first node N1. Here, a data signal of a corresponding frame is supplied to the data line Dj, whereby the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 is charged into the storage capacitor Cst.

[0090] A first electrode of the second transistor (driving transistor) T2 is electrically connected to the first driving power supply VDD, and a second electrode of the second transistor T2 is electrically connected to a first electrode of each of the light emitting elements LD. A gate electrode of the second transistor T2 is electrically connected to the first node N1. In this way, the second transistor T2 can control the amount of driving current to be supplied to the light emitting element LD in response to the voltage of the first node N1.

[0091] One electrode of the storage capacitor Cst is electrically connected to the first driving power source VDD, and the other electrode thereof is electrically connected to the first node N1. The storage capacitor Cst charges a voltage corresponding to the data signal supplied to the first node N1, and maintains the charged voltage until a data signal of a subsequent frame is supplied.

[0092] For illustration purposes, Figure 3a A pixel driving circuit 144 having a relatively simple structure is shown, which includes a first transistor T1 configured to transmit a data signal to a first subpixel SP1, a storage capacitor Cst configured to store the data signal, and a second transistor T2 configured to supply a driving current corresponding to the data signal to the light emitting element LD.

[0093] However, the present disclosure is not limited thereto, and the structure of the pixel driving circuit 144 may be changed in various ways. For example, the pixel driving circuit 144 may further include at least one transistor element such as a transistor element configured to compensate for the threshold voltage of the second transistor T2, a transistor element configured to initialize the first node N1, and / or a transistor element configured to control the emission time of the light emitting element LD, or other circuit elements such as a boost capacitor for boosting the voltage of the first node N1.

[0094] In addition, although Figure 3a , the transistors (e.g., the first transistor T1 and the second transistor T2) included in the pixel driving circuit 144 have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 included in the pixel driving circuit 144 may be changed to an N-type transistor.

[0095] Reference Figure 1a , Figure 2 and Figure 3b , the first transistor T1 and the second transistor T2 according to the embodiment of the present disclosure may be formed by N-type transistors. In addition to the change in the connection position of some components caused by the change in the transistor type, Figure 3b The configuration and operation of the pixel driving circuit 144 shown in FIG. Figure 3a The configuration and operation of the pixel driving circuit 144 are similar. Therefore, detailed descriptions thereof will be omitted.

[0096] In the embodiment of the present disclosure, the configuration of the pixel driving circuit 144 is not limited to Figure 3a and Figure 3b For example, the pixel driving circuit 144 can be connected with Figure 3c The embodiment shown in FIG. 1 is constructed in the same manner.

[0097] Reference Figure 1a , Figure 2 and Figure 3c , the pixel driving circuit 144 may be electrically connected to the scan line Si and the data line Dj of the first sub-pixel SP1. For example, if the first sub-pixel SP1 is disposed on the i-th row and the j-th column of the display area DA, the pixel driving circuit 144 of the first sub-pixel SP1 may be electrically connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0098] In an embodiment, the pixel driving circuit 144 may also be electrically connected to at least one scan line. For example, the first subpixel SP1 disposed on the i-th row of the display area DA may be further electrically connected to the i-1th scan line Si-1 and / or the i+1th scan line Si+1.

[0099] In an embodiment, the pixel driving circuit 144 may be electrically connected not only to the first driving power source VDD and the second driving power source VSS, but also to a third power source. For example, the pixel driving circuit 144 may also be electrically connected to an initialization power source Vint.

[0100] The pixel driving circuit 144 may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0101] The first electrode (e.g., source electrode) of the first transistor (driving transistor) T1 may be electrically connected to the first driving power source VDD via the fifth transistor T5, and the second electrode (e.g., drain electrode) thereof may be connected to the first end of the light emitting element LD via the sixth transistor T6. The gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may control the driving current flowing between the first driving power source VDD and the second driving power source VSS via the light emitting element LD in response to the voltage of the first node N1.

[0102] The second transistor (driving transistor) T2 may be electrically connected between the source electrode of the first transistor T1 and the j-th data line Dj electrically connected to the first sub-pixel SP1. The gate electrode of the second transistor T2 is electrically connected to the i-th scan line Si electrically connected to the first sub-pixel SP1. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied from the i-th scan line Si, the second transistor T2 is turned on to electrically connect the j-th data line Dj to the source electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj may be transmitted to the first transistor T1.

[0103] The third transistor T3 is electrically connected between the drain electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is electrically connected to the i-th scan line Si. When a scan signal having a gate-on voltage is supplied from the scan line Si, the third transistor T3 is turned on to electrically connect the drain electrode of the first transistor T1 to the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 can be connected in the form of a diode (or diode connection).

[0104] The fourth transistor T4 may be electrically connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is electrically connected to the previous scan line (e.g., the i-1th scan line Si-1). When the scan signal of the gate-on voltage is supplied to the i-1th scan line Si-1, the fourth transistor T4 is turned on so that the voltage of the initialization power supply Vint can be transmitted to the first node N1. Here, the initialization power supply Vint may have a voltage equal to or less than the minimum voltage of the data signal.

[0105] The fifth transistor T5 is electrically connected between the first driving power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is electrically connected to the corresponding emission control line (e.g., the i-th emission control line Ei). The fifth transistor T5 can be turned off when the emission control signal with the gate cut-off voltage is supplied to the i-th emission control line Ei, and can be turned on in other cases.

[0106] The sixth transistor T6 is electrically connected between the first transistor T1 and the first end of the light emitting element LD. The gate electrode of the sixth transistor T6 may be electrically connected to the i-th emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0107] The seventh transistor T7 is electrically connected between the first end of the light emitting element LD and the initialization power supply Vint. The gate electrode of the seventh transistor T7 is electrically connected to any one of the scan lines of the next stage (for example, electrically connected to the i+1th scan line Si+1). When the scan signal of the gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 can be turned on, so that the voltage of the initialization power supply Vint can be supplied to the first end of the light emitting element LD.

[0108] The storage capacitor Cst is connected between the first driving power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both the data signal applied to the first node N1 during each frame period and the threshold voltage of the first transistor T1.

[0109] For convenience purposes, Figure 3cIt is shown that all of the first transistor T1 to the seventh transistor T7 are formed by P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 included in the pixel driving circuit 144 may be formed by an N-type transistor, or all of the first transistor T1 to the seventh transistor T7 may be formed by N-type transistors.

[0110] In an embodiment, Figure 3d As shown in , the pixel driving circuit 144 may include a third transistor T3 in addition to the first transistor T1 and the second transistor T2. The third transistor T3 may be connected between the j-th data line Dj and the anode electrode of each of the light emitting elements LD. The gate electrode of the third transistor T3 may be connected to the control line CLi, so that the third transistor T3 may be turned on when a control signal is supplied to the control line CLi, and may be turned off in other cases.

[0111] For convenience purposes, Figure 3d It is shown that all of the first transistor T1 to the third transistor T3 are formed by P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the third transistor T3 included in the pixel driving circuit 144 may be formed by an N-type transistor, or all of the first transistor T1 to the third transistor T3 may be formed by N-type transistors.

[0112] Figure 4 It is schematically shown that the Figure 2 A plan view of first to third sub-pixels in one of the pixels shown in FIG. Figure 5 It is along Figure 4 A cross-sectional view taken along line II'.

[0113] exist Figure 4 In the embodiment of the present invention, for the purpose of illustration, a plurality of light emitting elements arranged in each sub-pixel are shown as being horizontally aligned. However, the alignment of the light emitting elements is not limited thereto. For example, at least some of the light emitting elements may be aligned in a direction intersecting the horizontal direction.

[0114] In addition, for illustrative purposes, Figure 4 Illustration of transistors connected to light-emitting elements and signal lines connected to the transistors has been omitted.

[0115] In addition, despite Figure 4 and Figure 5 A simplified structure of one pixel is shown (eg, each electrode is shown to have only a single electrode layer), but the present disclosure is not limited thereto.

[0116] Reference Figures 1a to 5, the display device according to an embodiment of the present disclosure may include a base layer BSL on which a plurality of pixels PXL are disposed.

[0117] Each of the pixels PXL may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3 disposed on the base layer BSL. In an embodiment of the present disclosure, the first subpixel SP1 may be a red subpixel, the second subpixel SP2 may be a green subpixel, and the third subpixel SP3 may be a blue subpixel.

[0118] Each of the first to third sub-pixels SP1 to SP3 may include an emission area EMA that emits light and a non-emission area PPA disposed around the periphery of the emission area EMA. In an embodiment of the present disclosure, the pixel area of ​​each of the first to third sub-pixels SP1 to SP3 may include the emission area EMA and the non-emission area PPA of the corresponding sub-pixel.

[0119] The base layer BSL, the pixel circuit layer PCL, and the display element layer DPL may be disposed in a pixel region of each of the first to third sub-pixels SP1 to SP3 .

[0120] The pixel circuit layer PCL of each of the first to third subpixels SP1 to SP3 may include a buffer layer BFL disposed on the base layer BSL, a driving voltage line DVL, and a first transistor T1 and a second transistor T2 disposed on the buffer layer BFL. In addition, the pixel circuit layer PCL of each of the first to third subpixels SP1 to SP3 may also include a passivation layer PSV disposed on the first transistor T1 and the second transistor T2 and the driving voltage line DVL.

[0121] The base layer BSL may include an insulating material such as glass, an organic polymer, or a crystal. In addition, the base layer BSL may be made of a material having flexibility so as to be bendable or foldable, and have a single-layer structure or a multi-layer structure.

[0122] The buffer layer BFL may be disposed on the base layer BSL and may prevent impurities from diffusing into the first transistor T1 and the second transistor T2. The buffer layer BFL may be omitted according to process conditions or materials of the base layer BSL.

[0123] A light shielding pattern SDL may be disposed between the base layer BSL and the buffer layer BFL.

[0124] The light shielding pattern SDL may be a light shielding layer formed of a conductive material, an insulating material, etc., and blocks light introduced into the rear surface of the base layer BSL, so that light can be blocked from being introduced into the pixel circuit layer PCL of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. In an embodiment, the light shielding pattern SDL may include a black matrix. The light shielding pattern SDL may be disposed on the base layer BSL to correspond to the lower portion of the semiconductor layer SCL of each of the first transistor T1 and the second transistor T2. In an embodiment, the light shielding pattern SDL may be formed of a metal as a conductive material. In this case, the light shielding pattern SDL may be electrically connected to a component of any one of the first transistor T1 and the second transistor T2.

[0125] The first transistor T1 may be a driving transistor electrically connected to some of the light emitting elements LD disposed in the display element layer DPL of the corresponding sub-pixel to drive the light emitting elements LD. The second transistor T2 may be a switching transistor configured to switch the first transistor T1.

[0126] Each of the first and second transistors T1 and T2 may include a semiconductor layer SCL, a gate electrode GE, and source and drain electrodes SE and DE.

[0127] The semiconductor layer SCL may be disposed on the buffer layer BFL. The semiconductor layer SCL may include a source region contacting the source electrode SE and a drain region contacting the drain electrode DE. A region between the source region and the drain region may be a channel region.

[0128] The semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region may be an intrinsic semiconductor as an undoped semiconductor pattern. Each of the source region and the drain region may be a semiconductor pattern doped with impurities.

[0129] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween.

[0130] The source electrode SE and the drain electrode DE may respectively contact the source region and the drain region of the semiconductor layer SCL through corresponding contact holes passing through the interlayer insulating layer ILD and the gate insulating layer GI.

[0131] In an embodiment of the present disclosure, each of the first transistor T1 and the second transistor T2 included in the pixel circuit layer PCL provided in each sub-pixel may be formed by an LTPS thin film transistor, but the present disclosure is not limited thereto. In some embodiments, each of the first transistor T1 and the second transistor T2 may be formed by an oxide semiconductor thin film transistor.

[0132] The drain electrode DE of each of the first transistor T1 and the second transistor T2 may be electrically connected to the light shielding pattern SDL disposed on the base layer BSL. In detail, the drain electrode DE of each of the first transistor T1 and the second transistor T2 may be electrically connected to the corresponding light shielding pattern SDL through a contact hole sequentially passing through the interlayer insulating layer ILD, the gate insulating layer GI, and the buffer layer BFL.

[0133] The driving voltage line DVL may be disposed on the interlayer insulating layer ILD, but the present disclosure is not limited thereto. In some embodiments, the driving voltage line DVL may be disposed on any insulating layer included in the pixel circuit layer PCL. The second driving power source ( Figure 3a VSS) can be applied to the driving voltage line DVL.

[0134] The passivation layer PSV may include a first contact hole CH1 exposing a portion of the drain electrode DE of the first transistor T1 and a second contact hole CH2 exposing a portion of the driving voltage line DVL.

[0135] The display element layer DPL of each of the first to third subpixels SP1 to SP3 may include a wall (or partition wall) PW disposed on the passivation layer PSV, first and second electrodes REL1 and REL2, first and second connection lines CNL1 and CNL2, a plurality of light emitting elements LD, and first and second contact electrodes CNE1 and CNE2.

[0136] A partition wall PW may be disposed on the passivation layer PSV in the emission area EMA of each of the first to third sub-pixels SP1 to SP3. A bank BNK formed of the same material as the partition wall PW may be formed and / or disposed in the non-emission area PPA between adjacent sub-pixels to define the emission area EMA of each sub-pixel.

[0137] In an embodiment of the present disclosure, the partition wall PW and the embankment BNK may be disposed on the same surface and formed and / or disposed by the same process. The partition wall PW and the embankment BNK may be disposed integrally with each other and may include the same material. In the case where the partition wall PW disposed in the emission area EMA of each of the first to third sub-pixels SP1 to SP3 and the embankment BNK disposed in the non-emission area PPA of each of the first to third sub-pixels SP1 to SP3 are formed and / or disposed by the same process, the number of mask processes may be reduced compared to the case where the partition wall PW and the embankment BNK are formed separately. Figure 8b A detailed description is given in this regard.

[0138] The partition wall PW may be spaced apart from a partition wall PW disposed adjacent thereto on the passivation layer PSV by a predetermined distance. Two adjacent partition walls PW may be disposed on the passivation layer PSV and spaced apart from each other by a length L of one or more light emitting elements LD. Figure 5 As shown in FIG. 4 , although the partition wall PW may have a trapezoidal cross-section whose width decreases upward from one surface of the passivation layer PSV, the present disclosure is not limited thereto.

[0139] In an embodiment, the partition wall PW may include a curved surface having a cross-sectional shape such as a semicircular shape and a semi-elliptical shape, the width of which decreases upward from one surface of the passivation layer PSV. In a cross-sectional view, the shape of each of the partition walls PW is not limited to the aforementioned example, and may be changed in various ways within a range that may enhance the efficiency of light emitted from each of the light emitting elements LD. Two adjacent partition walls PW may be disposed on the same plane on the passivation layer PSV and have the same height.

[0140] The first connection line CNL1 may extend from each of the first to third sub-pixels SP1 to SP3 in the first direction DR1. The first connection line CNL1 may be disposed only in one corresponding sub-pixel to independently drive each of the first to third sub-pixels SP1 to SP3.

[0141] The second connection line CNL2 may extend in a direction parallel to the direction in which the first connection line CNL1 extends. The second connection line CNL2 may be provided in common for the first to third subpixels SP1 to SP3. Therefore, the first to third subpixels SP1 to SP3 may be connected in common to the second connection line CNL2.

[0142] Each of the first and second electrodes REL1 and REL2 may be disposed in the emission area EMA of each of the first to third subpixels SP1 to SP3 and extend in a second direction DR2 crossing the first direction DR1. The first and second electrodes REL1 and REL2 may be disposed on the same plane and spaced apart from each other by a predetermined distance.

[0143] The first electrode REL1 may be connected to the first connection line CNL1. For example, the first electrode REL1 may be integrally connected to the first connection line CNL1. For example, the first electrode REL1 may include a 1-1 electrode REL1_1 and a 1-2 electrode REL1_2 that diverge from the first connection line CNL1 extending in the first direction DR1 in the second direction DR2. The 1-1 electrode REL1_1, the 1-2 electrode REL1_2, and the first connection line CNL1 may be integrally provided and electrically and / or physically connected to each other. In the case where the first electrode REL1 and the first connection line CNL1 are integrally formed and / or provided with each other, the first connection line CNL1 may be considered as a region of the first electrode REL1. However, the present disclosure is not limited thereto. For example, in some embodiments, the first electrode REL1 and the first connection line CNL1 may be formed separately and electrically connected to each other through a contact hole or through hole, etc., not shown.

[0144] The second electrode REL2 may extend in the second direction DR2 and be electrically connected to the second connection line CNL2. In an embodiment of the present disclosure, the second electrode REL2 may be bifurcated from the second connection line CNL2 in the second direction DR2. Therefore, the second electrode REL2 and the second connection line CNL2 may be integrally provided and electrically and / or physically connected to each other. In the case where the second electrode REL2 and the second connection line CNL2 are integrally formed and / or provided with each other, the second connection line CNL2 may be considered as a region of the second electrode REL2. However, the present disclosure is not limited thereto. For example, in some embodiments, the second electrode REL2 and the second connection line CNL2 may be formed separately and electrically connected to each other through contact holes or through holes not shown.

[0145] Each of the first electrode REL1 and the second electrode REL2 may function as an alignment electrode for aligning the light emitting element LD in the emission area EMA of each of the first to third sub-pixels SP1 to SP3 .

[0146] Before the light emitting element LD is aligned in the emission area EMA of each of the first to third sub-pixels SP1 to SP3, a first alignment voltage may be applied to the first electrode REL1 through the first connection line CNL1, and a second alignment voltage may be applied to the second electrode REL2 through the second connection line CNL2. The first alignment voltage and the second alignment voltage may have different voltage levels. When predetermined alignment voltages having different voltage levels are applied to the first electrode REL1 and the second electrode REL2, respectively, an electric field may be formed between the first electrode REL1 and the second electrode REL2. Therefore, the light emitting element LD may be aligned between the first electrode REL1 and the second electrode REL2.

[0147] The second electrode REL2 may be disposed between the 1-1 electrode REL1_1 and the 1-2 electrode REL1_2 in a plan view and spaced apart from each of the 1-1 electrode REL1_1 and the 1-2 electrode REL1_2 by a predetermined distance. The 1-1 electrode REL1_1, the 1-2 electrode REL1_2, and the second electrode REL2 may be alternately disposed on the passivation layer PSV.

[0148] After the light emitting element LD is aligned in the emission area EMA of each of the first to third sub-pixels SP1 to SP3 , each of the first and second electrodes REL1 and REL2 may function as a driving electrode for driving the light emitting element LD.

[0149] The first and second electrodes REL1 and REL2 may be made of a material having a predetermined reflectivity to allow light emitted from opposite ends EP1 and EP2 of each of the light emitting elements LD to travel in a direction in which an image of the display device is displayed (eg, in a front direction).

[0150] In an embodiment of the present disclosure, the first and second electrodes REL1 and REL2 , the first and second connection lines CNL1 and CNL2 may be disposed on the same layer and formed of the same material.

[0151] The first and second electrodes REL1 and REL2, the first and second connection lines CNL1 and CNL2 may be formed of a conductive material having a predetermined reflectivity. The conductive material may include a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or an alloy thereof, a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO), and a conductive polymer such as PEDOT.

[0152] The materials of the first and second electrodes REL1 and REL2 , the first and second connection lines CNL1 and CNL2 are not limited to the aforementioned materials.

[0153] Each of the first and second electrodes REL1 and REL2 , the first and second connection lines CNL1 and CNL2 may have a single layer structure, but the present disclosure is not limited thereto, for example, they may have a multilayer structure formed by stacking two materials of metal, alloy, conductive oxide, and conductive polymer.

[0154] Each of the first and second electrodes REL1 and REL2 , the first and second connection lines CNL1 and CNL2 may have a multilayer structure having at least two layers to minimize a voltage drop due to a signal delay when a signal is transmitted to opposite ends EP1 and EP2 of each of the light emitting elements LD.

[0155] Since the first electrode REL1 and the second electrode REL2 have a shape corresponding to the shape of the partition wall PW, light emitted from the opposite ends EP1 and EP2 of each of the light emitting elements LD can be reflected by the first electrode REL1 and the second electrode REL2 to more efficiently travel in the front direction of the display device. Therefore, the efficiency of light emitted from the light emitting element LD can be enhanced.

[0156] In an embodiment of the present disclosure, the partition wall PW and the first and second electrodes REL1 and REL2 may function as a reflective component that enables light emitted from each of the light emitting elements LD to travel in a front direction of the display device, thereby enhancing light output efficiency of the light emitting elements LD.

[0157] Any one of the first electrode REL1 and the second electrode REL2 may be an anode electrode, and the other may be a cathode electrode. In an embodiment of the present disclosure, the first electrode REL1 may be an anode electrode, and the second electrode REL2 may be a cathode electrode.

[0158] Each of the light emitting elements LD may be formed of a light emitting diode which is made of a material having an inorganic crystal structure and has an ultra-small size corresponding to, for example, a nano-scale size or a micro-scale size.

[0159] Although at least two or tens of light emitting elements LD are disposed in the emission area EMA of each of the first, second, and third subpixels SP1, SP2, and SP3, the present disclosure is not limited thereto. In embodiments, the number of light emitting elements LD disposed in each subpixel may be changed in various ways.

[0160] Each of the light emitting elements LD may include a stacked emission pattern formed by sequentially stacking a first conductive semiconductor layer 11, an active layer 12, a second conductive semiconductor layer 13, and an electrode layer 15 in the longitudinal direction of each light emitting element LD. In addition, each of the light emitting elements LD may further include an insulating film 14 surrounding the outer peripheral surface of the stacked emission pattern. In the embodiment of the present disclosure, each of the light emitting elements LD may have a cylindrical shape. In this case, each light emitting element LD may have a first end EP1 corresponding to any one of the lower part of the cylinder and the upper part of the cylinder and a second end EP2 corresponding to the other of the lower part of the cylinder and the upper part of the cylinder. Any one of the first conductive semiconductor layer 11 and the electrode layer 15 may be disposed on the first end EP1 of each light emitting element LD, and the other of the first conductive semiconductor layer 11 and the electrode layer 15 may be disposed on the second end EP2 of each light emitting element LD.

[0161] In an embodiment of the present disclosure, the light emitting element LD may be divided into a plurality of first light emitting elements LD1 aligned between the 1-1 electrode REL1_1 and the second electrode REL2 and a plurality of second light emitting elements LD2 aligned between the second electrode REL2 and the 1-2 electrode REL1_2 .

[0162] A second insulating layer INS2 for covering a portion of an upper surface of each of the light emitting elements LD may be disposed on the light emitting element LD. A first insulating layer INS1 may be disposed between each of the light emitting elements LD and the passivation layer PSV.

[0163] The first insulating layer INS1 may be filled into the space between the passivation layer PSV and each of the light emitting elements LD to stably support the light emitting element LD and prevent the light emitting element LD from being removed from the passivation layer PSV. The first insulating layer INS1 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. Although in an embodiment of the present disclosure, the first insulating layer INS1 may be formed of an inorganic insulating layer having an advantage of protecting the light emitting element LD from the pixel circuit layer PCL, the present disclosure is not limited thereto. In an embodiment, the first insulating layer INS1 may be formed of an organic insulating layer having an advantage in flattening the supporting surface of the light emitting element LD.

[0164] The second insulating layer INS2 may be an organic insulating layer including an organic material. In an embodiment of the present disclosure, the second insulating layer INS2 may be disposed on a portion of an upper surface of each of the light emitting elements LD so that opposite ends EP1 and EP2 of each of the light emitting elements LD may be exposed to the outside.

[0165] In an embodiment of the present disclosure, the first connection line CNL1 may be electrically connected to the drain electrode DE of the first transistor T1 through the first contact hole CH1 of the passivation layer PSV. Since the first connection line CNL1 is integrally provided with the first electrode REL1, a signal of the first transistor T1 applied to the first connection line CNL1 may be transmitted to the first electrode REL1.

[0166] The first electrode REL1 may be disposed adjacent to one of the opposite ends EP1 and EP2 of each of the light emitting elements LD and may be electrically connected to each of the light emitting elements LD through the first contact electrode CNE1. Therefore, a signal of the first transistor T1 applied to the first electrode REL1 may be transmitted to each of the light emitting elements LD through the first contact electrode CNE1.

[0167] In an embodiment of the present disclosure, the second connection line CNL2 may be electrically connected to the driving voltage line DVL through the second contact hole CH2 of the passivation layer PSV. Since the second connection line CNL2 is integrally provided with the second electrode REL2, the voltage of the second driving power source VSS of the driving voltage line DVL applied to the second connection line CNL2 may be transmitted to the second electrode REL2.

[0168] The second electrode REL2 may be disposed adjacent to the other of the opposite ends EP1 and EP2 of each of the light emitting elements LD and may be electrically connected to each of the light emitting elements LD through the second contact electrode CNE2. Therefore, the voltage of the second driving power VSS applied to the second electrode REL2 may be transmitted to each of the light emitting elements LD.

[0169] The first contact electrode CNE1 may be disposed on the first electrode REL1 to electrically and / or physically reliably connect the first electrode REL1 to one of the opposite ends EP1 and EP2 of each of the light emitting elements LD. The first contact electrode CNE1 may be formed of a transparent conductive material to allow light emitted from each of the light emitting elements LD and reflected by the first electrode REL1 in the front direction of the display device to travel in the front direction without loss.

[0170] In a plan view, the first contact electrode CNE1 may cover and overlap the first electrode REL1. In addition, the first contact electrode CNE1 may partially overlap one of the opposite ends EP1 and EP2 of each of the light emitting elements LD. The first contact electrode CNE1 may include a 1-1st contact electrode CNE1_1 disposed on the 1-1st electrode REL1_1 and a 1-2nd contact electrode CNE1_2 disposed on the 1-2nd electrode REL1_2.

[0171] The second contact electrode CNE2 may be disposed on the second electrode REL2. In a plan view, the second contact electrode CNE2 may cover the second electrode REL2 and overlap the second electrode REL2. In addition, the second contact electrode CNE2 may overlap the second end EP2 of each of the first light emitting elements LD1 and the first end EP1 of each of the second light emitting elements LD2. The second contact electrode CNE2 may be made of the same material as that of the first contact electrode CNE1, but the present disclosure is not limited thereto.

[0172] In an embodiment of the present disclosure, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same plane and spaced apart from each other by a predetermined distance on the second insulating layer INS2, so that the first contact electrode CNE1 and the second contact electrode CNE2 may be electrically and / or physically separated from each other. In other words, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same layer and formed by the same manufacturing process.

[0173] A third insulating layer INS3 for covering the first and second contact electrodes CNE1 and CNE2 may be disposed on the first and second contact electrodes CNE1 and CNE2. The third insulating layer INS3 may prevent the first and second contact electrodes CNE1 and CNE2 from being exposed to the outside, thereby preventing the first and second contact electrodes CNE1 and CNE2 from being corroded.

[0174] The third insulating layer INS3 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. Although the third insulating layer INS3 may have a single-layer structure as shown in the drawings, the present disclosure is not limited thereto. For example, the third insulating layer INS3 may have a multi-layer structure. In the case where the third insulating layer INS3 has a multi-layer structure, the third insulating layer INS3 may have a structure formed by alternately stacking a plurality of inorganic insulating layers and a plurality of organic insulating layers. For example, the third insulating layer INS3 may have a structure formed by sequentially stacking a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer.

[0175] An overcoat layer (not shown) may be provided on the third insulating layer INS3. The overcoat layer may be a planarization layer for alleviating a step difference formed by the partition wall PW, the first and second electrodes REL1 and REL2, the first and second contact electrodes CNE1 and CNE2, etc. provided below the overcoat layer. The overcoat layer may be an encapsulation layer provided to prevent oxygen, water, etc. from penetrating into the light emitting element LD.

[0176] A predetermined voltage may be applied to opposite ends EP1 and EP2 of each of the light emitting elements LD through the first electrode REL1 and the second electrode REL2, respectively. Therefore, each of the light emitting elements LD may emit light by combining electron-hole pairs in the active layer 12 of each of the light emitting elements LD. Here, the active layer 12 may emit light having a wavelength ranging from 400 nm to 900 nm.

[0177] Figure 6 It is shown Figure 4 Schematic plan view of another embodiment of a first sub-pixel in a pixel.

[0178] In addition to the structure in which the emission region includes a first sub-emission region and a second sub-emission region and the alignment shapes of the electrodes are different from each other in the respective sub-emission regions, Figure 6 The structure of the first sub-pixel shown in FIG. Figure 4 The structures of the first sub-pixels are substantially the same or similar.

[0179] Therefore, to avoid redundant explanation, Figure 6 The description of the first sub-pixel of the embodiment will focus on the differences from the previous embodiment. Components not separately described in the following description of this embodiment are consistent with the components of the previous embodiment. The same reference numerals will be used to identify the same components, and similar reference numerals will be used to identify similar components.

[0180] Reference Figure 1a , Figure 2 , Figure 4 and Figure 6 , the first sub-pixel SP1 may include an emission area EMA that may emit light and a non-emission area PPA disposed around the emission area EMA.

[0181] The display element layer of the first sub-pixel SP1 (see Figure 5 DPL) may include settings in the circuit element layer (refer to Figure 5 The partition wall PW on the PCL, the first and second electrodes REL1 and REL2, the first and second connection wires CNL1 and CNL2, the plurality of light emitting elements LD, and the first and second contact electrodes CNE1 and CNE2.

[0182] The light emitting element LD may include a first light emitting element LD1 and a second light emitting element LD2. Each of the first light emitting elements LD1 may include a first end EP1 and a second end EP2 in a first direction DR1. Here, the first direction DR1 may refer to a horizontal direction in a plan view. Each of the second light emitting elements LD2 may include a first end EP1 and a second end EP2 in a second direction DR2 intersecting the first direction DR1. Here, the second direction DR2 may refer to a vertical direction in a plan view. The first light emitting element LD1 may be aligned in a horizontal direction, and the second light emitting element LD2 may be aligned in a vertical direction.

[0183] In an embodiment of the present disclosure, the emission area EMA of the first sub-pixel SP1 may include a first sub-emission area SEMA1 in which the first light emitting element LD1 is disposed and a second sub-emission area SEMA2 in which the second light emitting element LD2 is disposed.

[0184] In an embodiment of the present disclosure, the first electrode REL1 may include a 1-1th electrode REL1_1 and a 1-2th electrode REL1_2 , and the second electrode REL2 may include a 2-1th electrode REL2_1 and a 2-2nd electrode REL2_2 .

[0185] In a plan view, a portion of the first electrode REL1 and a portion of the second electrode REL2 may be alternately disposed in the first direction DR1 in the first sub-emission region SEMA1. For example, a 1-1 electrode REL1_1 of the first electrode REL1 and a 2-1 electrode REL2_1 of the second electrode REL2 may be alternately disposed in the first direction DR1 in the first sub-emission region SEMA1.

[0186] In a plan view, another portion of the first electrode REL1 and another portion of the second electrode REL2 may be alternately disposed in the second direction DR2 in the second sub emission area SEMA2. For example, the 1-2 electrode REL1_2 of the first electrode REL1 and the 2-2 electrode REL2_2 of the second electrode REL2 may be alternately disposed in the second direction DR2 in the second sub emission area SEMA2.

[0187] In an embodiment of the present disclosure, the first contact electrode CNE1 may include a 1-1th contact electrode CNE1_1 and a 1-2th contact electrode CNE1_2, wherein the 1-1th contact electrode CNE1_1 is disposed on the 1-1th electrode REL1_1 and overlaps the 1-1th electrode REL1_1 in a plan view, and the 1-2nd contact electrode CNE1_2 is disposed on the 1-2th electrode REL1_2 and overlaps the 1-2th electrode REL1_2 in a plan view.

[0188] In addition, the second contact electrode CNE2 may include a 2-1st contact electrode CNE2_1 and a 2-2nd contact electrode CNE2_2 disposed on the 2-1st electrode REL2_1 and overlapping the 2-1st electrode REL2_1 in a plan view and a 2-2nd contact electrode CNE2_2 disposed on the 2-2nd electrode REL2_2 and overlapping the 2-2nd electrode REL2_2 in a plan view.

[0189] The distance between the 1-1 electrode REL1_1 and the 2-1 electrode REL2_1 in the first sub-emission area SEMA1 and the distance between the 1-2 electrode REL1_2 and the 2-2 electrode REL2_2 in the second sub-emission area SEMA2 can be designed to be the same as each other. The reason for this is because the alignment surface area of ​​the first light emitting element LD1 aligned in the first sub-emission area SEMA1 can be formed to be the same as the alignment surface area of ​​the second light emitting element LD2 aligned in the second sub-emission area SEMA2. In the case where the respective alignment surface areas of the first sub-emission area SEMA1 and the second sub-emission area SEMA2 are the same as each other, the first light emitting element LD1 and the second light emitting element LD2 can be prevented from being biased to one area.

[0190] A bank BNK disposed on the same plane as that of the partition wall PW may be disposed in the non-emission area PPA of the first subpixel SP1. The bank BNK may be formed and / or disposed in the non-emission area PPA between the first subpixel SP1 and subpixels adjacent to the first subpixel SP1 to define an emission area EMA of each subpixel.

[0191] In an embodiment of the present disclosure, the partition wall PW and the bank BNK may be formed of an organic insulating material including an organic material, but the present disclosure is not limited thereto. In an embodiment, the partition wall PW and the bank BNK may be formed of an inorganic insulating material including an inorganic material, or may be formed of a conductive material that can prevent the first electrode REL1 and the second electrode REL2 and the light emitting element LD from being directly affected by reflection of external light.

[0192] In an embodiment of the present disclosure, for the purpose of illustration, an example is shown in which a dam BNK disposed in a non-emission area PPA of a first sub-pixel SP1 is integrally disposed with a partition wall PW disposed in each of the first sub-emission area SEMA1 and the second sub-emission area SEMA2 and is thereby physically connected to the partition wall PW. However, the present disclosure is not limited thereto. In an embodiment, the dam BNK may be disposed in the non-emission area PPA of the first sub-pixel SP1 such that the dam BNK is spaced apart from the partition wall PW on the same plane by a predetermined distance.

[0193] In the non-emission area PPA of the first subpixel SP1 , the first and second connection lines CNL1 and CNL2 may be disposed on the corresponding bank BNK and thus overlap the corresponding bank BNK in a plan view.

[0194] Figure 7 It is shown Figure 4 Schematic plan view of another embodiment of a first sub-pixel in a pixel.

[0195] To avoid redundant explanation, Figure 7The description of the first sub-pixel of the embodiment will focus on the differences from the description of the previous embodiment. Components not separately described in the following description of this embodiment conform to the components of the previous embodiment. The same reference numerals will be used to identify the same components, and similar reference numerals will be used to identify similar components.

[0196] For the purpose of illustration, Figure 7 Only the first electrode and the second electrode, the light emitting element disposed between the first electrode and the second electrode, and the second connection line connected to the second electrode are shown.

[0197] Reference Figure 1a , Figure 2 , Figure 4 and Figure 7 , the first sub-pixel SP1 may include an emission area EMA that may emit light and a non-emission area PPA disposed around the emission area EMA.

[0198] The display element layer of the first sub-pixel SP1 (see Figure 5 DPL) may include settings in the circuit element layer (refer to Figure 5 The first electrode REL1 and the second electrode REL2 on the PCL, the second connection line CNL2 and the plurality of light emitting elements LD.

[0199] In an embodiment of the present disclosure, the first electrode REL1 and the second electrode REL2 may be disposed on the same plane on the passivation layer PSV and electrically connected to the light emitting element LD. Each of the first electrode REL1 and the second electrode REL2 may have a circular shape. In this case, if the first electrode REL1 and the second electrode REL2 are respectively supplied with corresponding alignment voltages, an electric field having a radial shape may be formed between the first electrode REL1 and the second electrode REL2. Therefore, the light emitting element LD may be aligned in different directions along the circumference of the first electrode REL1.

[0200] like Figure 1a As shown in , each of the light emitting elements LD may have a cylindrical shape. Specifically, each of the light emitting elements LD may include a first end EP1 and a second end EP2 in a longitudinal direction. The first conductive semiconductor layer 11 may be disposed on any one of the first end EP1 and the second end EP2 of each of the light emitting elements LD. The electrode layer 15 may be disposed on the other of the first end EP1 and the second end EP2 of each of the light emitting elements LD.

[0201] Although each of the first electrode REL1 and the second electrode REL2 may have a circular shape as shown in the drawings, the present disclosure is not limited thereto and may have various shapes such as an elliptical shape, a rectangular shape, and a polygonal shape.

[0202] The first electrode REL1 and the second electrode REL2 may be disposed in the emission area EMA of the first subpixel SP1. The second electrode REL2 may be disposed in a shape surrounding the periphery of the first electrode REL1. Specifically, the second electrode REL2 may extend in a circumferential direction around the first electrode REL1. In an embodiment of the present disclosure, the second electrode REL2 may include a 2-1st electrode REL2_1 and a 2-2nd electrode REL2_2. The 2-1st electrode REL2_1 and the 2-2nd electrode REL2_2 may be spaced apart from each other by a predetermined distance.

[0203] The 2-1st electrode REL2_1 may be electrically connected to another 2-1st electrode REL2_1 disposed on the same column in the second direction DR2 through a 2-1st connection line CNL2_1. The 2-2nd electrode REL2_2 may be electrically connected to another 2-2nd electrode REL2_2 disposed on the same column in the second direction DR2 through a 2-2nd connection line CNL2_2.

[0204] Figure 8a to Figure 8h The order is shown in the manufacturing Figure 5 A cross-sectional view of a method of displaying a device.

[0205] Reference Figures 1a to 8a A pixel circuit layer PCL is formed on each base layer BSL of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. The pixel circuit layer PCL may include a light shielding pattern SDL, first and second transistors T1 and T2, a driving voltage line DVL, and a passivation layer PSV.

[0206] The passivation layer PSV may include a first contact hole CH1 exposing the drain electrode DE of the first transistor T1 and a second contact hole CH2 exposing the driving voltage line DVL.

[0207] Reference Figures 1a to 8b After applying an insulating material layer (not shown) to the passivation layer PSV, a partition wall PW is formed in the emission area EMA of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 by patterning the insulating material layer using a mask (not shown), and at the same time, a bank BNK is formed in the non-emission area PPA between the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The mask used during the above-mentioned manufacturing process may be a half-tone mask.

[0208] In an embodiment of the present disclosure, the partition wall PW and the bank BNK may be disposed on the same surface and may include the same material. For example, the partition wall PW and the bank BNK may each be an organic insulating layer including an organic material.

[0209] As described above, when the passivation layer PSV and the partition wall PW are formed by the same process, the number of masks can be reduced compared to when the passivation layer PSV and the partition wall PW are formed by separate processes. Therefore, the process of manufacturing the display device can be further simplified.

[0210] Reference Figures 1a to 8c , first and second electrodes REL1 and REL2 including a conductive material having high reflectivity and first and second connection lines CNL1 and CNL2 are formed on the passivation layer PSV of each sub-pixel including the partition wall PW.

[0211] Each of the first and second electrodes REL1 and REL2 may be disposed and / or formed on a corresponding partition wall PW in the emission area EMA of each subpixel. Each of the first and second connection lines CNL1 and CNL2 may be disposed and / or formed in the non-emission area PPA of each subpixel.

[0212] In an embodiment of the present disclosure, the first connection line CNL1 may be electrically connected to the first transistor T1 of the pixel circuit layer PCL through the first contact hole CH1 of the passivation layer PSV. The first connection line CNL1 may be integrally provided with the first electrode REL1 and electrically and / or physically connected to the first electrode REL1. Therefore, the signal (or voltage) applied to the first transistor T1 may be transmitted to the first electrode REL1 through the first connection line CNL1.

[0213] The second connection line CNL2 may be electrically connected to the driving voltage line DVL of the pixel circuit layer PCL through the second contact hole CH2 of the passivation layer PSV. The second connection line CNL2 may be integrally provided with the second electrode REL2 and electrically and / or physically connected to the second electrode REL2. Therefore, the voltage of the second driving power VSS of the driving voltage line DVL may be transmitted to the second electrode REL2 through the second connection line CNL2.

[0214] Reference Figures 1a to 8d After depositing an insulating material layer (not shown) on the passivation layer PSV on which the first and second electrodes REL1 and REL2 are formed, the first insulating layer INS1 is formed by patterning the insulating material layer using a mask (not shown).

[0215] A first insulating layer INS1 may be formed and / or disposed in the emission area EMA of each subpixel between the first electrode REL1 and the second electrode REL2, and may be formed and / or disposed on the first and second connection lines CNL1 and CNL2 in the non-emission area PPA of each subpixel.

[0216] Reference Figures 1a to 8e, an electric field is formed between the first electrode REL1 and the second electrode REL2 by applying corresponding alignment voltages to the first electrode REL1 and the second electrode REL2 of each sub-pixel through the first connection line CNL1 and the second connection line CNL2, respectively. In the case where AC power or DC power having a predetermined voltage and period is repeatedly applied to each of the first electrode REL1 and the second electrode REL2 several times through the first connection line CNL1 and the second connection line CNL2, an electric field can be formed between the first electrode REL1 and the second electrode REL2 by the potential difference between the first electrode REL1 and the second electrode REL2.

[0217] After an electric field is formed between the first electrode REL1 and the second electrode REL2 formed in the emission area EMA of each sub-pixel, the light-emitting element LD is supplied by an inkjet printing scheme or the like. For example, the light-emitting element LD can be supplied to the passivation layer PSV of the emission area EMA of such a sub-pixel by setting a nozzle above the passivation layer PSV and dripping a solution including the light-emitting element LD onto the passivation layer PSV through the nozzle. The solution may be any one of acetone, water, ethanol and toluene, but the present disclosure is not limited thereto. For example, the solution may include a material that can evaporate at room temperature or by heating. In addition, the solution may have the form of ink or paste. The method of supplying the light-emitting element LD is not limited to the above method. The method of supplying the light-emitting element LD may be changed. Subsequently, the solution may be removed.

[0218] If the light emitting element LD is supplied to the passivation layer PSV, the self-alignment of the light emitting element LD can be caused by the electric field formed between the first electrode REL1 and the second electrode REL2. Therefore, the light emitting element LD can be aligned between the first electrode REL1 and the second electrode REL2. In other words, the light emitting element LD can be densely aligned in the target area (e.g., the emission area EMA of each sub-pixel).

[0219] Reference Figures 1a to 8f After alignment of the light emitting elements LD, a second insulating layer INS2 covering a portion of the upper surface of each light emitting element LD is formed by applying an insulating material layer (not shown) onto the passivation layer PSV and patterning the insulating material layer using a mask (not shown). Therefore, opposite ends EP1 and EP2 of each of the light emitting elements LD may be exposed to the outside.

[0220] Reference Figures 1a to 8g After forming a conductive layer (not shown) over the entire surface of the passivation layer PSV on the second insulating layer INS2, the first and second contact electrodes CNE1 and CNE2 are formed by patterning the conductive layer using a mask (not shown).

[0221] The first contact electrode CNE1 and the second contact electrode CNE2 may be spaced apart from each other by a predetermined distance on the second insulating layer INS2 and thus be electrically and / or physically separated from each other.

[0222] The portion of the first connection line CNL1 that is commonly connected to the sub-pixels and / or commonly provided for the sub-pixels can be removed by the aforementioned mask process, so that each sub-pixel can be driven independently of the adjacent sub-pixels. Therefore, each sub-pixel can be driven individually, and the display device according to the embodiment of the present disclosure can be implemented as an active matrix display device.

[0223] Reference Figure 1a to Figure 8h A third insulating layer INS3 is formed on the first contact electrode CNE1 and the second contact electrode CNE2.

[0224] In the display device manufactured by the above manufacturing process, during the process of manufacturing the display element layer DPL, the partition wall PW is formed in the emission area EMA of each sub-pixel, and at the same time, the bank BNK is formed in the non-emission area PPA of each sub-pixel. Therefore, the number of mask processes can be reduced.

[0225] Fig. 9 A display device according to an embodiment of the present disclosure is shown, and a color conversion layer is combined with Figure 5 A schematic cross-sectional view of the structure of a display device.

[0226] For the purpose of illustration, Fig. 9 A pixel region of one pixel among a plurality of pixels included in a display device is schematically shown.

[0227] In addition, for convenience, Fig. 9 , schematically shown with reference to Figure 5 The structures of some components are the same as the components of the display device described in detail, and their detailed description will be omitted.

[0228] Reference Figures 1a to 9 A display device according to an embodiment of the present disclosure may include a display panel DP, the display panel DP including a first substrate SUB1 and a second substrate SUB2 connected to the first substrate SUB1, and at least one pixel PXL (hereinafter, referred to as 'pixel') including a first subpixel SP1, a second subpixel SP2 and a third subpixel SP3 is arranged on the first substrate SUB1.

[0229] In an embodiment of the present disclosure, the pixel PXL is formed and / or arranged in a pixel area PXA defined on the first substrate SUB1. The pixel area PXA may include a first sub-pixel area SPA1 in which the first sub-pixel SP1 is formed and / or arranged, a second sub-pixel area SPA2 in which the second sub-pixel SP2 is formed and / or arranged, and a third sub-pixel area SPA3 in which the third sub-pixel SP3 is formed and / or arranged.

[0230] In an embodiment of the present disclosure, the first substrate SUB1 may include a base layer BSL and a pixel circuit layer PCL disposed on the base layer BSL. The display element layer DPL may be disposed on the first substrate SUB1.

[0231] The display element layer DPL may include a partition wall PW, a first electrode REL1 and a second electrode REL2, a plurality of light emitting elements LD, and a first contact electrode CNE1 and a second contact electrode CNE2 disposed on the pixel circuit layer PCL of the emission area EMA of each of the first subpixel SP1 to the third subpixel SP3. In addition, the display element layer DPL may include a dam BNK disposed in the non-emission area PPA of each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0232] In an embodiment of the present disclosure, the partition wall PW and the bank BNK may be disposed on the same surface and formed by the same process. In an embodiment of the present disclosure, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same surface and formed by the same process.

[0233] Each of the light emitting elements LD may include opposite ends EP1 and EP2 in the longitudinal direction.

[0234] The second substrate SUB2 may be disposed on the first substrate SUB1 to cover the display area DA in which the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are disposed. The second substrate SUB2 may form an upper substrate (e.g., an encapsulation substrate or a thin film encapsulation layer) and / or a window assembly of the display panel DP. In an embodiment, the second substrate SUB2 may be a rigid substrate or a flexible substrate, and its material or properties are not specifically limited. In addition, the second substrate SUB2 may be formed of the same material as that of the first substrate SUB1, or may be formed of a material different from that of the first substrate SUB1.

[0235] In addition, the display panel DP may include a light conversion pattern layer LCP disposed on one surface of the second substrate SUB2 to face the first substrate SUB1 , the second sub-pixel SP2 , and the third sub-pixel SP3 .

[0236] In an embodiment, the light conversion pattern layer LCP may include a first light conversion pattern layer LCP1 disposed to face the first sub-pixel SP1, a second light conversion pattern layer LCP2 disposed to face the second sub-pixel SP2, and a third light conversion pattern layer LCP3 disposed to face the third sub-pixel SP3. In an embodiment, at least some of the first light conversion pattern layer LCP1, the second light conversion pattern layer LCP2, and the third light conversion pattern layer LCP3 may include a color conversion layer CCL and / or a color filter CF.

[0237] For example, the first light conversion pattern layer LCP1 may include a first color conversion layer CCL1 and a first color filter CF1, the first color conversion layer CCL1 includes first color conversion particles corresponding to a first color, and the first color filter CF1 is configured to allow light of the first color to selectively pass therethrough. Similarly, the second light conversion pattern layer LCP2 may include a second color conversion layer CCL2 and a second color filter CF2, the second color conversion layer CCL2 includes second color conversion particles corresponding to a second color, and the second color filter CF2 is configured to allow light of the second color to selectively pass therethrough. The third light conversion pattern layer LCP3 may include at least one light scattering layer LSL and a third color filter CF3, the light scattering layer LSL includes light scattering particles SCT, and the third color filter CF3 is configured to allow light of a third color to selectively pass therethrough.

[0238] In an embodiment of the present disclosure, the light emitting elements LD aligned in the emission area EMA of each of the first sub-pixel SP1 to the third sub-pixel SP3 may emit light of the same color. The color conversion layer CCL may be disposed on at least some of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the first color conversion layer CCL1 and the second color conversion layer CCL2 may be disposed on the first sub-pixel SP1 and the second sub-pixel SP2, respectively. Therefore, the display device according to an embodiment of the present disclosure may display a full-color image.

[0239] In an embodiment, the first color conversion layer CCL1 may be disposed on one surface of the second substrate SUB2 to face the first sub-pixel SP1, and may include first color conversion particles that convert the color of light emitted from the light emitting element LD disposed in the corresponding sub-pixel into a first color. For example, in the case where the first sub-pixel SP1 is a red sub-pixel, the first color conversion layer CCL1 may include red quantum dots QDr that convert blue light emitted from the light emitting element LD disposed in the first sub-pixel SP1 into red light.

[0240] The first color filter CF1 may be disposed between the first color conversion layer CCL1 and the second substrate SUB2 and may include a color filter material that allows light of the first color converted by the first color conversion layer CCL1 to selectively pass therethrough. For example, the first color filter CF1 may be a red color filter.

[0241] In an embodiment, the second color conversion layer CCL2 may be disposed on one surface of the second substrate SUB2 to face the second sub-pixel SP2, and may include second color conversion particles that convert the color of light emitted from the light emitting element LD disposed in the corresponding sub-pixel into a second color. For example, in the case where the light emitting element LD disposed in the second sub-pixel SP2 is a blue light emitting element configured to emit blue light and the second sub-pixel SP2 is a green sub-pixel, the second color conversion layer CCL2 may include green quantum dots QDg that convert blue light emitted from the light emitting element LD disposed in the second sub-pixel SP2 into green light.

[0242] The second color filter CF2 may be disposed between the second color conversion layer CCL2 and the second substrate SUB2 and may include a color filter material that allows light of the second color converted by the second color conversion layer CCL2 to selectively pass therethrough. For example, the second color filter CF2 may be a green color filter.

[0243] The light scattering layer LSL may be disposed on one surface of the second substrate SUB2 to face the third sub-pixel SP3. For example, the light scattering layer LSL may be disposed between the third sub-pixel SP3 and the third color filter CF3.

[0244] The third color filter CF3 may be disposed on one surface of the second substrate SUB2 to face the third sub-pixel SP3 and may include a color filter material that allows the color light emitted from the light emitting element formed in the corresponding sub-pixel to selectively pass therethrough. For example, the third color filter CF3 may be a blue color filter.

[0245] In an embodiment, the black matrix BM may be disposed between the first color filter CF1, the second color filter CF2, and the third color filter CF3. For example, the black matrix BM may be disposed on the second substrate SUB2 to overlap the bank BNK on the first substrate SUB1.

[0246] As described above, in the embodiment of the present disclosure, each pixel PXL using the light emitting element LD for emitting the same color light and a display device including the same can be easily manufactured. Since the color conversion layer CCL is provided on at least some of the sub-pixels, a full-color pixel PXL and a display device including the same can be manufactured.

[0247] Furthermore, according to an embodiment of the present disclosure, some components of the display element layer DPL may be formed through the same process, so that the number of masks may be reduced, thereby simplifying the manufacturing process.

[0248] Fig.10 The display device according to the embodiment of the present disclosure is schematically shown. Figure 4 The cross-sectional view corresponding to the line II'.

[0249] In addition to the passivation layer, the partition wall and the bank being disposed on the same surface and comprising the same material, Fig.10 The display device can be constructed with Figure 5 The configurations of the display devices are substantially the same or similar.

[0250] Therefore, to avoid redundant explanation, Fig.10 The description of the display device will focus on the differences from the description of the previous embodiment. Components not separately described in the following description of this embodiment are consistent with the components of the previous embodiment. The same reference numerals will be used to identify the same components, and similar reference numerals will be used to identify similar components.

[0251] Reference Figure 1a , Figure 2 , Figure 3a , Figure 3b , Figure 3c , Figure 3d , Figure 4 and Fig.10 , the display device according to an embodiment of the present disclosure may include a base layer BSL on which a plurality of pixels PXL are disposed.

[0252] Each of the pixels PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 disposed on the base layer BSL.

[0253] The base layer BSL, the pixel circuit layer PCL, and the display element layer DPL may be disposed in an emission region of each of the first to third sub-pixels SP1 to SP3.

[0254] The pixel circuit layer PCL may include a light shielding pattern SDL, first and second transistors T1 and T2 , a driving voltage line DVL, and a passivation layer PSV disposed on the base layer BSL.

[0255] The display element layer DPL may include a partition wall PW, a bank BNK, first and second electrodes REL1 and REL2 , first and second connection lines CNL1 and CNL2 , a plurality of light emitting elements LD, and first and second contact electrodes CNE1 and CNE2 .

[0256] In an embodiment of the present disclosure, the passivation layer PSV of the pixel circuit layer PCL and the partition wall PW and the bank BNK of the display element layer DPL may be disposed on the same layer and include the same material. In other words, the passivation layer PSV, the partition wall PW and the bank BNK may be integrally disposed by the same process.

[0257] A passivation layer PSV, a partition wall PW, and a dam BNK may be formed and / or disposed in a target area in each sub-pixel by applying an organic insulating material layer (not shown) to a base layer BSL on which the first transistor T1 and the second transistor T2 are formed, and then patterning the organic insulating material layer using a half-tone mask (not shown), etc. For example, a passivation layer PSV may be formed and / or disposed on the first transistor T1 and the second transistor T2 in each sub-pixel. The partition wall PW may be formed and / or disposed in the emission area EMA of each sub-pixel. The dam BNK may be formed and / or disposed in the non-emission area PPA of each sub-pixel.

[0258] Figures 11a to 11g The manufacturing sequence is shown in Fig.10 A cross-sectional view of a method of displaying a device.

[0259] Reference Figure 1a , Figure 2 , Figure 3a , Figure 3b , Figure 3c , Figure 3d , Figure 4 , Fig.10 and Fig.11a The pixel circuit layer PCL may be disposed on the base layer BSL of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The pixel circuit layer PCL may include a light shielding pattern SDL, first and second transistors T1 and T2, and a driving voltage line DVL.

[0260] Thereafter, after an organic insulating material layer (not shown) is applied to the interlayer insulating layer ILD on which the driving voltage line DVL and the like are formed and / or provided, a mask process is performed using a half-tone mask (not shown) to pattern the organic insulating material layer. Through the aforementioned mask process, a partition wall PW is formed in the emission area EMA of each of the first to third sub-pixels SP1 to SP3, and at the same time, a dam BNK is formed in the non-emission area PPA of each of the first to third sub-pixels SP1 to SP3, and at the same time, a passivation layer PSV is formed on the driving voltage line DVL.

[0261] In addition, through the aforementioned mask process, the passivation layer PSV may include a first contact hole CH1 exposing a portion of the drain electrode DE of the first transistor T1 of the pixel circuit layer PCL and a second contact hole CH2 exposing a portion of the driving voltage line DVL.

[0262] In an embodiment of the present disclosure, the passivation layer PSV, the partition wall PW and the bank BNK may be integrally provided by the same process. In the case where the passivation layer PSV, the partition wall PW and the bank BNK are integrally formed and / or provided, the partition wall PW and the bank BNK may be considered as one region of the passivation layer PSV.

[0263] Reference Figure 1a , Figure 2 , Figure 3a , Figure 3b , Figure 3c , Figure 3d , Figure 4 , Fig.10 , Fig.11a and Fig.11b , the first electrode REL1, the second electrode REL2, and the first connection line CNL1 and the second connection line CNL2 are formed on the partition wall PW.

[0264] The first connection line CNL1 may be electrically connected to the first transistor T1 of the pixel circuit layer PCL through the first contact hole CH1 of the passivation layer PSV. The second connection line CNL2 may be electrically connected to the driving voltage line DVL through the second contact hole CH2 of the passivation layer PSV.

[0265] Reference Figure 1a , Figure 2 , Figure 3a , Figure 3b , Figure 3c , Figure 3d , Figure 4 , Fig.10 as well as Figures 11a to 11c A first insulating layer INS1 is formed on the pixel circuit layer PCL on which the first electrode REL1 and the second electrode REL2 are formed.

[0266] Reference Figure 1a , Figure 2 , Figure 3a , Figure 3b , Figure 3c , Figure 3d , Figure 4 , Fig.10 as well as Figures 11a to 11d , an electric field is formed between the first electrode REL1 and the second electrode REL2 by applying corresponding alignment voltages to the first electrode REL1 and the second electrode REL2 of each sub-pixel through the first connection line CNL1 and the second connection line CNL2 .

[0267] If the light emitting element LD is supplied to the passivation layer PSV, the self-alignment of the light emitting element LD can be caused by the electric field formed between the first electrode REL1 and the second electrode REL2. Therefore, the light emitting element LD can be aligned between the first electrode REL1 and the second electrode REL2. In other words, the light emitting element LD can be densely aligned in the target area (e.g., the emission area EMA of each sub-pixel).

[0268] Reference Figure 1a , Figure 2 , Figure 3a , Figure 3b , Figure 3c , Figure 3d , Figure 4 , Fig.10 as well as Figures 11a to 11e After the alignment of the light emitting elements LD, a second insulating layer INS2 is formed on a portion of the upper surface of each of the light emitting elements LD. In an embodiment of the present disclosure, the second insulating layer INS2 may be an organic insulating layer including an organic material.

[0269] Reference Figure 1a , Figure 2 , Figure 3a , Figure 3b , Figure 3c , Figure 3d , Figure 4 , Fig.10 as well as Figures 11a to 11f The first and second contact electrodes CNE1 and CNE2 are formed on the pixel circuit layer PCL having the second insulating layer INS2 formed thereon. The first and second contact electrodes CNE1 and CNE2 may be spaced apart from each other by a predetermined distance on the second insulating layer INS2 and thus electrically and / or physically separated from each other.

[0270] A portion of the first connection line CNL1 commonly connected to the sub-pixels and / or commonly set for the sub-pixels can be removed by the aforementioned mask process, so that each sub-pixel can be driven independently of the adjacent sub-pixels. Therefore, each sub-pixel can be driven separately, and the display device according to the embodiment of the present disclosure can be implemented as an active matrix display device.

[0271] In an embodiment, when the light emitting element LD is aligned in the emission area EMA of each of the first subpixel SP1 to the third subpixel SP3, some components included in the pixel circuit layer PCL can be used to align the light emitting element LD between the first electrode REL1 and the second electrode REL2, instead of applying an alignment voltage to the first connecting line CNL1 and the second connecting line CNL2 to align the light emitting element LD between the first electrode REL1 and the second electrode REL2.

[0272] For example, Figure 3d As shown in, in the case where the first electrode REL1 (e.g., anode electrode) is connected to the third transistor T3 in the first sub-pixel SP1 and the second electrode REL2 (e.g., cathode electrode) is connected to the second driving power source VSS, the third transistor T3 can be turned on by the control line CLi, so that the alignment voltage can be transmitted to the first electrode REL1 through the j-th data line Dj. Here, since the voltage of the second driving power source VSS is applied to the second electrode REL2, a predetermined electric field can be formed between the first electrode REL1 and the second electrode REL2. In the case where a solution including a light-emitting element LD is dropped onto the first sub-pixel SP1, the light-emitting element LD can be aligned in the emission area EMA of the first sub-pixel SP1 by the electric field formed between the first electrode REL1 and the second electrode REL2.

[0273] In this way, some components of the pixel circuit layer PCL can be used to perform alignment of the light emitting element LD in the emission area EMA of the corresponding sub-pixel, so that the corresponding sub-pixel can be driven individually. Therefore, the process of forming an alignment line for aligning the light emitting element LD in the emission area EMA of each sub-pixel and the process of removing the alignment line for being able to drive each sub-pixel individually can be omitted.

[0274] Therefore, since a process of forming an alignment line for aligning the light emitting element LD in the emission area EMA of each sub-pixel and a process of removing the alignment line can be omitted, the number of mask processes in the display device according to the embodiment of the present disclosure can be further reduced.

[0275] Reference Figure 1a , Figure 2 , Figure 3a , Figure 3b , Figure 3c , Figure 3d , Figure 4 , Fig.10 as well as Figures 11a to 11g A third insulating layer INS3 is formed on the first contact electrode CNE1 and the second contact electrode CNE2.

[0276] In the display device manufactured by the above manufacturing process, during the process of manufacturing the passivation layer PSV, the partition wall PW is formed in the emission area EMA of each sub-pixel, and at the same time, the bank BNK is formed in the non-emission area PPA of each sub-pixel. Therefore, the number of mask processes can be reduced.

[0277] Fig.12 A display device according to an embodiment of the present disclosure is shown, and a substrate is bonded to Fig.10 A schematic cross-sectional view of the structure of a display device.

[0278] For the purpose of illustration, Fig.12 A pixel region of one pixel among a plurality of pixels included in a display device is schematically shown.

[0279] In addition, for convenience, Fig.12 , schematically shown with reference to Fig.10 The structures of some components are the same as the components of the display device described in detail, and their detailed description will be omitted.

[0280] Reference Figure 1a , Figure 2 , Fig.10 and Fig.12 A display device according to an embodiment of the present disclosure may include a display panel DP, the display panel DP including a first substrate SUB1 on which at least one pixel PXL (hereinafter, referred to as 'pixel') including a first subpixel SP1, a second subpixel SP2 and a third subpixel SP3 is arranged, and a second substrate SUB2 connected to the first substrate SUB1.

[0281] In an embodiment of the present disclosure, the pixel PXL is formed and / or arranged in a pixel area PXA defined on the first substrate SUB1. The pixel area PXA may include a first sub-pixel area SPA1 in which the first sub-pixel SP1 is formed and / or arranged, a second sub-pixel area SPA2 in which the second sub-pixel SP2 is formed and / or arranged, and a third sub-pixel area SPA3 in which the third sub-pixel SP3 is formed and / or arranged.

[0282] In an embodiment of the present disclosure, the first substrate SUB1 may include a base layer BSL and a pixel circuit layer PCL disposed on the base layer BSL. The display element layer DPL may be disposed on the first substrate SUB1.

[0283] The display element layer DPL may include a partition wall PW, a first electrode REL1 and a second electrode REL2, a plurality of light emitting elements LD, and a first contact electrode CNE1 and a second contact electrode CNE2 disposed on the pixel circuit layer PCL of the emission area EMA of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. In addition, the display element layer DPL may include a dam BNK disposed in the non-emission area PPA of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0284] In an embodiment of the present disclosure, the partition wall PW and the bank BNK may be disposed on the same surface and formed by the same process. In an embodiment of the present disclosure, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same surface and formed by the same process.

[0285] Each of the light emitting elements LD may include opposite ends EP1 and EP2 in the longitudinal direction. The light emitting elements LD may include a first light emitting element LD1 disposed in the first subpixel SP1, a second light emitting element LD2 disposed in the second subpixel SP2, and a third light emitting element LD3 disposed in the third subpixel SP3.

[0286] In the embodiment of the present disclosure, the first light emitting element LD1 to the third light emitting element LD3 may emit light of different colors. For example, the first light emitting element LD1 may emit red light R, the second light emitting element LD2 may emit green light G, and the third light emitting element LD3 may emit blue light B. Therefore, red light R may be emitted from the first sub-pixel SP1, green light G may be emitted from the second sub-pixel SP2, and blue light B may be emitted from the third sub-pixel SP3.

[0287] In this case, the light conversion pattern layer (refer to FIG. 1 ) configured to convert the light of the color emitted from the display element layer DPL into light of a specific color may be omitted. Fig. 9 of LCP).

[0288] The second substrate SUB2 may be disposed on the first substrate SUB1 to cover the display area DA in which the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are disposed. The second substrate SUB2 may form an upper substrate (e.g., an encapsulation substrate or a thin film encapsulation layer) and / or a window assembly of the display panel DP. In an embodiment, the second substrate SUB2 may be a rigid substrate or a flexible substrate, and its material or properties are not specifically limited. In addition, the second substrate SUB2 may be formed of the same material as that of the first substrate SUB1, or may be formed of a material different from that of the first substrate SUB1.

[0289] In the case where the light conversion pattern layer LCP is omitted, the second substrate SUB2 may be connected to the first substrate SUB1 through the intermediate layer CTL.

[0290] The intermediate layer CTL may be disposed between the first substrate SUB1 and the second substrate SUB2. The intermediate layer CTL may protect the display element layer DPL between the first substrate SUB1 and the second substrate SUB2, and may play a role in bonding the first substrate SUB1 to the second substrate SUB2. The intermediate layer CTL may have viscosity or adhesiveness to perform a bonding function. In addition, the intermediate layer CTL may be made of a transparent material to allow an image to be transmitted to the second substrate SUB2. In addition, the intermediate layer CTL may be formed of an insulating material and have flexibility.

[0291] The material type of the intermediate layer CTL is not limited as long as the intermediate layer CTL is made of a material that can protect the display element layer DPL on the first substrate SUB1 and play a role in bonding the first substrate SUB1 to the second substrate SUB2. For example, the intermediate layer CTL may be formed of an organic material.

[0292] Although various embodiments have been described above, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure.

[0293] Therefore, the embodiments disclosed in this specification are only for illustrative purposes and do not limit the technical spirit of the present disclosure. The scope of the present disclosure must be defined by the appended claims.

Claims

1. A display device, comprising: A substrate layer including a display area and a non-display area; as well as A plurality of pixels are arranged in the display area, each of the plurality of pixels includes a plurality of sub-pixels, Each of the plurality of sub-pixels includes a pixel circuit layer and a display element layer, and the display element layer includes an emission region for emitting light and a non-emission region arranged around the periphery of the emission region. Wherein, the display element layer comprises: A wall disposed in the emission region of each sub-pixel; A bank disposed in the non-emitting region of each sub-pixel, the bank and the wall being on the same surface; A first electrode and a second electrode are disposed on the wall and are spaced apart from each other; and at least one light-emitting element that emits the light, the light-emitting element being disposed between the first electrode and the second electrode in the emission region of each sub-pixel, wherein the wall and the bank comprise the same material and are integral with each other, wherein the bank has a first height and the wall has a second height that is less than the first height, wherein the embankment includes an embankment portion extending in a first direction, wherein the wall includes a wall portion extending in a second direction different from the first direction, and Therein, the bank portion and the wall portion are directly adjacent to each other.

2. The display device according to claim 1, in, The light emitting element includes a first end and a second end opposite to the first end, and Wherein, the display element layer further includes: a first contact electrode electrically connecting the first electrode to one of the first end and the second end of the light emitting element; and The second contact electrode electrically connects the second electrode to the remaining one of the first end and the second end of the light emitting element.

3. The display device according to claim 2, wherein: The display element layer further comprises: A first insulating layer, disposed between the light emitting element and the pixel circuit layer; and The second insulating layer is disposed on a portion of the upper surface of the light emitting element.

4. The display device according to claim 3, wherein: The first contact electrode and the second contact electrode are disposed on the same layer, and are spaced apart from and electrically insulated from each other on the second insulating layer.

5. The display device according to claim 4, wherein: The pixel circuit layer comprises: at least one transistor disposed on the base layer; and A passivation layer is disposed on the transistor.

6. The display device according to claim 5, wherein: The passivation layer is on the same surface as the walls and the banks.

7. The display device according to claim 6, wherein: The passivation layer is integral with the walls and the banks and includes the same material as that of the walls and the banks.

8. The display device according to claim 7, further comprising: The conductive pattern is arranged between the base layer and the transistor.

9. The display device according to claim 8, wherein: The conductive pattern includes a light shielding pattern that blocks light from entering a rear surface of the base layer.

10. The display device according to claim 5, further comprising: A color conversion layer, disposed on the display element layer, the color conversion layer comprising color conversion particles for converting the light into light having a set color; as well as A substrate is disposed on the color conversion layer.

11. The display device according to claim 5, further comprising: A substrate, disposed on the display element layer; as well as The intermediate layer is arranged between the display element layer and the substrate.

12. The display device according to claim 11, wherein: The intermediate layer includes an adhesive material for bonding the display element layer to the substrate.

13. The display device according to claim 1, wherein: The first electrode and the second electrode are electrically separated from each other, and one of the first electrode and the second electrode surrounds the remaining one of the first electrode and the second electrode.

14. The display device according to claim 1, wherein: The light emitting element comprises: an ultra-small light emitting diode in the shape of a cylinder or a polygonal column, and the ultra-small light emitting diode is in the size of micrometer level or nanometer level.

15. A method for manufacturing a display device, the method comprising: providing a base layer having a pixel circuit layer formed thereon with a plurality of sub-pixels, each of the plurality of sub-pixels including an emission region and a non-emission region; as well as forming a display element layer on the pixel circuit layer for emitting light from the emission region of each sub-pixel, Wherein, forming the display element layer comprises: forming a wall in the emission region of each sub-pixel and, at the same time, forming a bank in the non-emission region of each sub-pixel; forming a first electrode and a second electrode spaced apart from each other on the wall; forming a first insulating layer exposing a portion of an upper surface of an electrode corresponding to each of the first electrode and the second electrode; Aligning a plurality of light emitting elements between the first electrode and the second electrode by applying corresponding alignment voltages to the first electrode and the second electrode respectively; forming a second insulating layer exposing opposite ends of each of the plurality of light emitting elements on the plurality of light emitting elements; and forming a first contact electrode and a second contact electrode on the second insulating layer, wherein the wall and the bank comprise the same material and are integral with each other, wherein the bank has a first height and the wall has a second height that is less than the first height, wherein the embankment includes an embankment portion extending in a first direction, wherein the wall includes a wall portion extending in a second direction different from the first direction, and Therein, the bank portion and the wall portion are directly adjacent to each other.

16. The method according to claim 15, wherein: The first contact electrode and the second contact electrode are disposed on the same layer, spaced apart from each other and electrically insulated from each other on the second insulating layer.

17. The method according to claim 15, wherein: Forming the pixel circuit layer includes: forming at least one transistor on the base layer; and A passivation layer is formed on the transistor.

18. The method according to claim 17, wherein: The passivation layer is integral with the walls and the banks, and the passivation layer, the walls and the banks include the same material.

19. The method according to claim 18, wherein: The first electrode and the second electrode are electrically separated from each other, and one of the first electrode and the second electrode surrounds the remaining one of the first electrode and the second electrode.

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