Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a semiconductor fin, a plurality of semiconductor nanostructures, a gate structure, a dielectric fin, a dielectric structure, and a dielectric layer. The semiconductor fin is vertically protruding from a semiconductor substrate. The plurality of semiconductor nanostructures is directly on the semiconductor fin. The gate is on the semiconductor fin and surrounds the semiconductor nanostructures. The dielectric fin is on the substrate. The dielectric structure is on the dielectric fin. An upper surface of the dielectric structure is higher than an upper surface of the gate. The dielectric layer is on the substrate. The dielectric fin laterally separates the gate from the dielectric layer and laterally separates the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is higher than an upper surface of the gate structure and an upper surface of the dielectric structure. A lower surface of the dielectric layer is lower than an upper surface of the dielectric fin.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for forming a semiconductor device with reduced space between nanostructured field-effect transistors. Background Technology

[0002] The integrated circuit manufacturing industry has experienced exponential growth over the past few decades. With the development of integrated circuits, the minimum structural size can be continuously reduced to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, or the like), allowing more electronic components to be integrated into a given area. Minimizing process size offers many advantages, such as increased throughput, reduced manufacturing costs, increased device performance, or similar benefits. One of the advancements in miniaturizing semiconductor devices in the integrated circuit industry is the multi-gate field-effect transistor (MOSFET). Some examples of multi-gate MOSFETs include dual-gate MOSFETs, tri-gate MOSFETs, Ω-gate MOSFETs, or fully wound gate MOSFETs. Summary of the Invention

[0003] The object of the present invention is to provide a semiconductor device to solve at least one of the above-mentioned problems.

[0004] Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a semiconductor fin that protrudes vertically from a semiconductor substrate. A plurality of semiconductor nanostructures are directly located on the semiconductor fin and vertically stacked. A gate structure is located on the semiconductor fin and surrounds the semiconductor nanostructures. A dielectric fin is located on the semiconductor substrate, wherein the gate structure and the semiconductor nanostructures are located on a first side of the dielectric fin, and wherein the upper surface of the dielectric fin is lower than the upper surface of the gate structure. A dielectric structure is directly located on the dielectric fin, wherein the first upper surface of the dielectric structure is higher than the upper surface of the gate structure. A dielectric layer is at least partially located on the semiconductor substrate, wherein the dielectric layer is located on a second side of the dielectric fin, and the first and second sides of the dielectric fin are opposite each other, wherein the upper surface of the dielectric layer is higher than the upper surface of the gate structure and the first upper surface of the dielectric structure, and wherein the lower surface of the dielectric layer is lower than the upper surface of the dielectric fin.

[0005] Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a first semiconductor fin and a second semiconductor fin, protruding perpendicularly from a semiconductor substrate, wherein the second semiconductor fin and the first semiconductor fin are laterally separated in a first direction, wherein the first semiconductor fin and the second semiconductor fin extend laterally in a second direction and are parallel to each other, and wherein the second direction is substantially perpendicular to the first direction. A first gate structure is located on the first semiconductor fin. A second gate structure is located on the second semiconductor fin and is laterally separated from the first gate structure in the first direction. A first dielectric fin is located on the semiconductor substrate, wherein the first dielectric fin is located between the first semiconductor fin and the second semiconductor fin, and between the first gate structure and the second gate structure. A second dielectric fin is located on the semiconductor substrate and is laterally separated from the first dielectric fin in the first direction, wherein the second dielectric fin is located between the first semiconductor fin and the second semiconductor fin, and between the first gate structure and the second gate structure. A first dielectric structure is located on the first dielectric fin. A second dielectric structure is located on the second dielectric fin and is laterally separated from the first semiconductor fin in a first direction. A dielectric layer is at least partially located on the semiconductor substrate, wherein the first dielectric structure laterally separates the dielectric layer from a first portion of the first gate structure, and the second dielectric structure laterally separates the dielectric layer from a first portion of the second gate structure.

[0006] Some embodiments of the present invention provide a method for forming a semiconductor device. The method includes receiving a workpiece. The workpiece includes a first dielectric fin located on a semiconductor substrate and laterally positioned between a first plurality of semiconductor nanostructures and a second plurality of semiconductor nanostructures; a second dielectric fin located on the semiconductor substrate and laterally positioned between a third plurality of semiconductor nanostructures and a second plurality of semiconductor nanostructures; a first conductive gate structure located on the semiconductor substrate and surrounding the first plurality of semiconductor nanostructures; a second conductive gate structure located on the semiconductor substrate and surrounding the second plurality of semiconductor nanostructures; a third conductive gate structure located on the semiconductor substrate and surrounding the third plurality of semiconductor nanostructures, wherein the second conductive gate structure is located between the first conductive gate structure and the third conductive gate structure and is laterally separated from the first conductive gate structure and the third conductive gate structure; a first dielectric structure directly located on the first dielectric fin, wherein the first dielectric structure and the first dielectric fin laterally separate the first conductive gate structure and the second conductive gate structure; and a second dielectric structure directly located on the second dielectric fin, wherein the second dielectric structure and the second dielectric fin laterally separate the third conductive gate structure and the second conductive gate structure. A first dielectric layer is formed on a first dielectric fin, a second dielectric fin, a first plurality of semiconductor nanostructures, a second plurality of semiconductor nanostructures, a third plurality of semiconductor nanostructures, a first dielectric structure, a second dielectric structure, a first conductive gate structure, a second conductive gate structure, and a third conductive gate structure. A first opening is formed in the first dielectric layer, wherein the first opening at least partially overlaps with the first dielectric structure, the second dielectric structure, and the second conductive gate structure. The second conductive gate structure is removed. A portion of the first dielectric structure under the first opening is removed to form a third dielectric structure directly located on the first dielectric fin. A portion of the second dielectric structure under the first opening is removed to form a fourth dielectric structure directly located on the second dielectric fin. The second plurality of semiconductor nanostructures are removed to form a second opening under the first opening. A second dielectric layer is formed in the first and second openings, and at least partially covers the third and fourth dielectric structures. Attached Figure Description

[0007] Figures 1 to 19 These are various figures illustrating methods used in some embodiments to form semiconductor devices with reduced space between nanostructured field-effect transistors.

[0008] Figures 20A to 20C These are various figures illustrating semiconductor devices with reduced space between nanostructured field-effect transistors in some embodiments.

[0009] Figure 21 In some embodiments, Figures 20A to 20C semiconductor devices along Figure 20A The sectional view of section line BB.

[0010] Figure 22 These are perspective views of a semiconductor device in some embodiments.

[0011] Figure 23 This is a flowchart of a method used in some embodiments to form a semiconductor device with reduced space between nanostructured field-effect transistors.

[0012] The attached figures are labeled as follows:

[0013] AA, BB: Section lines

[0014] D1: First Distance

[0015] D2: Second distance

[0016] H1: First Height

[0017] H2: Second Altitude

[0018] H3: Third Height

[0019] H4: Fourth Height

[0020] H5: Fifth Height

[0021] H6: Sixth Height

[0022] W1: First width

[0023] W2: Second width

[0024] 102: Substrate semiconductor structure

[0025] 104: Stacking of semiconductor layers

[0026] 106: First semiconductor layer

[0027] 108: Second semiconductor layer

[0028] 110: Hard mask layer

[0029] 202: First hard mask structure

[0030] 204: The first stack of semiconductor structures

[0031] 206: First Semiconductor Structure

[0032] 208: Second Semiconductor Structure

[0033] 210: Fins

[0034] 210a: First fin

[0035] 210b: Second fin

[0036] 210c: Third fin

[0037] 210d: Fourth fin

[0038] 210e: Fifth fin

[0039] 210f: Sixth fin

[0040] 212:Substrate

[0041] 214: First trench

[0042] 302: Lining layer

[0043] 304: First dielectric layer

[0044] 402: Isolation Structure

[0045] 404: Cover Structure

[0046] 406: Second trench

[0047] 502: Dielectric fins

[0048] 502a: First dielectric fin

[0049] 502b: Second dielectric fin

[0050] 502c: Third dielectric fin

[0051] 502d: Fourth dielectric fin

[0052] 502e: Fifth dielectric fin

[0053] 504: Dielectric band

[0054] 602: Dummy Gate Structure

[0055] 604: Dummy gate dielectric structure

[0056] 606: Dummy Gate Material Structure

[0057] 608: Second hard mask structure

[0058] 610: Third hard mask structure

[0059] 612: Fourth Hard Mask Structure

[0060] 702: First sidewall spacer

[0061] 704: First Multiple Dielectric Structures

[0062] 704a: First dielectric structure

[0063] 704b: Second dielectric structure

[0064] 704b / 704d: Retained dielectric structure

[0065] 704c: Third dielectric structure

[0066] 704d: Fourth dielectric structure

[0067] 704e: Fifth dielectric structure

[0068] 705: The second stack of semiconductor structures

[0069] 706: Third Semiconductor Structure

[0070] 708: Fourth Semiconductor Structure

[0071] 802: Second sidewall spacer

[0072] 902: First source / drain region

[0073] 902a: The first pair

[0074] 902b: The second pair

[0075] 902c: The fifth pair

[0076] 902d: The sixth pair

[0077] 904: Second source / drain region

[0078] 904a: The third pair

[0079] 904b: The fourth pair

[0080] 1002: First etch stop layer

[0081] 1004: Interlayer dielectric layer

[0082] 1102: Third trench

[0083] 1104: First mask structure

[0084] 1106: Fifth Hard Mask Structure

[0085] 1302: Nanostructure Stacking

[0086] 1302a: First Nanostructure Stack

[0087] 1302b: Second nanostructure stacking

[0088] 1302c: Third nanostructure stacking

[0089] 1302d: Fourth nanostructure stack

[0090] 1302e: Fifth nanostructure stack

[0091] 1302f: Sixth nanostructure stack

[0092] 1304: Nanostructure

[0093] 1402: Interface Layer

[0094] 1404: Gate dielectric layer

[0095] 1406: Gate layer

[0096] 1502: Gate Structure

[0097] 1502a: First gate structure

[0098] 1502b: Second gate structure

[0099] 1502c: Third gate structure

[0100] 1504: Second etch stop layer

[0101] 1506: Fourth dielectric layer

[0102] 1602: First Opening

[0103] 1604: Second mask structure

[0104] 1801: Second Opening

[0105] 1802: Recessed dielectric fins

[0106] 1804a: First recessed semiconductor fin

[0107] 1804b: Semiconductor fin with a second depression

[0108] 1806: Second Multiple Dielectric Structures

[0109] 1806a: Sixth Dielectric Structure

[0110] 1806b: Seventh Dielectric Structure

[0111] 1808: Gate Dielectric Structure

[0112] 1808a: First gate dielectric structure

[0113] 1808b: Second gate dielectric structure

[0114] 1810: Nanostructured Field-Effect Transistor

[0115] 1810a: First nanostructure field-effect transistor

[0116] 1810b: Second nanometer structure field-effect transistor

[0117] 1902: Fifth dielectric layer

[0118] 1904: Semiconductor Device

[0119] 2002: First inner sidewall

[0120] 2004: Second inner sidewall

[0121] 2102: Vertical section

[0122] 2102a: First vertical section

[0123] 2102b: Second vertical section

[0124] 2104: Horizontal section

[0125] 2104a: First horizontal section

[0126] 2104b: Second horizontal section

[0127] 2106: Region

[0128] 2202: First Surrounding Area

[0129] 2204: Second Peripheral Section

[0130] 2208: First upper surface

[0131] 2210: Second upper surface

[0132] 2300: Flowchart

[0133] 2302, 2304, 2306, 2308, 2310, 2312, 2314, 2316: Steps Detailed Implementation

[0134] The following description, with reference to the accompanying drawings, illustrates embodiments of the present invention. Similar reference numerals are used to identify similar units, and the structures shown in the drawings need not be drawn to scale. It should be understood that the detailed description and corresponding drawings are not limited to the scope of the embodiments of the present invention, and the detailed description and drawings only provide some examples illustrating some ways of implementing the concepts of the present invention.

[0135] The different embodiments or examples provided below can implement different structures of the present invention. The embodiments of specific components and configurations are used to simplify the content of the present invention and are not intended to limit the invention. For example, a description of forming a first component on a second component includes embodiments where the two are in direct contact, or embodiments where the two are spaced apart by other additional components rather than in direct contact. Furthermore, multiple embodiments of the present invention may use the same reference numerals repeatedly for brevity, but elements with the same reference numerals in various embodiments and / or configurations do not necessarily have the same correspondence.

[0136] Furthermore, spatial relative terms such as "below," "under," "lower," "above," "above," or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustration. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the illustration. Elements can also be rotated 90° or other angles, so directional terms are only used to describe the direction shown in the illustration.

[0137] In some embodiments, a semiconductor device (such as an integrated circuit) may include a first nanostructure field-effect transistor (such as a fully wound field-effect transistor) and a second nanostructure field-effect transistor laterally separated from the first nanostructure field-effect transistor. The first nanostructure field-effect transistor includes a first metal gate extending around a first plurality of nanostructures, laterally extending between a pair of first source / drain regions. The second nanostructure field-effect transistor includes a second metal gate extending around a second plurality of nanostructures, laterally extending between a pair of second source / drain regions.

[0138] Generally, the method for forming the aforementioned semiconductor device includes forming a metal layer that continuously extends over a first plurality of nanostructures and a second plurality of nanostructures. The metal layer is then selectively etched to form separate metal gates, thereby forming a first metal gate and a second metal gate. The selective etching step removes a portion of the metal layer between the first and second metal gates, thereby forming an opening laterally located between the first and second metal gates. A dielectric layer is then deposited in the opening. The dielectric layer is configured to improve the device performance of the semiconductor device (e.g., reduce leakage current between the first and second nanostructure field-effect transistors) and / or reduce fabrication costs (e.g., by subsequently employing a self-aligned contact process).

[0139] One challenge of the aforementioned method is that as the minimum structure size continues to shrink (e.g., 3nm technology node or smaller), it cannot provide sufficient control to reliably form separate metal gates. For example, as the space between the first and second nanostructure field-effect transistors shrinks (e.g., the lateral space between the first and second nanostructures is reduced to less than 40nm), the method is insufficient to ensure selective etching of portions of the metal layer, removing only predefined portions. Poor stacking control of multiple patterning processes can cause the selective etching step to unintentionally remove portions of the metal layer that are not predefined. In other words, the method may unintentionally remove other portions of the metal layer. Because the method unintentionally removes portions of the metal layer, as the minimum structure size continues to shrink, it can cause electrical short circuits (e.g., between the first and second metal gates), adversely affect device performance (due to the unintentional reduction in the size of the first and second metal gates), or similar problems, thus reducing throughput.

[0140] This invention relates to various embodiments of a method for forming a semiconductor device (such as an integrated circuit) with reduced space between nanostructured field-effect transistors. The method includes forming a first dielectric structure on a first dielectric fin and forming a second dielectric structure on a second dielectric fin. The first dielectric structure and the first dielectric fin laterally separate a first conductive structure and a second conductive structure. The second dielectric structure and the second dielectric fin laterally separate a second conductive structure and a third conductive structure. The first conductive structure extends around a first plurality of semiconductor nanostructures, the second conductive structure extends around a second plurality of semiconductor nanostructures, and the third conductive structure extends around a third plurality of semiconductor nanostructures. The second conductive structure is located between the first conductive structure and the third conductive structure and is laterally separated from them.

[0141] A first dielectric layer is formed on a first dielectric fin, a second dielectric fin, a first plurality of semiconductor nanostructures, a second plurality of semiconductor nanostructures, a third plurality of semiconductor nanostructures, a first dielectric structure, a second dielectric structure, a first conductive structure, a second conductive structure, and a third conductive structure. The first dielectric layer is then selectively etched to form a first opening in the first dielectric layer, which at least partially covers the second conductive structure, the first dielectric structure, and the second dielectric structure. A first etching process is then performed through the first opening to remove the second conductive structure. A second etching process is then performed through the first opening to remove the second plurality of semiconductor nanostructures, forming a second opening below the first opening. Furthermore, the second etching process removes a portion of the first dielectric structure to form a third dielectric structure on the first dielectric fin, and removes a portion of the second dielectric structure to form a fourth dielectric structure on the second dielectric fin. A second dielectric layer is then formed in the first and second openings, partially covering the third and fourth dielectric structures. Since the first dielectric structure is formed on the first dielectric fin and the second dielectric structure is formed on the second dielectric fin, the allowable range of the etching process for forming the first opening can be increased. For example, the first and second dielectric structures may form a first opening with a larger width (due to resolution limitations in photolithography) and / or the first opening may be laterally offset from a predefined position (due to poor overlay control), but it is still ensured that the first opening only covers the required structure (such as the second conductive structure).

[0142] Furthermore, when removing the second conductive structure, the first and second dielectric structures can act as barriers, allowing the first etching process to selectively remove the second conductive structure. For example, since the first dielectric structure laterally separates the first and second conductive structures, and the second dielectric structure laterally separates the second and third conductive structures, the first and second dielectric structures act as barriers to prevent the first etching process from unintentionally removing portions of the first and / or second conductive structures.

[0143] Furthermore, since the second etching process removes a portion of the first dielectric structure (e.g., forming the third dielectric structure) and a portion of the second dielectric structure (e.g., forming the fourth dielectric structure), the second dielectric layer can be formed in a self-aligned manner. For example, after the second etching process, the third dielectric structure can be located on the third fin, and the fourth dielectric structure can be located on the fourth fin. Therefore, when forming the second dielectric layer, the second dielectric layer can be self-aligned with the sidewalls of the third and fourth dielectric structures. In summary, as the structure size continues to shrink, the method can form semiconductor devices with reduced space between nanostructure field-effect transistors (the lateral space between the first plurality of nanostructures and the third plurality of nanostructures is less than 40 nm), thereby increasing throughput, improving device performance, and avoiding electrical short circuits, etc.

[0144] Figures 1 to 19 These are various figures illustrating a method for forming a semiconductor device 1904 with reduced space between nanostructured field-effect transistors 1810 in some embodiments. Figures 1 to 11 The series of perspective views shown represent multiple stages of a method for forming a semiconductor device 1904 with reduced space between nanostructured field-effect transistors 1810. Figures 12 to 19 The series of cross-sectional views shown represent multiple stages of the method for forming a semiconductor device 1904 with reduced space between nanostructured field-effect transistors 1810. Figures 12 to 19 The sectional view along Figure 11 Section AA, and continue Figure 11 The stages shown. For example, Figure 12 show Figure 11 The first stage following the stage shown, and along Figure 11 Section AA. Figure 13 show Figure 12 The second stage following the first stage, and along Figure 11 Section AA. Figure 14 show Figure 13 The third stage following the second stage, and along Figure 11 Section AA, and so on.

[0145] like Figure 1 As shown, a substrate semiconductor structure 102 is provided. The substrate semiconductor structure 102 includes any type of semiconductor substrate (such as single-crystal silicon, complementary metal-oxide-semiconductor substrate, silicon-germanium, silicon-on-insulator, or the like), which may be doped (e.g., doped with n-type or p-type dopant) or undoped. The substrate semiconductor structure 102 may be a semiconductor wafer (such as a dished silicon wafer) or a part of a semiconductor wafer.

[0146] like Figure 1 As shown, a semiconductor layer stack 104 is formed on a substrate semiconductor structure 102. The semiconductor layer stack 104 includes staggered first semiconductor layers 106 and second semiconductor layers 108. The semiconductor layer stack 104 may contain any number of first semiconductor layers 106 and any number of second semiconductor layers 108.

[0147] The first semiconductor layer 106 may be or include a first semiconductor material such as silicon, silicon-germanium, germanium, gallium arsenide, indium arsenide, indium phosphide, or the like. The second semiconductor layer 108 may be or include a second semiconductor material such as silicon, silicon-germanium, germanium, gallium arsenide, indium arsenide, indium phosphide, or the like, and the second semiconductor material may be different from the first semiconductor material. For example, the first semiconductor material may be silicon-germanium, and the second semiconductor material may be silicon. In these embodiments, the stack 104 of semiconductor layers includes interleaved silicon-germanium layers and silicon layers. The first semiconductor layer 106 may or may not be doped, depending on the design of the semiconductor device 1904. The second semiconductor layer 108 may or may not be doped, depending on the design of the semiconductor device 1904. The first semiconductor material may be different from the semiconductor material of the substrate semiconductor structure 102. For example, the semiconductor material of the substrate semiconductor structure 102 may be silicon, and the first semiconductor material may be silicon-germanium.

[0148] In some embodiments, the formation process of the semiconductor layer stack 104 includes epitaxially forming a first semiconductor layer 106 and a second semiconductor layer 108. For example, the first method for growing the first semiconductor layer 106 on the substrate semiconductor structure 102 may be a first epitaxial process, such as vapor phase epitaxy, liquid phase epitaxy, molecular beam epitaxy, some other epitaxial processes, or a combination thereof. Then, the first second semiconductor layer 108 is grown on the first first semiconductor layer 106, and its growth method may be a second epitaxial process such as vapor phase epitaxy, liquid phase epitaxy, molecular beam epitaxy, some other epitaxial processes, or a combination thereof. The first epitaxial process and the second epitaxial process are repeated in an alternating manner until the semiconductor layer stack 104 has a predetermined number of first semiconductor layers 106 and a predetermined number of second semiconductor layers 108. In some embodiments, after forming the semiconductor layer stack 104, a planarization process such as chemical mechanical polishing, etch-back process, or similar process may be performed to planarize the upper surface of the uppermost semiconductor layer of the semiconductor layer stack 104 (e.g., the uppermost first semiconductor layer 106).

[0149] In some embodiments, the first epitaxial process and the second epitaxial process can be performed in the same process chamber (e.g., an epitaxial growth chamber). In these embodiments, a first set of precursors for growing the first semiconductor layer 106 and a second set of precursors for growing the second semiconductor layer 108 can be cyclically pumped into the process chamber. The first set of precursors includes precursors for forming a first semiconductor material (e.g., silicon-germanium), and the second set of precursors includes precursors for forming a second semiconductor material (e.g., silicon). In some embodiments, the first set of precursors includes silicon precursors (e.g., silane) and germanium precursors (e.g., germanane), and the second set of precursors includes silicon precursors but no germanium precursors. Thus, silicon precursors can be flowed into the process chamber, followed by periodically performing the following steps: (1) flowing germanium precursors into the process chamber during the growth of the first semiconductor layer 106; and (2) preventing the flow of germanium precursors into the process chamber during the growth of the second semiconductor layer 108. It should be understood that in some embodiments, one or more cleanup steps may be performed during the formation of the semiconductor layer stack 104 (e.g., cleanup in the process chamber between the growth of the first semiconductor layer 106 and the second semiconductor layer 108).

[0150] like Figure 1 As shown, a hard mask layer 110 is formed on a semiconductor layer stack 104. The hard mask layer 110 covers the semiconductor layer stack 104. For example, the hard mask layer 110 may be or comprise an oxide (such as silicon oxide), a nitride (such as silicon nitride), an oxide oxynitride (such as silicon oxynitride), some other hard mask materials, or a combination thereof. In some embodiments, one of the processes for forming the hard mask layer 110 includes depositing or growing the hard mask layer 110 on the upper surface of the semiconductor layer stack 104. The deposition or growth method of the hard mask layer 110 may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal oxidation, some other deposition or growth processes, or a combination thereof. In other embodiments, the hard mask layer 110 may comprise multiple layers. For example, the hard mask layer 110 may comprise an oxide layer (such as silicon oxide) and a nitride layer (such as silicon nitride) on the oxide layer.

[0151] like Figure 2 As shown, a first hard mask structure 202, a first stack 204 of multiple semiconductor structures, a first semiconductor structure 206, a second semiconductor structure 208, and semiconductor fins 210 are formed. For clarity, only some of the first stack 204, first semiconductor structure 206, second semiconductor structure 208, and semiconductor fins 210 are specifically labeled. Figure 2 As shown, the substrate semiconductor structure 102 is recessed to form a semiconductor substrate 212. The semiconductor substrate 212 can then be regarded as a substrate.

[0152] The semiconductor fins 210 protrude vertically from the substrate 212. The semiconductor fins 210 are laterally separated (along the z-axis). For example, the first fin 210a, the second fin 210b, the third fin 210c, the fourth fin 210d, the fifth fin 210e, and the sixth fin 210f are laterally separated from each other (along the z-axis). The semiconductor fins 210 extend laterally (along the x-axis) on the substrate 212 and are parallel to each other.

[0153] The first stack 204 of semiconductor structures covers the semiconductor fins 210. The first stack 204 of semiconductor structures is laterally separated (along the z-axis). The first stack 204 of semiconductor structures extends laterally (along the x-axis) on the semiconductor fins 210 and is parallel to each other. Each of the first stack 204 of semiconductor structures may contain staggered first semiconductor structures 206 and second semiconductor structures 208. A first hard mask structure 202 covers the first stack 204 of semiconductor structures.

[0154] In some embodiments, the process of forming the first hard mask structure 202 includes forming a first patterned mask layer (not shown, such as positive photoresist and / or negative photoresist) on the hard mask layer 110. The method of forming the first patterned mask layer may be to form a mask layer (not shown) on the hard mask layer 110, develop the mask layer into a pattern (e.g., via a photolithography process such as photolithography, extreme ultraviolet lithography, or similar lithography), and develop the mask layer to form the first patterned mask layer. The first patterned mask layer may then be used, and a first etching process may be performed on the hard mask layer 110 to remove the unmasked portion of the hard mask layer 110. The masked portion of the hard mask layer 110 is then retained as the first mask structure 202. The first etching process may be a dry etching process, a wet etching process, a reactive ion etching process, some other etching processes, or a combination thereof. The first patterned mask layer may then be stripped off.

[0155] Next, a first hard mask structure 202 is used as an etching mask to etch and form the first stack 204, the first semiconductor structure 206, the second semiconductor structure 208, the semiconductor fins 210, and the substrate 212. With the first hard mask structure 202, a second etching process can be performed on the semiconductor layer stack 104 and the substrate semiconductor structure (see...). Figure 1The second etching process can remove the unmasked portions of the semiconductor layer stack 104, retaining the masked portions of the semiconductor layers as the first stack 204 of the semiconductor structure. In other words, the second etching process removes the unmasked portions of the first semiconductor layer 106 and the second semiconductor layer 108, retaining the masked portion of the first semiconductor layer 106 as the first semiconductor structure 206, and retaining the masked portion of the second semiconductor layer 108 as the second semiconductor structure 208. The second etching process can also recess the unmasked portions of the substrate semiconductor structure 102, retaining portions of the substrate semiconductor structure 102 (such as the masked portions and recessed portions) as the substrate 212 and the semiconductor fins 210. The second etching process can be a dry etching process, a wet etching process, a reactive ion etching process, some other etching processes, or a combination thereof.

[0156] Furthermore, the process of forming the first hard mask structure 202, the first stack 204 of the semiconductor structure, the first semiconductor structure 206, the second semiconductor structure 208, the semiconductor fins 210, and the substrate 212 can form a first trench 214 on the substrate 212. For clarity, only some of the first trenches 214 are specifically indicated. The first trenches 214 are laterally separated (along the z-axis). The semiconductor fins 210 can be laterally separated (along the z-axis) from the first trenches 214. In other words, the first trenches 214 are located on both sides of the semiconductor fins 210. The first trenches 214 extend laterally (along the x-axis) on the substrate 212 and are parallel to each other.

[0157] It should be understood that the formation methods of the first hard mask structure 202, the first stack of semiconductor structures 204, the first semiconductor structure 206, the second semiconductor structure 208, the semiconductor fins 210, and the substrate 212 can be any suitable method. For example, the formation methods of the first hard mask structure 202, the first stack of semiconductor structures 204, the first semiconductor structure 206, the second semiconductor structure 208, the semiconductor fins 210, and the substrate 212 can employ one or more photolithography processes, such as dual patterning processes, multi-patterning processes, or similar processes. The semiconductor fins 210 can then be considered as fins.

[0158] like Figure 3 As shown, along the sidewall of the first groove 214 and the lower surface of the first groove 214 (see...) Figure 2A pad layer 302 is formed. In other words, the pad layer 302 can be formed along the sidewalls of the fins 210, the upper surface of the substrate 212 (e.g., the upper surface between the fins 210), the sidewalls of the first stack 204 of the semiconductor structure, and the sidewalls of the first hard mask structure 202. In one embodiment, the pad layer 302 can be formed on the upper surface of the first hard mask structure 202. In other embodiments, the formation process of the pad layer 302 includes growing or depositing the pad layer 302, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, epitaxial processes, some other deposition or growth processes, or combinations thereof.

[0159] The padding layer 302 may be or include a semiconductor material (such as silicon, silicon germanium, or the like). In some embodiments, the semiconductor material of the padding layer 302 may be the same as the semiconductor material of the fin 210 (such as the semiconductor material of the substrate semiconductor structure 102). In other embodiments, the semiconductor material of the padding layer 302 may be the same as the semiconductor material of the first semiconductor structure 206 (e.g., the first semiconductor material). In other embodiments, the padding layer 302 is a compliant layer.

[0160] like Figure 3 As shown, a first dielectric layer 304 is formed on the substrate 212, the first hard mask structure 202, and the pad layer 302. The first dielectric layer 304 is formed after the pad layer 302 is formed. The first dielectric layer 304 is formed to fill the first trench 214 (see...). Figure 2 The first dielectric layer 304 may have a planarized upper surface. For example, the first dielectric layer 304 may be or include nitrides (such as silicon nitride), oxynitrides (such as silicon oxynitride), silicon carbonitride, silicon carbonitride, metal oxides (such as aluminum oxide, hafnium oxide, zirconium oxide, or yttrium oxide), some other dielectric materials, or combinations thereof. In some embodiments, the more specific first dielectric layer 304 is silicon carbonitride having a first silicon carbonitride composition. In other embodiments, the process of forming the first dielectric layer 304 includes depositing the first dielectric layer 304 in the first trench 214, on the pad layer 302, and on the first hard mask structure 202, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition processes, or combinations thereof.

[0161] like Figure 4As shown, an isolation structure 402 is formed on the substrate 212 between the fins 210. For clarity, only some isolation structures 402 are specifically indicated. The isolation structure 402 can be considered as a shallow trench isolation structure. The isolation structure 402 is laterally separated (along the z-axis). The fins 210 are laterally separated (along the z-axis) from the isolation structure 402. In some embodiments, the isolation structures 402 extend laterally (along the x-axis) on the substrate 212 and are parallel to each other. In other embodiments, the isolation structure 402 may be a portion of one or more continuous isolation structures laterally surrounding one or more fins 210 (e.g., some portions of a larger shallow trench isolation structure extend laterally along the x-axis, while other portions extend laterally along the z-axis, such that the larger shallow trench isolation structure laterally surrounds one or more fins 210).

[0162] The upper surface of the isolation structure 402 may be substantially flat. In other embodiments, the isolation structure 402 may have a raised or recessed upper surface. The upper surface of the isolation structure 402 is substantially aligned (e.g., flush) with the upper surface of the fin 210. In other embodiments, the upper surface of the isolation structure 402 may be higher or lower than the upper surface of the fin 210.

[0163] In some embodiments, the process of forming the isolation structure 402 includes recessing the first dielectric layer 304 (see...). Figure 3 The method for recessing the first dielectric layer 304 may be to perform a third etching process on the first dielectric layer 304. Therefore, the third etching process recesses the first dielectric layer 304 to a predefined height to retain the lower portion of the first dielectric layer 304 as the isolation structure 402. In some embodiments, the third etching process also removes the upper portion of the pad layer 302 to retain the lower portion of the pad layer 302 along the sidewalls of the fin 210 and the upper surface of the substrate 212, such as... Figure 4 As shown. In other embodiments, the third etching process is more selective for the first dielectric layer 304 than for the pad layer 302, so as to retain the pad layer 302 along the sidewalls of the first stack 204 of the semiconductor structure, the sidewalls of the first hard mask structure 202, and the upper surface of the first hard mask structure 202. For example, the third etching process may be a dry etching process, a wet etching process, some other etching process, or a combination thereof. In some embodiments, the third etching process may be considered as the first etching process.

[0164] like Figure 4As shown, cap structures 404 are formed on the first stack 204 of the semiconductor structures. Cap structures 404 are also formed on the isolation structure 402, the pad layer 302, and the first hard mask structure 202. For clarity, only some cap structures 404 are specifically designated. Cap structures 404 may be or contain semiconductor materials such as silicon, silicon-germanium, or the like. In some embodiments, the semiconductor material of cap structure 404 is the same as the semiconductor material of the first semiconductor structure 206 (e.g., the first semiconductor material). For example, cap structure 404 is silicon-germanium, and the first semiconductor structure 206 is silicon-germanium.

[0165] In some embodiments, the process of forming the cap structure 404 includes growing or depositing the cap structure 404 on the first stack 204 of the semiconductor structure and the first hard mask structure 202. For example, the growth or deposition method of the cap structure 404 may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, epitaxial processes, some other deposition or growth processes, or a combination of the above. In other embodiments, the cap structure 404 is selectively grown from the exposed surface of the pad layer 302 (e.g., by an epitaxial process), so the upper surface of the isolation structure 402 does not contain the cap structure 404.

[0166] Furthermore, the process of forming the isolation structure 402 and the cover structure 404 also forms second trenches 406 on the substrate 212. The second trenches 406 are also formed on the isolation structure 402. For clarity, only some of the second trenches 406 are specifically indicated. The second trenches 406 are laterally separated (along the z-axis). The cover structure 404 is laterally separated (along the z-axis) from the second trenches 406. In other words, the second trenches 406 are located on both sides of the cover structure 404 and on the isolation structure 402. The second trenches 406 extend laterally (along the x-axis) on the isolation structure 402 and are parallel to each other.

[0167] like Figure 5 As shown, dielectric fins 502 are formed on substrate 212 and fins 210. Dielectric fins 502 are formed on (e.g., directly on) isolation structure 402. The dielectric fins 502 are laterally separated (along the z-axis). For example, first dielectric fin 502a, second dielectric fin 502b, third dielectric fin 502c, fourth dielectric fin 502d, and fifth dielectric fin 502e are laterally separated (along the z-axis) from each other. Cover structure 404 is laterally separated (along the z-axis) from the dielectric fins 502. In other words, dielectric fins 502 are located on both sides of cover structure 404 and on isolation structure 402. Dielectric fins 502 extend laterally (along the x-axis) on isolation structure 402 and are parallel to each other.

[0168] The upper surface of the dielectric fin 502 is lower than the upper surface of the first stack 204 of the semiconductor structures. Specifically, the upper surface of the dielectric fin 502 is lower than the upper surface of the uppermost semiconductor structure of the first stack 204 (e.g., the upper surface of the uppermost first semiconductor structure 206 of the first stack 204). In some embodiments, the upper surface of the dielectric fin 502 is substantially aligned with the upper surface of the uppermost second semiconductor structure 208 of the first stack 204. In other embodiments, the upper surface of the dielectric fin 502 is lower than or higher than the upper surface of the uppermost second semiconductor structure 208 of the first stack 204. In other embodiments, the upper surface of the dielectric fin 502 may be substantially flat. In other embodiments, the upper surface of the dielectric fin 502 may be raised or recessed.

[0169] For example, the dielectric fin 502 may be or comprise a nitride (such as silicon nitride), a nitrogen oxide (such as silicon oxynitride), silicon carbonitride, silicon carbonitride, a metal oxide (such as aluminum oxide, hafnium oxide, zirconium oxide, or yttrium oxide), some other dielectric material, or a combination thereof. In some embodiments, the dielectric fin 502 is more specifically silicon carbonitride having a second silicon carbonitride composition. In some embodiments, the second silicon carbonitride composition differs from the first silicon carbonitride composition.

[0170] In some embodiments, the process of forming dielectric fins 502 includes forming a second dielectric layer (not shown) on a substrate 212, an isolation structure 402, a pad layer 302, a cap structure 404 and a first hard mask structure 202.

[0171] A second dielectric layer is formed to fill the second trench 406 (see Figure 4 The second dielectric layer may have a flat upper surface. For example, the second dielectric layer may be or comprise an oxide (such as silicon oxide), a nitride (such as silicon nitride), an oxide oxynitride (such as silicon oxynitride), silicon carbonitride, some other dielectric material, or a combination thereof. In some embodiments, the second dielectric layer is silicon carbonitride having a second silicon carbonitride composition. In some embodiments, the process of forming the second dielectric layer includes depositing the second dielectric layer in the second trench 406, on the isolation structure 402, and on the cap structure 404, and the formation method may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition process, or a combination thereof.

[0172] The second dielectric layer is then recessed to a predefined height. This recessing can be initiated by a fourth etching process. The fourth etching process has greater selectivity for the second dielectric layer than for other structures beneath it (such as cap structure 404 and the first hard mask structure 202). Therefore, the fourth etching process can recess the second dielectric layer to a predefined height to preserve the lower portion of the second dielectric layer as the dielectric fin 502. For example, the fourth etching process can be a dry etching process, a wet etching process, some other etching process, or a combination thereof. In some embodiments, the fourth etching process can be considered as a second etching process.

[0173] like Figure 5 As shown, dielectric strips 504 are formed on substrate 212. Dielectric strips 504 are also formed (e.g., directly on) dielectric fins 502. For clarity, only some dielectric strips 504 are specifically indicated. The dielectric strips 504 are laterally separated (along the z-axis). The cover structure 404 is laterally separated (along the z-axis) from the dielectric strips 504. In other words, the dielectric strips 504 are located on both sides of the cover structure 404 and on the dielectric fins 502. The dielectric strips 504 extend laterally (along the x-axis) on the dielectric fins 502 and are parallel to each other.

[0174] Dielectric strips 504 extend perpendicularly (along the y-axis) from the upper surface of dielectric fins 502. In other words, dielectric strips 504 contact the upper surface of dielectric fins 502 and extend perpendicularly from the upper surface of dielectric fins 502 to the upper surface of dielectric strips 504. The upper surface of dielectric strips 504 is substantially flat. The upper surface of dielectric strips 504 is substantially aligned with the upper surface of cap structure 404 and the upper surface of the first hard mask structure 202.

[0175] For example, dielectric band 504 may be or include oxides (such as silicon oxide), high dielectric constant dielectric layers (such as hafnium oxide, zirconium oxide, hafnium aluminum oxide, hafnium silicate, or some other dielectric materials with a dielectric constant greater than 3.9), silicon carbonitride, metal oxides (such as aluminum oxide, hafnium oxide, zirconium oxide, or yttrium oxide), some other dielectric materials, or combinations thereof. Dielectric band 504 and dielectric fin 502 comprise different dielectric materials. For example, dielectric band 504 is hafnium oxide, and dielectric fin 502 is silicon carbonitride. In some embodiments, since dielectric fin 502 comprises a first dielectric material (such as silicon carbonitride) and dielectric band 504 comprises a second dielectric material different from the first dielectric material (such as hafnium oxide), dielectric fin 502 and the corresponding dielectric band 504 may be considered together as a hybrid fin. For example, the first of the hybrid fins includes the first dielectric fin 502 and the first dielectric band 504 corresponding to the first dielectric fin 502.

[0176] In some embodiments, the process of forming the dielectric strip 504 includes forming a third dielectric layer (not shown) on the substrate 212, the dielectric fin 502, the cap structure 404, and the first hard mask structure 202. For example, the third dielectric layer may be or comprise an oxide (such as silicon oxide), a high dielectric constant dielectric layer (such as hafnium oxide, zirconium oxide, hafnium aluminate, hafnium silicate, or some other dielectric material with a dielectric constant greater than 3.9), silicon carbonitride, a metal oxide (such as aluminum oxide, hafnium oxide, zirconium oxide, or yttrium oxide), some other dielectric material, or a combination thereof. The third dielectric layer and the second dielectric layer comprise different dielectric materials. For example, the third dielectric layer is hafnium oxide, while the second dielectric layer is silicon carbonitride. In some embodiments, the method of forming a third dielectric layer includes depositing a third dielectric layer on the dielectric fin 502, the cap structure 404 and the first hard mask structure 202, and the method of forming the third dielectric layer may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition processes or a combination thereof.

[0177] A planarization process can then be performed on the third dielectric layer. This planarization process removes the upper portion of the third dielectric layer, leaving the lower portion as the dielectric strip 504. A planarization process is also performed on the first hard mask structure 202 and the cover structure 404. Therefore, the planarization process removes the upper portions of the first hard mask structure 202 and the cover structure 404, making the upper surfaces of the dielectric strip 504, the first hard mask structure 202, and the cover structure 404 coplanar.

[0178] like Figure 6 As shown, a dummy gate structure 602 is formed on a substrate 212, a fin 210, a first stack of semiconductor structures 204, an isolation structure 402, a pad layer 302, a cap structure 404, a dielectric fin 502, a dielectric strip 504, and a first hard mask structure 202. In some embodiments, the dummy gate structure 602 includes a dummy gate dielectric structure 604 and a dummy gate material structure 606. The dummy gate material structure 606 covers the dummy gate dielectric structure 604. For clarity, only some dummy gate structures 602, dummy gate dielectric structures 604, and dummy gate material structures 606 are specifically labeled.

[0179] The dummy gate structure 602 is laterally separated (along the x-axis). The dummy gate structure 602 extends laterally (along the z-axis) over the substrate 212, fin 210, first stack 204 of the semiconductor structure, isolation structure 402, pad layer 302, cap structure 404, dielectric fin 502, dielectric strip 504, and first hard mask structure 202. For example, the dummy gate material structure 606 may be or include polysilicon, but may be or include other materials. For example, the dummy gate dielectric structure 604 may be or include oxides (such as silicon oxide), nitrides (such as silicon nitride), oxynitrides (such as silicon oxynitride), some other dielectric materials, or combinations thereof.

[0180] In some embodiments, the process of forming the dummy gate structure 602 includes depositing a dummy gate dielectric layer (not shown) on a substrate 212, fins 210, a first stack of semiconductor structures 204, an isolation structure 402, a pad layer 302, a cap structure 404, dielectric fins 502, dielectric strips 504, and a first hard mask structure 202. The dummy gate dielectric layer may be deposited as a compliant layer. For example, the dummy gate dielectric layer may be or include oxides (such as silicon oxide), nitrides (such as silicon nitride), oxynitrides (such as silicon oxynitride), some other dielectric materials, or combinations thereof. In some embodiments, the deposition method of the dummy gate dielectric layer may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition processes, or combinations thereof.

[0181] Next, a dummy gate material (not shown) is deposited on and covers the dummy gate dielectric layer. For example, the dummy gate dielectric material may be or include polysilicon, but may be or include other materials. For example, the deposition method of the dummy gate material may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition processes, or a combination thereof.

[0182] A first hard mask layer (not shown) is then deposited or grown on and over the dummy gate material. For example, the first hard mask layer may be or include oxides (such as silicon oxide), nitrides (such as silicon nitride), oxynitrides (such as silicon oxynitride), some other hard mask materials, or combinations thereof. For example, the deposition or growth method of the first hard mask layer may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal oxidation, some other deposition or growth processes, or combinations thereof.

[0183] A second hard mask layer (not shown) is then deposited on and over the first hard mask layer. For example, the second hard mask layer may be or include oxides (such as silicon oxide), nitrides (such as silicon nitride), oxynitrides (such as silicon oxynitride), some other hard mask materials, or combinations thereof. The second hard mask layer and the first hard mask layer may contain different hard mask materials. For example, the first hard mask may be silicon oxide, and the second hard mask may be silicon nitride. The deposition or growth method of the second hard mask layer may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition processes, or combinations thereof.

[0184] A second patterned mask layer (not shown, such as positive photoresist and / or negative photoresist) is then formed on the second hard mask layer. In the presence of the second patterned mask layer, a fifth etching process is performed to remove the unmasked portion of the second hard mask layer, retaining the masked portion of the second hard mask layer as the second hard mask structure 608. With the second hard mask structure 608 located on the first hard mask layer, a sixth etching process is then performed to remove the unmasked portion of the first hard mask layer, retaining the masked portion of the first hard mask layer as the third hard mask structure 610. The second hard mask structure 608 and the third hard mask structure 610 can be considered together as the fourth hard mask structure 612. For example, the fifth etching process can be a dry etching process, a wet etching process, a reactive ion etching process, some other etching processes, or a combination thereof. For example, the sixth etching process can be a dry etching process, a wet etching process, a reactive ion etching process, some other etching processes, or a combination thereof.

[0185] Subsequently, with the fourth hard mask structure 612 located on the dummy gate material layer and the dummy gate dielectric layer, a seventh etching process is performed on the dummy gate material layer and the dummy gate dielectric layer to form the dummy gate structure 602. The seventh etching process removes the unmasked portion of the dummy gate material layer, retaining the masked portion of the dummy gate material layer as the dummy gate material structure 606. The seventh etching process also removes the unmasked portion of the dummy gate dielectric layer, retaining the masked portion of the dummy gate dielectric layer as the dummy gate dielectric structure 604. Thus, the dummy gate structure 602 is formed. For example, the seventh etching process can be a dry etching process, a wet etching process, a reactive ion etching process, some other etching process, or a combination of the above.

[0186] like Figure 7 As shown, first sidewall spacers 702 are formed along the sidewalls of the dummy gate material structure 606. In some embodiments, first sidewall spacers 702 are also formed along the sidewalls of the fourth hard mask structure 612. For clarity, only some of the first sidewall spacers 702 are specifically indicated.

[0187] In some embodiments, the process of forming the first sidewall spacer 702 includes depositing a first spacer layer on... Figure 6 On the structure shown. The first spacer layer can be compliantly deposited on Figure 6 The structure is shown. For example, the first spacer layer may be or include oxides (such as silicon oxide), nitrides (such as silicon nitride), oxynitrides (such as silicon oxynitride), some other hard mask materials, or combinations thereof. An eighth etching process may then be performed on the first spacer layer to remove horizontal portions of the first spacer layer (e.g., portions on the fourth hard mask structure 612, the first hard mask structure 202, the cap structure 404, and the dielectric strip 504), retaining vertical portions of the first spacer layer as first sidewall spacers 702 (e.g., portions along the sidewalls of the dummy gate dielectric structure 604, the dummy gate material structure 606, the third hard mask structure 610, and the second hard mask structure 608). For example, the eighth etching process may be a dry etching process, a wet etching process, a reactive ion etching process, some other etching processes, or combinations thereof.

[0188] like Figure 7 As shown, portions of the first hard mask structure 202, the first stack 204 of the semiconductor structure, the cap structure 404, and the dielectric strip 504 outside the boundary of the first sidewall spacer 702 (e.g., outside the outer sidewall of the first sidewall spacer 702) are removed (see Figure 1). Figure 6 In some embodiments, the process of removing portions of the first hard mask structure 202, the first stack 204 of the semiconductor structure, the cover structure 404, and the dielectric strip 504 outside the boundary of the first sidewall spacer 702 includes performing a ninth etching process on the first hard mask structure 202, the first stack 204 of the semiconductor structure, the cover structure 404, and the dielectric strip 504.

[0189] The ninth etching process can be anisotropic etching. For example, the ninth etching process can be a dry etching process, reactive ion etching, some other etching process, or a combination of the above. The etchant used in the ninth etching process is selective for the first hard mask structure 202, the first semiconductor structure 206, the second semiconductor structure 208, the cap structure 404, and the dielectric strip 504 (for example, the etching rate for these materials is higher than the etching rate for the dielectric fins 502 and / or the isolation structure 402).

[0190] During the ninth etching process, the dummy gate structure 602, the fourth hard mask structure 612, and the first sidewall spacer together serve as an etching mask. Therefore, the ninth etching process removes portions of the first hard mask structure 202, the first stack 204 of the semiconductor structure, the cap structure 404, and the dielectric strip 504 outside the boundary of the first sidewall spacer 702. The ninth etching process exposes the upper surface of the fin 210. In some embodiments, the ninth etching process terminates at (or near) the upper surface of the isolation structure 402.

[0191] The ninth etching process forms the first plurality of dielectric structures 704. For example, the ninth etching process forms the first dielectric structure 704a, the second dielectric structure 704b, the third dielectric structure 704c, the fourth dielectric structure 704d, and the fifth dielectric structure 704e. The first plurality of dielectric structures 704 are the separated portions of the dielectric band 504 retained after the ninth etching process. The first plurality of dielectric structures 704 are formed on (e.g., directly on) the dielectric fins 502 and under (e.g., directly on) the first sidewall spacers 702 and the dummy gate structure 602. The first plurality of dielectric structures 704 are separated from each other (along the z-axis and / or along the x-axis). It should be understood that the first plurality of dielectric structures 704 may include more dielectric structures than those listed (e.g., the first plurality of dielectric structures 704 may include other separated portions of the dielectric band 504, which are retained under other dummy gate structures 602, but are not shown due to perspective).

[0192] The ninth etching process also forms a second stack 705 of multiple semiconductor structures. Each second stack 705 of semiconductor structures includes interleaved third semiconductor structures 706 and fourth semiconductor structures 708. The third semiconductor structure 706 is a portion of the first semiconductor structure 206 retained after the ninth etching process. The fourth semiconductor structure 708 is a portion of the second semiconductor structure 208 retained after the ninth etching process. For clarity in the drawings, only some of the second stacks 705, third semiconductor structures 706, and fourth semiconductor structures 708 are specifically indicated.

[0193] The second stack 705 of the semiconductor structure is formed (e.g., directly on) the fin 210 and under (e.g., directly on) the first sidewall spacer 702 and the dummy gate structure 602. Specifically, the second stack 705 of the semiconductor structure is formed (e.g., directly on) the fin 210 and under (e.g., directly on) the separation portion of the first hard mask structure 202. The separation portion of the first hard mask structure 202 is formed by a ninth etching process. The separation portion of the first hard mask structure 202 is the separation portion of the first hard mask structure 202 retained after the ninth etching process. The separation portion of the first hard mask structure 202 is laterally separated (along the z-axis). The separation portion of the first hard mask structure 202 is laterally located (along the z-axis) between the cap structures 404. The separation portion of the first hard mask structure 202 is located (e.g., directly on) the second stack 705 of the semiconductor structure and under (e.g., directly on) the first sidewall spacer 702 and the dummy gate structure 602.

[0194] Because the ninth etching process is an isotropic etching process, the outer sidewalls (separated laterally along the x-axis) of each of the first plurality of dielectric structures 704, each of the separated portions of the first hard mask structure 202, each of the third semiconductor structure 706, and each of the fourth semiconductor structure 708 are substantially aligned with the outer sidewalls (separated laterally along the x-axis) of the first sidewall spacer 702. Furthermore, because the ninth etching process is an isotropic etching process, the portion of the cover structure 404 retained after the ninth etching process also has outer sidewalls (separated laterally along the x-axis), which are substantially aligned with the outer sidewalls (separated laterally in the x-axis) of the first sidewall spacer 702. In some embodiments, the first plurality of dielectric structures 704 can be considered as a first plurality of dielectric fin covers, as they cover and protect portions of the upper surface of the dielectric fins 502 in subsequent process steps.

[0195] like Figure 8 As shown, the second sidewall spacers 802 are formed along the outer sidewalls (laterally separated along the x-axis) of each third semiconductor structure 706. The second sidewall spacers 802 are also formed along the outer sidewalls (laterally separated along the z-axis) of the cover structure 404. Furthermore, the second sidewall spacers 802 may be formed partially along the two sidewalls (laterally separated along the z-axis) of the separated portions of the first hard mask structure 202. For clarity, only some of the second sidewall spacers 802 are specifically indicated. In some embodiments, the second sidewall spacers 802 may be considered as inner sidewall spacers.

[0196] In some embodiments, the process of forming the second sidewall spacer 802 includes performing a tenth etching process to laterally (along the x-direction) etch the third semiconductor structure 706 and the cap structure 404. The tenth etching process is selective for the materials of the third semiconductor structure 706 and the cap structure 404 (such as a first semiconductor material, like silicon-germanium), thus allowing the third semiconductor structure 706 and the cap structure 404 to be laterally recessed. After the tenth etching process, the outer sidewalls of each third semiconductor structure 706 and each cap structure 404 may be recessed relative to the outer sidewalls of the first hard mask structure 202, the outer sidewalls of the first sidewall spacer 702, and the outer sidewalls of the first plurality of dielectric structures 704.

[0197] A second spacer layer (not shown) can then be formed to fill the recess formed by the tenth etching process. The second spacer layer can be formed by depositing it within the recess formed by the tenth etching process, and over the substrate 212, fins 210, pad layer 302, isolation structure 402, dielectric fins 502, second stack of semiconductor structures 705, first hard mask structure 202, first plurality of dielectric structures 704, first sidewall spacers 702, dummy gate structure 602, and fourth hard mask structure 612. In some embodiments, the second spacer layer may be deposited as a compliant layer. In other embodiments, the second spacer layer may be or include oxides (such as silicon oxide), nitrides (such as silicon nitride), oxynitrides (such as silicon oxynitride), some other dielectric materials, or combinations thereof. For example, the deposition method of the second spacer layer may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition processes, or combinations thereof.

[0198] Next, an eleventh etching process is performed on the second spacer layer to partially remove the second spacer layer, leaving a portion of the second spacer layer along the outer sidewalls of the third semiconductor structure 706 and the outer sidewalls of the cap structure 404 as the second sidewall spacer 802. Specifically, the eleventh etching process is anisotropic, which trims the second spacer layer, so that only a portion of the second spacer layer remains in the recess formed by the tenth etching process. Therefore, the sidewalls of the second sidewall spacer 802 can be substantially aligned with the outer sidewalls of the first hard mask structure 202, the outer sidewalls of the first sidewall spacer 702, and the outer sidewalls of the first plurality of dielectric structures 704. For example, the eleventh etching process can be a plasma etching process, a dry etching process, a reactive ion etching process, some other etching process, or a combination thereof.

[0199] like Figure 9As shown, multiple pairs of first source / drain regions 902 and multiple pairs of second source / drain regions 904 are formed on the fin 210. For clarity, only some of the first source / drain regions 902 and some of the second source / drain regions 904 are specifically labeled. The first source / drain regions 902 are formed (e.g., directly on) some fins 210, and the second source / drain regions 904 are formed (e.g., directly on) some other fins 210. For example, the first source / drain region 902 of the first pair of 902a is formed on (e.g., directly on) the first fin 210a; the first source / drain region 902 of the second pair of 902b is formed on (e.g., directly on) the second fin 210b; the second source / drain region 904 of the third pair of 904a is formed on (e.g., directly on) the third fin 210c; the second source / drain region 904 of the fourth pair of 904b is formed on (e.g., directly on) the fourth fin 210d; the first source / drain region 902 of the fifth pair of 902c is formed on (e.g., directly on) the fifth fin 210e; and the first source / drain region 902 of the sixth pair of 902d is formed on (e.g., directly on) the sixth fin 210f.

[0200] Multiple pairs of first source / drain regions 902 (e.g., the first pair 902a, the second pair 902b, the fifth pair 902c, and the sixth pair 902d) are laterally separated (along the x-axis) and located on both sides of the dummy gate structure 602. Multiple pairs of second source / drain regions 904 (e.g., the third pair 904a and the fourth pair 904b) are laterally separated (along the x-axis) and located on both sides of the dummy gate structure 602. Multiple pairs of first source / drain regions 902 and multiple pairs of second source / drain regions 904 are laterally separated (along the z-axis). Dielectric fins 502 are laterally separated (along the z-axis) from multiple pairs of first source / drain regions 902 and multiple pairs of second source / drain regions 904. In other words, multiple pairs of first source / drain regions 902 and multiple pairs of second source / drain regions 904 are located on both sides of dielectric fins 502.

[0201] The fourth semiconductor structure 708 on the corresponding fin 210 extends laterally (along the x-axis) between the source / drain regions of the multiple pairs of source / drain regions on the corresponding fin 210. For example, one of the second stacks 705 of the semiconductor structures on the first fin 210a is located between the first source / drain regions 902 of the first pair 902a, and the fourth semiconductor structure 708 of one of the second stacks 705 of the semiconductor structures on the first fin 210a extends laterally (along the x-axis) between the first source / drain regions 902 of the first pair 902a. The second sidewall spacers 802 on the corresponding fin 210 are located between the source / drain regions of the multiple pairs of source / drain regions on the corresponding fin 210. For example, one of the second sidewall spacers 802 is along the outer sidewall of the third semiconductor structure 706 of one of the second stacks 705 of the semiconductor structures on the first fin 210a, and it is located between the first source / drain regions 902 of the first pair 902a.

[0202] For example, the first source / drain region 902 may be or include silicon, germanium, silicon-germanium, silicon carbide, some other semiconductor materials, or a combination thereof. In some embodiments, the first source / drain region 902 is an epitaxial semiconductor material, such as a semiconductor material formed by an epitaxial process, such as epitaxial silicon, epitaxial germanium, epitaxial silicon-germanium, epitaxial silicon carbide, or the like. For example, the second source / drain region 904 may be or include silicon, germanium, silicon-germanium, silicon carbide, some other semiconductor materials, or a combination thereof. In some embodiments, the second source / drain region 904 is an epitaxial semiconductor material, such as a semiconductor material formed by an epitaxial process, such as epitaxial silicon, epitaxial germanium, epitaxial silicon-germanium, epitaxial silicon carbide, or the like.

[0203] In some embodiments, the first source / drain region 902 and the second source / drain region 904 comprise the same semiconductor material. In other embodiments, the first source / drain region 902 and the second source / drain region 904 comprise different semiconductor materials. In other embodiments, the first source / drain region 902 has a first doping type (e.g., p-type). In other embodiments, the second source / drain region 904 has a second doping type (e.g., n-type) opposite to the first doping type.

[0204] In some embodiments, the process of forming the first source / drain region 902 and the second source / drain region 904 includes epitaxially forming the first source / drain region 902 and the second source / drain region 904. A third epitaxial process is performed to grow the first source / drain region 902 from the upper surface of the corresponding fin 210. For example, the first source / drain regions 902 of a first pair of 902a can be grown from the upper surface of the first fin 210a, the first source / drain regions 902 of a second pair of 902b can be grown from the upper surface of the second fin 210b, the first source / drain regions 902 of a fifth pair of 902c can be grown from the upper surface of the fifth fin 210e, and the first source / drain regions 902 of a sixth pair of 902d can be grown from the upper surface of the sixth fin 210f. In some embodiments, the third epitaxial process can be vapor phase epitaxy, liquid phase epitaxy, molecular beam epitaxy, some other epitaxial process, or a combination thereof. The third epitaxial process can dope the first doping type (such as p-type doping such as boron atoms) in situ to the first source / drain region 902.

[0205] A fourth epitaxial process can be performed to grow a second source / drain region 904 from the upper surface of the corresponding fin 210. For example, a third pair of second source / drain regions 904a can be formed from the upper surface of the third fin 210c, and a fourth pair of second source / drain regions 904b can be formed from the upper surface of the fourth fin 210d. In some embodiments, the fourth epitaxial process can be vapor phase epitaxy, liquid phase epitaxy, molecular beam epitaxy, some other epitaxial process, or a combination thereof. The fourth epitaxial process can in-situ dope the second source / drain region 904 with a second doping type (e.g., n-type doping such as phosphorus atoms). It should be understood that during the third epitaxial process, the upper surface of the fin 210 (where the second source / drain region 904 can be grown) can be masked by a mask layer. It should be understood that during the fourth epitaxial process, the first source / drain region 902 can be masked by a mask layer.

[0206] like Figure 10 As shown, a first etch stop layer 1002 (such as a contact etch stop layer) is formed in Figure 9 The structure shown is such that a first interlayer dielectric layer 1004 is formed on the first etch stop layer 1002. For example, the first etch stop layer 1002 may be or include an oxide (such as silicon oxide), a nitride (such as silicon nitride), an oxide oxynitride (such as silicon oxynitride), some other dielectric material, or a combination thereof. For example, the interlayer dielectric layer 1004 may be or include a dielectric layer with a low dielectric constant (such as a dielectric material with a dielectric constant less than about 3.9), an oxide (such as silicon oxide), or the like.

[0207] In some embodiments, the process of forming the first etch stop layer 1002 and the interlayer dielectric layer 1004 includes depositing the first etch stop layer 1002 on... Figure 9The structure shown covers Figure 9 The structure is shown. In some embodiments, a first etch stop layer 1002 is deposited, such as a compliant layer. For example, the deposition method of the first etch stop layer 1002 may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition process, or a combination thereof. An interlayer dielectric layer 1004 may then be deposited between the first etch stop layer 1002 and... Figure 9 The structure shown is covered with a first etch stop layer 1002 and Figure 9 The structure shown. Next, the interlayer dielectric layer 1004, the first etch stop layer 1002, and the fourth hard mask structure 612 (see...) Figure 9 A planarization process is performed on the first sidewall spacer 702. The planarization process can remove the interlayer dielectric layer 1004, the first etch stop layer 1002, the fourth hard mask structure 612, and the upper portion of the first sidewall spacer 702 to form Figure 10 The structure shown. Therefore, the planarization process can make the upper surface of the interlayer dielectric layer 1004, the first etch stop layer 1002 and the first sidewall spacer 702 coplanar.

[0208] like Figure 11 As shown, a dummy gate structure is removed to form a third trench 1102 between the inner sidewalls of the first sidewall spacer 702. For clarity, only some of the third trenches 1102 are specifically shown. The third trenches 1102 expose portions of the first plurality of dielectric structures 704 and portions of the first hard mask structure 202 located between the inner sidewalls of the first sidewall spacer 702. In some embodiments, the process of removing the dummy gate structure 602 includes performing a twelfth etching process (e.g., a wet etching process, a dry etching process, or a similar process) that selectively removes the dummy gate dielectric structure 604 and the dummy gate material structure 606. It should be understood that a multi-pass etching process may be used to remove the dummy gate structure 602 (e.g., after the twelfth etching process removes the dummy gate material structure 606, a subsequent etching process removes the dummy gate dielectric structure 604).

[0209] like Figure 11 As shown, a first mask structure 1104 is formed in a third trench 1102. The upper surface of the first mask structure 1104 may be located above the upper surface of the interlayer dielectric layer 1004. For example, the first mask structure 1140 includes a positive photoresist material, a negative photoresist material, or the like. A fifth hard mask structure 1106 is formed on the first mask structure 1104. For example, the fifth hard mask structure 1106 may be or include oxides (such as silicon oxide), nitrides (such as silicon nitride), oxynitrides (such as silicon oxynitride), some other hard mask materials, or combinations thereof.

[0210] In some embodiments, the process of forming the first mask structure 1104 and the fifth hard mask structure 1106 includes depositing a photoresist layer (such as a positive photoresist material and / or a negative photoresist material), the deposition method of which may be chemical vapor deposition, spin coating, or a similar process. The photoresist layer is deposited in the third trench 1102 (e.g., filling the third trench 1102) and on the upper surface of the interlayer dielectric layer 1004, the first etch stop layer 1002, and the first sidewall spacer 702. A hard mask layer (not shown) may then be deposited on the photoresist layer and cover it, the deposition method of which may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a similar process. A third patterned mask layer may then be formed on the hard mask layer. A third patterned mask layer is used, and a thirteenth etching process (such as wet etching, dry etching, reactive ion etching, or a similar process) is performed on the hard mask layer to remove the unmasked portion of the hard mask layer, thereby retaining the masked portion of the hard mask layer as the fifth hard mask structure 1106. The third patterned mask layer can then be peeled off.

[0211] Next, a fourteenth etching process (such as wet etching, dry etching, reactive ion etching, or a similar process) can be performed on the photoresist layer to form the first mask structure 1104. During the fourteenth etching process, the fifth hard mask structure 1106 serves as the etching mask. Therefore, the fourteenth etching process removes the unmasked portion of the photoresist layer and retains the remaining portion of the photoresist layer as the first mask structure 1104. In some embodiments, the first mask structure 1104 can be considered as a dicing metal gate mask.

[0212] Figures 12 to 19 A series of cross-sectional views showing various stages of the method for forming a reduced semiconductor device 1904 with a nanostructured field-effect transistor 1810. Figures 12 to 19 The sectional view along Figure 11 Section AA, and continue Figure 11 The stages shown. For example, Figure 12 show Figure 11 The first stage following the stage shown, and along Figure 11 Section AA. Figure 13 show Figure 12 The second stage following the first stage, and along Figure 11 Section AA. Figure 14 show Figure 13 The third stage following the second stage, and along Figure 11 Section AA, and so on. Because Figures 12 to 19 The sectional view along Figure 11 The section line AA, therefore Figures 12 to 19 The method shown comprises multiple stages of forming a semiconductor device 1904 with reduced space between nanostructured field-effect transistors 1810, only showing those stages that can be achieved by... Figure 11 The process of creating the structure as seen in the cross-section AA (e.g., removal, forming, recessing, or similar processes). However, in some embodiments, it should be understood that it may be possible to... Figures 12 to 19 The various stages shown apply to similar structures (such as those with...) Figures 12 to 19 The process is similar to the structure of the process in the middle, for example, with the structure of the process in the middle. Figures 12 to 19 A similar method is used to process similar structures, but because along... Figure 11 The section line AA is not shown in the figure.

[0213] like Figure 12 As shown, remove the third trench 1102 (see Figure 11 The first plurality of dielectric structures 704 are exposed and unmasked by the first mask structure 1104. For example, the third trench 1102 is exposed and the first mask structure 1104 does not mask the first dielectric structure 704a, the third dielectric structure 704c, and the fifth dielectric structure 704e (see...). Figure 9 Therefore, the aforementioned dielectric structure was removed. Although Figure 12 The removal of the first dielectric structure 704a, the third dielectric structure 704c, and the fifth dielectric structure 704e is shown, but it should be understood that any combination of dielectric structures of the first plurality of dielectric structures 704 (such as the first mask structure 1104 forming a predefined pattern) can be removed. In some embodiments, the dielectric structures of the first plurality of dielectric structures 704 exposed by the third trench 1102 and not masked by the first mask structure 1104 are removed (e.g., completely removed). In other embodiments, only a portion of the dielectric structures of the first plurality of dielectric structures 704 exposed by the third trench 1102 and not masked by the first mask structure 1104 is removed, such as retaining the remaining portions of these dielectric structures of the first plurality of dielectric structures 704 located directly under the first sidewall spacer 702.

[0214] like Figure 12As shown, the portion of the cover structure 404 exposed by the third trench 1102 and not masked by the first mask structure 1104 is removed, causing the inner sidewall of the cover structure 404 to tilt. For example, the third trench 1102 is exposed and the first mask structure 1104 does not cover the cover structure 404 along the sidewalls of the first dielectric fin 502a, the third dielectric fin 502c, and the fifth dielectric fin 502e. Therefore, the portion of the cover structure 404 along the sidewalls of the first dielectric fin 502a, the third dielectric fin 502c, and the fifth dielectric fin 502e is removed, causing the inner sidewall of the cover structure 404 along the sidewalls of the first dielectric fin 502a, the third dielectric fin 502c, and the fifth dielectric fin 502e to tilt. The tilted sidewall of the cover structure 404 can tilt from the corresponding dielectric fin 502 to the corresponding stack of the second stack 705 of the semiconductor structure. For example, a first inclined inner sidewall of one of the cover structures 404 along the first sidewall of the third dielectric fin 502c may be inclined from the third dielectric fin 502c to the second stack 705 of the semiconductor structure between the third dielectric fin 502c and the second dielectric fin 502b. A second inclined inner sidewall of the other of the cover structures 404 along the second sidewall of the third dielectric fin 502c (in the opposite direction to the first inclined inner sidewall) may be inclined from the third dielectric fin 502c to the second stack 705 of the semiconductor structure between the third dielectric fin 502c and the fourth dielectric fin 502d.

[0215] In some embodiments, the step of removing the first plurality of dielectric structures 704 that are exposed in the third trench 1102 and unmasked by the first mask structure 1104 includes Figure 11 A fifteenth etching process is performed on the structure shown to selectively remove a plurality of first dielectric structures 704 exposed in the third trench 1102 and unmasked by the first mask structure 1104. During the fifteenth etching process, the first mask structure 1104 acts as an etching mask, preventing the fifteenth etching process from etching away the plurality of first dielectric structures 704 (and portions of the cover structure 404) masked by the first mask structure 1104. Therefore, the fifteenth etching process selectively removes the plurality of first dielectric structures 704 exposed in the third trench 1102 and unmasked by the first mask structure 1104. Furthermore, the fifteenth etching process can remove portions of the cover structure 404 exposed in the third trench 1102 and unmasked by the first mask structure 1104, thereby tilting the inner sidewalls of the cover structure 404. In some embodiments, the fifteenth etching process may be a dry etching process, a wet etching process, some other etching process, or a combination thereof. Figure 12 As shown, the fifth hard mask structure 1106 can be removed by the fifteenth etching process.

[0216] After the fifteenth etching process, the first plurality of dielectric structures 704 can be retained, and thereafter they can be considered together as the retained dielectric structures 704b / 704d. Figure 12 For example, the retained dielectric structures 704b / 704d include the second dielectric structure 704b and the fourth dielectric structure 704d (because the second dielectric structure 704b and the fourth dielectric structure 704d are retained after the fifteenth etching process). It should be understood that other dielectric structures of the first plurality of dielectric structures 704 may be retained after the fifteenth etching process, such as other dielectric structures of the first plurality of dielectric structures 704 that are separate (along the x-axis) from the second dielectric structure 704b and the fourth dielectric structure 704d (not shown in the figure because the cross-sectional view is along...). Figure 11 (See section AA). It should be understood that the retained dielectric structures are designated "704b / 704d" for clarity, but this does not mean that the retained dielectric structures 704b / 704d are limited to including only the second dielectric structure 704b and the fourth dielectric structure 704d. Rather, after the fifteenth etching process, the retained dielectric structures 704b / 704d may include one or more (and / or any combination of) the first plurality of dielectric structures 704.

[0217] In some embodiments, the retained dielectric structures 704b / 704d can be considered as a second plurality of dielectric fin covers because they cover (and protect in subsequent process steps) a portion of the upper surface of the corresponding dielectric fin 502. For example, the second dielectric structure 704b covers (and protects in subsequent process steps) a portion of the upper surface of the second dielectric fin 502b, while the fourth dielectric structure 704d covers (and protects in subsequent process steps) a portion of the upper surface of the fourth dielectric fin 502d. Therefore, the second dielectric structure 704b can be considered as a first dielectric fin cover of the second plurality of dielectric fin covers, and the fourth dielectric structure 704d can be considered as a second dielectric fin cover of the second plurality of fin covers.

[0218] like Figure 13 As shown, the first mask structure 1104 is removed. In some embodiments, the process of removing the first mask structure 1104 includes... Figure 12 The process of removing the mask on the structure shown. For example, the mask removal process may be an etching process (such as a wet etching process, a dry etching process, or a similar process), an ashing process, a combination of the above, or a similar process.

[0219] like Figure 13As shown, the first hard mask structure 202 is removed. After removing the first mask structure 1104, the first hard mask structure 202 is removed. In some embodiments, the first hard mask structure 202 is selectively removed using a sixteenth etch process (such as a wet etching process, a dry etching process, or a similar process). In some embodiments, the sixteenth etch process recesses the first hard mask structure 202 rather than removing it, to retain a portion of the first hard mask structure 202 on the second stack 705 of the semiconductor structure (to protect the fourth semiconductor structure 708 during a subsequent release process).

[0220] By removing (or recessing) the first hard mask structure 202, the third trench 1102 can be extended (along the y-direction, see...). Figure 11 In some embodiments, removing (or recessing) at least a portion of the first hard mask structure 202 (along the x-axis) by undercutting (along the x-axis) the first sidewall spacer 702 may extend a portion of the third trench 1102 (along the y-axis). In other embodiments, the sides (separated along the x-axis) of the portion of the third trench 1102 extending (along the y-axis) by removing (or recessing) the first hard mask structure 202 are at least partially defined by the sidewalls of the first etch stop layer 1002. In other embodiments, the sides (separated along the x-axis) of the portion of the third trench 1102 extending (along the y-axis) by removing (or recessing) the first hard mask structure 202 are at least partially defined by the sidewalls of the first hard mask structure 202 (e.g., the remainder of the first hard mask structure 202 retained after the sixteenth etch process).

[0221] like Figure 13 As shown, multiple nanostructure stacks 1302 are formed on the fin 210. For example, a first nanostructure stack 1302a is formed on (e.g., directly on) the first fin 210a, a second nanostructure stack 1302b is formed on (e.g., directly on) the second fin 210b, a third nanostructure stack 1302c is formed on (e.g., directly on) the third fin 210c, a fourth nanostructure stack 1302d is formed on (e.g., directly on) the fourth fin 210d, a fifth nanostructure stack 1302e is formed on (e.g., directly on) the fifth fin 210e, and a sixth nanostructure stack 1302f is formed on (e.g., directly on) the sixth fin 210f. In some embodiments, the nanostructure stacks 1302 are formed after the first hard mask structure 202 is removed.

[0222] The nanostructure stack 1302 is laterally separated (along the z-axis). The dielectric fin 502 can be laterally separated (along the z-axis) from the nanostructure stack 1302. In other words, the nanostructure stack 1302 is located on both sides of the dielectric fin 502. For example, the first nanostructure stack 1302a is located on the first side of the first dielectric fin 502a, while the second nanostructure stack 1302b is located on the second side (opposite to the first side) of the first dielectric fin 502a.

[0223] Each of the nanostructure stacks 1302 comprises a plurality of nanostructures 1304 stacked perpendicularly to each other (along the y-axis), such that one is directly on top of another. The nanostructures 1304 extend laterally (along the x-axis) on the fin 210 and are parallel to each other. The nanostructures 1304 of each nanostructure stack 1302 extend (along the x-axis) between a corresponding pair of source / drain regions. For example, the nanostructures 1304 of the first nanostructure stack 1302a extend (along the x-axis) between the first source / drain regions 902 of the first pair 902a (see...). Figure 11 The second nanostructure stack 1302b, nanostructure 1304, extends (along the x-axis) between the first source / drain regions 902 of the second pair of 902b (see...). Figure 11 The third nanostructure stack 1302c nanostructure 1304 extends (along the x-axis) between the second source / drain regions 904 of the third pair of 904a (see...). Figure 11 The fourth nanostructure stack 1302d nanostructure 1304 extends (along the x-axis) between the second source / drain regions 904 of the fourth pair of 904b (see...). Figure 11 The fifth nanostructure stack 1302e nanostructure 1304 extends (along the x-axis) between the first source / drain regions 902 of the fifth pair of 902c (see...). Figure 11 Furthermore, the sixth nanostructure stack 1302f's nanostructure 1304 extends (along the x-axis) between the first source / drain regions 902 of the sixth pair of 902d (see...). Figure 11 ).

[0224] In some embodiments, the nanostructure stacks 1302 are separated from the fins 210 (along the y-axis). In some embodiments, the nanostructures 1304 of the nanostructure stacks 1302 are perpendicularly separated (along the y-axis). For example, the first nanostructure stack 1302a is separated from the upper surface of the first fin 210a (along the y-axis), and the nanostructures 1304 of the first nanostructure stack 1302a are perpendicularly separated from each other (along the y-axis).

[0225] In some embodiments, the nanostructure 1304 may have a rectangular profile, such as Figure 13As shown. In other embodiments, nanostructure 1304 may have a square outline, an oval outline, a stadium-shaped (e.g., oblong) outline, a hexagonal outline (e.g., vertically separated or merged hexagonal outlines), some other geometric shape, or a combination thereof. If nanostructure 1304 has a square outline, nanostructure 1304 can be considered as a square nanowire. If nanostructure 1304 has an oval outline, nanostructure 1304 can be considered as a nanoring. If nanostructure 1304 has a hexagonal or stadium-shaped outline, nanostructure 1304 can be considered as a horizontal nanosheet or horizontal nanoplate. If nanostructure 1304 has a hexagonal outline, nanostructure 1304 can be considered as a hexagonal nanowire.

[0226] In some embodiments, the process of forming the nanostructure stack 1302 includes removing the third semiconductor structure 706 and the cap structure 404 exposed by the third trench 1102 (e.g., an extended third trench 1102). By removing the third semiconductor structure 706 and the cap structure 404, a fourth semiconductor structure 708 can be released to form the nanostructure 1304. In other words, after removing the third semiconductor structure 706 and the cap structure 404, portions of the fourth semiconductor structure 708 can be retained as the nanostructure 1304.

[0227] The third semiconductor structure 706 and the cap structure 404 can be removed by a seventeenth etching process (such as a wet etching process, a dry etching process, or a similar process). Since the third semiconductor structure 706 and the cap structure 404 comprise the same semiconductor material (e.g., a first semiconductor material such as silicon-germanium), the seventeenth etching process can selectively remove the third semiconductor structure 706 and the cap structure 404 to form the nanostructure 1304. In some embodiments, the seventeenth etching process can selectively remove the third semiconductor structure 706 and the cap structure 404 using a wet etchant such as ammonium hydroxide, tetramethylammonium hydroxide solution, ethylenediamine catechol, potassium hydroxide solution, or the like. In other embodiments, the seventeenth etching process can slightly etch the semiconductor material of the fourth semiconductor structure 708 (e.g., a second semiconductor material such as silicon) so that the cross-sectional area of ​​the nanostructure 1304 is slightly smaller than that of the fourth semiconductor structure 708. It should be understood that the seventeenth etching process may not release some portions of the nanostructure 1304 (e.g., portions directly beneath the first sidewall spacer 702, see...). Figure 11 Conversely, the second sidewall spacers 802 surround these portions of the nanostructure 1304 (see...). Figure 11 ).

[0228] like Figure 14As shown, an interface layer 1402 is formed around each nanostructure 1304. For example, the interface layer 1402 may be an oxide (such as silicon oxide), a nitride (such as silicon nitride), an oxide oxynitride (such as silicon oxynitride), some other dielectric material, or a combination thereof. In some embodiments, the process of forming the interface layer 1402 includes depositing or growing the interface layer 1402 on the surface (such as the outer sidewall) of the nanostructure 1304, and the deposition or growth method may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal oxidation, some other deposition or growth process, or a combination thereof. In other embodiments, the interface layer 1402 is an oxide grown by a thermal oxidation process, and therefore the interface layer 1402 is not formed on the dielectric fins 502 or the retained dielectric structures 704b / 704d. Although not illustrated in... Figure 14 However, it should be understood that in some embodiments, an interface layer 1402 may also be formed on the upper surface of the fin 210 and the upper surface of the padding layer 302, for example, a thermal oxidation process may be used to grow an interface layer 1402 on the upper surface of the fin 210 and the upper surface of the padding layer 302.

[0229] like Figure 14 As shown, a gate dielectric layer 1404 is formed around each nanostructure 1304. The gate dielectric layer 1404 is also formed around the interface layer 1402, on the fins 210, on the pad layer 302, on the dielectric fins 502, on the retained dielectric structures 704b / 704d, and on the isolation structure 402. The gate dielectric layer 1404 may be or include a high dielectric constant dielectric layer such as hafnium oxide, zirconium oxide, hafnium aluminate, hafnium silicate, some other dielectric materials with a dielectric constant greater than 3.9, or a combination thereof.

[0230] After the interface layer 1402 is formed, the gate dielectric layer 1404 is formed. In some embodiments, the process of forming the gate dielectric layer 1404 may include depositing the gate dielectric layer 1404 on the surfaces of the interface layer 1402, the fin 210, the pad layer 302, the dielectric fin 502, the retained dielectric structures 704b / 704d, and the isolation structure 402, such as Figure 14 As shown. For example, the gate dielectric layer 1404 may be deposited using atomic layer deposition, chemical vapor deposition, physical vapor deposition, some other deposition processes, or a combination thereof. In other embodiments, the gate dielectric layer 1404 may be formed as a compliant layer.

[0231] like Figure 14 As shown, a gate layer 1406 is formed on a gate dielectric layer 1404, fins 210, a pad layer 302, dielectric fins 502, retained dielectric structures 704b / 704d, an isolation structure 402, and a nanostructure stack 1302. In some embodiments, the gate layer 1406 is also formed around and between each nanostructure 1304, such as... Figure 14 As shown.

[0232] In some embodiments, the process of forming the gate layer 1406 includes depositing gate material in the third trench 1102 (e.g., an extended third trench 1102), on the gate dielectric layer 1404, on the fin 210, on the pad layer 302, on the dielectric fin 502, on the retained dielectric structures 704b / 704d, on the isolation structure 402, on the nanostructure stack 1302, and around and between each nanostructure 1304. Gate material is also deposited on the interlayer dielectric layer 1004, the first sidewall spacer 702, and the first etch stop layer 1002 (see [link to documentation]). Figure 11 For example, the gate material may be or include polysilicon (such as doped polysilicon), metals (such as aluminum, tungsten, or the like), titanium nitride, tantalum nitride, titanium aluminum carbide, titanium aluminum silicide, some other conductive materials, or combinations thereof. The gate material may comprise multiple layers of gate material, such as a work function layer (such as titanium nitride, tantalum nitride, or the like), a metal filler layer (such as tungsten), and the like.

[0233] For example, the deposition method for the gate material can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, electrochemical plating, electroless plating, some other deposition processes, or a combination thereof. After depositing the gate material, a planarization process such as chemical mechanical polishing can be performed on the gate material to remove the upper portion of the gate material, thereby retaining the lower portion of the gate material as the gate layer 1406. For example, the gate layer 1406 can be or include polysilicon (such as doped polysilicon), metal (such as aluminum, tungsten, or the like), titanium nitride, tantalum nitride, titanium aluminum carbide, titanium aluminum silicide, some other conductive materials, or a combination thereof. The gate layer 1406 can comprise multiple layers, such as a work function layer (such as titanium nitride, tantalum nitride, or the like), a metal filling layer (such as tungsten), and the like. The planarization process can also remove the upper portion of the interlayer dielectric layer 1004, the first etch stop layer 1002 and the first sidewall spacer 702, so that the upper surfaces of the gate layer 1406, the interlayer dielectric layer 1004, the first etch stop layer 1002 and the first sidewall spacer 702 are coplanar.

[0234] like Figure 15 As shown, multiple gate structures 1502 are formed on the fin 210, the pad layer 302, the dielectric fin 502, the isolation structure 402, and the nanostructure stack 1302. The corresponding dielectric fin 502 is laterally separated (along the z-axis) from the corresponding retained dielectric structures 704b / 704d of the gate structure 1502. The upper surface of the gate structure 1502 is lower than the upper surface of the retained dielectric structures 704b / 704d. In some embodiments, the upper surface of the gate structure 1502 is lower than the lower surface of the first sidewall spacer 702 (see...). Figure 11A gate structure 1502 is formed between one or more source / drain regions corresponding to multiple pairs of source / drain regions. In some embodiments, the gate structure 1502 is formed around each nanostructure 1304 of one or more corresponding nanostructure stacks 1302.

[0235] For example, a first gate structure 1502a, a second gate structure 1502b, and a third gate structure 1502c are formed. The second dielectric structure 704b and the second dielectric fin 502b are laterally separated (along the z-axis) from the first gate structure 1502a and the second gate structure 1502b, and the fourth dielectric structure 704d and the fourth dielectric fin 502d are also laterally separated (along the z-axis) from the second gate structure 1502b and the third gate structure 1502c. The upper surfaces of the first gate structure 1502a, the second gate structure 1502b, and the third gate structure 1502c are lower than the upper surfaces of the second dielectric structure 704b and the fourth dielectric structure 704d.

[0236] The first gate structure 1502a is formed between the first source / drain regions 902 of the first pair of 902a and between the first source / drain regions 902 of the second pair of 902b (see...). Figure 11 The second gate structure 1502b is formed between the second source / drain regions 904 of the third pair of 904a and between the second source / drain regions 904 of the fourth pair of 904b (see...). Figure 11 The third gate structure 1502c is formed between the first source / drain regions 902 of the fifth pair of 902c and between the first source / drain regions 902 of the sixth pair of 902d (see...). Figure 11 In some embodiments, the upper surface of the first gate structure 1502a is lower than the lower surface of one of the first sidewall spacers 702 extending (along the z-axis) between the first source / drain regions 902 of the first pair 902a and the second pair 902b. In other embodiments, the upper surfaces of the second gate structure 1502b and / or the third gate structure 1502c are lower than the lower surface of one of the first sidewall spacers 702.

[0237] The first gate structure 1502a surrounds each nanostructure 1304 of the first nanostructure stack 1302a and each nanostructure 1304 of the second nanostructure stack 1302b. The second gate structure 1502b surrounds each nanostructure 1304 of the third nanostructure stack 1302c and each nanostructure 1304 of the fourth nanostructure stack 1302d. The third gate structure 1502c surrounds each nanostructure 1304 of the fifth nanostructure stack 1302e and each nanostructure 1304 of the sixth nanostructure stack 1302f.

[0238] It should be understood that the first gate structure 1502a, the second gate structure 1502b, and the third gate structure 1502c can surround any number of nanostructures 1304 of the nanostructure stack 1302, depending on the intended function of the semiconductor device 1904. For example, the first gate structure 1502a can be formed around each nanostructure 1304 of one nanostructure stack 1302, or around each nanostructure 1304 of two nanostructure stacks 1302 (e.g., ...). Figure 15 As shown), it is formed around each nanostructure 1304 of three nanostructure stacks 1302 or around each nanostructure 1304 of any other number of nanostructure stacks 1302. It should be understood that the first gate structure 1502a, the second gate structure 1502b, and the third gate structure 1502c may be formed on the same number of nanostructure stacks 1302 (e.g., ...). Figure 15 Around each nanostructure 1304 of the two nanostructure stacks shown, or around each nanostructure 1304 of the first gate structure 1502a, the second gate structure 1502b, and the third gate structure 1502c, different numbers of nanostructure stacks 1302 may be formed. It should be understood that the number of nanostructure stacks 1302 around which the gate structure 1502 is formed depends on the pattern of the first mask structure 1104 (see...). Figure 12 ).

[0239] In some embodiments, the process of forming the gate structure 1502 includes forming the gate layer 1406 (see Figure 14 The gate layer 1406 is recessed below the upper surface of the retained dielectric structure 704b / 704d. For example, the method of recessing the gate layer 1406 may be an etching process (such as a wet etching process, a dry etching process, or a similar process) that is selective to the gate layer 1406 (such as removing material from the gate layer 1406 without substantially attacking the gate dielectric layer 1404).

[0240] After recessing the gate layer 1406, the separated lower portions of the gate layer are retained as gate structure 1502. For example, after recessing the gate layer 1406, the second dielectric structure 704b and the fourth dielectric structure 704d separate the three lower portions of the gate layer 1406, thus forming the first gate structure 1502a, the second gate structure 1502b, and the third gate structure 1502c in a self-aligned manner.

[0241] Because the gate structure 1502 is formed in a self-aligned manner, the method described herein offers several advantages over a reference diced metal gate process. The reference diced metal gate process involves forming openings in the gate layer 1406 during this process stage and filling these openings with dielectric material to diced the gate layer 1406 into the gate structure 1502. As structure sizes continue to shrink (e.g., 3nm or smaller), the reference diced metal gate process becomes difficult to fill the openings due to their high aspect ratios. Improperly filling the openings can cause electrical short circuits between the gate structures 1502 and may lead to device failure. The improved method provided herein forms the gate structure 1502 in a self-aligned manner, thus avoiding device failure and improving throughput.

[0242] like Figure 15 As shown, a second etch stop layer 1504 is formed on (e.g., directly on) the gate structure 1502. The second etch stop layer 1504 is formed after the gate structure 1502 is formed. The upper surface of the second etch stop layer 1504 may be lower than the upper surface of the retained dielectric structures 704b / 704d. In some embodiments, the upper surface of the second etch stop layer 1504 is lower than the lower surface of the first sidewall spacer 702 (see...). Figure 11 In other embodiments, the second etch stop layer 1504 may be a fluorine-free tungsten layer. The second etch stop layer 1504 may serve as an etch stop layer in subsequent etch processes and / or help reduce the resistance between the gate structure 1502 and subsequently formed conductive contacts (such as metal contacts electrically coupled to the gate structure 1502).

[0243] In some embodiments, the process of forming the second etch stop layer 1504 includes depositing the second etch stop layer 1504 on the gate structure 1502, and the deposition method may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, electrochemical plating, electroless plating, some other deposition processes, or a combination thereof. The second etch stop layer 1504 may be selectively deposited on the gate structure 1502 by a selective chemical vapor deposition process. The second etch stop layer 1504 is deposited after the formation of the gate structure 1502. In addition, the second etch stop layer 1504 is deposited in trenches (not shown) created in the step of forming the gate structure 1502 (e.g., recessing the gate layer 1406). The trenches formed in the formation of the gate structure 1502 extend vertically between the inner sidewalls of the first sidewall spacer 702, extend to the upper surface of the gate structure 1502, and extend to the surface of the gate dielectric layer 1404 (e.g., the upper surface and sidewalls, which are higher than the upper surface of the gate structure 1502).

[0244] like Figure 15As shown, the fourth dielectric layer 1506 is formed (e.g., directly on) the retained dielectric structures 704b / 704d, the gate dielectric layer 1404, the gate structure 1502, the dielectric fins 502, and the second etch stop layer 1504. The fourth dielectric layer 1506 is formed after the second etch stop layer 1504 is formed. The fourth dielectric layer 1506 extends vertically (along the y-axis) between the inner sidewalls of the first sidewall spacers 702, extends to the upper surface of the second etch stop layer 1504, and extends to the surface of the gate dielectric layer 1404 (which is higher than the upper surface of the second etch stop layer 1504). In other words, the fourth dielectric layer 1506 is formed in the remaining portion of the trench formed when the gate structure 1502 is formed (e.g., the unfilled portion of the trench in the second etch stop layer 1504). A fourth dielectric layer 1506 is formed, such that the upper surface of the second dielectric structure 704b and the upper surface of the fourth dielectric structure 704d are located between the uppermost and lowermost surfaces of the fourth dielectric layer 1506, as shown below. Figure 15 As shown. In some embodiments, the uppermost surface of the fourth dielectric layer 1506 is substantially flat.

[0245] In some embodiments, the process of forming the fourth dielectric layer 1506 includes depositing a third dielectric material on the retained dielectric structures 704b / 704d, the gate dielectric layer 1404, the gate structure 1502, the dielectric fin 502, the second etch stop layer 1504, the first sidewall spacer 702, the first etch stop layer 1002, and the interlayer dielectric layer 1004. In other words, the third dielectric material is deposited on the upper surface of the first sidewall spacer 702, the upper surface of the first etch stop layer 1002, and the upper surface of the interlayer dielectric layer 1004 (see...). Figure 11 The third dielectric material is used to fill the remaining portion of the trench formed when forming the gate structure 1502 (e.g., the unfilled portion of the trench in the second etch stop layer 1504). For example, the third dielectric material may be or include nitrides (such as silicon nitride), carbonitrides (such as silicon carbonitride), silicon carbonitride, oxynitrides (such as silicon oxynitride), metal oxides (such as aluminum oxide, hafnium oxide, zirconium oxide, or yttrium oxide), oxides (such as silicon oxide), some other dielectric materials, or combinations thereof. The third dielectric material has a different chemical composition from the interlayer dielectric layer 1004, so the interlayer dielectric layer 1004 can be selectively etched in subsequent process steps (such as when forming the source / drain contacts).

[0246] For example, the deposition method of the third dielectric material can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition processes, or a combination thereof. After depositing the third dielectric material, a planarization process (such as chemical mechanical polishing) can be performed on the third dielectric material to remove the upper portion of the third dielectric material, thereby retaining the lower portion of the third dielectric material as the fourth dielectric layer 1506. The planarization process also removes the upper portions of the interlayer dielectric layer 1004, the first etch stop layer 1002, and the first sidewall spacer 702, so that the upper surfaces of the fourth dielectric layer 1506, the interlayer dielectric layer 1004, the first etch stop layer 1002, and the first sidewall spacer 702 are coplanar.

[0247] like Figure 16 As shown, a first opening 1602 is formed in the fourth dielectric layer 1506. The first opening 1602 extends vertically (along the y-axis) between the inner sidewall of one of the first sidewall spacers 702 and the second etch stop layer 1504. The first opening 1602 at least partially overlaps with the second gate structure 1502b. The first opening 1602 partially overlaps with the second dielectric structure 704b and / or the fourth dielectric structure 704d.

[0248] In some embodiments, the first opening 1602 overlaps with the second gate structure 1502b, partially overlaps with the second dielectric structure 704b, and partially overlaps with the fourth dielectric structure 704d. In other words, the second gate structure 1502b is located between the sidewalls of the first opening 1602, the second dielectric structure 704b is partially located between the sidewalls of the first opening 1602, and the fourth dielectric structure 704d is partially located between the sidewalls of the first opening 1602. The first opening 1602 also overlaps with the third nanostructure stack 1302c, the fourth nanostructure stack 1302d, the third dielectric fin 502c, the third fin 210c, and the fourth fin 210d. In some embodiments, the inner sidewall of the fourth dielectric layer 1506, the inner sidewall of one of the first sidewall spacers 702, the upper surface of the second etch stop layer 1504, and the surface of the gate dielectric layer 1404 (such as the sidewall and the upper surface) may at least partially define the surface of the first opening 1602 (such as the sidewall and the lower surface).

[0249] In some embodiments, the process of forming the first opening 1602 includes forming a second mask structure 1604 on the fourth dielectric layer 1506. For example, the second mask structure 1604 may be or include a positive photoresist and / or a negative photoresist material, a hard mask material, a combination of the above, or the like. In other embodiments, the process of forming the second mask structure 1604 includes depositing a mask material (such as a positive photoresist and / or a negative photoresist) on the upper surface of the fourth dielectric layer 1506. The mask material is then exposed to a pattern (e.g., via a photolithography process such as photolithography, extreme ultraviolet lithography, or similar lithography) and the mask material is developed to form the second mask structure 1604 on the fourth dielectric layer 1506.

[0250] Subsequently, an eighteenth etch process is performed on the fourth dielectric layer 1506 to remove the unmasked portion of the fourth dielectric layer 1506 from the second mask structure 1604, thereby forming a first opening 1602 in the fourth dielectric layer 1506. In some embodiments, the eighteenth etch process terminates at the second etch stop layer 1504. In other embodiments, the eighteenth etch process terminates at both the second etch stop layer 1504 and the gate dielectric layer 1404. The eighteenth etch process may be a dry etching process, a wet etching process, a reactive ion etching process, some other etching processes, or a combination thereof.

[0251] Because the second dielectric structure 704b is located on the second dielectric fin 502b and the fourth dielectric structure 704d is located on the fourth dielectric fin 502d, the etching process tolerance of the first opening 1602 can be improved compared to the reference dicing metal gate process. In this process stage, the reference dicing metal gate process includes forming an opening in the gate layer 1406 and filling the opening with dielectric material to dicing the gate layer 1406 into the gate structure 1502. For example, the second dielectric structure 704b and the fourth dielectric structure 704d allow the first opening 1602 to have a larger size (due to photolithographic resolution limitations) and / or be laterally offset from a predefined position (due to poor stacking control), but still ensure that the first opening 1602 only overlaps with the desired structure (such as the second gate structure 1502b). In contrast, if the opening in the reference metal gate dicing process (e.g., the opening formed in the gate layer 1406 and filled with dielectric material to form the gate structure 1502) is too large and / or misaligned, the reference metal gate dicing process may unintentionally remove a portion of the gate layer 1406 (and / or unintentionally retain a portion of the gate layer 1406), causing device failure and reduced throughput. Therefore, as structural dimensions continue to shrink (e.g., 3nm or smaller), the method described herein can avoid device failure and improve throughput.

[0252] like Figure 17 As shown, remove (e.g., peel off) the second mask structure 1604. Figure 17As shown, a portion of the second etch stop layer 1504 exposed by the first opening 1602 is removed, and the second gate structure 1502b is removed. In some embodiments, the nineteenth etch process may remove the second gate structure 1502b and a portion of the second etch stop layer 1504 exposed by the first opening 1602. In other embodiments, before removing the second gate structure 1502b, the gate structure 1502 may be considered as a conductive gate structure (to distinguish between the functional gate structure present in the semiconductor device 1904 and the conductive gate structure removed during the formation of the semiconductor device 1904). For example, before removing the second gate structure 1502b, the first gate structure 1502a, the second gate structure 1502b, and the third gate structure 1502c may be considered as a first conductive gate structure, a second conductive gate structure, and a third conductive gate structure, respectively.

[0253] The nineteenth etching process is anisotropic etching. This process is selective for the second etch stop layer 1504 and the second gate structure 1502b, thus allowing the removal of the second gate structure 1502b and a portion of the second etch stop layer 1504 exposed by the first opening 1602, without removing a portion of the gate dielectric layer 1404 or retaining the dielectric structures 704b / 704d. The nineteenth etching process can be a dry etching process, a wet etching process, some other etching processes, or a combination thereof.

[0254] Because the second dielectric structure 704b laterally separates the first gate structure 1502a and the second gate structure 1502b, and the fourth dielectric structure 704d laterally separates the second gate structure 1502b and the third gate structure 1502c, the second dielectric structure 704b and the fourth dielectric structure 704d can act as barriers, allowing the nineteenth etching process to selectively remove the second gate structure 1502b. In other words, due to the positions of the second dielectric structure 704b and the fourth dielectric structure 704d, and because the second dielectric structure 704b and the fourth dielectric structure 704d extend onto the upper surfaces of the gate structure 1502 and the gate structure 1502, the nineteenth etching process can avoid unintentionally removing portions of the first gate structure 1502a and the third gate structure 1502c. Therefore, as the structure size continues to shrink (e.g., 3nm or smaller), the method described here is more effective in preventing device failures and improving throughput.

[0255] like Figure 18 As shown, the second opening 1801 is formed within the boundary of the first opening 1602 (e.g., within the inner sidewall of the first opening 1602) and extends from the first opening 1602 toward the substrate 212 (along the y-axis). The first opening 1602 and the second opening 1801 are continuous regions of free space (e.g., cavities in any material). In some embodiments, the process of forming the second opening 1801 includes... Figure 17 The twentieth etching process is performed on the structure shown. For example, the twentieth etching process can be a wet etching process, a dry etching process, a reactive ion etching process, some other etching process, or a combination of the above.

[0256] The twelfth etching process removes (or recesses) the structure exposed (and / or beneath) the first opening 1602. In some embodiments, the twelfth etching process is a highly directional etching process that can etch the structure exposed (and / or beneath) the first opening 1602 vertically (e.g., downwardly) without etching the structure exposed (and / or beneath) the first opening 1602 laterally (e.g., sideways). In other embodiments, the twelfth etching process is selective for the structure exposed (and / or beneath) the first opening 1602. In other words, the twelfth etching process is more selective for the structure exposed (and / or beneath) the first opening 1602 than for the fourth dielectric layer 1506. Therefore, by... Figure 17 A twelfth etching process is performed on the structure shown, which can selectively remove (or recess) the structure exposed (and / or beneath) the first opening 1602. The removal and recessing of the structure exposed (and / or beneath) the first opening 1602 (e.g., by the twelfth etching process) is detailed below.

[0257] The twelfth etching process can remove (e.g., completely remove) portions of the nanostructure 1304 of the third nanostructure stack 1302c, the nanostructure 1304 of the fourth nanostructure stack 1302d, and the interface layer 1402 exposed (and / or below) the first opening 1602. Furthermore, the twelfth etching process causes the third dielectric fin 502c to be recessed, thereby forming a recessed dielectric fin 1802. The upper surface of the recessed dielectric fin 1802 is lower than the upper surfaces of the first dielectric fin 502a, the second dielectric fin 502b, the fourth dielectric fin 502d, and the fifth dielectric fin 502e. Figure 18 As shown, the twelfth etching process removes two nanostructure stacks 1302 (e.g., a third nanostructure stack 1302c and a fourth nanostructure stack 1302d), but it should be understood that the twelfth etching process can remove any number of nanostructure stacks 1302. Specifically, the twelfth etching process can remove approximately 1 nanometer of structure stacks to approximately 100 nanometers of structure stacks.

[0258] The twelfth etching process recesses the third fin 210c to form a recessed portion of the third fin 210c. The twelfth etching process also recesses the fourth fin 201d to form a recessed portion of the fourth fin 201d. For clarity, the recessed portion of the third fin 210c can be considered as the first recessed semiconductor fin 1804a, and the recessed portion of the fourth fin 210d can be considered as the second recessed semiconductor fin 1804b, to more clearly distinguish the first recessed semiconductor fin 1804a of the third fin 210c and the second recessed semiconductor fin 1804b of the fourth fin 210d. However, it should be understood that the first recessed semiconductor fin 1804a can be regarded as a recessed portion of the third fin 210c (not all third fins 210c have unrecessed portions), and the second recessed semiconductor fin 1804b can be regarded as a recessed portion of the fourth fin 210d (not all fourth fins 210d have unrecessed portions).

[0259] In some embodiments, the upper surfaces of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b are perpendicularly located between the lower surface (e.g., the lowest surface) and the upper surface (e.g., the highest surface) of the isolation structure 402. In other embodiments, the upper surfaces of the first recessed semiconductor fin 1804a and / or the second recessed semiconductor fin 1804b are lower than the lower surface of the isolation structure 402. The upper surfaces of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b may be rounded, such as... Figure 18 As shown. In these embodiments, the upper surfaces of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b may have a recessed shape. In other embodiments, the upper surfaces of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b may be substantially flat.

[0260] The twelfth etching process causes a portion of the pad layer 302 exposed (and / or beneath) the first opening 1602 to be recessed. In some embodiments, the portion of the pad layer 302 exposed (and / or beneath) the first opening 1602 is recessed such that the upper surface of the pad layer 302 is substantially aligned with the upper surfaces of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b. The upper surface of the pad layer 302 substantially aligned with the upper surfaces of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b may be rounded. In some embodiments, the radius of curvature of the rounded upper surface of the pad layer 302 is the same as the radius of curvature of the upper surfaces of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b. In other embodiments, the radius of curvature of the rounded upper surface of the pad layer 302 differs from the radius of curvature of the upper surfaces of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b. In other embodiments, the rounded upper surface of the pad layer 302 extends arcuately from the substantially flat upper surfaces of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b to the sidewalls of the corresponding isolation structure 402.

[0261] The twelfth etching process removes a portion of the retained dielectric structure 704b / 704d (see...). Figure 17 This is done to form a second plurality of dielectric structures 1806. For example, a portion of the second dielectric structure 704b exposed (and / or beneath) the first opening 1602 is removed (see...). Figure 17 The remaining portion of the second dielectric structure 704b is retained as the sixth dielectric structure 1806a, which is one of the dielectric structures of the second plurality of dielectric structures 1806. Furthermore, a portion of the fourth dielectric structure 704d exposed (and / or beneath) the first opening 1602 is removed, retaining the retained portion of the fourth dielectric structure 704d as the seventh dielectric structure 1806b, which is another dielectric structure of the second plurality of dielectric structures 1806.

[0262] In some embodiments, the sixth dielectric structure 1806a has an L-shaped profile (e.g., along section line AA). In other embodiments, the seventh dielectric structure 1806b has an L-shaped profile (e.g., along section line AA). The L-shaped profiles of the sixth dielectric structure 1806a and the seventh dielectric structure 1806b face opposite directions. For example, the sixth dielectric structure 1806a has a first vertical portion (extending along the y-axis) and a first lateral portion (extending along the z-axis). The first lateral portion extends from the first vertical portion (along the z-axis) in a first direction. The seventh dielectric structure 1806b has a second vertical portion (extending along the y-axis) and a second lateral portion (extending along the z-axis). The second lateral portion extends from the second vertical portion (along the z-axis) in a second direction, and the second direction is opposite to the first direction.

[0263] The twelfth etching process can remove (e.g., completely remove) a portion of the gate dielectric layer 1404 exposed (and / or beneath) the first opening 1602, thereby forming multiple gate dielectric structures 1808. For example, by removing a portion of the gate dielectric layer 1404 exposed (and / or beneath) the first opening 1602, a first portion of the gate dielectric layer 1404 can be retained as a first gate dielectric structure 1808a, and a second portion of the gate dielectric layer 1404 can be retained as a second gate dielectric structure 1808b. The first gate dielectric structure 1808a separates the first gate structure 1502a from the first fin 210a, the second fin 210b, the pad layer 302, the isolation structure 402, the first dielectric fin 502a, the second dielectric fin 502b, the sixth dielectric structure 1806a, each nanostructure 1304 of the first nanostructure stack 1302a, and each nanostructure 1304 of the second nanostructure stack 1302b. The first gate dielectric structure 1808a is also separated from the sixth dielectric structure 1806a, the second etch stop layer 1504, and the fourth dielectric layer 1506.

[0264] The second gate dielectric structure 1808b separates the third gate structure 1502c and the fifth fin 210e, the sixth fin 210f, the pad layer 302, the isolation structure 402, the fourth dielectric fin 502d, the fifth dielectric fin 502e, the seventh dielectric structure 1806b, each nanostructure 1304 of the fifth nanostructure stack 1302e, and each nanostructure 1304 of the sixth nanostructure stack 1302f. The second gate dielectric structure 1808b also separates the seventh dielectric structure 1806b and the second etch stop layer 1504 and the fourth dielectric layer 1506.

[0265] Because the twelfth etching process is a highly directional etching process, it can perpendicularly etch the structure exposed (and / or below) the first opening 1602, and Figure 18The various surfaces (such as sidewalls) of the illustrated structure can be substantially aligned. For example, the first inner sidewall of the fourth dielectric layer 1506 is substantially aligned with the outer sidewall of the first gate dielectric structure 1808a, and the outer sidewall of the first gate dielectric structure 1808a is substantially aligned with the first sidewall of the sixth dielectric structure 1806a (e.g., the sidewall of the first vertical portion of the sixth dielectric structure 1806a). The second inner sidewall of the fourth dielectric layer 1506 (opposite to the first inner sidewall of the fourth dielectric layer 1506) is substantially aligned with the outer sidewall of the second gate dielectric structure 1808b, and the outer sidewall of the second gate dielectric structure 1808b is substantially aligned with the first sidewall of the seventh dielectric structure 1806b (e.g., the sidewall of the second vertical portion of the seventh dielectric structure 1806b). The second sidewall of the sixth dielectric structure 1806a (e.g., a sidewall of the first lateral portion of the sixth dielectric structure 1806a) is substantially aligned with the outer sidewall of the second dielectric fin 502b. The second sidewall of the seventh dielectric structure 1806b (e.g., one sidewall of the second transverse portion of the seventh dielectric structure 1806b) is substantially aligned with the outer sidewall of the fourth dielectric fin 502d.

[0266] In some embodiments, the outer sidewalls of the first gate dielectric structure 1808a, the outer sidewalls of the second gate dielectric structure 1808b, the surfaces (e.g., sidewalls and upper surfaces) of the second plurality of dielectric structures 1806, the outer sidewalls of the second dielectric fin 502b, the outer sidewalls of the fourth dielectric fin 502d, the surfaces (e.g., sidewalls and upper surfaces) of the recessed dielectric fin 1802, the surfaces (e.g., sidewalls and upper surfaces) of the isolation structure 402, the upper surface of the pad layer 302, the upper surface of the first recessed semiconductor fin 1804a, and the upper surface of the second recessed semiconductor fin 1804b may at least partially define the surface (e.g., sidewalls and lower surface) of the second opening 1801. In other embodiments, since the process of forming the second opening (e.g., a twelfth etch process) removes (or recesses) the structure exposed (and / or below) the first opening 1602, the process of forming the second opening can be considered as a process used to extend the depth (or height) of the first opening 1602.

[0267] like Figure 18As shown, the step of forming the second opening 1801 can form a plurality of nanostructure field-effect transistors 1810. For example, the step of forming the second opening 1801 can form a first nanostructure field-effect transistor 1810a on a first side of the second opening 1801 and form a second nanostructure field-effect transistor 1810b on a second side of the second opening 1801, with the first side and the second side of the second opening 1801 opposite to each other. The second opening 1801 laterally separates (along the z-axis) the first nanostructure field-effect transistor 1810a and the second nanostructure field-effect transistor 1810b. In some embodiments, the step of forming the gate dielectric structure 1808 completes the formation of the first nanostructure field-effect transistor 1810a and the second nanostructure field-effect transistor 1810b.

[0268] The first nanostructure field-effect transistor 1810a includes a first gate structure 1502a, a first gate dielectric structure 1808a, a first nanostructure stack 1302a, a second nanostructure stack 1302b, and a first source / drain region 902 of the first pair of 902a (see...). Figure 11 ) and the first source / drain region 902 of the second pair of 902b (see Figure 11 The first plurality of selective conductive channels (not shown) are located in nanostructures 1304 of the first nanostructure stack 1302a and nanostructures 1304 of the second nanostructure stack 1302b, respectively. The selective conductive channels located in nanostructures 1304 of the first nanostructure stack 1302a may extend (along the x-axis) between the first source / drain regions 902 of the first pair of 902a. The selective conductive channels located in nanostructures 1304 of the second nanostructure stack 1302b may extend (along the x-axis) between the first source / drain regions 902 of the second pair of 902b. In addition to comprising two nanostructure stacks and corresponding two pairs of first source / drain regions 902, it should be understood that the first nanostructure field-effect transistor 1810a may comprise any number of nanostructure stacks and corresponding any number of multiple pairs of first source / drain regions 902.

[0269] The second nanostructure field-effect transistor 1810b includes a third gate structure 1502c, a second gate dielectric structure 1808b, a fifth nanostructure stack 1302e, a sixth nanostructure stack 1302f, and a first source / drain region 902 of the fifth pair of 902c (see...). Figure 11 ) and the first source / drain region 902 of the sixth pair of 902d (see Figure 11The second plurality of selective conductive channels (illustrated) are located in nanostructures 1304 of the fifth nanostructure stack 1302e and the sixth nanostructure stack 1302f, respectively. The selective conductive channel located in nanostructure 1304 of the fifth nanostructure stack 1302e extends (along the x-direction) between the first source / drain regions 902 of the fifth pair of 902c. The selective conductive channel located in nanostructure 1304 of the sixth nanostructure stack 1302f extends (along the x-axis) between the first source / drain regions 902 of the sixth pair of 902d. In addition to comprising two nanostructure stacks and corresponding two pairs of first source / drain regions 902, it should be understood that the second nanostructure field-effect transistor 1810b may comprise any number of nanostructure stacks and corresponding multiple pairs of first source / drain regions 902. It should also be understood that the first nanostructure field-effect transistor 1810a and the second nanostructure field-effect transistor 1810b may contain the same (or different) number of nanostructure stacks and corresponding multiple pairs of first source / drain regions 902.

[0270] like Figure 19 As shown, a fifth dielectric layer 1902 is formed (e.g., filled) in the first opening 1602 and the second opening 1801. The fifth dielectric layer 1902 is formed on the first recessed semiconductor fin 1804a, the second recessed semiconductor fin 1804b, the pad layer 302, the isolation structure 402, the recessed dielectric fin 1802, the dielectric fin 502, the second plurality of dielectric structures 1806, and the gate dielectric structure 1808. In some embodiments, the fifth dielectric layer 1902 has a flat upper surface.

[0271] In some embodiments, the process of forming the fifth dielectric layer 1902 includes depositing a fourth dielectric material on the first recessed semiconductor fin 1804a, the second recessed semiconductor fin 1804b, the pad layer 302, the isolation structure 402, the recessed dielectric fin 1802, the dielectric fin 502, the second plurality of dielectric structures 1806, the gate dielectric structure 1808, the gate structure 1502, the second etch stop layer 1504, the fourth dielectric layer 1506, the first sidewall spacer 702, the first etch stop layer 1002, and the interlayer dielectric layer 1004. In other words, the fourth dielectric material is formed on the upper surface of the fourth dielectric layer 1506, the upper surface of the first sidewall spacer 702, the upper surface of the first etch stop layer 1002, and the upper surface of the interlayer dielectric layer 1004 (see [link to documentation]). Figure 11 ), and fill in (for example, completely fill in) the second opening 1801 and the first opening 1602.

[0272] For example, the fourth dielectric material may be or include nitrides (such as silicon nitride), silicon carbonitride, silicon carbonitride, oxide oxynitride (such as silicon oxynitride), metal oxides (such as aluminum oxide, hafnium oxide, zirconium oxide, or yttrium oxide), oxides (such as silicon oxide), some other dielectric materials, or combinations thereof. The fourth dielectric material has a different chemical composition than the interlayer dielectric layer 1004, therefore the interlayer dielectric layer 1004 can be selectively etched in subsequent process steps (such as when forming the source / drain contacts). In some embodiments, the fourth dielectric material has the same chemical composition as the third dielectric material, for example, the same dielectric material is used. In other embodiments, the fourth dielectric material has a different chemical composition than the third dielectric material, for example, the third dielectric material and the fourth dielectric material are different dielectric materials.

[0273] For example, the deposition method for the fourth dielectric material can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition processes, or a combination thereof. After depositing the fourth dielectric material, a planarization process such as chemical mechanical polishing can be performed on the fourth dielectric material to remove the upper portion of the fourth dielectric material, thereby retaining the lower portion of the fourth dielectric material as the fifth dielectric layer 1902. The planarization process can also remove the upper portions of the interlayer dielectric layer 1004, the first etch stop layer 1002, the first sidewall spacer 702, and the fourth dielectric layer 1506, so that the upper surfaces of the fifth dielectric layer 1902, the interlayer dielectric layer 1004, the first etch stop layer 1002, the first sidewall spacer 702, and the fourth dielectric layer 1506 are coplanar.

[0274] A fifth dielectric layer 1902 laterally separates (along the z-axis) the first nanostructure field-effect transistor 1810a and the second nanostructure field-effect transistor 1810b. In some embodiments, the fifth dielectric layer 1902 improves the electrical insulation between the first nanostructure field-effect transistor 1810a and the second nanostructure field-effect transistor 1810b, thereby improving device performance. For example, as the structural size continues to shrink (e.g., 3 nm or smaller), the lateral space (along the z-axis) between the first nanostructure field-effect transistor 1810a and the second nanostructure field-effect transistor 1810b shrinks, which can cause leakage current in both transistors. The fifth dielectric layer 1902 can reduce leakage current, thereby improving the device performance of the first nanostructure field-effect transistor 1810a and / or the second nanostructure field-effect transistor 1810b.

[0275] Since the sixth dielectric structure 1806a is located on the second dielectric fin 502b and the seventh dielectric structure 1806b is located on the fourth dielectric fin 502d, the fifth dielectric layer 1902 is formed in a self-aligned manner. For example, during the deposition of the fourth dielectric material, the fourth dielectric material self-aligns with the first sidewall of the sixth dielectric structure 1806a (e.g., the sidewall of the first vertical portion of the sixth dielectric structure 1806a) and the first sidewall of the seventh dielectric structure 1806b (e.g., the sidewall of the second vertical portion of the seventh dielectric structure 1806b). Therefore, the fifth dielectric layer 1902 is formed in a self-aligned manner, with the fifth dielectric layer self-aligned (along the z-axis). Therefore, as the structure size continues to shrink (e.g., 3 nm or smaller), the method described herein can improve the device performance of the first nanostructure field-effect transistor 1810a and / or the second nanostructure field-effect transistor 1810b.

[0276] Although not illustrated, it should be understood that interconnect structures can be formed on the first nanostructure field-effect transistor 1810a, the second nanostructure field-effect transistor 1810b, the interlayer dielectric layer 1004, the fourth dielectric layer 1506, and the fifth dielectric layer 1902 to electrically couple various electronic devices (such as the first nanostructure field-effect transistor 1810a, the second nanostructure field-effect transistor 1810b, and similar electronic devices) of the semiconductor device 1904 together in a predefined manner. For example, the interconnect structure can be formed by (1) forming a conductive power / drain contact (such as a metal contact) through the interlayer dielectric layer 1004 to the first source / drain region 902 and / or the second source / drain region 904; (2) forming a conductive gate contact (such as a metal contact) through the fourth dielectric layer 1506 and / or the fifth dielectric layer 1902 to the gate structure 1502; (3) forming additional interlayer dielectric layers stacked on the interlayer dielectric layer 1004, the fourth dielectric layer 1506 and the fifth dielectric layer 1902; and (4) forming conductive lines (such as metal lines) and conductive vias (such as metal vias) in the additional interlayer dielectric layer stack, so that various electronic devices of the semiconductor device 1904 (such as the first nanostructure field-effect transistor 1810a, the second nanostructure field-effect transistor 1810b or the like) are electrically coupled together in a predefined manner.

[0277] In some embodiments, the source / drain contacts can be formed using a self-aligned contact process. For example, the chemical compositions of the fourth dielectric layer 1506 and the fifth dielectric layer 1902 differ from those of the interlayer dielectric layer 1004 as described above, therefore the interlayer dielectric layer 1004 can be selectively etched. Furthermore, the fourth dielectric layer 1506 and the fifth dielectric layer 1902 cover the gate structure 1502 but not the interlayer dielectric layer 1004, as described above. Therefore, an etching process can be performed to selectively etch the interlayer dielectric layer 1004, thereby forming source / drain contact openings (and / or trenches) in the interlayer dielectric layer 1004 to expose the source / drain regions. A conductive material such as tungsten, copper, or the like is then filled into the source / drain contact openings (and / or trenches), and a planarization process is performed on the conductive material to flush with the conductive material as the source / drain region contacts. It should be understood that a silicide process may be performed to form a silicide layer on the source / drain regions exposed by the contact openings (and / or trenches) before the conductive material is filled into the source / drain contact openings (and / or trenches).

[0278] Because the etching process selectively etches the interlayer dielectric layer 1004, it does not expose the gate structure 1502 (e.g., it does not etch the fourth dielectric layer 1506 and the fifth dielectric layer 1902 to expose the gate structure 1502). Therefore, if the source / drain junction opening (and / or trench) is too large and / or misaligned, conductive material (or silicide layer) will not be deposited on the gate structure 1502, thereby avoiding an electrical short circuit between the gate structure 1502 and the source / drain regions (such as the first source / drain region 902 and / or the second source / drain region 904). Conversely, conductive material (and silicide layer) can be deposited to self-align the conductive material with the source / drain regions (such as the first source / drain region 902 and / or the second source / drain region 904). In summary, in some embodiments, the fourth dielectric layer 1506 can be regarded as a first self-aligned contact dielectric structure, and the fifth dielectric layer 1902 can be regarded as a second self-aligned contact dielectric structure.

[0279] In some embodiments, the semiconductor device 1904 (such as an integrated circuit) is completed after the interconnect structure is formed. At least for the reasons stated above, the space between the first nanostructure field-effect transistor 1810a and the second nanostructure field-effect transistor 1810b of the semiconductor device 1904 formed by the method described herein is reduced (e.g., the lateral space (along the z-axis) between the second nanostructure stack 1302b and the fifth nanostructure stack 1302e is less than 40 nm). In summary, the method described herein, as the structural size continues to shrink (e.g., 3 nm or smaller), can improve throughput, prevent device failure, or improve device performance, etc., as detailed above.

[0280] Figures 20A to 20CThese are various figures showing a semiconductor device 1904 with reduced space between nanostructured field-effect transistors 1810 in some embodiments. Figure 20A This shows a perspective view of a semiconductor device 1904 with reduced space between nanostructured field-effect transistors 1810 in some embodiments. Figure 20B show Figure 20A Semiconductor devices 1904 along Figure 20A A sectional view of section line AA. Figure 20C show Figure 20A Semiconductor devices 1904 along Figure 20A The sectional view of section line BB.

[0281] like Figures 20A to 20C As shown, the second plurality of dielectric structures 1806 extend laterally (along the x-axis) such that the second plurality of dielectric structures 1806 undercut the lower surface of the corresponding first sidewall spacer 702. For example, a sixth dielectric structure 1806a (and a seventh dielectric structure 1806b) extends laterally (along the x-axis) such that the sixth dielectric structure 1806a (and the seventh dielectric structure 1806b) undercuts the lower surface of one of the first sidewall spacers 702 (e.g., extending (along the z-axis) between the first source / drain regions 902 of the first pair 902a, the second pair 902b, the fifth pair 902c, and the sixth pair 902d). In some embodiments, the sixth dielectric structure 1806a (and the seventh dielectric structure 1806b) contacts (e.g., directly contacts) the lower surface of one of the first sidewall spacers 702. In other embodiments, the first gate structure 1502a (and the third gate structure 1502c), the second etch stop layer 1504, and the fourth dielectric layer 1506 can undercut the lower surface of one of the first sidewall spacers 702.

[0282] In some embodiments, a sixth dielectric structure 1806a (and a seventh dielectric structure 1806b) extends laterally (along the x-axis) between opposing inner sidewalls of the first etch stop layer 1002. For example, the first etch stop layer 1002 has opposing first inner sidewalls 2002 and second inner sidewalls 2004. The first inner sidewalls 2002 and second inner sidewalls 2004 extend along the outer sidewalls of one of the first sidewall spacers 702 (along the y-axis). The sixth dielectric structure 1806a (and the seventh dielectric structure 1806b) extends laterally (along the x-axis) between the first inner sidewalls 2002 and second inner sidewalls 2004. In some embodiments, the sixth dielectric structure 1806a (and the seventh dielectric structure 1806b) contacts (e.g., directly contacts) the first inner sidewalls 2002 and second inner sidewalls 2004.

[0283] Figure 21 In some embodiments, Figures 20A to 20Csemiconductor devices along Figure 20A The sectional view with section line BB. To make the accompanying drawings clear, Figure 21 Labels that do not include certain structural features.

[0284] like Figure 21 As shown, the fourth dielectric layer 1506 has a first height H1. In some embodiments, the first height H1 is between about 5 nm and about 50 nm. The dielectric fin 502 has a second height H2. The second height H2 may be between about 30 nm and about 80 nm. The nanostructure stack 1302 has a third height H3 (e.g., the distance between the uppermost surface of the uppermost nanostructure 1304 of the first nanostructure stack 1302a and the lowermost surface of the lowermost nanostructure 1304 of the first nanostructure stack 1302a). The third height H3 may be between about 30 nm and about 80 nm. In some embodiments, the third height H3 is substantially equal to the second height H2. In some embodiments, the third height H3 is different from the second height H2 (e.g., the third height H3 is smaller than the second height H2).

[0285] The second plurality of dielectric structures 1806 each have a vertical portion 2102 (extending along the y-axis) and a lateral portion 2104 (extending along the z-axis). For example, the sixth dielectric structure 1806a has a first vertical portion 2102a (extending along the y-axis) and a first lateral portion 2104a (extending along the z-axis). The first lateral portion 2104a extends from the first vertical portion 2102a in a first direction (along the z-axis). The seventh dielectric structure 1806b has a second vertical portion 2102b (extending along the y-axis) and a second lateral portion 2104b (extending along the z-axis). The second lateral portion 2104b extends from the second vertical portion 2102b in a second direction (along the z-axis), and the second direction is opposite to the first direction.

[0286] The second plurality of dielectric structures 1806 has a fourth height H4. The fourth height H4 corresponds to the height of the vertical portion 2102 of the second plurality of dielectric structures 1806. In some embodiments, the fourth height H4 is an overall height, such as the distance between the uppermost surface and the lowermost surface of the sixth dielectric structure 1806a. In some embodiments, the ratio between the second height H2 and the fourth height H4 is between 3:5 and 16:1. In other embodiments, the ratio between the second height H2 and the fourth height H4 is between 8:5 and 6:1. In other embodiments, the fourth height H4 is between about 5 nm and about 50 nm.

[0287] The second plurality of dielectric structures 1806 has a fifth height H5. The fifth height H5 corresponds to the height of the lateral portion 2104 of the second plurality of dielectric structures 1806. In some embodiments, the difference between the fourth height H4 and the fifth height H5 is greater than or equal to 3 nm. In other embodiments, the difference between the fourth height H4 and the fifth height H5 is between about 3 nm and 47 nm. In other embodiments, the fifth height H5 is between about Between approximately 47nm.

[0288] Nanostructure 1304 has a first width W1. In some embodiments, the first width W1 is between about 50 nm and about 150 nm. Nanostructure 1304 has a sixth height H6. The sixth height H6 may be between about 3 nm and about 10 nm. The first distance D1 between the nanostructures 1304 of the nanostructure stack 1302 and each other may be between about 3 nm and about 15 nm. In some embodiments, the nanostructure stack 1302 may include about 2 to 10 nanostructures 1304.

[0289] The second plurality of dielectric structures 1806 has a second width W2. In some embodiments, the ratio of the second width W2 to the fourth height H4 is between 1:10 and 20:1. In other embodiments, the ratio of the second width W2 to the first width W1 is between 1:30 and 1:1. In other embodiments, the second width W2 is between about 5 nm and about 100 nm.

[0290] The fifth dielectric layer 1902 extends from the lower surface of the recessed dielectric fin 1802 toward the semiconductor substrate 212 by a second distance D2 (along the y-axis). In other words, the second distance D2 corresponds to the distance from the lowermost surface of the fifth dielectric layer 1902 to the lowermost surface of the recessed dielectric fin 1802. In some embodiments, the second distance D2 is between about 20 nm and about 100 nm.

[0291] Figure 22 In some embodiments, Figure 21 Perspective view of region 2106 of semiconductor device 1904.

[0292] like Figure 22 As shown, a first vertical portion 2102a extends from the second dielectric fin 502b (along the y-axis) to the first gate dielectric structure 1808a. A first lateral portion 2104a extends from the first vertical portion 2102a (along the z-axis). In some embodiments, the sixth dielectric structure 1806a has a first peripheral portion 2202 and a second peripheral portion 2204. The first peripheral portion 2202 and the second peripheral portion 2204 are separate (along the x-axis).

[0293] A first vertical portion 2102a extends (along the x-axis) between a first peripheral portion 2202 and a second peripheral portion 2204. A first lateral portion 2104a extends (along the x-axis) between the first peripheral portion 2202 and the second peripheral portion 2204. The first peripheral portion 2202 and the second peripheral portion 2204 are located (e.g., directly located) below the lower surface of one of the first sidewall spacers 702. In some embodiments, the outer sidewalls of the first peripheral portion 2202 and the second peripheral portion 2204 are substantially aligned with the outer sidewalls of one of the first sidewall spacers 702, respectively. In other embodiments, the outer sidewall of the first peripheral portion 2202 may contact (e.g., directly contact) the second inner sidewall 2004 of the first etch stop layer 1002 (see...). Figure 20C In other embodiments, the outer sidewall of the second peripheral portion 2204 may contact (e.g., directly contact) the first inner sidewall 2002 of the first etch stop layer 1002 (see...). Figure 20C ).

[0294] The sixth dielectric structure 1806a has a first upper surface 2208 and a second upper surface 2210. The first upper surface 2208 corresponds to the upper surface of the first vertical portion 2102a. The second upper surface 2210 corresponds to the upper surface of the first lateral portion 2104a.

[0295] The first upper surface 2208 is located on the second upper surface 2210. In some embodiments, the first upper surface 2208 is the uppermost surface of the sixth dielectric structure 1806a. The second upper surface 2210 is laterally located (along the z-axis) between the first upper surface 2208 and the second dielectric fin 502b (see...). Figure 21 The first upper surface 2208 is laterally located (along the z-axis) between the second upper surface 2210 and the first gate structure 1502a (see...). Figure 21 ).

[0296] The first gate dielectric structure 1808a extends along the first upper surface 2208 of the sixth dielectric structure 1806a. In some embodiments, the first gate dielectric structure 1808a also extends along the first sidewall of the first gate dielectric structure 1808a, the first sidewall of the second dielectric fin 502b, the upper surface of the second fin 210b, the sidewall of the first dielectric fin 502a, the upper surface of the first dielectric fin 502a, and the upper surface of the first fin 210a (see...). Figure 20BA first sidewall of the first gate dielectric structure 1808a extends vertically (along the y-axis) from the first upper surface 2208 to the second dielectric fin 502b. In some embodiments, the first sidewall of the first gate dielectric structure 1808a is substantially aligned with the first sidewall of the second dielectric fin 502b. In other embodiments, the first gate dielectric structure 1808a extends continuously along the first upper surface 2208, the sidewall of the first gate dielectric structure 1808a, the sidewall of the second dielectric fin 502b, the upper surface of the second fin 210b, the sidewall of the first dielectric fin 502a, the upper surface of the first dielectric fin 502a, and the upper surface of the first fin 210a.

[0297] The first gate dielectric structure 1808a has a first sidewall and a second sidewall on both sides. In other words, the second sidewall of the first gate dielectric structure 1808a is laterally separated from the first sidewall (along the z-axis). The second sidewall of the first gate dielectric structure 1808a extends vertically from the first upper surface 2208 to the second upper surface 2210 (along the y-axis). In some embodiments, the second sidewall of the first gate dielectric structure 1808a is substantially aligned with one sidewall of the first gate dielectric structure 1808a.

[0298] The third sidewall of the first gate dielectric structure 1808a is opposite to the first sidewall of the first gate dielectric structure 1808a. In other words, the third sidewall of the first gate dielectric structure 1808a is laterally separated from the first sidewall of the first gate dielectric structure 1808a (along the z-axis). The third sidewall of the first gate dielectric structure 1808a extends vertically from the second upper surface 2210 (along the y-axis) to the lower surface of the first gate dielectric structure 1808a (e.g., the lowest surface of the first gate dielectric structure 1808a that contacts the upper surface of the second dielectric fin 502b). The second upper surface 2210 is laterally located (along the z-axis) between the second sidewall and the third sidewall of the first gate dielectric structure 1808a. In some embodiments, the second upper surface 2210 extends from the third sidewall of the first gate dielectric structure 1808a to the second sidewall of the first gate dielectric structure 1808a. In other embodiments, the third sidewall of the first gate dielectric structure 1808a is substantially aligned with the second sidewall of the second dielectric fin 502b (opposite to the first sidewall of the second dielectric fin 502b), and the first sidewall of the second dielectric fin 502b is laterally separated from the second sidewall (along the z-axis).

[0299] In some embodiments, the first upper surface 2208 is higher than the upper surface of the first gate structure 1502a (such as the uppermost surface, see...). Figure 21 In other embodiments, the second upper surface 2210 is lower than the upper surface of the first gate structure 1502a (see...). Figure 21The first upper surface 2208 may be higher than the second etch stop layer 1504. The second upper surface 2210 may be lower than the second etch stop layer 1504. Although Figure 22 Features of the sixth dielectric structure 1806a (such as structural features) are shown, but it should be understood that each of the plurality of dielectric structures may include substantially similar features.

[0300] Figure 23 This is a flowchart 2300 of a method for forming a semiconductor device with reduced space between nanostructured field-effect transistors in some embodiments. Although Figure 23 The flowchart 2300 shown herein illustrates a series of actions or events, but it should be understood that the order in which these actions or events are described is not intended to limit the embodiments. For example, some actions may be performed in a different order, and / or some actions may occur together with other actions or events besides those shown and / or described herein. Furthermore, one or more embodiments need not implement all the actions described herein, and one or more of the actions described herein may be performed by one or more separate actions and / or methods.

[0301] In step 2302, multiple nanostructures are stacked on multiple semiconductor fins, each of the multiple nanostructure stacks comprising multiple stacked nanostructures, and multiple dielectric fins laterally separating the multiple nanostructure stacks, wherein a first dielectric structure is located on the first dielectric fin of the dielectric fin, and a second dielectric structure is located on the second dielectric fin of the dielectric fin, and wherein a third dielectric fin of the fin is laterally located between the first dielectric fin and the second dielectric fin, and laterally located between the first dielectric structure and the second dielectric structure. Figures 1-13 The accompanying drawings of some embodiments correspond to step 2302.

[0302] In step 2304, a plurality of conductive gate structures are formed on the nanostructure stack, on the semiconductor fin, and around the nanostructure of the nanostructure stack. The first dielectric fin laterally separates the first conductive gate structure and the second conductive gate structure of the conductive gate structure. The second dielectric fin laterally separates the third conductive gate structure and the second conductive gate structure of the conductive gate structure. The second conductive gate structure is laterally located between the first dielectric fin and the second dielectric fin. Figure 14 and Figure 15 The series of cross-sectional views of some embodiments shown correspond to step 2304.

[0303] In step 2306, a first dielectric layer is formed to cover the conductive gate structure, the first dielectric structure, and the second dielectric structure. Figure 15 The cross-sectional views of some embodiments shown correspond to step 2306.

[0304] In step 2308, a first opening is formed in the first dielectric layer, wherein the first opening overlaps with the second conductive gate structure, partially overlaps with the first dielectric structure, and partially overlaps with the second dielectric structure. Figure 16 The cross-sectional views of some embodiments shown correspond to step 2308.

[0305] In step 2310, the second conductive gate structure is removed. Figure 17 The cross-sectional views of some embodiments shown correspond to step 2310.

[0306] In step 2312, a portion of the first dielectric structure and a portion of the second dielectric structure under the first opening are removed to form a third dielectric structure on the first fin and a fourth dielectric structure on the second fin, respectively. Figure 18 The cross-sectional views of some embodiments shown correspond to step 2312.

[0307] In step 2314, the nanostructure stack under the first opening is removed and the semiconductor fin under the first opening is recessed to form a second opening under the first opening. Figure 18 The cross-sectional views of some embodiments shown correspond to step 2314.

[0308] In step 2316, a second dielectric layer is formed in the first opening and the second opening, wherein the second dielectric layer at least partially covers the third dielectric structure and the fourth dielectric structure. Figure 19 The cross-sectional views of some embodiments shown correspond to step 2316.

[0309] Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a semiconductor fin that protrudes vertically from a semiconductor substrate. A plurality of semiconductor nanostructures are directly located on the semiconductor fin and vertically stacked. A gate structure is located on the semiconductor fin and surrounds the semiconductor nanostructures. A dielectric fin is located on the semiconductor substrate, wherein the gate structure and the semiconductor nanostructures are located on a first side of the dielectric fin, and wherein the upper surface of the dielectric fin is lower than the upper surface of the gate structure. A dielectric structure is directly located on the dielectric fin, wherein the first upper surface of the dielectric structure is higher than the upper surface of the gate structure. A dielectric layer is at least partially located on the semiconductor substrate, wherein the dielectric layer is located on a second side of the dielectric fin, and the first and second sides of the dielectric fin are opposite each other, wherein the upper surface of the dielectric layer is higher than the upper surface of the gate structure and the first upper surface of the dielectric structure, and wherein the lower surface of the dielectric layer is lower than the upper surface of the dielectric fin.

[0310] In some embodiments, the dielectric structure has an L-shaped profile.

[0311] In some embodiments, the dielectric structure includes a second upper surface, which is located between the first upper surface of the dielectric structure and the upper surface of the dielectric fin.

[0312] In some embodiments, the first upper surface of the dielectric structure is laterally located between the second upper surface of the dielectric structure and the gate structure.

[0313] In some embodiments, the semiconductor device further includes: a gate dielectric structure located between the gate structure and the semiconductor fin, wherein the gate dielectric structure separates the dielectric fin from the gate structure and separates the dielectric structure from the gate structure.

[0314] In some embodiments, the gate dielectric structure extends continuously along the upper surface of the semiconductor fin, the first sidewall of the dielectric fin, the first sidewall of the dielectric structure, and the first upper surface of the dielectric structure.

[0315] In some embodiments, the second sidewall of the dielectric structure is opposite to the first sidewall of the dielectric structure and substantially aligned with the sidewall of the gate dielectric structure.

[0316] In some embodiments, the dielectric structure includes a third sidewall, which is opposite to the first sidewall of the dielectric structure; and a second sidewall of the dielectric structure is laterally located between the first sidewall and the third sidewall of the dielectric structure.

[0317] In some embodiments, the second upper surface of the dielectric structure extends laterally from the third sidewall of the dielectric structure to the second sidewall of the dielectric structure; and the second upper surface of the dielectric structure is located vertically between the first upper surface of the dielectric structure and the upper surface of the dielectric fin.

[0318] In some embodiments, the third sidewall of the dielectric structure is substantially aligned with the second sidewall of the dielectric fin, and the second sidewall of the dielectric fin is opposite to the first sidewall of the dielectric fin.

[0319] Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a first semiconductor fin and a second semiconductor fin, protruding perpendicularly from a semiconductor substrate, wherein the second semiconductor fin and the first semiconductor fin are laterally separated in a first direction, wherein the first semiconductor fin and the second semiconductor fin extend laterally in a second direction and are parallel to each other, and wherein the second direction is substantially perpendicular to the first direction. A first gate structure is located on the first semiconductor fin. A second gate structure is located on the second semiconductor fin and is laterally separated from the first gate structure in the first direction. A first dielectric fin is located on the semiconductor substrate, wherein the first dielectric fin is located between the first semiconductor fin and the second semiconductor fin, and between the first gate structure and the second gate structure. A second dielectric fin is located on the semiconductor substrate and is laterally separated from the first dielectric fin in the first direction, wherein the second dielectric fin is located between the first semiconductor fin and the second semiconductor fin, and between the first gate structure and the second gate structure. A first dielectric structure is located on the first dielectric fin. A second dielectric structure is located on the second dielectric fin and is laterally separated from the first semiconductor fin in a first direction. A dielectric layer is at least partially located on the semiconductor substrate, wherein the first dielectric structure laterally separates the dielectric layer from a first portion of the first gate structure, and the second dielectric structure laterally separates the dielectric layer from a first portion of the second gate structure.

[0320] In some embodiments, the semiconductor device further includes: a fourth dielectric structure located on and partially covering the first gate structure; and a fifth dielectric structure located on and partially covering the second gate structure, wherein: a dielectric layer is laterally located between the fourth and fifth dielectric structures; the dielectric layer partially covers the first and second dielectric structures; and the lowermost surface of the dielectric layer is lower than the lowermost surface of the fourth and fifth dielectric structures.

[0321] In some embodiments, the first dielectric structure has an L-shaped profile; and the second dielectric structure has an L-shaped profile.

[0322] In some embodiments, the first upper surface of the first dielectric structure is higher than the upper surface of the first gate structure; the second upper surface of the first dielectric structure is located between the first upper surface of the first dielectric structure and the upper surface of the first dielectric fin; the first upper surface of the second dielectric structure is higher than the upper surface of the second gate structure; the second upper surface of the second dielectric structure is located between the first upper surface of the second dielectric structure and the upper surface of the second dielectric fin; and the second upper surface of the first dielectric structure and the second upper surface of the second dielectric structure are laterally located between the first upper surface of the first dielectric structure and the first upper surface of the second dielectric structure.

[0323] In some embodiments, the semiconductor device further includes: a plurality of vertically stacked first semiconductor nanostructures directly located on a first semiconductor fin, wherein the first semiconductor nanostructures extend from a first source / drain region to a second source / drain region in a second direction; and a plurality of vertically stacked second semiconductor nanostructures directly located on a second semiconductor fin, wherein the second semiconductor nanostructures extend from a third source / drain region to a fourth source / drain region in a second direction, and wherein the third source / drain region and the fourth source / drain region are separated from the first source / drain region and the second source / drain region in a first direction.

[0324] In some embodiments, the first gate structure extends around the first semiconductor nanostructure, and the second gate structure extends around the second semiconductor nanostructure.

[0325] In some embodiments, the semiconductor device further includes: a third dielectric fin located on the semiconductor substrate and laterally separated from the first dielectric fin and the second dielectric fin, wherein the third dielectric fin is located between the first dielectric fin and the second dielectric fin, and wherein the upper surface of the third dielectric fin is lower than the upper surfaces of the first dielectric fin and the second dielectric fin.

[0326] In some embodiments, a first dielectric structure extends vertically from the upper surface of a first dielectric fin; and a second dielectric structure extends vertically from the upper surface of a second dielectric fin.

[0327] In some embodiments, a dielectric layer covers a third dielectric fin; a first portion of the dielectric layer extends vertically toward a semiconductor substrate between the first and third dielectric fins; a second portion of the dielectric layer extends vertically toward a semiconductor substrate between the second and third dielectric fins; the lower surface of the first portion of the dielectric layer is rounded; and the lower surface of the second portion of the dielectric layer is rounded.

[0328] Some embodiments of the present invention provide a method for forming a semiconductor device. The method includes receiving a workpiece. The workpiece includes a first dielectric fin located on a semiconductor substrate and laterally positioned between a first plurality of semiconductor nanostructures and a second plurality of semiconductor nanostructures; a second dielectric fin located on the semiconductor substrate and laterally positioned between a third plurality of semiconductor nanostructures and a second plurality of semiconductor nanostructures; a first conductive gate structure located on the semiconductor substrate and surrounding the first plurality of semiconductor nanostructures; a second conductive gate structure located on the semiconductor substrate and surrounding the second plurality of semiconductor nanostructures; a third conductive gate structure located on the semiconductor substrate and surrounding the third plurality of semiconductor nanostructures, wherein the second conductive gate structure is located between the first conductive gate structure and the third conductive gate structure and is laterally separated from the first conductive gate structure and the third conductive gate structure; a first dielectric structure directly located on the first dielectric fin, wherein the first dielectric structure and the first dielectric fin laterally separate the first conductive gate structure and the second conductive gate structure; and a second dielectric structure directly located on the second dielectric fin, wherein the second dielectric structure and the second dielectric fin laterally separate the third conductive gate structure and the second conductive gate structure. A first dielectric layer is formed on a first dielectric fin, a second dielectric fin, a first plurality of semiconductor nanostructures, a second plurality of semiconductor nanostructures, a third plurality of semiconductor nanostructures, a first dielectric structure, a second dielectric structure, a first conductive gate structure, a second conductive gate structure, and a third conductive gate structure. A first opening is formed in the first dielectric layer, wherein the first opening at least partially overlaps with the first dielectric structure, the second dielectric structure, and the second conductive gate structure. The second conductive gate structure is removed. A portion of the first dielectric structure under the first opening is removed to form a third dielectric structure directly located on the first dielectric fin. A portion of the second dielectric structure under the first opening is removed to form a fourth dielectric structure directly located on the second dielectric fin. The second plurality of semiconductor nanostructures are removed to form a second opening under the first opening. A second dielectric layer is formed in the first and second openings, and at least partially covers the third and fourth dielectric structures.

[0329] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: A semiconductor fin protrudes vertically from a semiconductor substrate; Multiple semiconductor nanostructures are located directly on the semiconductor fin and stacked vertically. A gate structure is located on the semiconductor fin and surrounds the plurality of said semiconductor nanostructures; A dielectric fin is located on the semiconductor substrate, wherein the gate structure and a plurality of said semiconductor nanostructures are located on a first side of the dielectric fin, and wherein the upper surface of the dielectric fin is lower than the upper surface of the gate structure; A dielectric structure is located directly on the dielectric fin, wherein a first upper surface of the dielectric structure is higher than the upper surface of the gate structure; and A dielectric layer is at least partially located on the semiconductor substrate, wherein the dielectric layer is located on a second side of the dielectric fin and the first side of the dielectric fin is opposite to the second side, wherein the upper surface of the dielectric layer is higher than the upper surface of the gate structure and the first upper surface of the dielectric structure, and wherein the lower surface of the dielectric layer is lower than the upper surface of the dielectric fin.

2. The semiconductor device of claim 1, wherein the dielectric structure has an L-shaped profile.

3. The semiconductor device of claim 1, wherein the dielectric structure includes a second upper surface disposed between the first upper surface of the dielectric structure and the upper surface of the dielectric fin.

4. The semiconductor device of claim 3, wherein the first upper surface of the dielectric structure is laterally located between the second upper surface of the dielectric structure and the gate structure.

5. The semiconductor device of claim 1, further comprising: A gate dielectric structure is located between the gate structure and the semiconductor fin, wherein the gate dielectric structure separates the dielectric fin from the gate structure and separates the dielectric structure from the gate structure.

6. The semiconductor device of claim 5, wherein the gate dielectric structure extends continuously along the upper surface of the semiconductor fin, the first sidewall of the dielectric fin, the first sidewall of the dielectric structure, and the first upper surface of the dielectric structure.

7. The semiconductor device of claim 6, wherein the second sidewall of the dielectric structure is opposite to the first sidewall of the dielectric structure and substantially aligned with the sidewall of the gate dielectric structure.

8. The semiconductor device of claim 7, wherein: The dielectric structure includes a third sidewall, and the third sidewall of the dielectric structure is opposite to the first sidewall of the dielectric structure; and The second sidewall of the dielectric structure is located laterally between the first sidewall and the third sidewall of the dielectric structure.

9. The semiconductor device of claim 8, wherein: The second upper surface of the dielectric structure extends laterally from the third sidewall of the dielectric structure to the second sidewall of the dielectric structure; and The second upper surface of the dielectric structure is located vertically between the first upper surface of the dielectric structure and the upper surface of the dielectric fin.

10. The semiconductor device of claim 9, wherein the third sidewall of the dielectric structure is substantially aligned with the second sidewall of the dielectric fin, and the second sidewall of the dielectric fin is opposite to the first sidewall of the dielectric fin.

11. A semiconductor device, comprising: A first semiconductor fin and a second semiconductor fin protrude vertically from a semiconductor substrate, wherein the second semiconductor fin and the first semiconductor fin are laterally separated in a first direction, wherein the first semiconductor fin and the second semiconductor fin extend laterally in a second direction and are parallel to each other, and wherein the second direction is substantially perpendicular to the first direction. A first gate structure is located on the first semiconductor fin; A second gate structure is located on the second semiconductor fin and is laterally separated from the first gate structure in the first direction; A first dielectric fin is located on the semiconductor substrate, wherein the first dielectric fin is located between the first semiconductor fin and the second semiconductor fin, and between the first gate structure and the second gate structure; A second dielectric fin is located on the semiconductor substrate and is laterally separated from the first dielectric fin in the first direction, wherein the second dielectric fin is located between the first semiconductor fin and the second semiconductor fin, and between the first gate structure and the second gate structure. A first dielectric structure is located on the first dielectric fin; A second dielectric structure is located on the second dielectric fin and is laterally separated from the first semiconductor fin in the first direction; and A dielectric layer is at least partially located on the semiconductor substrate, wherein a first dielectric structure laterally separates the dielectric layer from a first portion of the first gate structure, and a second dielectric structure laterally separates the dielectric layer from a first portion of the second gate structure.

12. The semiconductor device of claim 11, further comprising: A fourth dielectric structure is located on the first gate structure and partially located on the first dielectric structure; A fifth dielectric structure is located on and partially on the second gate structure, wherein: The dielectric layer is laterally located between the fourth dielectric structure and the fifth dielectric structure; The dielectric layer is partially located on the first dielectric structure and the second dielectric structure; and The lowest surface of the dielectric layer is lower than the lowest surface of the fourth dielectric structure and the lowest surface of the fifth dielectric structure.

13. The semiconductor device of claim 11, wherein: The first dielectric structure has an L-shaped profile; and The second dielectric structure has an L-shaped profile.

14. The semiconductor device of claim 13, wherein: The first upper surface of the first dielectric structure is higher than the upper surface of the first gate structure; The second upper surface of the first dielectric structure is located between the first upper surface of the first dielectric structure and the upper surface of the first dielectric fin; The first upper surface of the second dielectric structure is higher than the upper surface of the second gate structure; The second upper surface of the second dielectric structure is located between the first upper surface of the second dielectric structure and the upper surface of the second dielectric fin; and The second upper surface of the first dielectric structure and the second upper surface of the second dielectric structure are laterally located between the first upper surface of the first dielectric structure and the first upper surface of the second dielectric structure.

15. The semiconductor device of claim 11, further comprising: Multiple first semiconductor nanostructures are vertically stacked and located directly on the first semiconductor fin, wherein the multiple first semiconductor nanostructures extend from a first source / drain region to a second source / drain region in the second direction. as well as A plurality of vertically stacked second semiconductor nanostructures are located directly on the second semiconductor fin, wherein the plurality of second semiconductor nanostructures extend from a third source / drain region to a fourth source / drain region in the second direction, and wherein the third source / drain region and the fourth source / drain region are separated from the first source / drain region and the second source / drain region in the first direction.

16. The semiconductor device of claim 15, wherein: The first gate structure extends around a plurality of the first semiconductor nanostructures; and The second gate structure extends around a plurality of the second semiconductor nanostructures.

17. The semiconductor device of claim 11, further comprising: A third dielectric fin is located on the semiconductor substrate and is laterally separated from the first dielectric fin and the second dielectric fin, wherein the third dielectric fin is located between the first dielectric fin and the second dielectric fin, and wherein the upper surface of the third dielectric fin is lower than the upper surfaces of the first dielectric fin and the second dielectric fin.

18. The semiconductor device of claim 17, wherein: The first dielectric structure extends vertically from the upper surface of the first dielectric fin; and The second dielectric structure extends vertically from the upper surface of the second dielectric fin.

19. The semiconductor device of claim 18, wherein: The dielectric layer is located on the third dielectric fin; The first portion of the dielectric layer extends vertically toward the semiconductor substrate between the first dielectric fin and the third dielectric fin; The second portion of the dielectric layer extends vertically toward the semiconductor substrate between the second dielectric fin and the third dielectric fin; The lower surface of the first portion of the dielectric layer is rounded; and The lower surface of the second part of the dielectric layer is rounded.

20. A semiconductor device, comprising: Multiple first semiconductor nanostructures are located on a first semiconductor fin; Multiple second semiconductor nanostructures are located on a second semiconductor fin; A first gate structure is located on the first semiconductor fin and around a plurality of the first semiconductor nanostructures; A second gate structure is located on the second semiconductor fin and around a plurality of the second semiconductor nanostructures; A first dielectric fin is laterally located between a plurality of first semiconductor nanostructures and a plurality of second semiconductor nanostructures; A second dielectric fin is laterally located between a plurality of first semiconductor nanostructures and a plurality of second semiconductor nanostructures; A first dielectric structure is located on the first dielectric fin, wherein the first dielectric structure has a first L-shaped profile; A second dielectric structure is located on the second dielectric fin, wherein the second dielectric structure has a second L-shaped profile, and wherein the first L-shaped profile and the second L-shaped profile face opposite directions; and A dielectric layer laterally separates the first dielectric fin and the second dielectric fin, laterally separates the first gate structure and the second gate structure, and laterally separates the first dielectric structure and the second dielectric structure. The dielectric layer extends vertically from its lower surface to its upper surface. The lower surface of the dielectric layer is lower than the upper surface of the first semiconductor fin. The upper surface of the dielectric layer is higher than the first dielectric structure. The first dielectric structure laterally separates the dielectric layer and the first gate structure, and the second dielectric structure laterally separates the dielectric layer and the second gate structure.

21. A method for forming a semiconductor device, comprising: Receive a workpiece, and the workpiece includes: A dielectric fin-like structure is located on a semiconductor substrate and between a plurality of first semiconductor nanostructures and a plurality of second semiconductor nanostructures; A first conductive gate structure is located on the semiconductor substrate and around a plurality of first semiconductor nanostructures; A second conductive gate structure is located on the semiconductor substrate and around a plurality of the second semiconductor nanostructures; and A dielectric fin cap is located on the dielectric fin, wherein the dielectric fin cap and the dielectric fin are laterally located between the first conductive gate structure and the second conductive gate structure, and wherein the upper surface of the first conductive gate structure and the upper surface of the second conductive gate structure are perpendicularly located between the first upper surface of the dielectric fin cap and the semiconductor substrate. A dielectric layer is formed on the dielectric fin, the plurality of first semiconductor nanostructures, the plurality of second semiconductor nanostructures, the first conductive gate structure, the second conductive gate structure, and the dielectric fin cover. A first opening is formed in the dielectric layer, wherein the first opening is partially located on the dielectric fin cap and the second conductive gate structure; and A first etching process is performed to remove the second conductive gate structure, and the first etching process exposes the second conductive gate structure to a first etchant through the first opening.

22. The method of forming a semiconductor device as claimed in claim 21, further comprising: After the second conductive gate structure is removed, a second etching process is performed to remove a plurality of the second semiconductor nanostructures, and the second etching process exposes the plurality of the second semiconductor nanostructures to a second etchant through the first opening, wherein the second etching process removes a first portion of the dielectric fin cap, and wherein the second etching process forms a second opening within the outer boundary of the first opening.

23. The method of forming a semiconductor device as claimed in claim 22, further comprising: A dielectric material is deposited in the first opening and the second opening, wherein the dielectric material is deposited on the second upper surface of the dielectric fin cover, and the step of removing the first portion of the dielectric fin cover exposes the second upper surface of the dielectric fin cover.

24. The method of forming a semiconductor device as claimed in claim 23, further comprising: Before forming the dielectric layer, an etch stop layer is formed on the first conductive gate structure and the second conductive gate structure, wherein the upper and lower surfaces of the etch stop layer are both vertically located between the first upper and lower surfaces of the dielectric fin cover, and wherein the step of forming the first opening in the dielectric layer includes performing a third etch process, and the third etch process ends on the etch stop layer.

25. A method for forming a semiconductor device, comprising: A first stacked semiconductor structure is formed on a first semiconductor fin; A second stacked semiconductor structure is formed on a second semiconductor fin; A dielectric fin is formed, which is laterally located between the first stacked semiconductor structure and the second stacked semiconductor structure; A dielectric band structure is formed on the dielectric fin, and the dielectric band structure is laterally located between the first stacked semiconductor structure and the second stacked semiconductor structure; A portion of the first stacked semiconductor structure is removed to form a third stacked semiconductor structure; A portion of the second stacked semiconductor structure is removed to form a fourth stacked semiconductor structure; A portion of the dielectric strip structure is removed to form a dielectric structure on the dielectric fin, and the dielectric structure is laterally located between the third stacked semiconductor structure and the fourth stacked semiconductor structure. The third stacked semiconductor structure and the fourth stacked semiconductor structure are etched to form a first nanostructure stacked on the first semiconductor fin and a second nanostructure stacked on the second semiconductor fin. A gate layer is formed on the first semiconductor fin, on the second semiconductor fin, on the dielectric fin, on the dielectric structure, around the first nanostructure stack, and around the second nanostructure stack. The gate layer is recessed below the upper surface of the dielectric structure to form a first gate structure around the first nanostructure stack and on the first side of the dielectric structure, and a second gate structure around the second nanostructure stack and on the second side of the dielectric structure, with the first side and the second side of the dielectric structure facing each other. A dielectric layer is formed on the first gate structure, the second gate structure, the dielectric fin, and the dielectric structure; An opening is formed in the dielectric layer, wherein the opening is located on the dielectric structure and the second gate structure; and After the opening is formed in the dielectric layer, the second gate structure is removed, wherein the opening is used to remove the second gate structure.

26. The method of forming a semiconductor device as claimed in claim 25, wherein the step of removing the second gate structure using the opening comprises: An etching process is performed that exposes the second gate structure to an etchant through the opening.

27. The method of forming a semiconductor device as claimed in claim 25, further comprising: After the opening is formed, the second nanostructure stack is removed, wherein the opening is used to remove the second nanostructure stack.

28. The method of forming a semiconductor device as claimed in claim 27, wherein the step of removing the second nanostructure stack using the opening comprises: A first etching process is performed, which exposes the second nanostructure stacked onto a first etchant through the opening.

29. The method of forming a semiconductor device as claimed in claim 28, wherein the first etching process exposes a portion of the dielectric structure to the first etchant via the opening to remove the portion of the dielectric structure.

30. The method of forming a semiconductor device as claimed in claim 29, wherein the step of removing the second gate structure using the opening comprises: A second etching process is performed, which exposes the second gate structure to a second etchant through the opening, wherein the second etchant is different from the first etchant, and the first etching process is performed after the second etching process.

31. The method of forming a semiconductor device as claimed in claim 30, wherein the uppermost surface of the dielectric structure defines the uppermost surface of the portion of the dielectric structure before the portion of the dielectric structure is removed.

32. A method for forming a semiconductor device, comprising: Receive a workpiece, and the workpiece includes: A first dielectric fin is located on a semiconductor substrate and laterally positioned between a plurality of first semiconductor nanostructures and a plurality of second semiconductor nanostructures; A second dielectric fin is located on the semiconductor substrate and laterally positioned between a plurality of third semiconductor nanostructures and a plurality of second semiconductor nanostructures; A first conductive gate structure is located on the semiconductor substrate and surrounds a plurality of the first semiconductor nanostructures; A second conductive gate structure is located on the semiconductor substrate and surrounds a plurality of second semiconductor nanostructures; A third conductive gate structure is located on the semiconductor substrate and surrounds a plurality of said third semiconductor nanostructures, wherein the second conductive gate structure is located between the first conductive gate structure and the third conductive gate structure and is laterally separated from the first conductive gate structure and the third conductive gate structure; A first dielectric structure is located on the first dielectric fin, wherein the first dielectric structure and the first dielectric fin are laterally separated from the first conductive gate structure and the second conductive gate structure; and A second dielectric structure is located on the second dielectric fin, wherein the second dielectric structure is laterally separated from the second dielectric fin by the third conductive gate structure and the second conductive gate structure. A first dielectric layer is formed on the first dielectric fin, the second dielectric fin, a plurality of first semiconductor nanostructures, a plurality of second semiconductor nanostructures, a plurality of third semiconductor nanostructures, the first dielectric structure, the second dielectric structure, the first conductive gate structure, the second conductive gate structure, and the third conductive gate structure; A first opening is formed in the first dielectric layer, wherein the first opening is at least partially located on the first dielectric structure, the second dielectric structure, and the second conductive gate structure; Remove the second conductive gate structure; Remove a portion of the first dielectric structure below the first opening to form a third dielectric structure on the first dielectric fin; Remove a portion of the second dielectric structure under the first opening to form a fourth dielectric structure on the second dielectric fin; Multiple second semiconductor nanostructures are removed to form a second opening below the first opening; as well as A second dielectric layer is formed in the first opening and the second opening, and is at least partially located on the third dielectric structure and the fourth dielectric structure.

33. The method of forming a semiconductor device as claimed in claim 32, wherein the step of forming the opening in the first dielectric layer comprises: A mask layer is formed on the first dielectric layer, wherein the mask layer includes a third opening to expose a portion of the first dielectric layer; as well as In conjunction with the mask layer on the first dielectric layer, a first etching process is performed on the first dielectric layer to remove that portion of the first dielectric layer.

34. The method of forming a semiconductor device as claimed in claim 33, wherein: The mask layer partially defines the third opening with its opposing first and second sidewalls; The first sidewall of the mask layer is laterally located between the opposing sidewalls of the first dielectric structure; and The second sidewall of the mask layer is laterally located between the opposing sidewalls of the second dielectric structure.

35. The method of forming a semiconductor device as claimed in claim 33, wherein the step of removing the second conductive gate structure comprises: A second etching process is performed on the second conductive gate structure, and the second etching process is different from the first etching process.

36. The method of forming a semiconductor device as claimed in claim 35, wherein the step of forming the second opening comprises: A third etching process is performed on the plurality of second semiconductor nanostructures, the first dielectric structure, and the second dielectric structure, and the third etching process is different from the second etching process, wherein the third etching process removes the plurality of second semiconductor nanostructures, portions of the first dielectric structure, and portions of the second dielectric structure.

37. The method of forming a semiconductor device as claimed in claim 36, wherein the second etching process is an isotropic etching process.

38. The method of forming a semiconductor device as claimed in claim 37, wherein: The workpiece includes a third dielectric fin laterally located between the first dielectric fin and the second dielectric fin; and The third etching process removes the upper portion of the third dielectric fin to form a recessed dielectric fin.

39. The method of forming a semiconductor device as claimed in claim 38, wherein the upper surface of the recessed dielectric fin is lower than the upper surface of the first dielectric fin and the upper surface of the second dielectric fin.

40. The method of forming a semiconductor device as claimed in claim 39, wherein: The workpiece includes a semiconductor fin that protrudes vertically from the semiconductor substrate; Multiple second semiconductor nanostructures are located on the semiconductor fin; as well as The third etching process removes the upper portion of the semiconductor fin.

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