Integrated circuit semiconductor device

Abstract

An integrated circuit semiconductor device is provided. The integrated circuit semiconductor device includes a plurality of cylindrical structures separated from each other on a base, and a plurality of support members having an open area exposing side surfaces of the plurality of cylindrical structures, the plurality of support members being in contact with the side surfaces of the plurality of cylindrical structures and supporting the plurality of cylindrical structures, wherein each of the plurality of support members has two side surfaces having a slope and has a top width smaller than a bottom width in a vertical cross-sectional view.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0138200 filed on October 31, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates to an integrated circuit semiconductor device, and more particularly, to an integrated circuit semiconductor device including a cylindrical structure. Background Art

[0003] For integrated circuit semiconductor devices (eg, dynamic random access memory (DRAM) devices), as integration density increases, the device area decreases, but capacitance needs to be maintained or increased. Therefore, the lower electrode of the capacitor is formed into a three-dimensional cylindrical structure.

[0004] The aspect ratio of a cylindrical structure (e.g., a cylindrical lower electrode) increases depending on the desired capacitance. Consequently, bridging, where cylindrical structures adhere to each other, is likely to occur, making it difficult to form a cylindrical structure. Furthermore, the cylindrical structure may collapse or break before subsequent processes (e.g., the process of forming a dielectric layer). Summary of the Invention

[0005] The inventive concept provides an integrated circuit semiconductor device including cylindrical structures (eg, cylindrical lower electrodes) that are stably arranged without adhering to each other and without collapsing or breaking.

[0006] According to one aspect of the inventive concept, an integrated circuit semiconductor device is provided, comprising: a plurality of cylindrical structures separated from each other on a substrate; and a plurality of support members having opening areas exposing side surfaces of the plurality of cylindrical structures, the plurality of support members contacting the side surfaces of the plurality of cylindrical structures and supporting the plurality of cylindrical structures, wherein, in a vertical cross-sectional view, each of the plurality of support members has two side surfaces with a slope and has a top width that is smaller than a bottom width.

[0007] According to another aspect of the inventive concept, an integrated circuit semiconductor device is provided, comprising: a plurality of cylindrical structures separated from each other on a substrate; and a plurality of support members having opening areas exposing side surfaces of the plurality of cylindrical structures, the plurality of support members being in contact with the side surfaces of the plurality of cylindrical structures, being located at a height lower than the top surfaces of the plurality of cylindrical structures, and supporting the plurality of cylindrical structures.

[0008] The multiple cylindrical structures include a first horizontal electrode portion, a second horizontal electrode portion, and a third horizontal electrode portion, the first horizontal electrode portion having a first height from the base, the second horizontal electrode portion having a second height from the top of the first horizontal electrode portion, and the third horizontal electrode portion having a third height from the top of the second horizontal electrode portion.

[0009] In a vertical cross-sectional view, each of the first and second horizontal electrode portions has two side surfaces with slopes and a top width larger than a bottom width, and the third horizontal electrode portion has two side surfaces with slopes and a top width smaller than a bottom width.

[0010] The side surface of the first horizontal electrode portion and the side surface of the second horizontal electrode portion are connected to the side surface of the third horizontal electrode portion, and when viewed at positive and negative angles, the slope of the side surfaces of the first horizontal electrode portion and the second horizontal electrode portion is opposite to the slope of the side surface of the third horizontal electrode portion.

[0011] According to another aspect of the inventive concept, an integrated circuit semiconductor device is provided, comprising: a plurality of cylindrical structures separated from each other on a substrate; and a plurality of support members having opening areas exposing side surfaces of the plurality of cylindrical structures, the plurality of support members contacting the side surfaces of the plurality of cylindrical structures and supporting the plurality of cylindrical structures.

[0012] The multiple cylindrical structures include a first horizontal electrode portion, a second horizontal electrode portion, and a third horizontal electrode portion, the first horizontal electrode portion having a first height from the base, the second horizontal electrode portion having a second height from the top of the first horizontal electrode portion, and the third horizontal electrode portion having a third height from the top of the second horizontal electrode portion.

[0013] In a vertical cross-sectional view, each of the first and second horizontal electrode portions has two side surfaces with slopes and a top width larger than a bottom width, and the third horizontal electrode portion has two side surfaces with slopes and a top width smaller than a bottom width.

[0014] In the vertical cross-sectional view, the side surface of each of the first horizontal electrode portion and the second horizontal electrode portion has a positive slope, the opposite side surface of each of the first horizontal electrode portion and the second horizontal electrode portion has a negative slope, the side surface of the third horizontal electrode portion connected to the side surface of each of the first horizontal electrode portion and the second horizontal electrode portion has a negative slope, and the opposite side surface of the third horizontal electrode portion connected to the opposite side surface of each of the first horizontal electrode portion and the second horizontal electrode portion has a positive slope.

[0015] In a vertical cross-sectional view, each of the plurality of support members is located at a side surface of the second horizontal electrode portion, has two side surfaces having slopes, and has a top width smaller than a bottom width. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Embodiments of the inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is a plan view schematically illustrating an arrangement of a cylindrical structure of an integrated circuit semiconductor device and a support member supporting the cylindrical structure according to example embodiments;

[0018] Figure 2A and Figure 2B It is along Figure 1 A schematic cross-sectional view of the integrated circuit semiconductor device taken along line II-II in FIG.

[0019] Figure 3 yes Figure 2A An enlarged view of the cylindrical structure and support members in FIG;

[0020] Figure 4A and Figure 4B is a cross-sectional view of an integrated circuit semiconductor device according to an example embodiment;

[0021] Figure 5 yes Figure 4A An enlarged view of the cylindrical structure and support members in FIG;

[0022] Figure 6 is a cross-sectional view for describing a cylindrical structure and a support member of an integrated circuit semiconductor device according to example embodiments;

[0023] Figure 7 is a cross-sectional view for describing a cylindrical structure and a support member of an integrated circuit semiconductor device according to example embodiments;

[0024] Figures 8 to 15 is a cross-sectional view for describing a method of manufacturing an integrated circuit semiconductor device according to example embodiments;

[0025] Figure 16 and Figure 17 is a cross-sectional view for describing a method of manufacturing an integrated circuit semiconductor device according to example embodiments;

[0026] Figure 18 is a schematic layout plan view for describing main elements in a cell array region of a dynamic random access memory (DRAM) device according to example embodiments; and

[0027] 19A to 19Iare diagrams for describing a method of manufacturing a DRAM device according to example embodiments. DETAILED DESCRIPTION

[0028] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent the same elements, and redundant descriptions thereof will be omitted.

[0029] Figure 1 is a plan view schematically illustrating an arrangement of a cylindrical structure of an integrated circuit semiconductor device and a support member supporting the cylindrical structure according to example embodiments.

[0030] For example, the integrated circuit semiconductor device 1 may include a plurality of cylindrical structures 28 separated from each other. The horizontal cross-section of the cylindrical structure 28 may have a substantially circular shape, but exemplary embodiments are not limited thereto. The horizontal cross-section of the cylindrical structure 28 may have other shapes besides a circular shape, such as an elliptical shape, a polygonal shape, etc. In addition, the area of ​​the horizontal cross-section of the cylindrical structure 28 may vary along the height direction. The cylindrical structure 28 may be referred to as a pillar structure. The cylindrical structure 28 may include a metal nitride layer, such as a titanium nitride (TiN) layer or a titanium silicon nitride (Ti—Si—N) layer.

[0031] The cylindrical structures 28 may be repeatedly arranged along a first direction (eg, X direction) and a second direction (eg, Y direction). Figure 1 The number of cylindrical structures 28 shown in FIG. 1 is an example, and more or fewer cylindrical structures may be arranged. For example, when cylindrical structures 28 are lower electrodes of cell capacitors of a dynamic random access memory (DRAM) device, at least several million cylindrical structures 28 may be densely arranged.

[0032] Despite Figure 1 , the cylindrical structures 28 are arranged in a straight line in the first direction (eg, X direction), but the cylindrical structures 28 may be arranged in a zigzag pattern in the first direction (eg, X direction). Figure 1 , the cylindrical structures 28 are arranged in a zigzag pattern in the second direction (eg, Y direction), but the cylindrical structures 28 may be arranged in a straight line in the second direction (eg, Y direction).

[0033] The integrated circuit semiconductor device 1 may include a support 14 supporting a cylindrical structure 28. The support 14 may be referred to as a support pattern. Figure 1 , the supports 14 are shown to be connected to each other, but the supports 14 may be formed in an island-type support pattern or an isolated support pattern separated from each other like islands. The supports 14 may include a silicon nitride layer or a silicon oxynitride layer.

[0034] An opening area OP exposing the side surface (or sidewall) of each cylindrical structure 28 may be formed inside the support member 14. In other words, the opening area OP is formed at the level of the support member 14, thereby exposing the side surface of the cylindrical structure 28. The support member 14 may support the cylindrical structure 28 by partially contacting the side surface of the cylindrical structure 28.

[0035] Despite Figure 1 In the embodiment, the opening area OP exposes the side surfaces of seven cylindrical structures 28, but the embodiment is not limited thereto. When necessary, the opening area OP may expose the side surfaces of at least four cylindrical structures 28. Figure 1 In the top view of FIG, the opening area OP has a trapezoidal shape, but the shape of the opening area OP as seen from the top view may be a polygon, such as a quadrilateral or a pentagon. The embodiment is not limited by the shape of the opening area OP as seen from the top view.

[0036] Figure 2A and Figure 2B It is along Figure 1 Schematic cross-sectional view of the integrated circuit semiconductor device taken along line II-II in FIG. Figure 3 yes Figure 2A Magnified view of the cylindrical structure and support.

[0037] For example, in addition to forming a slit SE inside each cylindrical structure 28, Figure 2B The integrated circuit semiconductor device 1-2 and Figure 2A The following description can be applied to the integrated circuit semiconductor device 1-1. Figure 2A Integrated circuit semiconductor device 1-1 and Figure 2B The integrated circuit semiconductor devices 1-1 and 1-2 may include cylindrical structures 28 separated from each other on a substrate Sb. In some embodiments, the substrate Sb may include a silicon substrate containing silicon (Si) (e.g., crystalline Si, polycrystalline Si, or amorphous Si). In some embodiments, the substrate Sb may include a semiconductor element, such as germanium (Ge).

[0038] In some embodiments, the substrate Sb may include at least one compound semiconductor selected from silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, the substrate Sb may include a silicon-on-insulator (SOI) substrate, a ceramic substrate, a quartz substrate, or a display glass substrate.

[0039] For example, unit elements (not shown) such as various kinds of active elements or passive elements may be formed in the substrate Sb. The unit elements may include transistors of a volatile memory device (eg, a DRAM device) or a nonvolatile memory device (eg, a flash memory device).

[0040] An interlayer insulating layer 10 may be formed on the substrate Sb to cover the cell elements. Contact plugs 11 electrically connected to the cell elements may be formed in the interlayer insulating layer 10. In the case of a DRAM device, the contact plugs 11 may be landing pads connected to the cylindrical lower electrodes of the capacitors. Wires (not shown) connected to the contact plugs 11 may be formed in the interlayer insulating layer 10.

[0041] For example, the cylindrical structure 28 may be a cylindrical lower electrode of a capacitor of a DRAM device. The cylindrical structure 28 may be connected to a source / drain region (not shown) of a transistor (not shown) formed in the substrate Sb of the DRAM device through a contact plug 11. However, the embodiment is not limited to the cylindrical lower electrode of a capacitor of a DRAM device and may be applied to any cylindrical structure 28 having a high aspect ratio and being repeatedly arranged.

[0042] The bottom surface of each cylindrical structure 28 may be fixed to the contact plug 11 on the substrate Sb. The cylindrical structure 28 may have an elongated shape extending in a third direction (e.g., the Z direction) perpendicular to the first and second directions. The cylindrical structure 28 may have an aspect ratio of approximately 8 to approximately 30 (e.g., an aspect ratio of 20), where the aspect ratio is the ratio of the height H to the width W1, W2, W3, W4, W5, or W6. For example, the widths W1 to W6 of the cylindrical structures 28 may be in the range of approximately 30 nm to approximately 100 nm. The height H of the cylindrical structure 28 may be in the range of approximately 500 nm to approximately 4000 nm.

[0043] The gap SE in the form of a void can be formed in Figure 2B In some embodiments, the slit SE may have a central width B that is larger than the upper width A and the lower width C. In some embodiments, the slit SE may be formed when the cylindrical structures 28 are formed. In some embodiments, the slit SE may be formed when the cylindrical structures 28 are shrunk after they are formed.

[0044] As mentioned above, Figure 3 As shown in FIG, the open area OP is formed at the level of the support 14, and there is also an open space below the support 14. Therefore, subsequent processes can also be performed on the portion of the cylindrical structure 28 below the support 14.

[0045] For example, when the cylindrical structure 28 is a cylindrical lower electrode of a DRAM device, a dielectric layer 30 and an upper electrode 32 may be formed on the surface of the cylindrical structure 28 in a subsequent process. The dielectric layer 30 may include a TaO film, a TaAlO film, a TaON film, an AlO film, an HfO film, a ZrO film, a ZrSiO film, a TiO film, a TiAlO film, a (Ba, Sr)TiO (BST) film, a SrTiO (STO) film, a BaTiO (BTO) film, a Pb (Zr, Ti) O (PZT) film, a (Pb, La) (Zr, Ti) O film, a Ba (Zr, Ti) O film, a Sr (Zr, Ti) O film, or a combination thereof.

[0046] The upper electrode 32 may cover the cylindrical structures 28 and completely fill the space between the cylindrical structures 28. The upper electrode 32 may include a metal film, a metal oxide film, or a metal nitride film, such as a Ru film, a RuO film, a Pt film, a PtO film, an Ir film, an IrO film, a SrRuO (SRO) film, a (Ba, Sr)RuO (BSRO) film, a CaRuO (CRO) film, a BaRuO film, a La (Sr, Co) O film, a Ti film, a TiN film, a W film, a WN film, a Ta film, a TaN film, a TiAlN film, a TiSiN film, a TaAlN film, a TaSiN film, or a combination thereof. The capacitor ca1 may be formed by the above process.

[0047] In the following, we will use Figure 2A The structure of the cylindrical structures 28, the intervals between the cylindrical structures 28, and the structure of the support member 14 will be described in detail with reference to the integrated circuit semiconductor device 1-1.

[0048] The cylindrical structure 28 may include a first horizontal electrode portion LV1 having a first height H1 in a third direction (e.g., Z direction), a second horizontal electrode portion LV2 having a second height H2 from the top of the first horizontal electrode portion LV1 in the third direction (e.g., Z direction), and a third horizontal electrode portion LV3 having a third height H3 from the top of the second horizontal electrode portion LV2 in the third direction (e.g., Z direction).

[0049] In this specification, the term "horizontal" refers to a height from the main surface of the substrate Sb in the vertical direction. In other words, "located at the same level" or "located at a certain level" means "having the same height from the main surface of the substrate Sb in the vertical direction" or "located at a certain position", and "located at a low / high level" means "located at a low / high position relative to the main surface of the substrate Sb in the vertical direction."

[0050] The first height H1 of the first horizontal electrode portion LV1 may be greater than the second height H2 of the second horizontal electrode portion LV2 and the third height H3 of the third horizontal electrode portion LV3. The second height H2 of the second horizontal electrode portion LV2 may be approximately equal to the third height H3 of the third horizontal electrode portion LV3. The first height H1, the second height H2, and the third height H3 are arbitrary and do not limit the embodiment.

[0051] Opposing side surfaces of the first horizontal electrode portion LV1 have a slope (also referred to as an inclination or slope). A width W2 of the top of the first horizontal electrode portion LV1 may be greater than a width W1 of the bottom of the first horizontal electrode portion LV1. Opposing side surfaces of the second horizontal electrode portion LV2 have a slope. A width W4 of the top of the second horizontal electrode portion LV2 may be greater than a width W3 of the bottom of the second horizontal electrode portion LV2.

[0052] The opposite sides of the third horizontal electrode portion LV3 have a slope. The width W6 of the top of the third horizontal electrode portion LV3 may be smaller than the width W5 of the bottom of the third horizontal electrode portion LV3. The top and bottom of the first to third horizontal electrode portions LV1 to LV3 may include portions thereof near the top and bottom.

[0053] The side surface LV1a of the first horizontal electrode portion LV1 and the side surface LV2a of the second horizontal electrode portion LV2 may be connected to the side surface LV3a of the third horizontal electrode portion LV3, and the opposite side surface LV1b of the first horizontal electrode portion LV1 and the opposite side surface LV2b of the second horizontal electrode portion LV2 may be connected to the opposite side surface LV3b of the third horizontal electrode portion LV3. When viewed at positive and negative viewing angles, the slope +SL1 of the side surfaces LV1a and LV2a of the first horizontal electrode portion LV1 and the second horizontal electrode portion LV2 and the slope -SL1 of the opposite side surfaces LV1b and LV2b of the first horizontal electrode portion LV1 and the second horizontal electrode portion LV2 may be opposite to the slopes -SL2 and +SL2 of the side surfaces LV3a and LV3b of the third horizontal electrode portion LV3.

[0054] In other words, when viewed at positive and negative viewing angles, the positive slope +SL1 of the side surfaces LV1a and LV2a of the first horizontal electrode portion LV1 and the second horizontal electrode portion LV2 may be opposite to the negative slope -SL2 of the side surface LV3a of the third horizontal electrode portion LV3. Furthermore, when viewed at positive and negative viewing angles, the negative slope -SL1 of the side surfaces LV1b and LV2b of the first horizontal electrode portion LV1 and the second horizontal electrode portion LV2 may be opposite to the positive slope +SL2 of the side surface LV3b of the third horizontal electrode portion LV3.

[0055] For example, the side surfaces LV1a and LV2a of the first horizontal electrode portion LV1 and the second horizontal electrode portion LV2 may have a positive slope of +SL1, and the opposite side surfaces LV1b and LV2b of the first horizontal electrode portion LV1 and the second horizontal electrode portion LV2 may have a negative slope of -SL1. The side surface LV3a of the third horizontal electrode portion LV3, which is connected to the side surfaces LV1a and LV2a of the first horizontal electrode portion LV1 and the second horizontal electrode portion LV2 having the positive slope of +SL1, may have a negative slope of -SL2. The opposite side surface LV3b of the third horizontal electrode portion LV3, which is connected to the opposite side surfaces LV1b and LV2b of the first horizontal electrode portion LV1 and the second horizontal electrode portion LV2 having the negative slope of -SL1, may have a positive slope of +SL2.

[0056] The bottom spacing S1 between the first horizontal electrode portions LV1 may be greater than the top spacing S2 between the first horizontal electrode portions LV1. When the bottom spacing S1 between the first horizontal electrode portions LV1 is greater than the top spacing S2 between the first horizontal electrode portions LV1, a film (e.g., a dielectric layer or an electrode layer) may be easily formed on the lower portion of the first horizontal electrode portion LV1 near the substrate Sb. The support member 14 may be located between the second horizontal electrode portions LV2.

[0057] The bottom spacing S3 between the third horizontal electrode portions LV3 may be smaller than the top spacing S4 between the third horizontal electrode portions LV3. In other words, the top spacing S4 between the third horizontal electrode portions LV3 may be larger than the bottom spacing S3 between the third horizontal electrode portions LV3. When the top spacing S4 between the third horizontal electrode portions LV3 is larger than the bottom spacing S3 between the third horizontal electrode portions LV3, a film (e.g., a dielectric layer or an electrode layer) may be easily formed on the third horizontal electrode portion LV3 located above the substrate Sb.

[0058] The cylindrical structure 28 having a high aspect ratio may not stand upright on its own, but may lean toward the adjacent cylindrical structure 28 or may break. Specifically, when the cylindrical structure 28 having a high aspect ratio includes a gap SE therein, the cylindrical structure 28 is very likely to lean or break. Therefore, the support member 14 supporting the cylindrical structure 28 may be arranged so that the cylindrical structures 28 can stand upright and separate from each other.

[0059] As described above, the support member 14 can support the cylindrical structure 28 by partially contacting the side surface of the cylindrical structure 28. The side surface 14a and the opposite side surface 14b of each support member 14 can have a slope. The top width W8 of the support member 14 can be smaller than the bottom width W7. The side surfaces 14a and 14b of the support member 14 can respectively contact the cylindrical structure 28 (for example, the side surfaces LV2a and LV2b of the corresponding adjacent second horizontal electrode portion LV2).

[0060] The support 14 can include a side surface 14a and an opposite side surface 14b corresponding to the side surface 14a. The side surface 14a and the opposite side surface 14b of the support 14 can have a negative slope -SL3 and a positive slope +SL3, respectively. When the side surface 14a and the opposite side surface 14b of the support 14 have slopes and the bottom width W7 of the support 14 is greater than the top width W8 of the support 14, it can be easy to reduce or prevent the cylindrical structures 28 from tilting or breaking.

[0061] The support 14 can be located at a certain height lower than the top surface of the cylindrical structures 28. The support 14 can be located at a height of at least 7 / 10 of the height H of the cylindrical structures 28. The support 14 can have a thickness of about 1 / 10 to about 3 / 10 of the height of the cylindrical structures 28.

[0062] As described above, the cylindrical structures 28 (e.g., the third horizontal electrode portion LV3) located higher than the support 14 can have side surfaces LV3a and opposite side surfaces LV3b having slopes, and the width W6 of the top of the third horizontal electrode portion LV3 can be smaller than the width W5 of the bottom of the third horizontal electrode portion LV3. The top spacing S4 between the cylindrical structures 28 (e.g., the third horizontal electrode portion LV3) located higher than the support 14 can be greater than the bottom spacing S3 between the cylindrical structures 28 (e.g., the third horizontal electrode portion LV3) located higher than the support 14.

[0063] As described above, the cylindrical structures 28 (e.g., the second horizontal electrode portion LV2) located at the same level as the support 14 can have side surfaces LV2a and opposite side surfaces LV2b having slopes, and the width W4 of the top of the second horizontal electrode portion LV2 can be greater than the width W3 of the bottom of the second horizontal electrode portion LV2. The cylindrical structures 28 (e.g., the first horizontal electrode portion LV1) located lower than the support 14 can have side surfaces LV1a and opposite side surfaces LV1b having slopes, and the width W2 of the top of the first horizontal electrode portion LV1 can be greater than the width W1 of the bottom of the first horizontal electrode portion LV1.

[0064] As described above, when the support 14 is located at a level lower than the top surface of the cylindrical structures 28, it can be easy to reduce or prevent the cylindrical structures 28 from tilting or breaking. In addition, when the width W6 of the top of the cylindrical structures 28 (e.g., the third horizontal electrode portion LV3) located above the support 14 is smaller than the width W5 of the bottom of the cylindrical structures 28 (e.g., the third horizontal electrode portion LV3) located above the support 14, it can be possible to reduce or prevent the cylindrical structures 28 from adhering to each other.

[0065] Figure 4A and Figure 4B is a cross-sectional view of an integrated circuit semiconductor device according to an embodiment, Figure 5 yes Figure 4A Magnified view of the cylindrical structure and support.

[0066] For example, in addition to the structure of the cylindrical structure 28a, Figure 4A Integrated circuit semiconductor device 3-1 and Figure 4B The integrated circuit semiconductor device 3-2 can be respectively along Figure 1 Schematic cross-sectional view taken along line II-II in FIG.

[0067] In addition to the contours of the side walls of each cylindrical structure 28a, Figure 4A The integrated circuit semiconductor device 3-1 can be used with Figure 4B In other words, except that the slope NSL is formed at each of the two side walls of the lower portion of the cylindrical structure 28a, Figure 4B The integrated circuit semiconductor device 3-2 can be connected with Figure 4A The integrated circuit semiconductor device 3-1 is the same.

[0068] In addition to the side profile or structure of the cylindrical structure 28a and the presence or absence of a seam, Figures 4A to 5 The integrated circuit semiconductor devices 3, 3-1 and 3-2 can be connected with Figures 1 to 3 The integrated circuit semiconductor devices 1, 1-1 and 1-2 are almost the same. Figures 1 to 5 In the drawings, like reference numerals denote like elements.

[0069] The integrated circuit semiconductor devices 3-1 and 3-2 may include cylindrical structures 28a separated from each other on a substrate Sb. Contact plugs 11 may be formed in the interlayer insulating layer 10 on the substrate Sb. The bottom surface of each cylindrical structure 28a may be fixed to the contact plug 11 on the substrate Sb, and the cylindrical structure 28a may have an elongated shape extending in a third direction (e.g., Z direction) perpendicular to the first direction (e.g., X direction) and the second direction (e.g., Y direction).

[0070] When the cylindrical structure 28a is a cylindrical lower electrode of a DRAM device, a dielectric layer 30 and an upper electrode 32 may be formed on the surface of the cylindrical structure 28a. The capacitor ca2 may be formed through the above process.

[0071] In the following, we will use Figure 4A The structure of the cylindrical structures 28 a , the intervals between the cylindrical structures 28 a , and the structure of the support member 14 will be described in detail with reference to the integrated circuit semiconductor device 3 - 1 .

[0072] The cylindrical structure 28a may include a first horizontal electrode portion having a first height H1 in a third direction (e.g., Z direction), a second horizontal electrode portion LV2 having a second height H2 from the top of the first horizontal electrode portion in the third direction (e.g., Z direction), and a third horizontal electrode portion LV3-1 having a third height H3 from the top of the second horizontal electrode portion LV2 in the third direction (e.g., Z direction).

[0073] The first horizontal electrode portion includes a lower horizontal electrode portion LV1-1 and an upper horizontal electrode portion LV1-2, the lower horizontal electrode portion LV1-1 having a fourth height H4 from the top of the substrate Sb in a third direction (e.g., the Z direction), and the upper horizontal electrode portion LV1-2 having a fifth height H5 from the top of the lower horizontal electrode portion LV1-1 in the third direction (e.g., the Z direction). The fourth height H4 and the fifth height H5 are arbitrary and do not limit the embodiment.

[0074] The lower horizontal electrode portion LV1-1 may have a top width W9 and a bottom width W1. Both side surfaces of the lower horizontal electrode portion LV1-1 may have a slope. The top width W9 of the lower horizontal electrode portion LV1-1 may be greater than the bottom width W1 of the lower horizontal electrode portion LV1-1.

[0075] The upper horizontal electrode portion LV1-2 may have side surfaces LV1c and LV1d respectively recessed inwardly by a first depth RS1 from the side surfaces LV1a and LV1b of the lower horizontal electrode portion LV1-1. The upper horizontal electrode portion LV1-2 may have side surfaces LV1c and LV1d respectively recessed inwardly by a second depth RS2 from the side surfaces LV2a and LV2b of the second horizontal electrode portion LV2. Figure 4B As shown in , not a horizontal surface but a slope NSL may be formed as a sidewall between the lower horizontal electrode portion LV1 - 1 and the upper horizontal electrode portion LV1 - 2 .

[0076] The upper horizontal electrode portion LV1-2 may have a top width W11 and a bottom width W10. The bottom width W10 of the upper horizontal electrode portion LV1-2 may be smaller than the top width W9 of the lower horizontal electrode portion LV1-1. The bottom width W3 of the second horizontal electrode portion LV2 may be larger than the top width W11 of the upper horizontal electrode portion LV1-2. Both side surfaces of the second horizontal electrode portion LV2 may have a slope. The top width W4 of the second horizontal electrode portion LV2 may be larger than the bottom width W3 of the second horizontal electrode portion LV2.

[0077] The third horizontal electrode portion LV3-1 may have side surfaces LV3c and LV3d that are respectively recessed inward by a third depth RS3 from the side surfaces LV2a and LV2b of the second horizontal electrode portion LV2. The third horizontal electrode portion LV3-1 may have a top width W13 and a bottom width W12. The bottom width W12 of the third horizontal electrode portion LV3-1 may be smaller than the top width W4 of the second horizontal electrode portion LV2. Both side surfaces of the third horizontal electrode portion LV3-1 may have a slope.

[0078] Side surfaces LV1a and LV1b of the lower horizontal electrode portion LV1-1 may be connected to side surfaces LV1c and LV1d of the upper horizontal electrode portion LV1-2, respectively, via recessed flat surfaces. Side surfaces LV1c and LV1d of the upper horizontal electrode portion LV1-2 may be connected to side surfaces LV2a and LV2b of the second horizontal electrode portion LV2, respectively, via recessed flat surfaces. Side surfaces LV2a and LV2b of the second horizontal electrode portion LV2 may be connected to side surfaces LV3c and LV3d of the third horizontal electrode portion LV3-1, respectively, via recessed flat surfaces.

[0079] When viewed at positive and negative angles, the slope +SL4 of the side surface LV1a of the lower horizontal electrode portion LV1-1, the slope +SL5 of the side surface LV1c of the upper horizontal electrode portion LV1-2, and the slope +SL6 of the side surface LV2a of the second horizontal electrode portion LV2, as well as the slope -SL4 of the opposite side surface LV1b of the lower horizontal electrode portion LV1-1, the slope -SL5 of the opposite side surface LV1d of the upper horizontal electrode portion LV1-2, and the slope -SL6 of the opposite side surface LV2b of the second horizontal electrode portion LV2 may be opposite to the slopes -SL7 and +SL7 of the side surfaces LV3c and LV3d of the third horizontal electrode portion LV3-1.

[0080] In other words, when viewed at positive and negative viewing angles, the positive slope +SL4 of the side surface LV1a of the lower horizontal electrode portion LV1-1, the positive slope +SL5 of the side surface LV1c of the upper horizontal electrode portion LV1-2, and the positive slope +SL6 of the side surface LV2a of the second horizontal electrode portion LV2 may be opposite to the negative slope -SL7 of the side surface LV3c of the third horizontal electrode portion LV3-1. In addition, when viewed at positive and negative viewing angles, the negative slope -SL4 of the side surface LV1b of the lower horizontal electrode portion LV1-1, the negative slope -SL5 of the side surface LV1d of the upper horizontal electrode portion LV1-2, and the negative slope -SL6 of the side surface LV2b of the second horizontal electrode portion LV2 may be opposite to the positive slope +SL7 of the side surface LV3d of the third horizontal electrode portion LV3-1.

[0081] Slopes +SL4 and -SL4 can be used with Figure 3The slopes +SL1 and -SL1 in are similar or identical. The slopes +SL6 and -SL6 can be Figure 3 The slopes +SL1 and -SL1 in are similar or identical. The slopes +SL7 and -SL7 can be Figure 3 The slopes +SL2 and -SL2 are similar or the same.

[0082] For example, the side surfaces LV1a, LV1c and LV2a of the lower horizontal electrode portion LV1-1, the upper horizontal electrode portion LV1-2 and the second horizontal electrode portion LV2 may have positive slopes +SL4, +SL5 and +SL6, and the relative side surfaces LV1b, LV1d and LV2b of the lower horizontal electrode portion LV1-1, the upper horizontal electrode portion LV1-2 and the second horizontal electrode portion LV2 may have negative slopes -SL4, -SL5 and -SL6.

[0083] When viewed at positive and negative viewing angles, the side surface LV3c of the third horizontal electrode portion LV3-1, which is connected to the side surfaces LV1a, LV1c, and LV2a of the lower horizontal electrode portion LV1-1, the upper horizontal electrode portion LV1-2, and the second horizontal electrode portion LV2, which have the positive slopes +SL4, +SL5, and +SL6, may have a negative slope -SL7 opposite to the positive slopes +SL4, +SL5, and +SL6. When viewed at positive and negative viewing angles, the opposite side surface LV3d of the third horizontal electrode portion LV3-1, which is connected to the opposite side surfaces LV1b, LV1d, and LV2b of the lower horizontal electrode portion LV1-1, the upper horizontal electrode portion LV1-2, and the second horizontal electrode portion LV2, which have the negative slopes -SL4, -SL5, and -SL6, may have a positive slope +SL7 opposite to the negative slopes -SL4, -SL5, and -SL6.

[0084] The bottom spacing S5 between the lower horizontal electrode portions LV1-1 may be greater than the top spacing S6 between the lower horizontal electrode portions LV1-1. Figure 3 The bottom spacing S1 between the upper horizontal electrode portions LV1-2 may be similar or identical. The bottom spacing S7 between the upper horizontal electrode portions LV1-2 may be larger than the top spacing S8 between the upper horizontal electrode portions LV1-2. The top spacing S8 may be larger than Figure 3 The top spacing S2 between the third horizontal electrode portions LV3-1 may be greater than the top spacing S10 between the third horizontal electrode portions LV3-1. The bottom spacing S9 may be greater than the top spacing S10 between the third horizontal electrode portions LV3-1. Figure 3 The bottom spacing S3 is large.

[0085] The support members 14 supporting the cylindrical structures 28a can be arranged so that the cylindrical structures 28a can stand upright and separate from each other. As described above, the support members 14 can support the cylindrical structures 28a by partially contacting the side surfaces of the cylindrical structures 28a. The side surfaces 14a and the opposing side surfaces 14b of each support member 14 can have a slope. The top width W8 of the support member 14 can be smaller than the bottom width W7 of the support member 14.

[0086] The side surfaces 14a and 14b of the support member 14 may respectively contact the cylindrical structure 28a (e.g., the side surfaces LV2a and LV2b of the corresponding adjacent second horizontal electrode portion LV2). The support member 14 may include a side surface 14a and an opposite side surface 14b corresponding to the side surface 14a. The side surface 14a and the opposite side surface 14b of the support member 14 may respectively have a negative slope -SL3 and a positive slope +SL3.

[0087] In the integrated circuit semiconductor devices 3-1 and 3-2, the upper horizontal electrode portion LV1-2 is formed by Figures 1 to 3 The first horizontal electrode portion LV1 is formed to be recessed inward. Figures 1 to 3 The third horizontal electrode portion LV3 in the integrated circuit semiconductor devices 3-1 and 3-2 can increase the surface area of ​​the cylindrical structure 28a. When the cylindrical structure 28a forms a cylindrical lower electrode, the capacitance can be increased.

[0088] Furthermore, because the top width W13 of the cylindrical structure 28a above the support member 14 is much smaller than the bottom width W12, the integrated circuit semiconductor devices 3-1 and 3-2 can reduce or prevent the cylindrical structures 28a from fitting together.

[0089] Figure 6 is a cross-sectional view for describing a cylindrical structure and a support member of an integrated circuit semiconductor device according to example embodiments.

[0090] For example, in addition to the integrated circuit semiconductor device 5 including the additional support member 14-1, the integrated circuit semiconductor device 5 may be Figure 3 The integrated circuit semiconductor device 1 is the same. Figure 3 and Figure 6 In the drawings, like reference numerals denote like elements.

[0091] The integrated circuit semiconductor device 5 can include an additional support 14-1 on a side surface of the first horizontal electrode portion LV1 of each cylindrical structure 28. Similar to the support 14, the side surface 14a-1 and the opposite side surface 14b-1 of the additional support 14-1 can have slopes, and a top width W15 of the additional support 14-1 can be smaller than a bottom width W14 of the additional support 14-1. The side surface 14a-1 and the opposite side surface 14b-1 of the additional support 14-1 can be in contact with the cylindrical structure 28 (e.g., the side surfaces LV1a and LV1b of the corresponding adjacent first horizontal electrode portion LV1, respectively).

[0092] The additional support 14-1 can include a side surface 14a-1 and an opposite side surface 14b-1 corresponding to the side surface 14a-1. The side surface 14a-1 and the opposite side surface 14b-1 of the additional support 14-1 can have a negative slope -SL8 and a positive slope +SL8, respectively. When the side surface 14a-1 and the opposite side surface 14b-1 of the additional support 14-1 have slopes and the bottom width W14 of the additional support 14-1 is larger than the top width W15 of the additional support 14-1, it can be easier to reduce or prevent the cylindrical structure 28 from tilting or breaking. Figure 6 In the embodiment, the integrated circuit semiconductor device 5 includes one additional support 14-1, but a plurality of additional supports can be provided on the first horizontal electrode portion LV1 in the vertical direction (e.g., the Z direction).

[0093] Figure 7 is a cross-sectional view for describing a cylindrical structure and a support of an integrated circuit semiconductor device according to an example embodiment.

[0094] For example, the integrated circuit semiconductor device 7 can be the same as the integrated circuit semiconductor device 3 of Figure 5 except that the integrated circuit semiconductor device 7 further includes an additional support 14-2. In Figure 5 and Figure 7 the same reference numerals denote the same elements.

[0095] The integrated circuit semiconductor device 7 can include an additional support 14-2 on a side surface of the upper horizontal electrode portion LV1-2 of each cylindrical structure 28a. Similar to the support 14, the side surface 14a-2 and the opposite side surface 14b-2 of the additional support 14-2 can have slopes, and a top width W17 of the additional support 14-2 can be smaller than a bottom width W16 of the additional support 14-2. The side surface 14a-2 and the opposite side surface 14b-2 of the additional support 14-2 can be in contact with the cylindrical structure 28a (e.g., the side surfaces LV1c and LV1d of the corresponding adjacent upper horizontal electrode portion LV1-2, respectively).

[0096] The additional support member 14-2 may include a side surface 14a-2 and an opposite side surface 14b-2 corresponding to the side surface 14a-2. The side surface 14a-2 and the opposite side surface 14b-2 of the additional support member 14-2 may have a negative slope of -SL9 and a positive slope of +SL9, respectively. When the side surface 14a-2 and the opposite side surface 14b-2 of the additional support member 14-2 have slopes and the bottom width W16 of the additional support member 14-2 is larger than the top width W17 of the additional support member 14-2, it is easier to reduce or prevent the cylindrical structure 28a from tilting or breaking. Figure 7 In the embodiment, the integrated circuit semiconductor device 7 includes one additional support member 14 - 2 , but a plurality of additional support members may be provided on the upper horizontal electrode portion LV1 - 2 along the vertical direction (eg, the Z direction).

[0097] Figures 8 to 15 is a cross-sectional view for describing a method of manufacturing an integrated circuit semiconductor device according to example embodiments.

[0098] For example, Figures 8 to 15 Is used to describe manufacturing Figures 1 to 3 FIG1 is a diagram of a method of an integrated circuit semiconductor device. Figures 1 to 3 and Figures 8 to 15 In the drawings, the same reference numerals may denote the same elements. Figures 8 to 15 , for the convenience of description, the substrate Sb is not shown.

[0099] Reference Figure 8 , on the base (Fig. 2 and Figure 3 An interlayer insulating layer 10 (hereinafter referred to as a first interlayer insulating layer 10) is formed on the Sb in the film, and a contact plug 11 is formed in the first interlayer insulating layer 10. A second interlayer insulating layer 12m, a support layer 14S, a third interlayer insulating layer 16m, an etch stop layer 18r, and a mask layer 20r are sequentially formed on the first interlayer insulating layer 10 and the contact plug 11. The second interlayer insulating layer 12m is thicker than the support layer 14S and the third interlayer insulating layer 16m.

[0100] The first interlayer insulating layer 10, the second interlayer insulating layer 12m, and the third interlayer insulating layer 16m may include a silicon oxide layer, the support layer 14S and the etch stop layer 18r may include a silicon nitride layer or a silicon oxynitride layer, and the mask layer 20r may include a polysilicon layer.

[0101] Reference Figure 9 and Figure 10 ,like Figure 9 As shown in FIG, a mask pattern 20 and an etch stop pattern 18 are formed by patterning a mask layer 20r and an etch stop layer 18r using photolithography. A first hole 21a exposing the third interlayer insulating layer 16m may be formed between the mask pattern 20 and the etch stop pattern 18.

[0102] like Figure 10 As shown in FIG, the third interlayer insulating layer 16m, the support layer 14S, and the second interlayer insulating layer 12m are sequentially etched using the mask pattern 20 and the etch barrier pattern 18 as etching masks. Thus, the second interlayer insulating pattern 12, the support 14, and the third interlayer insulating pattern 16 can be formed on the first interlayer insulating layer 10.

[0103] Due to the nature of etching, the width of the second interlayer insulating pattern 12, the support member 14, and the third interlayer insulating pattern 16 may decrease as they move away from the first interlayer insulating layer 10. In other words, due to the nature of etching, the width of each of the second interlayer insulating pattern 12, the support member 14, and the third interlayer insulating pattern 16 may increase as they move away from the top toward the bottom. Both side surfaces of each of the second interlayer insulating pattern 12, the support member 14, and the third interlayer insulating pattern 16 may have a slope.

[0104] When the second interlayer insulating pattern 12, the support member 14, and the third interlayer insulating pattern 16 are formed, a second hole 21b exposing the contact plug 11 may be formed. The second hole 21b may be connected to the first hole 21a. Due to the nature of etching, the second hole 21b may become wider as it moves away from the contact plug 11. In other words, the second hole 21b may become narrower from top to bottom toward the contact plug 11.

[0105] Reference Figure 11 and Figure 12 ,like Figure 11 , the mask pattern 20 and the etch barrier pattern 18 are removed. During the removal of the mask pattern 20, the etch stop pattern 18 may also be removed. As a result, the second interlayer insulating pattern 12, the support member 14, and the third interlayer insulating pattern 16 with the second hole 21 b therebetween may be formed on the first interlayer insulating layer 10, wherein the second hole 21 b exposes the contact plug 11.

[0106] like Figure 12 As shown in FIG, a spacer layer 22 is formed on both side surfaces and the top surface of each third interlayer insulating pattern 16. The spacer layer 22 may include a silicon nitride layer. The spacer layer 22 may be formed only on both side surfaces of the third interlayer insulating pattern 16, but not on both side surfaces of the support member 14 and both side surfaces of the second interlayer insulating pattern 12.

[0107] Reference Figure 13 and Figure 14 ,like Figure 13As shown in , a cylindrical material layer 24 is formed to fully fill the second hole 21b. The cylindrical material layer 24 may be formed on top of the contact plug 11 and between the second interlayer insulating pattern 12, the support member 14, and the third interlayer insulating pattern 16. The cylindrical material layer 24 may include a metal nitride layer, for example, a titanium nitride (TiN) layer or a titanium silicon nitride (Ti—Si—N) layer.

[0108] like Figure 14 As shown in FIG, the cylindrical structure 28 and the spacer 26 are formed by etching and planarizing the cylindrical material layer 24 and the spacer layer 22 using the top surface of the third interlayer insulating pattern 16 as an etching stop line or etching stop point. The spacers 26 may be respectively formed on both side surfaces of the third interlayer insulating pattern 16. The spacers 26 may be respectively formed on both side surfaces of the third interlayer insulating pattern 16 and have an inverted triangular shape whose width decreases from the top toward the bottom.

[0109] The cylindrical structure 28 may be formed in the second hole 21b and on the contact plug 11 between the second interlayer insulating pattern 12, the support member 14, and the spacer 26. The outer surface profile (or structure) of the cylindrical structure 28 may be formed by Figure 12 The inner contour of the second hole 21b and the side contour of the spacer layer 22 are defined.

[0110] Reference Figure 15 , a third hole 27a is formed by removing the third interlayer insulating pattern 16, the spacer 26, and the second interlayer insulating pattern 12. The third hole 27a can be Figure 1 Corresponding to the opening area OP in.

[0111] The third interlayer insulating pattern 16, the spacer 26, and the second interlayer insulating pattern 12 may be removed by wet etching. In some embodiments, an etchant (e.g., limulus amoebocyte lysate (LAL)) may be used to remove the third interlayer insulating pattern 16, the spacer 26, and the second interlayer insulating pattern 12. While etching the third interlayer insulating pattern 16 and the second interlayer insulating pattern 12, the spacer 26 may also be removed.

[0112] As a result of removing the third interlayer insulating pattern 16 , the spacer 26 , and the second interlayer insulating pattern 12 , a cylindrical structure 28 may be formed on the contact plug 11 , and the support 14 may be located at a height lower than a top surface of the cylindrical structure 28 .

[0113] As described above, the cylindrical structure 28 may include a first horizontal electrode portion LV1, a second horizontal electrode portion LV2, and a third horizontal electrode portion LV3. The side profile of the first horizontal electrode portion LV1 may have a slope according to the side profile of the second interlayer insulating pattern 12. The side profile of the third horizontal electrode portion LV3 may have a slope according to the side profile of the spacer 26. The side profile of the cylindrical structure 28 has been described above, and thus a repeated description of the side profile of the cylindrical structure 28 is omitted.

[0114] Figure 16 and Figure 17 is a cross-sectional view for describing a method of manufacturing an integrated circuit semiconductor device according to example embodiments.

[0115] For example, Figure 16 and Figure 17 Is used to describe manufacturing Figure 4A and Figure 5 FIG3-1 is a diagram of a method of an integrated circuit semiconductor device. Figure 4A 、 Figure 5 and Figures 8 to 17 In the drawings, like reference numerals may denote like elements.

[0116] Execute the above Figures 8 to 14 The results, such as Figure 14 As shown in FIG, a second interlayer insulating pattern 12, a support member 14, a third interlayer insulating pattern 16, and a spacer 26 are formed on the first interlayer insulating layer 10. A cylindrical structure 28 may be formed in the second hole 21b and on the contact plug 11 between the second interlayer insulating pattern 12, the support member 14, and the spacer 26.

[0117] Reference Figure 16 The fourth hole 27b is formed by removing all of the third interlayer insulating pattern 16 and the spacer 26 and part of the second interlayer insulating pattern 12. The fourth interlayer insulating pattern 12a may be formed in the fourth hole 27b. The fourth interlayer insulating pattern 12a may be a remnant of the second interlayer insulating pattern 12.

[0118] In some embodiments, as described above, an etchant (e.g., LAL) may be used to remove all of the third interlayer insulating pattern 16 and the spacer 26, as well as a portion of the second interlayer insulating pattern 12. While removing a portion of the second interlayer insulating pattern 12 and the third interlayer insulating pattern 16, the spacer 26 may also be removed.

[0119] The fourth interlayer insulating pattern 12a may be formed to a certain thickness on the top of the first interlayer insulating layer 10 and on both sidewalls of the lower portion of the cylindrical structure 28. Due to the fourth interlayer insulating pattern 12a, both sidewalls of the cylindrical structure 28 below the support member 14 may be exposed through the fourth hole 27b. Both sidewalls of the cylindrical structure 28 above the support member 14 may also be exposed through the fourth hole 27b.

[0120] Reference Figure 17 The cylindrical structure 28a having a concave portion is formed by further etching the two sidewalls of the cylindrical structure 28 exposed by the fourth hole 27b inward. The cylindrical structure 28a having a concave portion is formed by further etching the two sidewalls of the cylindrical structure 28 inward to a first depth RS1, a second depth RS2, and a third depth RS3.

[0121] The recess etching that recesses the two sidewalls of the cylindrical structure 28 can be performed by an etching device using a supercritical fluid (e.g., supercritical carbon dioxide (CO2)). A supercritical fluid refers to any fluid above a certain temperature and pressure called a critical point, where there is no distinct liquid phase and gas phase. In the case of carbon dioxide, the critical conditions may include a critical temperature of 31.7°C and a critical pressure of 72.8 atm. Because supercritical fluids have no surface tension like gases in terms of diffusion power and are similar to liquid solvents in terms of dissolving power, thin cylindrical structures 28 can be recessedly etched by supercritical fluids.

[0122] Next, the fifth hole 27c is formed by removing the fourth interlayer insulating pattern 12a. The fifth hole 27c may be Figure 1 The fourth interlayer insulating pattern 12a may be removed by wet etching.

[0123] As a result, as described above, the cylindrical structure 28a with a concave portion may include a lower horizontal electrode portion LV1-1, an upper horizontal electrode portion LV1-2, a second horizontal electrode portion LV2, and a third horizontal electrode portion LV3-1. The side profile of the cylindrical structure 28a with a concave portion has been described above, so its description will be omitted.

[0124] The following includes Figures 1 to 3 An embodiment in which a capacitor including the cylindrical structure 28 (eg, a cylindrical lower electrode) is applied to a cell transistor of a DRAM device will be described.

[0125] Figure 18 is a schematic layout plan view for describing main elements in a cell array region of a DRAM device according to example embodiments.

[0126] For example, DRAM device 100 may include a plurality of active regions ACT. In some embodiments, active regions ACT may be arranged to have long axes in an oblique direction (eg, D direction) of a first direction (eg, X direction) and a second direction (eg, Y direction).

[0127] The plurality of word lines WL may extend parallel to each other in a first direction (e.g., X direction) intersecting the active area ACT, and the plurality of bit lines BL may extend parallel to each other on the word lines WL in a second direction (e.g., Y direction) intersecting the first direction (e.g., X direction).

[0128] The bit lines BL may be connected to the active area ACT via direct contacts DC. In some embodiments, a plurality of buried contacts BC may be formed between two adjacent bit lines BL among the bit lines BL. Each buried contact BC may extend above one of the two adjacent bit lines BL. In some embodiments, the buried contacts BC may be arranged in rows in a first direction (e.g., X direction) and a second direction (e.g., Y direction).

[0129] A plurality of bonding pads LP may be formed above the buried contact BC. The buried contact BC and the bonding pad LP may connect a lower electrode (not shown) of a capacitor formed above the bit line BL to the active area ACT. Each bonding pad LP may partially overlap the buried contact BC.

[0130] 19A to 19I are diagrams for describing a method of manufacturing a DRAM device according to example embodiments. 19A to 19I It is along Figure 18 Cross-sectional views taken along lines AA', BB' and CC'.

[0131] Reference Figure 19A , a device isolation trench 116T is formed in the substrate 110. A device isolation layer 116 may be formed in the device isolation trench 116T. An active region 118 may be defined in the substrate 110 by the device isolation layer 116. The active region 118 may be divided into a first active region 118a located on the substrate 110 and a second active region 118b located on the first active region 118a. Figure 18 Like the active region ACT in FIG. 1 , the active region 118 may have a relatively long island shape having a short axis and a long axis.

[0132] The substrate 110 may correspond to the above-mentioned substrate Sb. The substrate 110 may include a conductive region, for example, an impurity-doped well or an impurity-doped structure.

[0133] For example, the device isolation layer 116 can include a material including at least one selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The device isolation layer 116 can include a single film including one insulating film, a dual film including two insulating films, or a multi-film including a combination of at least three insulating films.

[0134] In some embodiments, the device isolation layer 116 can include a first device isolation layer 116A and a second device isolation layer 116B. The first device isolation layer 116A can include a material different from a material of the second device isolation layer 116B. For example, the first device isolation layer 116A can include a silicon oxide film, and the second device isolation layer 116B can include a silicon nitride film. However, the configuration of the device isolation layer 116 is not limited to the above description.

[0135] A plurality of word line trenches 120T can be formed in the second active region 118b. The word line trenches 120T can extend in parallel to each other in a first direction (e.g., an X direction in FIG. 1), and can have a linear shape crossing the active region 118. As shown in a cross-sectional view taken along line B-B', in order to form the word line trenches 120T having a step in a bottom thereof, the device isolation layer 116 and the second active region 118b can be etched separately by separate etching processes such that an etching depth of the device isolation layer 116 is different from an etching depth of the second active region 118b. Figure 18 After cleaning the resulting structure including the word line trenches 120T, a gate dielectric layer 122, a plurality of word lines 120, and a plurality of buried insulating layers 124 can be sequentially formed in the word line trenches 120T. The word lines 120 can form word lines WL in FIG. 1.

[0136] Figure 18 The top surface of the word lines 120 can be located at a level lower than that of the top surface of the second active region 118b. The bottom surface of the word lines 120 can have a concave-convex shape, and transistors having a horse-shoe structure (e.g., a horse-shoe field effect transistor (FinFET)) can be formed in the active region 118.

[0137] As described above, the term “level” refers to a height from a main surface of the substrate 110 in a vertical direction. In some embodiments, after forming the word lines 120, impurity ions can be implanted into the second active region 118b respectively located at both sides of each of the word lines 120, thereby forming source and drain regions in the active region 118. In some embodiments, the process of implanting impurity ions to form the source and drain regions can be performed before forming the word lines 120. In some embodiments, the word lines 120 can include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof.

[0138] As described above, the term “level” refers to a height from a main surface of the substrate 110 in a vertical direction. In some embodiments, after forming the word lines 120, impurity ions can be implanted into the second active region 118b respectively located at both sides of each of the word lines 120, thereby forming source and drain regions in the active region 118. In some embodiments, the process of implanting impurity ions to form the source and drain regions can be performed before forming the word lines 120. In some embodiments, the word lines 120 can include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof.

[0139] ​The gate dielectric layer 122 may include at least one selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide / nitride / oxide (ONO), and a high-k dielectric film having a dielectric constant higher than that of the silicon oxide film. For example, the gate dielectric layer 122 may have a dielectric constant of about 10 to about 25. In some embodiments, the gate dielectric layer 122 may include a metal dielectric film including, for example, at least one material selected from the group consisting of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0140] The top surface of the buried insulating layer 124 may be located at the same or substantially the same level as the top surface of the second active region 118b. The buried insulating layer 124 may include a material film selected from silicon oxide films, silicon nitride films, silicon oxynitride films, and combinations thereof.

[0141] Reference Figure 19B A first insulating layer 111 and a second insulating layer 113 are formed on the device isolation layer 116, the second active region 118b, and the buried insulating layer 124. The first insulating layer 111 may include a non-metallic dielectric film. For example, the first insulating layer 111 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. The second insulating layer 113 may include a metal dielectric film. The second insulating layer 113 may have a higher dielectric constant than that of the first insulating layer 111. For example, the second insulating layer 113 may include at least one material selected from the metal dielectric films included in the gate dielectric layer 122 described above.

[0142] Then, a first conductive layer 132 is formed on the second insulating layer 113. The first conductive layer 132 may include, for example, a doped semiconductor material. In some embodiments, the first conductive layer 132 may include a doped polysilicon film. A hard mask layer 138 is formed on the first conductive layer 132. Thereafter, a second photoresist pattern M2 is formed on the hard mask layer 138.

[0143] The hard mask layer 138 may include, but is not particularly limited to, a material having sufficient etching selectivity with respect to the first conductive layer 132. For example, the hard mask layer 138 may include a carbon-based material.

[0144] The second photoresist pattern M2 is formed by depositing a photoresist on the hard mask layer 138 and patterning the photoresist through exposure and development. At this time, the second photoresist pattern M2 may have an opening G2 partially exposing the hard mask layer 138.

[0145] Reference Figure 19C , by etching Figure 19B The hard mask layer 138 in Figure 19B The second photoresist pattern M2 Figure 19B The portion exposed by the opening G2 in the etchant is used to form a hard mask pattern 138A. Thereafter, the hard mask pattern 138A is used as an etching mask to etch the etchant. Figure 19B ) first conductive layer 132, ( Figure 19B The second insulating layer 113 ( Figure 19B ) first insulating layer 111 and ( Figure 19B ) in the upper portion of the second active region 118b.

[0146] As a result, a direct contact hole DCH exposing the second active region 118b is formed. In addition, a first conductive pattern 132A, a second insulating pattern 113A, and a first insulating pattern 111A defining the direct contact hole DCH are formed. In some embodiments, the bottom surface of the direct contact hole DCH may be lower than the top surface of the second active region 118b.

[0147] Reference Figure 19D , remove Figure 19C The hard mask pattern 138A in the first conductive pattern 132A may be removed using an ashing process and / or a stripping process. In addition, the hard mask pattern 138A may be removed under conditions in which etching of the first conductive pattern 132A is suppressed.

[0148] In some embodiments, after removing the hard mask pattern 138A, silicon processing may be performed. The silicon processing is performed on the second active region 118b, etc. Figure 19C The described etching process is a process of weakly etching or cleaning the surface that has been damaged during the etching process, thereby providing a high-quality surface state. Thereafter, a cleaning process can be performed to remove native oxide and other contaminants.

[0149] Next, a fully filled ( Figure 19C The second conductive layer 134 directly contacts the hole DCH and covers the top surface of the first conductive pattern 132A. The second conductive layer 134 may include, for example, a doped semiconductor material. In some embodiments, the second conductive layer 134 may include doped polysilicon.

[0150] In other words, the second conductive layer 134 and ( Figure 19BThe first conductive layer 132 may include a doped semiconductor material, for example, a doped polysilicon film. In addition, the second conductive layer 134 may have a higher doping concentration than the first conductive layer 132. However, the configurations of the first conductive layer 132 and the second conductive layer 134 are not limited to the above description.

[0151] Reference Figure 19E , by ( Figure 19D ) second conductive layer 134 and ( Figure 19D The first conductive pattern 132A is blanket-etched to form a direct contact 134A and a thinned first conductive pattern 132B. The blanket etching process can be performed using an etch-back method or a chemical mechanical polishing (CMP) method. The upper portion of the first conductive pattern 132A is removed by the blanket etching process, thereby forming a thinned first conductive pattern 132B that is thinner than the first conductive pattern 132A.

[0152] The top surface of the direct contact 134A and the top surface of the thinned first conductive pattern 132B may be exposed, and the top surface of the direct contact 134A may be located at the same level as the top surface of the thinned first conductive pattern 132B. Both side surfaces of the direct contact 134A may contact the thinned first conductive pattern 132B, and the interface is between the direct contact 134A and the thinned first conductive pattern 132B. However, the configuration of the direct contact 134A and the thinned first conductive pattern 132B is not limited to the above description.

[0153] Reference Figure 19F , forming a metal layer 143 covering the direct contact 134A and the thinned first conductive pattern 132B. Thereafter, an insulating cover layer 146 is formed on the metal layer 143. In some embodiments, the metal layer 143 may have a stacked structure in which a lower metal layer 142 and an upper metal layer 144 are stacked. Although the metal layer 143 is shown as having a double-layer conductive stacked structure including the lower metal layer 142 and the upper metal layer 144, this is merely an example and the embodiment is not limited thereto. For example, the metal layer 143 may include a single layer or a stacked structure including at least three layers.

[0154] In some embodiments, the lower metal layer 142 may include TiN or Ti-Si-N (TSN). The upper metal layer 144 may include tungsten (W) or tungsten silicide (WSi). x In some embodiments, the lower metal layer 142 may serve as a diffusion barrier layer.

[0155] An insulating capping layer 146 may be formed on the metal layer 143. The insulating capping layer 146 may include, for example, a silicon nitride film. In some embodiments, the insulating capping layer 146 may be thicker than the metal layer 143.

[0156] Next, a third photoresist pattern M3 is formed on the insulating capping layer 146. The third photoresist pattern M3 is formed by depositing a photoresist on the insulating capping layer 146 and patterning the photoresist using exposure and development. At this time, the third photoresist pattern M3 may have an opening G3 partially exposing the insulating capping layer 146.

[0157] Reference Figure 19G , a bit line structure 148 is formed on the second active region 118b. For example, using ( Figure 19F The third photoresist pattern M3 in the etching process is used as an etching mask to etch the Figure 19F The thinned first conductive pattern 132B, ( Figure 19F The lower metal layer 142, ( Figure 19F The upper metal layer 144 and ( Figure 19F An insulating cap layer 146 is formed on the bit lines 140. As a result, a plurality of bit lines 140 are formed, each including a thinned first conductive line 132C having a line shape, a lower metal line 142A, and an upper metal line 144A. Subsequently, a plurality of insulating cap lines 146A are formed on each of the bit lines 140. One bit line 140 and one insulating cap line 146A can form one bit line structure 148.

[0158] The bit line 140 and the insulating cover line 146A may be arranged in a second direction (eg, Figure 18 The bit lines 140 may be formed in parallel with each other in the Y direction. Figure 18 The bit line BL is shown in FIG.

[0159] During the etching process for forming the bit line 140, a portion of the direct contact 134A that does not overlap the bit line 140 in a vertical direction relative to the main surface of the substrate 110 may also be etched, thereby forming a direct contact conductive pattern 134B. In some embodiments, a top surface of the direct contact conductive pattern 134B may be located at a higher level than a top surface of the second insulating pattern 113A.

[0160] Although the bit line 140 includes the thinned first conductive line 132C including doped polysilicon, the bit line 140 may have a relatively thin vertical stack structure.

[0161] Reference Figure 19H , a DRAM device 100 including a plurality of bit line structures 148 can be formed. For example, both sidewalls of each bit line structure 148 can be covered with an insulating spacer structure 150. The insulating spacer structure 150 can include a first insulating spacer 152, a second insulating spacer 154, and a third insulating spacer 156.

[0162] In some embodiments, the first insulating spacer 152, the second insulating spacer 154, and the third insulating spacer 156 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof, and the second insulating spacer 154 between the first insulating spacer 152 and the third insulating spacer 156 may include an air spacer.

[0163] A plurality of buried contact holes 170H may be formed between the bit lines 140. An inner space of each buried contact hole 170H may be defined by the active region 118 and an insulating spacer structure 150 located between two adjacent bit lines 140 among the bit lines 140 and covering sidewalls of each of the two adjacent bit lines 140.

[0164] A plurality of buried contacts 170 and a plurality of bonding pads 180 connected to the plurality of active regions 118, respectively, may be formed in the buried contact holes 170H between the bit lines 140. The buried contacts 170 and the bonding pads 180 may be connected to the plurality of active regions 118, respectively. Figure 18 The buried contact BC corresponds to the bonding pad LP.

[0165] The buried contacts 170 may be respectively formed in a third direction (eg, Figure 18 The bonding pads 180 extend from the active region 118 in the Z direction (in the Z direction). The bonding pads 180 are respectively located on the buried contacts 170 and may extend over the bit lines 140. The bonding pads 180 may be connected to the cell active region through the buried contacts 170.

[0166] The bonding pad 180 may be electrically connected to the buried contact 170 , and may extend from inside the buried contact hole 170H to above the bit line structure 148 and thereby vertically overlap the bit line structure 148 .

[0167] The bonding pad 180 may be arranged in a third direction (eg, perpendicular to the main surface of the substrate 110) Figure 18 The bonding pad 180 extends in a region between the bit lines in the Z direction (in the Z direction) and may cover at least a portion of a top surface of the bit line 140 such that the bonding pad 180 vertically overlaps at least a portion of the bit line 140.

[0168] A metal silicide layer 172 may be formed between the buried contact 170 and the bonding pad 180. The metal silicide layer 172 may include cobalt silicide (CoSi), nickel silicide (NiSi), or manganese silicide (MnSi), but is not limited thereto.

[0169] A conductive barrier layer 174 may be formed between the bonding pad 180 and the insulating spacer structure 150 and between the bonding pad 180 and the bit line structure 148. The conductive barrier layer 174 may include a metal, a conductive metal nitride, or a combination thereof. For example, the conductive barrier layer 174 may have a Ti / TiN stacked structure.

[0170] An insulating layer 130 may be formed around the bit line structure 148 and the insulating spacer structure 150. The insulating layer 130 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

[0171] Bonding pad 180 may be formed using chemical vapor deposition (CVD) or physical vapor deposition (PVD). In some embodiments, bonding pad 180 may include metal, metal nitride, conductive polysilicon, or a combination thereof. For example, bonding pad 180 may include tungsten (W).

[0172] Reference Figure 19I , can be formed on the bonding pad 180 Figures 1 to 3 The capacitor ca1 in the DRAM device 100 is formed. The capacitor ca1 includes Figures 1 to 3 The cylindrical structure 28 in FIG. 2 serves as a cylindrical lower electrode. Capacitor CA1 can be completed by forming a dielectric layer 30 and an upper electrode 32 on cylindrical structure 28. Dielectric layer 30 and upper electrode 32 can include the materials described above. When forming capacitor CA1, insulating layers 182 and 184 can be formed at the same level as capacitor CA1 in other cross sections.

[0173] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit semiconductor device, comprising: multiple cylindrical structures separated from each other on a substrate; as well as a plurality of support members having open areas exposing side surfaces of the plurality of cylindrical structures, the plurality of support members being in contact with the side surfaces of the plurality of cylindrical structures and supporting the plurality of cylindrical structures, wherein, in a vertical cross-sectional view, each of the plurality of support members has two side surfaces with slopes and a top width that is smaller than a bottom width, In which, in the vertical sectional view, when viewed at a positive angle and a negative angle, the slope of the side surface of the first side of the portion of each of the multiple cylindrical structures located at the same level as the multiple support members is opposite to the slope of the side surface of the first side of the portion of each of the multiple cylindrical structures higher than the multiple support members.

2. The integrated circuit semiconductor device according to claim 1, wherein: The plurality of supports are located at a height lower than top surfaces of the plurality of cylindrical structures.

3. The integrated circuit semiconductor device according to claim 2, wherein: In a vertical cross-sectional view, a portion of each of the plurality of cylindrical structures higher than the plurality of support members has two side surfaces having slopes and has a top width smaller than a bottom width.

4. The integrated circuit semiconductor device according to claim 2, wherein: A top spacing between portions of the plurality of cylindrical structures that are higher than the plurality of support members is greater than a bottom spacing between portions of the plurality of cylindrical structures that are higher than the plurality of support members.

5. The integrated circuit semiconductor device according to claim 2, wherein: In a vertical cross-sectional view, a portion of each of the plurality of cylindrical structures located at the same level as the plurality of supports has two side surfaces having slopes and has a top width greater than a bottom width.

6. The integrated circuit semiconductor device according to claim 2, wherein: In a vertical cross-sectional view, a portion of each of the plurality of cylindrical structures lower than the plurality of support members has two side surfaces having slopes and has a top width greater than a bottom width.

7. The integrated circuit semiconductor device according to any one of claims 1 to 6, further comprising an additional support member located below the plurality of support members, the additional support member contacting side surfaces of the plurality of cylindrical structures and supporting the plurality of cylindrical structures.

8. The integrated circuit semiconductor device according to claim 1, wherein: The plurality of supports are located at a height lower than top surfaces of the plurality of cylindrical structures, and In a vertical cross-sectional view, a portion of each of the plurality of cylindrical structures higher than the plurality of support members has two side surfaces having a slope and being concave inward and has a top width smaller than a bottom width.

9. The integrated circuit semiconductor device according to claim 1, wherein: The plurality of supports are located at a height lower than top surfaces of the plurality of cylindrical structures, and In a vertical cross-sectional view, a portion of each of the plurality of cylindrical structures lower than the plurality of support members has two side surfaces having a slope and being concave inward and has a top width greater than a bottom width.

10. The integrated circuit semiconductor device according to claim 1, wherein: The plurality of cylindrical structures include cylindrical lower electrodes having slits therein, dielectric films between the cylindrical lower electrodes and on side surfaces of the cylindrical lower electrodes, and upper electrodes on the dielectric films.

11. An integrated circuit semiconductor device, comprising: multiple cylindrical structures separated from each other on a substrate; as well as a plurality of support members having open areas exposing side surfaces of the plurality of cylindrical structures, the plurality of support members being in contact with the side surfaces of the plurality of cylindrical structures, being located at a height lower than top surfaces of the plurality of cylindrical structures, and supporting the plurality of cylindrical structures, wherein the plurality of cylindrical structures include a first horizontal electrode portion, a second horizontal electrode portion, and a third horizontal electrode portion, the first horizontal electrode portion having a first height from the base, the second horizontal electrode portion having a second height from the top of the first horizontal electrode portion, and the third horizontal electrode portion having a third height from the top of the second horizontal electrode portion, wherein the second horizontal electrode portion and the plurality of support members are located at the same level, In a vertical cross-sectional view, each of the first and second horizontal electrode portions has two side surfaces with a slope and has a top width greater than a bottom width, and the third horizontal electrode portion has two side surfaces with a slope and has a top width smaller than a bottom width, and The side surface of the first horizontal electrode portion and the side surface of the second horizontal electrode portion are connected to the side surface of the third horizontal electrode portion, and when viewed at positive and negative angles, the slope of the side surfaces of the first horizontal electrode portion and the second horizontal electrode portion is opposite to the slope of the side surface of the third horizontal electrode portion.

12. The integrated circuit semiconductor device according to claim 11, wherein: Each of the plurality of support members is located at a side surface of the second horizontal electrode part.

13. The integrated circuit semiconductor device according to claim 11, wherein: In a vertical cross-sectional view, each of the plurality of support members has two side surfaces with slopes, and has a top width smaller than a bottom width.

14. The integrated circuit semiconductor device according to any one of claims 11 to 13, wherein: A first height of the first horizontal electrode portion is greater than a second height of the second horizontal electrode portion and a third height of the third horizontal electrode portion, and The additional support is formed at a sidewall of the first horizontal electrode part.

15. The integrated circuit semiconductor device according to claim 11, wherein The first horizontal electrode portion includes a lower horizontal electrode portion located on the top of the substrate and an upper horizontal electrode portion located on the lower horizontal electrode portion, In a vertical cross-sectional view, two side walls of each of the plurality of cylindrical structures located between the lower horizontal electrode portion and the upper horizontal electrode portion have slopes, and A bottom width of the upper horizontal electrode portion is smaller than a top width of the lower horizontal electrode portion.

16. The integrated circuit semiconductor device according to claim 11, wherein: The first horizontal electrode portion includes a lower horizontal electrode portion located on the top of the substrate and an upper horizontal electrode portion located on the lower horizontal electrode portion, and A bottom width of the second horizontal electrode portion is greater than a top width of the upper horizontal electrode portion.

17. The integrated circuit semiconductor device according to claim 11, wherein: A bottom width of the third horizontal electrode portion is smaller than a top width of the second horizontal electrode portion.

18. An integrated circuit semiconductor device, comprising: multiple cylindrical structures separated from each other on a substrate; as well as a plurality of support members having open areas exposing side surfaces of the plurality of cylindrical structures, the plurality of support members being in contact with the side surfaces of the plurality of cylindrical structures and supporting the plurality of cylindrical structures, wherein the plurality of cylindrical structures include a first horizontal electrode portion, a second horizontal electrode portion, and a third horizontal electrode portion, the first horizontal electrode portion having a first height from the base, the second horizontal electrode portion having a second height from the top of the first horizontal electrode portion, and the third horizontal electrode portion having a third height from the top of the second horizontal electrode portion, wherein the second horizontal electrode portion and the plurality of support members are located at the same level, In a vertical cross-sectional view, each of the first and second horizontal electrode portions has two side surfaces with a slope and a top width greater than a bottom width, and the third horizontal electrode portion has two side surfaces with a slope and a top width smaller than a bottom width, In a vertical cross-sectional view, a side surface of each of the first horizontal electrode portion and the second horizontal electrode portion has a positive slope, an opposite side surface of each of the first horizontal electrode portion and the second horizontal electrode portion has a negative slope, a side surface of the third horizontal electrode portion connected to a side surface of each of the first horizontal electrode portion and the second horizontal electrode portion has a negative slope, and an opposite side surface of the third horizontal electrode portion connected to the opposite side surface of each of the first horizontal electrode portion and the second horizontal electrode portion has a positive slope, and In a vertical cross-sectional view, each of the plurality of support members is located at a side surface of the second horizontal electrode portion, has two side surfaces having slopes, and has a top width smaller than a bottom width.

19. The integrated circuit semiconductor device according to claim 18, wherein: The first horizontal electrode portion includes a lower horizontal electrode portion located on the top of the substrate and an upper horizontal electrode portion located on the lower horizontal electrode portion, The upper horizontal electrode portion is recessed inwardly and has a bottom width smaller than a top width of the lower horizontal electrode portion, In a vertical cross-sectional view, two side walls of each of the plurality of cylindrical structures located between the lower horizontal electrode portion and the upper horizontal electrode portion have slopes, and A bottom width of the second horizontal electrode portion is greater than a top width of the upper horizontal electrode portion.

20. The integrated circuit semiconductor device according to claim 18, wherein The third horizontal electrode portion is recessed inwardly, and a bottom width of the third horizontal electrode portion is smaller than a top width of the second horizontal electrode portion.

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