Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a first-first wire located on a substrate, a second-first wire located on the first-first wire, a first contact connected to the first-first wire, and a second contact connected to the second-first wire, wherein the first-first wire protrudes beyond the second-first wire in a first direction, the first-first wire includes a first region having a first thickness, a second region having a second thickness, and a third region having a third thickness, the second thickness is greater than the first thickness, the third thickness is less than the first thickness and less than the second thickness, and the second region of the first-first wire is between the first region of the first-first wire and the third region of the first-first wire.

Description

[0001] Korean Patent Application No. 10-2019-0136289, filed on October 30, 2019, entitled "Semiconductor Memory Device and Method of Manufacturing Semiconductor Memory Device", is incorporated herein by reference in its entirety. Technical Field

[0002] The embodiments relate to a semiconductor memory device and a method of manufacturing the semiconductor memory device. Background Technology

[0003] To improve the integration density of dynamic random access memory, a structure has been proposed in which cell elements, each consisting of transistors and capacitors, are formed horizontally and stacked vertically. Summary of the Invention

[0004] An embodiment can be implemented by providing a semiconductor memory device comprising: a first-first conductor located on a substrate; a second-first conductor located on the first-first conductor; a first contact connected to the first-first conductor; and a second contact connected to the second-first conductor, wherein the first-first conductor protrudes beyond the second-first conductor in a first direction, the first-first conductor includes a first region having a first thickness, a second region having a second thickness, and a third region having a third thickness, the second thickness being greater than the first thickness, the third thickness being smaller than the first thickness and smaller than the second thickness, and the second region of the first-first conductor being between the first region of the first-first conductor and the third region of the first-first conductor.

[0005] An embodiment can be implemented by providing a semiconductor memory device comprising: a first semiconductor pattern and a second semiconductor pattern extending over a substrate in a second direction, the first semiconductor pattern being spaced apart from the second semiconductor pattern in a third direction different from the second direction; a first-first conductor connected to the first semiconductor pattern and extending in a first direction different from the second direction and the third direction; a second-first conductor connected to the second semiconductor pattern and extending in the first direction; a gate electrode extending in a third direction, adjacent to the first semiconductor pattern and the second semiconductor pattern; and a contact connected to the first-first conductor, wherein the second-first conductor extends over the first-first conductor along the first-first conductor, the first-first conductor protruding beyond the second-first conductor in the first direction, the first-first conductor including a first region having a first thickness in a third direction and a second region having a second thickness in a third direction, the second thickness being greater than the first thickness, and the contact being connected to the second region of the first-first conductor.

[0006] An embodiment can be implemented by providing a semiconductor memory device comprising: a plurality of semiconductor patterns stacked on a substrate along a third direction and extending in a second direction different from the third direction; a plurality of first wires respectively connected to the plurality of semiconductor patterns and extending in a first direction different from the second direction and the third direction; and a plurality of first gate electrodes respectively adjacent to the plurality of semiconductor patterns and extending in a third direction, wherein the plurality of wires includes a first-first wire and a second-first wire, the second-first wire being adjacent to the first-first wire in the third direction, the first-first wire including a protrusion extending beyond the second-first wire in the first direction, and the thickness of the portion of the first-first wire overlapping the second-first wire in the third direction in the third direction being smaller than the thickness of the protrusion of the first-first wire in the third direction in the third direction. Attached Figure Description

[0007] Features will be apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 A circuit diagram of a cell array of a semiconductor memory device according to some embodiments of the present disclosure is shown;

[0009] Figure 2 A perspective view of a semiconductor memory device according to some embodiments of the present disclosure is shown;

[0010] Figure 3A , Figure 3B and Figure 3C It shows along Figure 2 A sectional view taken from lines A-A', B-B', and C-C';

[0011] Figure 3D It shows Figure 3A An enlarged sectional view of region M;

[0012] Figure 3E It shows Figure 3C An enlarged cross-sectional view of region N;

[0013] Figure 4 A perspective view of a semiconductor memory device according to other embodiments of the present disclosure is shown;

[0014] Figure 5A It shows along Figure 4 A sectional view taken by lines A-A' and B-B';

[0015] Figure 5B It shows along Figure 4 A sectional view taken by line C-C';

[0016] Figure 6 A cross-sectional view is shown of a stage in a method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure;

[0017] Figure 7 and Figure 8 A cross-sectional view is shown of a stage in a method of manufacturing a contact region of a semiconductor memory device according to some embodiments of the present disclosure;

[0018] Figure 9A and Figure 9B A cross-sectional view is shown of a stage in a method of manufacturing a contact region of a semiconductor memory device according to some embodiments of the present disclosure;

[0019] Figures 10A to 10C A cross-sectional view is shown of a stage in a method of manufacturing a contact region of a semiconductor memory device according to other embodiments of the present disclosure;

[0020] Figures 11 to 15 A cross-sectional view is shown of a stage in a method of manufacturing a contact region of a semiconductor memory device according to some embodiments of the present disclosure;

[0021] Figure 16 A plan view of a semiconductor memory device according to other embodiments of the present disclosure is shown; and

[0022] Figure 17 It shows along Figure 16 A sectional view taken from lines A-A' and B-B'. Detailed Implementation

[0023] Figure 1 This is a circuit diagram of a cell array of a semiconductor memory device according to some embodiments of the present disclosure. (Refer to...) Figure 1 The cell array of a three-dimensional (3D) semiconductor memory device may include multiple sub-cell arrays (SCAs). The sub-cell arrays (SCAs) may be arranged along a second direction D2.

[0024] Each subcell array (SCA) may include multiple bit lines (BL), multiple word lines (WL), and multiple memory cell transistors (MCTs). The memory cell transistors (MCTs) may be located between the word lines (WL) and the bit lines (BL).

[0025] Bit lines BL can be conductive patterns (e.g., metal lines) on and spaced apart from the substrate. Bit lines BL can extend in a first direction D1 (e.g., intersecting the second direction D2). Bit lines BL can be spaced apart from each other in a vertical direction (e.g., a third direction D3 intersecting the first direction D1 and the second direction D2).

[0026] The word lines WL can be conductive patterns (e.g., metal lines) extending from the substrate in a vertical direction (third direction D3). The word lines WL can be spaced apart from each other in the first direction D1.

[0027] The gate of a memory cell transistor (MCT) can be connected to the word line WL, and the source of the MCT can be connected to the bit line BL. The MCT may include an information storage element DS. In one embodiment, the information storage element DS may be a capacitor, the drain of the MCT may be connected to the first electrode of the capacitor, and the second electrode of the capacitor may be connected to the ground line PP.

[0028] Figure 2 This is a perspective view of a semiconductor memory device according to some embodiments of the present disclosure. Figure 3A , Figure 3B and Figure 3C It is along Figure 2 A sectional view taken from lines A-A', B-B', and C-C'. Figure 3D yes Figure 3A An enlarged sectional view of region M. Figure 3E yes Figure 3C An enlarged cross-sectional view of region N.

[0029] Reference Figure 2 and Figures 3A to 3D A substrate 100, including the cell region CAR and the contact region CTR, can be provided. A first interlayer insulating film ILD1 can be on the substrate 100. The substrate 100 can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. As used herein, the term "or" is not an exclusive term; for example, "A or B" would include A, B, or A and B.

[0030] First stacked structures SS1 to fourth stacked structures SS4 may be on substrate 100. First stacked structures SS1 to fourth stacked structures SS4 may be perpendicularly spaced from substrate 100 via a first interlayer insulating film ILD1. First stacked structures SS1 to fourth stacked structures SS4 may extend parallel to each other in a first direction D1. First stacked structures SS1 to fourth stacked structures SS4 may be arranged along a second direction D2. Each of the first stacked structures SS1 to fourth stacked structures SS4 may include, for example... Figure 1 The diagram shows multiple sub-cell arrays SCA.

[0031] Each of the first stacked structures SS1 to the fourth stacked structures SS4 may include (e.g., along the third direction D3) alternately stacked semiconductor patterns SP and interlayer insulating films IL on a first interlayer insulating film ILD1. The vertically stacked semiconductor patterns SP may be perpendicularly spaced apart from each other by the interlayer insulating films IL. The interlayer insulating films IL may be between perpendicularly adjacent semiconductor patterns SP. Each interlayer insulating film IL may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-based silicon oxide film, a carbon-based silicon nitride film, or a carbon-based silicon oxynitride film.

[0032] The semiconductor pattern SP can be formed as a line, strip (bar), or pillar extending in the second direction D2. In embodiments, the semiconductor pattern SP may include silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO). Each semiconductor pattern SP may include a first impurity region SD1, a second impurity region SD2, and a channel region CH.

[0033] The channel region CH can be located between the first impurity region SD1 and the second impurity region SD2. The first impurity region SD1 and the second impurity region SD2 can have a first conductivity type (e.g., n-type). The channel region CH can be undoped or can have a second conductivity type different from the first conductivity type (e.g., p-type). The channel region CH can be... Figure 1 Each memory cell transistor (MCT) corresponds to a channel. The first impurity region SD1 and the second impurity region SD2 can be associated with... Figure 1 Each memory cell transistor (MCT) has a corresponding source and drain.

[0034] Semiconductor patterns SP can be on the cell region CAR of substrate 100. Each of the first stacking structures SS1 to the fourth stacking structures SS4 may include a first semiconductor pattern row R1 to a fourth semiconductor pattern row R4. Each of the first semiconductor pattern row R1 to the fourth semiconductor pattern row R4 may include semiconductor patterns SP stacked vertically on top of each other. In an embodiment, each of the first semiconductor pattern row R1 to the fourth semiconductor pattern row R4 may include, for example, six semiconductor patterns SP. The first semiconductor pattern row R1 to the fourth semiconductor pattern row R4 may be arranged along a first direction D1 (e.g., spaced apart from each other in the first direction D1).

[0035] Each of the first stack structure SS1 to the fourth stack structure SS4 may further include a first conductor CL1 stacked vertically. The first conductors CL1 may be spaced perpendicularly to each other by an interlayer insulating film IL. An interlayer insulating film IL may be between each pair of vertically adjacent first conductors CL1.

[0036] The first conductor CL1 may have the shape of a line or bar extending in the first direction D1. The first conductor CL1 may extend from the cell region CAR of the substrate 100 to the contact region CTR of the substrate 100.

[0037] Each first conductor CL1 can be in direct contact with a semiconductor pattern SP. In an embodiment, each first conductor CL1 can be located substantially at the same level as a corresponding semiconductor pattern in the semiconductor pattern SP (e.g., the first conductor CL1 can be at the same distance from the substrate 100 in the third direction D3 as a laterally adjacent semiconductor pattern in the semiconductor pattern SP). Each first conductor CL1 can be connected to a first impurity region SD1 of the corresponding semiconductor pattern SP in the semiconductor pattern SP. Semiconductor patterns SP located at the same level as each of the first conductors CL1 in the first semiconductor pattern rows R1 to the fourth semiconductor pattern rows R4 can extend in the second direction D2.

[0038] Reference Figures 3A to 3E The second conductor CL2 may be on the cell region CAR of the substrate 100 to penetrate each of the first stacked structures SS1 to the fourth stacked structures SS4. The second conductor CL2 may be formed as a pillar or strip (bar) extending in a direction perpendicular to the top surface of the substrate 100 (e.g., in a third direction D3). The second conductor CL2 may be arranged or spaced along a first direction D1. The second conductor CL2 may be adjacent to the first semiconductor pattern row R1 to the fourth semiconductor pattern row R4 of each of the first stacked structures SS1 to the fourth stacked structures SS4.

[0039] In one embodiment, the first-second conductor CL2 penetrating the third stacked structure SS3 may be adjacent to the sidewall of the semiconductor pattern SP of the first semiconductor pattern row R1 of the third stacked structure SS3, and the second-second conductor CL2 penetrating the third stacked structure SS3 may be adjacent to the sidewall of the semiconductor pattern SP of the second semiconductor pattern row R2 of the third stacked structure SS3. The vertical insulating pattern VIP may be located between the first-second conductor CL2 and the second semiconductor pattern row R2 of the third stacked structure SS3. The vertical insulating pattern VIP may include a silicon oxide film.

[0040] Each second conductor CL2 may be adjacent to the channel region CH of the adjacent row of semiconductor patterns SP. The second conductor CL2 may be a gate electrode. In an embodiment, the second conductor CL2 may be... Figure 1The gate of the memory cell transistor (MCT). The gate insulating film (GI) may be located between the second conductor CL2 and the channel region CH of the semiconductor pattern SP in each row. Each gate insulating film (GI) may comprise a high-k film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. In embodiments, the high-k film may comprise, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0041] The second conductive wire CL2 may include a conductive material. In embodiments, the conductive material may include, for example, a doped semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound. The second conductive wire CL2 may be... Figure 1 The letter line WL.

[0042] Reference Figure 3C Each of the first stacked structures SS1 to the fourth stacked structures SS4 (e.g., the third stacked structure SS3) may have a stepped structure on the contact area CTR of the substrate 100. The length of the first conductor CL1 of the third stacked structure SS3 stacked on the contact area CTR in the first direction D1 may decrease in the direction of movement away from the top surface of the substrate 100. For example, among the first conductors CL1 of the third stacked structure SS3, the lowermost first conductor CL1 (e.g., the first conductor CL1 adjacent to the substrate 100 in the third direction D3) may be longer than the other first conductors CL1 (e.g., the first conductor CL1 away from the substrate 100 in the third direction D3). The uppermost first conductor CL1 may be shorter than the other first conductors CL1 (e.g., may have the minimum length in the first direction D1).

[0043] The first conductive wire CL1 may include a conductive material. In embodiments, the conductive material may include a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), a metal (e.g., tungsten, titanium, or tantalum), or a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide). The first conductive wire CL1 may be... Figure 1 The bit line BL.

[0044] Each of the first stacked structures SS1 to the fourth stacked structure SS4 may further include vertically stacked information storage elements DS. The information storage elements DS may be perpendicularly spaced from each other by an interlayer insulating film IL. The information storage elements DS may extend from the semiconductor pattern SP along a second direction D2.

[0045] The information storage element DS can be in direct contact with the semiconductor pattern SP. For example, the information storage element DS can be located at substantially the same level as the semiconductor pattern SP. The information storage element DS can be connected to the second impurity region SD2 of the semiconductor pattern SP.

[0046] Reference Figure 3D The information storage element DS may include a first electrode EL1, an insulating film DL, and a second electrode EL2. In some embodiments, the information storage element DS may be a capacitor.

[0047] The first electrode EL1 can be directly connected to a second impurity region SD2 of the semiconductor pattern SP. The first electrode EL1 can be in the shape of a hollow cylinder. The first electrode EL1 can include, for example, a metal, a metal nitride, or a metal silicide. In an embodiment, the first electrode EL1 can include a film of a metal with a high melting point (e.g., cobalt, titanium, nickel, tungsten, or molybdenum). In an embodiment, the first electrode EL1 can include a metal nitride film, such as a titanium nitride film, a titanium silicon nitride film, a titanium aluminum nitride film, a tantalum nitride film, a tantalum silicon nitride film, a tantalum aluminum nitride film, or a tungsten nitride film.

[0048] An insulating film DL can be located between the first electrode EL1 and the second electrode EL2. The insulating film DL can directly cover the inner sidewall of the first electrode EL1. In an embodiment, the insulating film DL may include a metal oxide (e.g., hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, or titanium oxide) or a dielectric material with a perovskite structure (e.g., SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, Pb(Zr,Ti)O3 (PZT), or PbLa(Zr,Ti)O3 (PLZT)).

[0049] The second electrode EL2 may be on the insulating film DL. The second electrode EL2 may fill the interior of the first electrode EL1, which has a cylindrical shape. The second electrode EL2 may be connected to the third wire CL3, which will be described in more detail below. The second electrode EL2 may include, for example, silicon doped with impurities, metal, metal nitride, or metal silicide. In embodiments, the second electrode EL2 may comprise substantially the same material as the first electrode EL1.

[0050] The third conductor CL3 may extend parallel to the first stacked structures SS1 to the fourth stacked structures SS4 in the first direction D1, and may be on the cell region CAR of the substrate 100. The first-third conductor CL3 may be between the first stacked structure SS1 and the second stacked structure SS2, and the second-third conductor CL3 may be between the third stacked structure SS3 and the fourth stacked structure SS4.

[0051] The first and third conductors CL3 can be connected together to the second electrode EL2 of the capacitor in each of the first stacked structure SS1 and the second stacked structure SS2, and the second and third conductors CL3 can be connected together to the second electrode EL2 of the capacitor in each of the third stacked structure SS3 and the fourth stacked structure SS4.

[0052] The third conductive wire CL3 may include a conductive material. In embodiments, the conductive material may include, for example, a doped semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound. The third conductive wire CL3 may be... Figure 1 PP grounding wiring.

[0053] The first stacked structure SS1 and the second stacked structure SS2 may have substantially the same structure as the third stacked structure SS3 and the fourth stacked structure SS4. The first stacked structure SS1 and the second stacked structure SS2 may be symmetrical with respect to the third stacked structure SS3 and the fourth stacked structure SS4. The first stacked structure SS1 and the second stacked structure SS2 may be mirror-symmetrical with respect to the third conductor CL3 (e.g., with respect to a line extending through the third conductor CL3 in the first direction D1). The third stacked structure SS3 and the fourth stacked structure SS4 may be mirror-symmetrical with respect to the third conductor CL3. The second stacked structure SS2 and the third stacked structure SS3 may be mirror-symmetrical with respect to the second interlayer insulating film ILD2 filled between the second stacked structure SS2 and the third stacked structure SS3.

[0054] Reference Figure 3E The upper first conductor CL1 may be on the lower first conductor CL1 along a third direction D3. An interlayer insulating film IL may be on the bottom surface of the lower first conductor CL1, and another interlayer insulating film IL may be between the lower first conductor CL1 and the upper first conductor CL1. The side of the upper first conductor CL1 may be aligned with the side of the interlayer insulating film IL that contacts the upper first conductor CL1 (e.g., contacts the bottom surface of the upper first conductor CL1).

[0055] Each first conductor CL1 can be divided into three parts based on its thickness (such as its thickness measured along a third direction D3). Each first conductor CL1 may include a first region CR1 with a first thickness W1, a second region CR2 with a second thickness W2, and a third region CR3 with a third thickness W3. The second region CR2 may be located between the first region CR1 and the third region CR3, and may be directly connected to the first region CR1 and the third region CR3.

[0056] The first thickness W1 of the first region CR1 may be smaller than the second thickness W2 of the second region CR2. The first region CR1 may partially contact the interlayer insulating film IL and partially contact the second interlayer insulating film ILD2, which covers the first stacked structures SS1 to the fourth stacked structures SS4 on the first interlayer insulating film ILD1. Each of the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2 may include, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0057] The second thickness W2 of the second region CR2 can be greater than the first thickness W1 of the first region CR1 and greater than the third thickness W3 of the third region CR3. In an embodiment, the bottom surfaces (e.g., the surfaces facing the substrate 100) of the first region CR1 and the second region CR2 can be on the same plane. In an embodiment, the side surface of the second region CR2 can be aligned with the side surface of the interlayer insulating film IL that contacts the bottom surface of the second region CR2.

[0058] The third thickness W3 of the third region CR3 may be smaller than the first thickness W1 of the first region CR1 and may be smaller than the second thickness W2 of the second region CR2. The bottom surface of the third region CR3 (e.g., the surface facing the substrate 100) may be higher than the bottom surface of the second region CR2 in the third direction D3 (e.g., farther away from the substrate 100 than the bottom surface of the second region CR2).

[0059] Figure 4 This is a perspective view of a semiconductor memory device according to some embodiments of the present disclosure. Figure 5A It is along Figure 4 A sectional view taken from lines A-A' and B-B'. Figure 5B It is along Figure 4 The sectional view taken along line C-C'. The following text will focus primarily on the... Figure 1 , Figure 2 and Figures 3A to 3E To describe the differences in semiconductor memory devices Figures 4 to 5B Semiconductor memory devices.

[0060] Reference Figure 4 , Figure 5A and Figure 5B The substrate 100 may include a cell region CAR, a contact region CTR, a first peripheral circuit region PER1, and a second peripheral circuit region PER2. The contact region CTR may be located between the cell region CAR and the first peripheral circuit region PER1.

[0061] The first peripheral circuit region PER1 and the second peripheral circuit region PER2 may include peripheral transistors, resistors, and capacitors electrically connected to the memory cell array. For example, the first peripheral circuit region PER1 may include a sense amplifier connected to the bit line BL in the cell region CAR, and the second peripheral circuit region PER2 may include a line decoder and / or sub-word line driver connected to the word line WL in the cell region CAR.

[0062] Reference Figure 5A The isolation film defining the active region can be on the first peripheral circuit region PER1 of the substrate 100. The transistor can be in the active region and can be electrically connected to the lower wiring LML, which extends on or towards the cell region CAR on the first interlayer insulating film ILD1. The arrangement and structure of the first peripheral circuit region PER1 can be substantially the same as the arrangement and structure of the second peripheral circuit region PER2.

[0063] The first stacked structures SS1 to the fourth stacked structures SS4 can be on the cell region CAR and contact region CTR of the substrate 100. The first stacked structures SS1 to the fourth stacked structures SS4 can be on the first interlayer insulating film ILD1. The first stacked structures SS1 to the fourth stacked structures SS4 can be positioned higher (on the third direction D3) than the peripheral transistors in the first peripheral circuit region PER1 and the second peripheral circuit region PER2. For convenience, the semiconductor pattern SP of each of the first stacked structures SS1 to the fourth stacked structures SS4 is not shown.

[0064] The contact CNT that contacts the first conductor CL1 on the contact area CTR can penetrate the second interlayer insulating film ILD2 covering the first stack structure SS1 to the fourth stack structure SS4. The contact CNT that contacts the lower wiring LML can be on the first peripheral circuit area PER1 and the second peripheral circuit area PER2 to penetrate the second interlayer insulating film ILD2.

[0065] like Figure 5A As shown, the contact CNT that contacts the first conductor CL1 on the contact area CTR can contact the second region CR2 of the first conductor CL1. The contact CNT that contacts the first conductor CL1 on the contact area CTR may not contact the bottom surface of the second region CR2 of the first conductor CL1 or the interlayer insulating film IL that contacts the first interlayer insulating film ILD1.

[0066] The contacts (CNTs) in the contact region CTR can be arranged or spaced along the first direction D1. The contacts (CNTs) in the contact region CTR can be on a stepped structure of the first stack structure SS1 to the fourth stack structure SS4. In an embodiment, the horizontal level of the bottom surface of the contact (CNT) in the contact region CTR (e.g., the distance from the substrate 100 in the third direction D3) can increase with proximity to the cell region CAR. In an embodiment, the bottom surface of the contact (CNT) adjacent to the first peripheral circuit region PER1 can be at a first height H1, and the bottom surface of the contact (CNT) adjacent to the cell region CAR can be at a second height H2. The second height H2 can be higher than the first height H1 in the third direction D3.

[0067] In the first peripheral circuit region PER1, the contact CNTs that contact the lower wiring LML can be arranged in a zigzag pattern in the second direction D2. The contact CNTs can be arranged in a zigzag pattern in the first peripheral circuit region PER1, and process margins can be sufficiently ensured between adjacent contact CNTs. In an embodiment, the first lower wiring LML in the first peripheral circuit region PER1 can have a first end EN1, and the second lower wiring LML in the first peripheral circuit region PER1 can have a second end EN2. Compared to the first end EN1 being closer to the contact region CTR, the second end EN2 can be (e.g., in the first direction D1) closer to the contact region CTR.

[0068] The third interlayer insulating film ILD3 and the fourth interlayer insulating film ILD4 can be on the second interlayer insulating film ILD2. Via VI can be in the third interlayer insulating film ILD3. First wiring ML1, second wiring ML2, third wiring ML3, fourth wiring ML4, fifth wiring ML5, and sixth wiring ML6 can be in the fourth interlayer insulating film ILD4. First wiring ML1, second wiring ML2, third wiring ML3, fourth wiring ML4, fifth wiring ML5, and sixth wiring ML6 can contact via VI.

[0069] The first wiring ML1, the second wiring ML2, the third wiring ML3, and the fourth wiring ML4 can be electrically connected to the first conductor CL1 of the first stacked structure SS1, the first conductor CL1 of the second stacked structure SS2, the first conductor CL1 of the third stacked structure SS3, and the first conductor CL1 of the fourth stacked structure SS4 via vias VI and contacts CNT above the contact area CTR.

[0070] The first wiring ML1 can be connected to the first conductor CL1 of the first stack structure SS1 above the contact area CTR. The second wiring ML2 can be connected to the first conductor CL1 of the second stack structure SS2 above the contact area CTR. The third wiring ML3 can be connected to the first conductor CL1 of the third stack structure SS3 above the contact area CTR. The fourth wiring ML4 can be connected to the first conductor CL1 of the fourth stack structure SS4 above the contact area CTR.

[0071] The number of first wirings ML1 can be the same as the number of first conductors CL1 in the first stack structure SS1. The number of second wirings ML2 can be the same as the number of first conductors CL1 in the second stack structure SS2. The number of third wirings ML3 can be the same as the number of first conductors CL1 in the third stack structure SS3. The number of fourth wirings ML4 can be the same as the number of first conductors CL1 in the fourth stack structure SS4.

[0072] The first wiring ML1, the second wiring ML2, the third wiring ML3, and the fourth wiring ML4 may each include a first portion extending in the first direction D1 and a second portion extending in the second direction D2. For example, the first portions of the first wiring ML1 may be spaced apart from each other by a predetermined distance in the second direction D2. The second portions of the first wiring ML1 may be connected to a contact CNT above the first conductor CL1.

[0073] First wiring ML1, second wiring ML2, third wiring ML3 and fourth wiring ML4 can extend from contact area CTR to first peripheral circuit area PER1. First wiring ML1, second wiring ML2, third wiring ML3 and fourth wiring ML4 can be electrically connected to lower wiring LML via via VI and contact CNT above first peripheral circuit area PER1.

[0074] The fifth wiring ML5 can be electrically connected to the second conductor CL2 via via VI above the cell area CAR. The fifth wiring ML5 can extend in the second direction D2. The fifth wiring ML5 can extend from the cell area CAR to the second peripheral circuit area PER2. The fifth wiring ML5 can be electrically connected to the lower wiring LML via via VI and contact CNT above the second peripheral circuit area PER2.

[0075] Each fifth wiring ML5 can be connected to the second conductor CL2 of the first stack structure SS1 to the fourth stack structure SS4. In an embodiment, the second conductor CL2 arranged along the first direction D1 in the second stack structure SS2 can form a first row C1, and the second conductor CL2 arranged along the first direction D1 in the third stack structure SS3 can form a second row C2.

[0076] The first-to-second conductor CL2 in row C1 and the first-to-second conductor CL2 in row C2 can be arranged along the second direction D2 or spaced apart. The first-to-second conductor CL2 in row C1 and the first-to-second conductor CL2 in row C2 can be connected together to the first-fifth wiring ML5. The second-to-second conductor CL2 in row C1 and the second-to-second conductor CL2 in row C2 can be arranged along the second direction D2 or spaced apart. The second-to-second conductor CL2 in row C1 and the second-to-second conductor CL2 in row C2 can be connected together to the second-fifth wiring ML5.

[0077] The first to fifth wirings ML5 can extend over the second peripheral circuit area PER2 located on one side of the cell area CAR. The second to fifth wirings ML5 can extend over the second peripheral circuit area PER2 located on the other side of the cell area CAR.

[0078] The sixth wiring ML6 can be electrically connected to the third conductor CL3 via via VI above the cell area CAR. The sixth wiring ML6 can extend in the second direction D2. The sixth wiring ML6 can be connected to the upper wiring via the upper via UVI.

[0079] The bottom wiring LML, contact CNT, via VI, first wiring ML1, second wiring ML2, third wiring ML3, fourth wiring ML4, fifth wiring ML5 and sixth wiring ML6 may include metals, such as aluminum, copper, tungsten, molybdenum or cobalt.

[0080] Figure 6 This is a cross-sectional view illustrating a stage in a method for manufacturing a contact region (CTR) of a semiconductor memory device according to some embodiments of the present disclosure.

[0081] Reference Figure 6 A stacked structure in which a first interlayer insulating film ILD1, a first lower film LL1, multiple pad films L and interlayer insulating films ILD are sequentially stacked on a substrate 100 can be formed.

[0082] A pad film L extending in the same direction (e.g., in the first direction D1) can be stacked on the first lower film LL1. In an embodiment, as... Figure 6 As shown, five pads L can be set, or the number of pads L can be different.

[0083] Each pad film L may include an upper pad film HL and a lower pad film LL, and an interlayer insulating film ILD may be formed on the uppermost pad film L. The upper pad film HL of the pad film L may be formed of a conductive material or a semiconductor material (e.g., silicon, germanium, silicon-germanium, or IGZO).

[0084] Each of the lower pads LL of the pad film L may include an insulating material (e.g., a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-based silicon oxide film, a carbon-based silicon nitride film, or a carbon-based silicon oxynitride film), or may be formed of a conductive material or a semiconductor material (e.g., silicon, germanium, silicon germanium, or IGZO).

[0085] The manufacturing process described below can also be performed depending on the material of the lower pad LL of the pad L. The upper pad HL and the lower pad LL of the pad L can have similar electrical and chemical properties, but can include different materials.

[0086] Figure 7 and Figure 8 This is a cross-sectional view illustrating a stage in a method for manufacturing a contact region of a semiconductor memory device according to some embodiments of the present disclosure.

[0087] Reference Figure 7 This allows for the removal of portions of the interlayer insulating film (ILD) and the pad film (L) to form a stepped stacked structure.

[0088] The entire upper pad film HL of the topmost pad film L can be exposed, and the upper pad films HL of the other pad films L and the first lower film LL1 can be partially exposed. The sides of the lower pad film LL of the pad film L can be exposed.

[0089] Forming a stepped stacked structure may include performing a trimming process on the stacked structure. In an embodiment, the trimming process may include forming a mask pattern covering the thin film structure in the cell region CAR and the contact region CTR, etching portions of the thin film structure, and reducing the horizontal dimension of the mask pattern, and the steps of etching portions of the thin film structure and reducing the horizontal dimension of the mask pattern may be repeated. As a result of the trimming process, the stacked structure may be formed as a stepped stacked structure descending in the direction from the contact region CTR to the first peripheral circuit region PER1.

[0090] Reference Figure 8 In the contact region CTR, pad silicon films PS can be stacked along the top and side surfaces of a stepped stacking structure. The pad silicon films PS can include silicon films of a first conductivity type (e.g., n-type). In embodiments, the pad silicon films PS can be undoped or can have a second conductivity type (e.g., p-type) different from the first conductivity type. The pad silicon films PS can include the same material as the upper pad film HL of the pad film L.

[0091] The thickness of the silicon pad film (PS) can be uniform across the top and sides of the stepped stacked structure, and the PS can be formed by, for example, atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PE-CVD), atmospheric pressure chemical vapor deposition (AP-CVD), or flowable chemical vapor deposition (FCVD).

[0092] Figure 9A and Figure 9B This is a cross-sectional view illustrating a stage in a method for manufacturing a contact region (CTR) of a semiconductor memory device according to some embodiments of the present disclosure.

[0093] Figure 9A and Figure 9B This illustrates how to remove the pad silicon film (PS) from the side of the stacked structure in the contact region CTR. (See reference...) Figure 9A and Figure 9B Carbon ions can be implanted into the silicon pad film (PS) by performing ion implantation along a direction aligned with the third direction D3. Based on the arrangement of the PS and the direction of carbon ion implantation, the PS can be divided into regions containing carbon impurities and regions excluding carbon impurities.

[0094] Depending on the direction of the implanted carbon ions, the portion of the silicon pad film PS located on the side of the stacked structure in the contact region CTR may not contain carbon impurities. The portion of the silicon pad film PS without carbon impurities can be removed by wet etching, and the portion of the silicon pad film PS containing carbon impurities can be retained without removal. The retained / unremoved portion of the silicon pad film PS can be used as a lifting pad RP to cover the upper pad film HL and the lower pad film LL. In an embodiment, an ammonia deionization mixture (ADM) solution can be used to wet-etch the silicon pad film PS.

[0095] Figure 10A , Figure 10B and Figure 10C This is a cross-sectional view illustrating a stage in a method for manufacturing a contact region (CTR) of a semiconductor memory device according to other embodiments of the present disclosure.

[0096] Figure 10A , Figure 10B and Figure 10C The following illustrates how the pad silicon film PS can be removed from the side of a stacked structure in the contact region CTR according to other embodiments of the present disclosure. (Refer to...) Figures 10A to 10C A sacrificial insulating film SILD with low step coverage can be stacked along the top and side surfaces of the pad silicon film PS. In an embodiment, the sacrificial insulating film SILD may include, for example, silicon oxide.

[0097] Due to the low step coverage of the sacrificial insulating film SILD, the width or thickness W1 of the portion of the sacrificial insulating film SILD on the top surface of the pad silicon film PS (e.g., in the third direction D3) can be larger than the width or thickness W2 of the portion of the sacrificial insulating film SILD on the side surface of the pad silicon film PS (e.g., in the first direction D1).

[0098] The portion of the sacrificial insulating film SILD on the top surface of the pad silicon film PS can be etched as much as the width W2, so that the sacrificial insulating film SILD can be retained only on a portion of the top surface of the pad silicon film PS as having a width or thickness W3.

[0099] The retained portion of the sacrificial insulating film SILD can be used as a passivation film for the pad silicon film PS, allowing the side portions of the pad silicon film PS to be removed by wet etching, while the portions of the pad silicon film PS on the top surface of the pad film L and on the top surface of the first lower film LL1 can be retained without removal (e.g., forming a lifting pad RP). In an embodiment, an ADM solution can be used to wet-etch the pad silicon film PS. As a result of the wet etching, the retained portion of the sacrificial insulating film SILD can be removed.

[0100] Figures 11 to 15 A cross-sectional view is shown of a stage in a method for manufacturing a contact region of a semiconductor memory device according to some embodiments of the present disclosure.

[0101] Reference Figure 11 After removing the pad silicon film PS from the side of the pad film L, the contact area CTR can be filled with a second interlayer insulating film ILD2. The second interlayer insulating film ILD2 may include insulating materials, such as silicon oxide film, silicon nitride film, silicon oxynitride film, carbon-based silicon oxide film, carbon-based silicon nitride film, or carbon-based silicon oxynitride film.

[0102] The second interlayer insulating film ILD2 can cover the uppermost pad film L and can be formed in the space between the lifting pad RP and the pad film L. The second interlayer insulating film ILD2 can also be formed in the space between the first lower film LL1 and the lowermost lifting pad RP.

[0103] Reference Figure 12 It can pass through the second interlayer insulating film ILD2 and through the lifting pad RP to form contact holes in the upper pad film HL of the pad film L and in the first lower film LL1. Contact holes can be formed in the second region CR2 (refer to...). Figure 3E In ), and can be arranged or spaced apart along the first direction D1.

[0104] The depth of the contact holes formed in the first lower membrane LL1 can be greater than the depth of the contact holes formed in the uppermost membrane HL.

[0105] Reference Figure 13 A metal can be used to form contacts in the contact hole. In an embodiment, the metal may include, for example, tungsten (W).

[0106] When the lower pad LL of the pad L is formed of a conductive or semiconductor material (e.g., silicon, germanium, silicon germanium, or IGZO), the lower pad LL of the pad L can be replaced with an insulating film (e.g., silicon oxide film, silicon nitride film, silicon oxynitride film, carbon-based silicon oxide film, carbon-based silicon nitride film, or carbon-based silicon oxynitride film).

[0107] Reference Figure 14 and Figure 15 The lower pad LL of the pad film L can be formed as an interlayer insulating film IL, and the upper pad HL and lifting pad RP of the pad film L can be replaced with a first conductive wire CL1 filled with conductive material. The conductive material may include, for example, a doped semiconductor material, a conductive metal nitride, a metal, or a metal semiconductor compound.

[0108] Figure 16 This is a plan view of a semiconductor memory device according to other embodiments of the present disclosure. Figure 17 It is along Figure 16 The sectional view is taken from lines A-A' and B-B'. The following text will focus primarily on the section with... Figure 1 , Figure 2 , Figures 3A to 3E , Figure 4 , Figure 5A and Figure 5B To describe the differences in semiconductor memory devices Figure 16 and Figure 17 Semiconductor memory devices.

[0109] Reference Figure 16 and Figure 17 The first conductor CL1, extending along the first direction D1 above the contact area CTR, can be used as a word line WL instead of a bit line BL. The spacer PSP, common source contact CSC, and vertical structure ST, extending along the third direction D3 in the cell area CAR, can penetrate the first conductor CL1. The wiring ML can be electrically connected to the first conductor CL1 above the contact area CTR via via VI and contact CNT.

[0110] In one embodiment, the common source contact (CSC) may include, for example, tungsten, copper, aluminum, titanium, or tantalum. A spacer (PSP) may surround the outer wall of the common source contact (CSC). In another embodiment, the spacer (PSP) may include an insulating material, such as a silicon oxide film or a silicon nitride film.

[0111] The vertical structure ST may include a vertical channel layer VC, a vertical insulating pattern GL, and an information storage element DS within the vertical structure ST. Each vertical channel layer VC may be in the shape of a hollow tube, column, or cup. The vertical channel layer VC may be electrically connected to the substrate 100. Each vertical channel layer VC may include a single film or multiple films. Each vertical channel layer VC may include, for example, a single-crystal silicon film, an organic semiconductor film, or a carbon nanostructure.

[0112] The vertical insulating pattern GL can be located in the space surrounded by the vertical channel layer VC. Each vertical insulating pattern GL can include an insulating material. In an embodiment, each vertical insulating pattern GL can include, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0113] The information storage element DS in the vertical structure ST can be located between the vertical channel layer VC and the first conductor CL1. The information storage element DS in the vertical structure ST can extend along the outer surface of the vertical channel layer VC in a third direction D3. In one embodiment, the information storage element DS in the vertical structure ST can have a shape surrounding the outer surface of the vertical channel layer VC. In another embodiment, the information storage element DS can be a charge storage film used to form a capacitor.

[0114] The pad MP can be located above, or on, the vertical channel layer VC, the information storage element DS, and the vertical insulating pattern GL in the vertical structure ST. The pad MP can be electrically connected to the vertical channel layer VC. The pad MP can include a conductive material or a semiconductor material doped with impurities of a different conductivity type than the vertical channel layer VC.

[0115] The second conductor CL2 can be electrically connected to the pad MP via the contact CNT. The second conductor CL2 can operate as a drain and can cross over in the second direction D2. Figure 16 and Figure 17 The extension of semiconductor memory devices.

[0116] In summary and review, in addition to vertically stacked DRAM, contacts can be bonded in memory devices with multi-layer structures using a stepped-pad process. Because the upper and lower contacts are etched at different rates, the upper pad is sometimes pierced and connected to the pad directly below it.

[0117] According to an embodiment, the open pad area can be selectively thickened during the stepped pad process, thereby minimizing perforation defects.

[0118] One or more embodiments may provide a semiconductor memory device with a vertical structure in which the opening regions are selectively thickened during a stepped pad process.

[0119] One or more embodiments may provide a method for manufacturing a semiconductor memory device having a vertical structure in which the opening regions are selectively thickened during a stepped pad process.

[0120] Example embodiments have been disclosed herein, and although specific terminology has been used, they are used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, as of the time of filing of this application, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: The first-first conductor is located on the substrate; The second-first conductor is located on the first-first conductor; The first interlayer insulating film is located between the first-first conductor and the second-first conductor; The first contact element is connected to the first-first wire; as well as The second contact is connected to the second-first wire. in: The first-first conductor protrudes beyond the second-first conductor in the first direction. The first conductor includes a first region having a first thickness, a second region having a second thickness, and a third region having a third thickness, wherein the second thickness is greater than the first thickness, and the third thickness is smaller than both the first and second thicknesses. The second region of the first-first conductor is located between the first region of the first-first conductor and the third region of the first-first conductor. The second-first conductor includes regions four and five. The thickness of the fourth region of the second-first conductor is greater than the thickness of the fifth region of the second-first conductor. The bottom surface of the first contact is lower than the top surface of the first region of the first-first conductor, and The side surface of the fourth region of the second-first conductor is coplanar with the side surface of the first interlayer insulating film.

2. The semiconductor memory device according to claim 1, in, The first interlayer insulating film is located on the first region of the first-first conductor.

3. The semiconductor memory device according to claim 2, wherein, A portion of the first region of the first conductor protrudes beyond the side of the first interlayer insulation film in the first direction.

4. The semiconductor memory device according to claim 2, wherein, The second-first conductor includes a protrusion that extends beyond the side of the first interlayer insulation film in a first direction.

5. The semiconductor memory device according to claim 1, wherein, The first contact is connected to the second region of the first-first conductor.

6. The semiconductor memory device of claim 1, further comprising a second interlayer insulating film located between the substrate and the first-first conductive line. in, The side of the second interlayer insulating film is aligned with the side of the second region of the first-first conductor.

7. The semiconductor memory device according to claim 1, wherein, The second region of the first-first conductor is directly connected to the first region of the first-first conductor, and is also directly connected to the third region of the first-first conductor.

8. The semiconductor memory device according to claim 1, wherein: The height of the bottom surface of the first region of the first-first conductor from the top surface of the substrate is the same as the height of the bottom surface of the second region of the first-first conductor from the top surface of the substrate, and The height of the bottom surface of the second region of the first-first conductor from the top surface of the substrate is smaller than the height of the bottom surface of the third region of the first-first conductor from the top surface of the substrate.

9. The semiconductor memory device according to claim 1, wherein, The third region of the first-first conductor protrudes from the side of the second region of the first-first conductor in the first direction.

10. The semiconductor memory device of claim 1, further comprising: A semiconductor pattern is connected to a first-first wire and a second-first wire, and extends in a second direction different from the first direction; as well as The gate electrode extends upward in a third direction, different from the first and second directions, and is adjacent to the semiconductor pattern. in: The semiconductor pattern includes a first impurity region, a second impurity region, and a channel region, wherein the channel region is located between the first impurity region and the second impurity region. The first wire is electrically connected to the first impurity region, and The gate electrode is adjacent to the channel region.

11. The semiconductor memory device of claim 1, further comprising a vertical structure penetrating the first-first wire and the second-first wire. in, The vertical structure includes: a vertical insulating pattern; a vertical channel layer extending along the outer side of the vertical insulating pattern; and a charge storage film located between the vertical channel layer and the first-first conductor and the second-first conductor.

12. A semiconductor memory device, the semiconductor memory device comprising: A first semiconductor pattern and a second semiconductor pattern extend on a substrate along a second direction, with the first semiconductor pattern spaced apart from the second semiconductor pattern in a third direction different from the second direction. First-first wire, connected to first semiconductor pattern, and extending in a first direction different from the second direction and the third direction; The second-first wire is connected to the second semiconductor pattern and extends in the first direction; An interlayer insulating film is located between the first-first conductor and the second-first conductor; A gate electrode extends upward in a third direction, and the gate electrode is adjacent to a first semiconductor pattern and a second semiconductor pattern; as well as Contact element, connected to the first-first wire, in: The second-first conductor extends along the first-first conductor above it. The first-first conductor protrudes beyond the second-first conductor in the first direction. The first conductor includes a first region having a first thickness in a third direction and a second region having a second thickness in a third direction, the second thickness being greater than the first thickness. The second-first conductor includes regions four and five. The thickness of the fourth region of the second-first conductor is greater than the thickness of the fifth region of the second-first conductor. The contact is connected to the second region of the first-first conductor, and the bottom surface of the contact is lower than the top surface of the first region of the first-first conductor. The side surface of the fourth region of the second-first conductor is coplanar with the side surface of the interlayer insulating film.

13. The semiconductor memory device according to claim 12, in, A portion of the first region of the first conductor protrudes beyond the side of the interlayer insulation film in the first direction.

14. The semiconductor memory device according to claim 12, wherein, The second-first conductor does not overlap with the second region of the first-first conductor in the third direction.

15. The semiconductor memory device according to claim 12, wherein: The first-first conductor also includes a third region, which protrudes beyond the side of the second region of the first-first conductor in a first direction, and The third region of the first-first conductor has a third thickness that is smaller than the first thickness and smaller than the second thickness in the third direction.

16. The semiconductor memory device according to claim 12, wherein: The first semiconductor pattern includes a first impurity region, a second impurity region, and a channel region, wherein the channel region is located between the first impurity region and the second impurity region. The first wire is electrically connected to the first impurity region, and The gate electrode is adjacent to the channel region.

17. The semiconductor memory device of claim 16, further comprising a capacitor connected to the second impurity region.

18. A semiconductor memory device, the semiconductor memory device comprising: Multiple semiconductor patterns are stacked on a substrate along a third direction and extend in a second direction different from the third direction; Multiple first wires are respectively connected to the multiple semiconductor patterns and extend in a first direction different from the second direction and the third direction; A plurality of first gate electrodes are respectively adjacent to the plurality of semiconductor patterns and extend upward in a third direction, wherein the plurality of first wires include a first-first wire and a second-first wire, and the second-first wire is adjacent to the first-first wire in a third direction. An interlayer insulating film is located between the first-first conductor and the second-first conductor; and a contact element is connected to the first-first conductor. in: The first-first conductor includes a protrusion that extends beyond the second-first conductor in a first direction. The thickness of the portion of the first-first conductor overlapping the second-first conductor in the third direction is smaller than the thickness of the protrusion of the first-first conductor in the third direction. The second-first conductor includes a first region and a second region. The thickness of the first region of the second-first conductor is greater than the thickness of the second region of the second-first conductor. The bottom surface of the contact is lower than the top surface of the portion of the first-first wire that overlaps with the second-first wire in the third direction, and The side surface of the first region of the second-first conductor is coplanar with the side surface of the interlayer insulating film.

19. The semiconductor memory device according to claim 18, wherein, The insulating material is located between the protrusions of the second-first conductor and the first-first conductor.

20. The semiconductor memory device of claim 18, wherein, The height of the protrusion of the first conductor from the top surface of the substrate is smaller than the height of the second conductor from the top surface of the substrate.

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