Semiconductor device

Abstract

Disclosed is a semiconductor device including a lower structure, an upper pattern, a stacked structure, a separation structure passing through the stacked structure, a vertical structure including a channel layer, wherein the stacked structure includes a plurality of interlayer insulating layers and a plurality of gate layers, the lower structure includes a first lower pattern and a second lower pattern having a material different from that of the first lower pattern, the first lower pattern includes a first portion located between the second lower pattern and the channel layer, a second portion extending from the first portion to a region between the second lower pattern and the upper pattern, and a third portion extending from the first portion to a region between the second lower pattern and a base structure, and the first lower pattern does not extend toward a side surface of the upper pattern.

Description

[0001] Korean Patent Application No. 10-2019-0137329 filed on October 31, 2019, in the Korean Intellectual Property Office and entitled "Semiconductor Device," is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor device including a lower structure between a substrate and a stacked structure, and a method of forming the same. BACKGROUND

[0003] To improve the integration of a semiconductor device, a semiconductor device including stacked gates spaced apart in a direction perpendicular to an upper surface of a substrate has been developed. As the number of stacked gates increases, unexpected process defects can occur, making it difficult to improve the productivity of the semiconductor device. SUMMARY

[0004] A technical problem of the present disclosure is to provide a semiconductor device having improved reliability.

[0005] Another technical problem is to provide a semiconductor device having improved integration.

[0006] A semiconductor device according to an example embodiment is provided. The semiconductor device includes a substrate structure, a lower structure on the substrate structure, an upper pattern on the lower structure, a stacked structure on the lower structure, a separation structure through the stacked structure, vertical structures between the separation structures, through the stacked structure, the upper pattern, and the lower structure and extending into the substrate structure, and including channel layers, contact plugs on the vertical structures, and wires on the contact plugs, wherein the stacked structure includes a plurality of interlayer insulation layers and a plurality of gate layers alternately and repeatedly stacked, the lower structure includes a first lower pattern and a second lower pattern having a material different from that of the first lower pattern, the first lower pattern includes a first portion between the second lower pattern and the channel layers, a second portion extending from the first portion to an area between the second lower pattern and the upper pattern, and a third portion extending from the first portion to an area between the second lower pattern and the substrate structure, and the first lower pattern does not extend toward a side surface of the upper pattern.

[0007] A semiconductor device according to some embodiments is provided. The semiconductor device includes a lower structure on a base structure, an upper pattern on the lower structure, a stack structure on the upper pattern, a vertical structure passing through the stack structure, the upper pattern, and the lower structure and extending into the base structure, and a separation structure passing through the stack structure, the upper pattern, and the lower structure and spaced apart from the vertical structure, wherein the upper pattern includes an upper portion parallel to an upper surface of the base structure and a support portion extending from the upper portion and in contact with the base structure, the lower structure is between the upper portion of the upper pattern and the base structure, the separation structure includes a first separation portion passing through the stack structure, the upper portion of the upper pattern, and the lower structure, and a second separation portion passing through the stack structure and in contact with the support portion of the upper pattern, the stack structure includes a plurality of gate layers stacked and spaced apart in a direction perpendicular to the upper surface of the base structure, the vertical structure includes a channel layer passing through the plurality of gate layers, the upper portion of the upper pattern, and the lower structure and extending into the base structure, the lower structure includes a first lower pattern and a second lower pattern having a material different from that of the first lower pattern, and the first lower pattern includes a first portion between the second lower pattern and the channel layer, a second portion extending from the first portion to an area between the second lower pattern and the upper pattern, and a third portion extending from the first portion to an area between the second lower pattern and the base structure.

[0008] A semiconductor device according to some embodiments is provided. The semiconductor device includes a lower structure on a base structure, an upper pattern on the lower structure, a stack structure on the upper pattern, a vertical structure passing through the stack structure, the lower structure, and the upper pattern and extending into the base structure, and a separation structure passing through the stack structure, the upper pattern, and the lower structure and spaced apart from the vertical structure, wherein the stack structure includes a plurality of gate layers stacked and spaced apart in a direction perpendicular to an upper surface of the base structure, the vertical structure includes a channel layer passing through the plurality of gate layers, the upper pattern, and the lower structure and extending into the base structure, and the lower structure includes a first lower pattern and a second lower pattern having a material having etching selectivity with respect to a material of the first lower pattern, wherein the first lower pattern includes a first portion between the second lower pattern and the channel layer, a second portion extending from the first portion to an area between the second lower pattern and the upper pattern, and a third portion extending from the first portion to an area between the second lower pattern and the base structure, and at least one of the second portion of the first lower pattern, the third portion of the first lower pattern, and the second lower pattern has a side surface recessed compared to a side surface of the upper pattern. BRIEF DESCRIPTION OF DRAWINGS

[0009] Features will become apparent to those of ordinary skill in the art upon examination of the following details description of example embodiments in conjunction with the accompanying drawings, in which:

[0010] FIG. 1 is a plan view of a semiconductor device according to example embodiments;

[0011] FIG. 2 is a sectional view of the area taken along the line I-I' of FIG. 1

[0012] FIG. 3A and FIG. 3B is an enlarged sectional view of a portion of FIG. 2

[0013] FIG. 4A is a partial enlarged sectional view of a modified example embodiment of the semiconductor device according to the example embodiment;

[0014] FIG. 4B is a partial enlarged sectional view of a modified example embodiment of the semiconductor device according to the example embodiment;

[0015] FIG. 4C is a partial enlarged sectional view of a modified example embodiment of the semiconductor device according to the example embodiment;

[0016] FIG. 4D is a partial enlarged sectional view of a modified example embodiment of the semiconductor device according to the example embodiment;

[0017] FIG. 4E is a partial enlarged sectional view of a modified example embodiment of the semiconductor device according to the example embodiment;

[0018] FIG. 4F is a partial enlarged sectional view of a modified example embodiment of the semiconductor device according to the example embodiment; and

[0019] FIG. 5A through FIG. 5E is a sectional view of a method for manufacturing a semiconductor device according to the example embodiment. DETAILED DESCRIPTION

[0020] Hereinafter, a semiconductor device according to an example embodiment will be described with reference to FIG. 1 , FIG. 2 , FIG. 3A and FIG. 3B . FIG. 1 is a plan view of a semiconductor device according to the example embodiment, FIG. 2 is a sectional view of the area taken along the line I-I' of FIG. 1 FIG. 3A is an enlarged sectional view of the area "A" of FIG. 2 FIG. 3B is an enlarged sectional view of the area "B" of FIG. 2

[0021] based on FIG. 1 , FIG. 2 , FIG. 3A and FIG. 3B ​​​​​A substrate structure 3 may be provided. In the example, the substrate structure 3 may include a lower substrate 5, a peripheral circuit region 7 on the lower substrate 5, and / or an upper substrate 9 on the peripheral circuit region 7.

[0022] In this example, the lower substrate 5 can be a semiconductor substrate, such as a single-crystal silicon substrate. The upper substrate 9 can be an N-type conductive polycrystalline silicon substrate.

[0023] In another example, the upper substrate 9 may include at least one conductive material selected from metal nitrides (e.g., titanium nitride (TiN), tungsten nitride (WN), etc.), metal semiconductor compounds (e.g., titanium silicide (TiSi), tungsten silicide (WSi), etc.) and metals (e.g., tungsten (W), etc.) and a polycrystalline silicon layer located on the layer of conductive material.

[0024] In the example, the peripheral circuit region 7 may include a peripheral circuit 7a and a lower insulating layer 7b covering the peripheral circuit 7a. A lower structure 75 may be disposed on the substrate structure 3. An upper pattern 16 may be disposed on the lower structure 75. A stacked structure 20' may be disposed on the upper pattern 16. A first upper insulating layer 53 may be disposed on the stacked structure 20'. A separating structure 84 may be disposed through the first upper insulating layer 53 and the stacked structure 20'.

[0025] A vertical structure 33, passing through the stacked structure 20', the upper pattern 16, and the lower structure 75 and extending into the base structure 3, can be disposed between the partition structures 84. A second upper insulating layer 87 can be disposed on the first upper insulating layer 53. A contact plug 90 can be disposed passing through the second upper insulating layer 87 and the first upper insulating layer 53 and electrically connected to the vertical structure 33. A wire 93 can be disposed on the contact plug 90.

[0026] In the example, the conductor 93 may have a shape extending in a first horizontal direction X, while the separator structure 84 may have a line shape extending in a second horizontal direction Y perpendicular to the first horizontal direction X. The first horizontal direction X and the second horizontal direction Y may be parallel to the upper surface 3s of the base structure 3.

[0027] The stacking structure 20' may include a lower stacking structure 20L' and an upper stacking structure 20U' located on the lower stacking structure 20L'.

[0028] The lower stacked structure 20L' and the upper stacked structure 20U' may include a plurality of interlayer insulating layers 25 and a plurality of horizontal layers 81 that are stacked alternately and repeatedly along the vertical direction Z. The vertical direction Z may refer to the direction perpendicular to the upper surface 3s of the substrate structure 3.

[0029] In the lower stacked structure 20L' and the upper stacked structure 20U', the uppermost interlayer insulating layer 25 of the interlayer insulating layer 25 may be thicker than the interlayer insulating layer 25 between the horizontal layers 81.

[0030] In the example, the interlayer insulating layer 25 can be formed of silicon oxide.

[0031] In the example, each horizontal layer 81 may include a conductive material.

[0032] In the example, each horizontal layer 81 may include a first layer 81a and a second layer 81b. The first layer 81a is located between the second layer 81b and the vertical structure 33, and may cover the upper and lower surfaces of the second layer 81b.

[0033] In the example, the first layer 81a and the second layer 81b can be formed of different materials. For example, the second layer 81b can be formed of a conductive material (such as doped silicon, metal nitrides (e.g., TiN, WN, etc.), metal semiconductor compounds (e.g., TiSi, WSi, etc.) or a metal (e.g., W, etc.)), while the first layer 81a can be formed of an insulating material. The first layer 81a can be formed of a high-k dielectric such as aluminum oxide (AlO).

[0034] In another example, the first layer 81a may be formed of a metal nitride (e.g., TiN, WN, etc.), while the second layer 81b may be formed of a metal (e.g., W, etc.).

[0035] In another example, the horizontal layer 81 may be formed of at least one conductive material, such as doped silicon, metal nitride (e.g., TiN, WN, etc.), metal semiconductor compound (e.g., TiSi, WSi, etc.) or metal (e.g., W, etc.)).

[0036] Horizontal layer 81 may be a gate layer. The portion of horizontal layer 81 formed of conductive material may be a gate electrode. For example, in some example embodiments where the first layer 81a is formed of insulating material and the second layer 81b is formed of conductive material, the second layer 81b of horizontal layer 81 may be a gate electrode.

[0037] The horizontal layer 81 may include a plurality of lower gate layers 81L, a plurality of intermediate gate layers 81M located on the plurality of lower gate layers 81L, and a plurality of upper gate layers 81U located on the plurality of intermediate gate layers 81M.

[0038] An insulating spacer pattern 30 may be partially disposed within the stacked structure 20'. The insulating spacer pattern 30 may be formed of an insulating material such as silicon oxide. The insulating spacer pattern 30 may extend through multiple upper gate layers 81U. The insulating spacer pattern 30 may be disposed on multiple intermediate gate layers 81M.

[0039] There can be multiple vertical structures 33. Some of the multiple vertical structures 33 can pass through the insulating separation pattern 30. As previously described, some of the vertical structures 33 that pass through the insulating separation pattern 30 can be dummy vertical structures 33d.

[0040] The vertical structure 33 may include a core region 48, a pad pattern 50 located on the core region 48, a channel layer 46 covering the side and bottom surfaces of the core region 48 and in contact with the pad pattern 50, and a dielectric structure 36 surrounding the outer side surface of the channel layer 46.

[0041] The channel layer 46 may be formed of a semiconductor material. The channel layer 46 may be formed of polysilicon. The pad pattern 50 may be formed of polysilicon (e.g., N-type conductive polysilicon). The pad pattern 50 may contact the contact plug 90. The core region 48 may include an insulating material, or include an insulating material forming voids therein.

[0042] The dielectric structure 36 may include a first dielectric layer 38, a second dielectric layer 42, and a data storage material layer 40 located between the first dielectric layer 38 and the second dielectric layer 42. The first dielectric layer 38 may be disposed between the data storage material layer 40 and the stacked structure 20', and the second dielectric layer 42 may be disposed between the data storage material layer 40 and the channel layer 46. The data storage material layer 40 may be a charge trapping layer, such as silicon nitride. The data storage material layer 40 may include regions capable of storing information in a semiconductor device such as a vertical NAND flash memory device.

[0043] In the example, at least the lowest of the plurality of lower gate layers 81L may be the gate layer of the erase transistor used in a vertical NAND flash memory device that utilizes gate-induced drain leakage (GIDL) to erase the transistor.

[0044] In the example, the gate layer of one of the plurality of lower gate layers 81L located on the gate layer of the erase transistor used in the erase process can be the ground selection layer of the ground selection transistor.

[0045] In the example, at least a few of the multiple intermediate gate layers 81M may be word lines forming memory cells of a vertical NAND flash memory.

[0046] In the example, at least the uppermost of the plurality of upper gate layers 81U may be the gate layer of the erase transistor used in a vertical NAND flash memory device that utilizes gate-induced drain leakage (GIDL) to erase.

[0047] In the example, one or more gate layers among the multiple upper gate layers 81U located below the erase transistor gate layer can be the gate layer of the string select transistor of the vertical NAND flash memory device.

[0048] The dielectric structure 36 may include a first dielectric structure 36a and a second dielectric structure 36b spaced apart.

[0049] The first dielectric structure 36a is in contact with the horizontal layer 81 and also with a portion of the upper pattern 16. The second dielectric structure 36b can be in contact with the substrate structure 3.

[0050] The upper pattern 16 may include a horizontal portion 16a located on the lower structure 75 and a support portion 16b extending from the horizontal portion 16a and contacting the base structure 3. The horizontal portion 16a may be disposed between the lower structure 75 and the stacked structure 20'. The lower structure 75 includes a first side surface that contacts the support portion 16b of the upper pattern 16 and a second side surface that contacts the partition structure 84.

[0051] The lower structure 75 may include a first lower pattern 65 and a second lower pattern 69. The first lower pattern 65 and the second lower pattern 69 may be formed of different materials. The first lower pattern 65 may be formed of silicon. The first lower pattern 65 may be formed of doped polycrystalline silicon (e.g., N-type conductive polycrystalline silicon).

[0052] The second lower pattern 69 can be formed of a material that is etch-selective to the material of the first lower pattern 65. For example, the second lower pattern 69 can be formed of an insulating material (e.g., silicon oxide). The second lower pattern 69 can be replaced with a material different from silicon oxide. For example, the second lower pattern 69 can be replaced with a conductive material different from the material of the first lower pattern 65 (e.g., TiN, TaN, WN, TiSi, WSi, TaSi, W, Ta, Ti, etc.).

[0053] In the example, the first lower pattern 65 and the upper pattern 16 can be formed from the same material (such as polycrystalline silicon).

[0054] In the example, the first lower pattern 65 and the second lower pattern 69 may not extend toward the side surface 16s of the upper pattern 16. The first lower pattern 65 and the second lower pattern 69 may not extend toward the area between the side surface 16s of the upper pattern 16 and the separating structure 84.

[0055] The second lower pattern 69 can be separated from the base structure 3 and the upper pattern 16.

[0056] The first lower pattern 65 may include a first portion 65a located between the second lower pattern 69 and the channel layer 46, a second portion 65b extending from the first portion 65a to the region between the second lower pattern 69 and the upper pattern 16, and a third portion 65c extending from the first portion 65a to the region between the second lower pattern 69 and the substrate structure 3.

[0057] The first lower pattern 65 may further include an upper extension 65e1 extending from the first portion 65a to the region between the upper pattern 16 and the channel layer 46, and a lower extension 65e2 extending to the region between the substrate structure 3 and the channel layer 46. The upper extension 65e1 may contact the first dielectric structure 36a, and the lower extension 65e2 may contact the second dielectric structure 36b.

[0058] The first portion 65a, the upper extension portion 65e1, and the lower extension portion 65e2 in the first lower pattern 65 can contact the channel layer 46.

[0059] The first lower pattern 65 may also include a fourth part 65d extending from the second part 65b and the third part 65c and located between the second lower pattern 69 and the support part 16b of the upper pattern 16.

[0060] The separator 84 may include an insulating material. For example, the separator 84 may be formed of an insulating material such as silicon oxide. In another example, the separator 84 may include a conductive material and an insulating material that electrically isolates the conductive material from the stacked structure 20'.

[0061] The partition structure 84 may include a first partition portion 84a passing through the horizontal portion 16a of the upper pattern 16 and the lower structure 75, and a second partition portion 84b contacting the support portion 16b of the upper pattern 16.

[0062] In the partition structure 84, the first partition portion 84a can contact the lower structure 75, and the second partition portion 84b can be spaced apart from the lower structure 75.

[0063] In an embodiment, by filling the space between the horizontal portion 16a of the upper pattern 16 and the substrate structure 3 with a lower structure 75 comprising a first lower pattern 65 and a second lower pattern 69 formed of different materials, defects that may occur between the horizontal portion 16a of the upper pattern 16 and the substrate structure 3 can be reduced or prevented. Therefore, a semiconductor device with improved reliability can be provided.

[0064] Reference FIG. 4A through FIG. 4C Various modified example embodiments of structure 75 and the first dividing portion 84a are described below. FIG. 4A through FIG. 4C It is shown FIG. 2 Enlarged cross-sectional views of various modified example embodiments of region "B".

[0065] In the modified example embodiment, based on FIG. 4A Previous reference FIG. 1 through FIG. 3B The described substructure ( FIG. 1 through FIG. 3B75) can be replaced by a lower structure 75a having recessed side surfaces 65s and 69s. For example, in the lower structure 75a, the side surfaces 65s of the first lower pattern 65 and the second lower pattern 69 can be more recessed than the side surface 16s of the upper pattern 16. (Previously referred to) FIG. 1 through FIG. 3B The described partition structure ( FIG. 1 through FIG. 3B The first dividing portion 84a of 84) can be replaced by the first dividing portion 84aa having a protrusion 84p extending into the area between the base structure 3 and the upper pattern 16.

[0066] In the modified example embodiment, based on FIG. 4B Previous reference FIG. 1 through FIG. 3B The described substructure ( FIG. 1 through FIG. 3B 75) can be replaced by a lower structure 75b including a protrusion 69p. For example, the first lower pattern 65 in the lower structure 75b can be modified to have a recessed side surface 65s, and the second lower pattern 69 can be modified to include a protrusion 69p that protrudes further along a first horizontal direction X compared to the first lower pattern 65. The first horizontal direction X can refer to a direction parallel to the upper surface 3s of the base structure 3. (Previously referred to...) FIG. 1 through FIG. 3B The described partition structure ( FIG. 1 through FIG. 3B The first dividing portion 84a of 84) can be replaced by a first dividing portion 84ab, which includes a portion 84p1 extending into the region between the upper pattern 16 and the second lower pattern 69 and a portion 84p2 extending into the region between the base structure 3 and the second lower pattern 69. Compared to the first lower pattern 65, the protrusion 69p of the second lower pattern 69 can protrude in the first horizontal direction X facing the first dividing portion 84ab.

[0067] In the modified example embodiment, based on FIG. 4C Previous reference FIG. 1 through FIG. 3B The described substructure ( FIG. 1 through FIG. 3B 75) can be replaced by a lower structure 75c including recessed side surfaces 65sa and 69sa. For example, in the lower structure 75c, the first lower pattern 65 can be modified to have a side surface 65sa that is more recessed than the side surface 16s of the upper pattern 16. The second lower pattern 69 can be modified to have a side surface 69sa that is more recessed than the side surface 65sa of the first lower pattern 65. Therefore, compared to the second lower pattern 69, the first lower pattern 65 can include a protrusion 65p in the horizontal direction X. Previous reference FIG. 1 through FIG. 3B The described partition structure ( FIG. 1 through FIG. 3BThe first dividing portion 84a of the first lower pattern 65 can be replaced by a first dividing portion 84ac including a portion 84p' extending into the region between the upper pattern 16 and the substrate structure 3. In the first dividing portion 84ac, the central region of portion 84p' extending into the region between the upper pattern 16 and the substrate structure 3 can extend into the region between the second portion 65b and the third portion 65c of the first lower pattern 65. However, the exemplary embodiments according to this disclosure are not limited thereto. In the exemplary embodiments according to this disclosure, at least one of the second portion 65b of the first lower pattern 65, the third portion 65c of the first lower pattern 65, and the second lower pattern 69 can have a side surface that is recessed compared to the side surface 16s of the upper pattern 16.

[0068] Reference FIG. 4D through FIG. 4F Various modified example embodiments of structure 75 and the first dividing portion 84a are described below. FIG. 4D through FIG. 4F It is shown FIG. 2 Enlarged cross-sectional views of various modified example embodiments of region "B".

[0069] In the modified example embodiment, based on FIG. 4D Previous reference FIG. 4A The described substructure ( FIG. 4A 75a) can be modified to include a lower structure 75d that also includes a third lower pattern 72a. In the lower structure 75d, the third lower pattern 72a can be set in the lower structure ( FIG. 4A The first lower pattern 65 and the second lower pattern 69 of (75a) are between the separation structure 84. The third lower pattern 72a can be formed of polysilicon. The second lower pattern 69 can be formed of a material that is etch-selective to the materials of the upper pattern 16, the first lower pattern 65, and the third lower pattern 72a. For example, the upper pattern 16, the first lower pattern 65, and the third lower pattern 72a can be formed of polysilicon, and the second lower pattern 69 can be formed of a material that is etch-selective to polysilicon. For example, the second lower pattern 69 can be formed of an insulating material (e.g., silicon oxide) or a conductive material (e.g., TiN, TaN, WN, TiSi, WSi, TaSi, W, Ta, Ti, etc.) different from polysilicon.

[0070] In the modified example embodiment, based on FIG. 4E Previous reference FIG. 4B The described substructure ( FIG. 4B 75b) can be modified to include a lower structure 75e that also includes a third lower pattern 72b. In the lower structure 75e, the third lower pattern 72b can be set in the lower structure ( FIG. 4B The first lower pattern 65 and the second lower pattern 69 of 75b are between the separator structure 84. The third lower pattern 72b can be formed of polycrystalline silicon.

[0071] In the modified example embodiment, based on FIG. 4F Previous reference FIG. 4C The described substructure ( FIG. 4C 75c can be modified to include a lower structure 75f that also includes a third lower pattern 72c. In the lower structure 75f, the third lower pattern 72c can be set in the lower structure ( FIG. 4C The first lower pattern 65 and the second lower pattern 69 of 75c are between the separator structure 84. The third lower pattern 72c can be formed of polycrystalline silicon.

[0072] Reference FIG. 5A through FIG. 5E A method for manufacturing a semiconductor device according to an example embodiment of the present disclosure is described. FIG. 5A through FIG. 5E It is along FIG. 1 A cross-sectional view of the area intercepted by line I-I'.

[0073] based on FIG. 1 and FIG. 5A A substrate structure 3 can be prepared. The substrate structure 3 may include a lower substrate 5, a peripheral circuit region 7 located on the lower substrate 5, and an upper substrate 9 located on the peripheral circuit region 7.

[0074] In some example embodiments, the lower substrate 5 may be a semiconductor substrate such as a single-crystal silicon substrate.

[0075] In some example embodiments, the upper substrate 9 may be a polycrystalline silicon substrate. The upper substrate 9 may be an N-type conductive polycrystalline silicon substrate.

[0076] In some example embodiments, the peripheral circuit region 7 may include a peripheral circuit 7a and a lower insulating layer 7b covering the peripheral circuit 7a.

[0077] A sacrificial pattern 14 with an opening 14a can be formed on the substrate structure 3.

[0078] Pattern 16 can be formed on the sacrificial pattern 14.

[0079] The upper pattern 16 may include a horizontal portion 16a covering the upper surface of the sacrificial pattern 14 and a support portion 16b extending from the horizontal portion 16a into the filling opening 14a.

[0080] A stacked structure 20 can be formed on the pattern 16 above.

[0081] In some example embodiments, the stacking structure 20 may include a lower stacking structure 20L and an upper stacking structure 20U.

[0082] The lower stack structure 20L and the upper stack structure 20U may include alternating and repeated stacked interlayer insulating layers 25 and sacrificial horizontal layers 28.

[0083] In each of the lower stack structure 20L and the upper stack structure 20U, the uppermost and lowermost layers of the interlayer insulation layer 25 and the sacrificial horizontal layer 28 may be the interlayer insulation layer 25.

[0084] In each of the lower stack structure 20L and the upper stack structure 20U, the uppermost layer of the interlayer insulation layer 25 may be thicker than the interlayer insulation layer 25 between the sacrificial horizontal layers 28.

[0085] In some example embodiments, the interlayer insulating layer 25 may be formed of silicon oxide.

[0086] In some example embodiments, the sacrificial horizontal layer 28 may be formed of a material (such as silicon nitride) that has etch selectivity for the interlayer insulating layer 25.

[0087] In some example embodiments, the sacrificial horizontal layer 28 may be formed of a conductive material.

[0088] An insulating separation pattern 30 may be partially formed inside the upper stacked structure 20U. The insulating separation pattern 30 may pass through one or more sacrificial horizontal layers 28 located in the upper portion of the upper stacked structure 20U.

[0089] A vertical structure 33 can be formed that passes sequentially through the stacked structure 20, the upper pattern 16 and the sacrificial pattern 14 and extends into the upper base 9 of the base structure 3.

[0090] In some example embodiments, the formation of the vertical structure 33 may include: forming a channel hole 32 extending into the upper substrate 9 of the substrate structure 3, sequentially passing through the stacked structure 20, the upper pattern 16, and the sacrificial pattern 14; and forming a dielectric structure covering the inner wall of the channel hole 32. FIG. 3A 36); forming a covering dielectric structure ( FIG. 3A 36) channel layer ( FIG. 3A 46); in the channel layer ( FIG. 3A Partially filling the channel hole is formed on 46) FIG. 5A The core region of (32) FIG. 3A 48); and in the core area ( FIG. 3A A pad pattern is formed on (48) to partially fill the remaining area of ​​the channel hole 32. FIG. 3A (of 50).

[0091] The vertical structure 33 can be formed in multiple ways. Among the multiple vertical structures 33, some vertical structures ( FIG. 1 33d) can pass through the insulating separator pattern 30. As previously described, some vertical structures ( ) pass through the insulating separator pattern 30. FIG. 1 33d) can be a fictitious vertical structure.

[0092] based on FIG. 1 andFIG. 5B A first upper insulating layer 53 may be formed on the stacked structure 20. A separating trench 56 may be formed through the first upper insulating layer 53 and the stacked structure 20. Protective spacers 58 may be formed on the side surface of the separating trench 56.

[0093] The dividing groove 56 can expose a portion of the upper pattern 16, while simultaneously exposing the sacrificial pattern. FIG. 5A 14).

[0094] Each dividing groove 56 may include a portion passing through the horizontal portion 16a and a portion overlapping the support portion 16b of the upper pattern 16.

[0095] This can be achieved by removing the exposed sacrificial pattern ( FIG. 5A 14) to form the lower space 60.

[0096] In some example embodiments, this can be achieved by removing the exposed sacrificial pattern ( FIG. 5A 14) to expose the channel layer 46 of the vertical structure 33.

[0097] The support portion 16b of the upper pattern 16 can reduce or prevent the stacked structure 20 from collapsing or deforming.

[0098] based on FIG. 1 and FIG. 5C It can form a first lower layer 64 that conformally covers the sidewalls of the dividing trench 56 and the sidewalls of the lower space 60.

[0099] A second lower layer 68 can be formed on the first lower layer 64. The second lower layer 68 fills the lower space 60 and can extend into the dividing trench 56.

[0100] In some example embodiments, the first lower layer 64 may be formed of amorphous silicon material.

[0101] In some example embodiments, the second lower layer 68 may be formed of a material that is etch-selective to the first lower layer 64. For example, the second lower layer 68 may be formed of an insulating material (e.g., silicon oxide). In some example embodiments of this disclosure, the second lower layer 68 may be replaced with a material different from silicon oxide.

[0102] based on FIG. 1 and FIG. 5D A second lower pattern 69 retained within the lower space 60 can be formed by partially etching the second lower layer 68. A first lower pattern 65 retained within the lower space 60 can be formed by partially etching the first lower layer 64.

[0103] The sacrificial horizontal layer 28 can be exposed by removing the protective spacer 58.

[0104] In some example embodiments, after forming the first lower pattern 65 and the second lower pattern 69, annealing is performed to form the amorphous silicon material of the first lower layer 64 into a polycrystalline silicon material. Therefore, the first lower layer 64 can be formed of polycrystalline silicon material.

[0105] based on FIG. 1 and FIG. 5E An empty space 78 can be formed by removing the sacrificial horizontal layer 28 exposed by removing the protective spacer 58.

[0106] based on FIG. 1 through FIG. 3B It can form a space to fill the empty space. FIG. 5E 78) Horizontal layer 81.

[0107] The formation of horizontal layer 81 may include: forming a space that covers the void ( FIG. 5E The first layer of the inner wall of (78) FIG. 3A 81a) and in the first layer ( FIG. 3A Fill the empty space on 81a) FIG. 5E The second layer of 78) FIG. 3A (81b).

[0108] A partition structure 84 can be formed to fill the partition groove 56. A second upper insulating layer 87 can be formed to cover the partition structure 84 and the first upper insulating layer 53. A contact plug 90 can be formed through the first upper insulating layer 53 and the second upper insulating layer 87 and electrically connected to the pad pattern 50 of the vertical structure 33. A wire 93 can be formed on the contact plug 90.

[0109] In the embodiments, such as FIG. 5B The space formed in the middle ( FIG. 5B After 60), use FIG. 5C and FIG. 5D The method described in the text is to fill the empty space with the first lower pattern 65 and the second lower pattern 69. FIG. 5B (60), thereby reliably and stably manufacturing the lower structure 75 including the first lower pattern 65 and the second lower pattern 69. Therefore, it is possible to reduce or prevent potential issues arising from empty spaces ( FIG. 5B The defect (60) is caused by the inclusion of doped polycrystalline silicon material inside. This is due to the filling of empty spaces ( FIG. 5B The lower structure 75 of (60) can be formed into a stable structure, thus improving the reliability of the semiconductor device.

[0110] According to embodiments of this disclosure, a method is disclosed for stably and / or reliably forming a first lower pattern of a lower structure that contacts a channel layer through the stacked structure between a substrate and a stacked structure. Since a semiconductor device including a lower structure formed by this method is provided, the reliability of the semiconductor device can be improved.

[0111] Although exemplary embodiments have been shown and described above with reference to the accompanying drawings, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Substrate structure; The lower structure is located on the base structure; The upper pattern is located on the lower structure; A stacked structure is located on the lower structure; A separating structure, passing through the stacked structure; A vertical structure, located between the separating structures, passes through the stacked structure, the upper pattern, and the lower structure and extends into the base structure, and includes a channel layer; A contact plug is located on the vertical structure; as well as The wire is located on the contact plug. The stacked structure includes multiple interlayer insulating layers and multiple gate layers that are stacked alternately and repeatedly. The lower structure includes a first lower pattern and a second lower pattern made of a different material than the first lower pattern. The first lower pattern includes a first portion located between the second lower pattern and the channel layer, a second portion extending from the first portion to a region between the second lower pattern and the upper pattern, and a third portion extending from the first portion to a region between the second lower pattern and the substrate structure. The first lower pattern does not extend toward the side surface of the upper pattern, and The lower structure further includes a third lower pattern. The third lower pattern is located between the separating structure and the first lower pattern, and also between the second lower pattern and the separating structure. The second lower pattern is formed of silicon oxide.

2. The semiconductor device according to claim 1, wherein: The first lower pattern and the upper pattern are formed of polycrystalline silicon.

3. The semiconductor device according to claim 1, wherein, The vertical structure further includes a first dielectric structure and a second dielectric structure in contact with the channel layer. Wherein, the first dielectric structure is located between the channel layer and the stacked structure and extends into the region between the upper pattern and the channel layer, and The second dielectric structure is located between the channel layer and the substrate structure.

4. The semiconductor device according to claim 3, wherein, The first lower pattern also includes an upper extension extending from the first portion to the region between the upper pattern and the channel layer, and a lower extension extending from the first portion to the region between the substrate structure and the channel layer. Wherein, the upper extension portion is in contact with the first dielectric structure, and The lower extension portion is in contact with the second dielectric structure.

5. The semiconductor device according to claim 3, wherein: The first dielectric structure includes a first dielectric layer, a second dielectric layer, and a data storage material layer located between the first dielectric layer and the second dielectric layer.

6. The semiconductor device according to claim 1, wherein, The first lower pattern and the second lower pattern have side surfaces that are recessed compared to the side surfaces of the upper pattern.

7. The semiconductor device according to claim 1, wherein, The second lower pattern includes a portion that protrudes horizontally compared to the first lower pattern, and The horizontal direction is parallel to the upper surface of the substrate structure.

8. The semiconductor device according to claim 1, wherein: The first lower pattern includes a portion that protrudes horizontally compared to the second lower pattern, and The horizontal direction is parallel to the upper surface of the substrate structure.

9. The semiconductor device according to claim 1, wherein, The upper pattern includes an upper portion parallel to the upper surface of the base structure and a support portion extending from the upper portion and contacting the base structure. The lower structure is located between the upper portion of the upper pattern and the base structure. The lower structure includes a first side surface that contacts the supporting portion of the upper pattern and a second side surface that contacts the separating structure. The first lower pattern extends into the area between the supporting portion of the upper pattern and the second lower pattern.

10. The semiconductor device according to claim 1, wherein: The substrate structure includes a lower substrate, a peripheral circuit region located on the lower substrate, and an upper substrate located on the peripheral circuit region. The lower structure is in contact with the upper substrate and is located on the upper substrate.

11. The semiconductor device according to claim 1, wherein, The stacking structure includes a lower stacking structure and an upper stacking structure located on the lower stacking structure. Each of the lower stacked structure and the upper stacked structure includes a plurality of interlayer insulating layers and a plurality of gate layers that are alternately and repeatedly stacked. In each of the lower and upper stacked structures, the uppermost layer of the plurality of interlayer insulating layers and the plurality of gate layers is an interlayer insulating layer, and The topmost interlayer insulating layer in each of the lower stacked structure and the upper stacked structure is an interlayer insulating layer with a thickness greater than the thickness of each interlayer insulating layer between the plurality of gate layers.

12. A semiconductor device, the semiconductor device comprising: The substructure is located on the base structure; The upper pattern is located on the lower structure; A stacked structure is located on the lower structure; A vertical structure that passes through the stacked structure, the upper pattern, and the lower structure and extends into the base structure; as well as A separating structure, passing through the stacked structure and spaced apart from the vertical structure. The upper pattern includes an upper portion parallel to the upper surface of the base structure and a supporting portion extending from the upper portion and contacting the base structure. The lower structure is located between the upper portion of the upper pattern and the base structure. The separating structure includes a first separating portion passing through the stacked structure, the upper portion of the upper pattern, and the lower structure, and a second separating portion passing through the stacked structure and contacting the supporting portion of the upper pattern. The stacked structure includes a plurality of gate layers stacked and spaced apart in a direction perpendicular to the upper surface of the substrate structure. The vertical structure includes a channel layer extending through the plurality of gate layers, the upper portion of the upper pattern, and the lower structure, and extending into the substrate structure. The lower structure includes a first lower pattern and a second lower pattern made of a different material than the first lower pattern. The first lower pattern includes a first portion located between the second lower pattern and the channel layer, a second portion extending from the first portion to a region between the second lower pattern and the upper pattern, and a third portion extending from the first portion to a region between the second lower pattern and the substrate structure. The lower structure further includes a third lower pattern. The third lower pattern is located between the separating structure and the first lower pattern, and also between the second lower pattern and the separating structure. The second lower pattern is formed of silicon oxide.

13. The semiconductor device according to claim 12, wherein, The vertical structure further includes a first dielectric structure and a second dielectric structure in contact with the channel layer. The first dielectric structure is located between the channel layer and the stacked structure and extends into the region between the upper pattern and the channel layer. The second dielectric structure is located between the channel layer and the substrate structure, and The first lower pattern also includes an upper extension extending from the first portion to the region between the upper pattern and the channel layer, and a lower extension extending from the first portion to the region between the substrate structure and the channel layer. Wherein, the upper extension portion is in contact with the first dielectric structure, and The lower extension portion is in contact with the second dielectric structure.

14. A semiconductor device, the semiconductor device comprising: The substructure is located on the base structure; The upper pattern is located on the lower structure; A stacked structure is located on the upper pattern; A vertical structure that passes through the stacked structure, the lower structure, and the upper pattern and extends into the base structure; as well as A separating structure, passing through the stacked structure, the upper pattern, and the lower structure, and spaced apart from the vertical structure. The stacked structure includes multiple gate layers spaced apart and stacked simultaneously in a direction perpendicular to the upper surface of the substrate structure. The vertical structure includes a channel layer that passes through the plurality of gate layers, the upper pattern, and the lower structure and extends into the substrate structure. The lower structure includes a first lower pattern and a second lower pattern, wherein the material of the second lower pattern has etch selectivity relative to the material of the first lower pattern. The first lower pattern includes a first portion located between the second lower pattern and the channel layer, a second portion extending from the first portion to a region between the second lower pattern and the upper pattern, and a third portion extending from the first portion to a region between the second lower pattern and the substrate structure. The second portion of the first lower pattern, the third portion of the first lower pattern, and at least one of the second lower pattern have a side surface that is recessed compared to the side surface of the upper pattern. The lower structure further includes a third lower pattern. The third lower pattern is located between the separating structure and the first lower pattern, and also between the second lower pattern and the separating structure. The second lower pattern is formed of silicon oxide.

15. The semiconductor device according to claim 14, wherein, The second lower pattern includes a protrusion that protrudes horizontally and faces the separating structure compared to the first lower pattern, and The horizontal direction is the direction parallel to the upper surface of the substrate structure.

16. The semiconductor device according to claim 14, wherein, At least one of the second portion of the first lower pattern and the third portion of the first lower pattern includes a portion that protrudes horizontally from the dividing structure compared to the second lower pattern, and The horizontal direction is the direction parallel to the upper surface of the substrate structure.

17. The semiconductor device according to claim 14, wherein, The upper pattern, the first lower pattern, and the third lower pattern are formed of polycrystalline silicon.

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