Display substrate and display device

Abstract

This invention provides a display substrate and a display device. The display substrate includes a display area and a notch area, the notch area and the display area together forming a closed pattern, wherein the notch area is located at the edge of the closed pattern. The display area includes a first area adjacent to the notch area and a second area excluding the first area. The display substrate includes a low-level signal line disposed within the first area, the low-level signal line being used to receive a preset signal and forming a capacitance with the traces within the first area to increase the load capacitance of the traces. The display substrate and display device provided by this invention can ensure the display effect of the display device.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] Currently, display devices with built-in front-facing cameras and other sensors generally adopt a notch-screen design (such as the "notch screen" commonly seen on the market). This design concentrates the sensors in the non-display cutout area, allowing all areas of the screen except the cutout area to be displayed, thus increasing the screen-to-body ratio of the display device.

[0003] Because of the presence of the cut-out area, the number of sub-pixels connected to some traces is reduced, resulting in fewer sub-pixels connected to some traces than to others. This causes the load on some traces to be less than that on others, leading to different signal delays for some traces compared to others, thus reducing the display effect of the display device. Summary of the Invention

[0004] This invention provides a display substrate and a display device to solve the problem in related technologies where the signal delay of some traces differs from that of other traces due to pixel reduction in the cutout area, thereby improving the display effect of the display device.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] In a first aspect, embodiments of the present invention provide a display substrate, including a display area and a cutout area, wherein the cutout area and the display area together form a closed pattern, and the cutout area is located at the edge of the closed pattern;

[0007] The display area includes a first area adjacent to the grooved area and a second area other than the first area;

[0008] The display substrate includes a low-level signal line disposed in the first area. The low-level signal line is used to receive a preset signal and form a capacitance with the traces in the first area to increase the load capacitance of the traces.

[0009] Furthermore, the trace is a gate line located in the first region or a reset line located in the first region.

[0010] The orthographic projection of the trace on the substrate coincides with the orthographic projection of the low-level signal line on the substrate.

[0011] Furthermore, the width of the low-level signal line in the column direction is greater than the sum of the widths of the traces in the column direction within the first region.

[0012] Furthermore, the display substrate includes a polysilicon layer, a wiring layer, a first insulating layer, and a low-level signal line disposed sequentially from the substrate to the encapsulation layer, wherein the first insulating layer includes a first portion located between the low-level signal line and the wiring layer, and a second portion located between two adjacent wirings in the wiring layer.

[0013] Furthermore, a second insulating layer is provided between the polysilicon layer and the wiring layer, and a via is formed in the display substrate that penetrates the second portion of the first insulating layer and the second insulating layer. The low-level signal line is connected to the polysilicon layer through the via.

[0014] Furthermore, the outer contour of the trench area is a quadrilateral, a triangle, or a circle.

[0015] Furthermore, the outer contour of the trench area is an isosceles trapezoid, the first base of the isosceles trapezoid is located at the edge of the closed shape, and the length of the first base is greater than the length of the second base.

[0016] Furthermore, a first row of sub-pixels and a second row of sub-pixels are arranged sequentially from the first bottom edge to the second bottom edge of the cutout area. The display brightness of the first row of sub-pixels is greater than that of the second row of sub-pixels. The cutout area is located on the straight line where the first row of sub-pixels and the straight line where the second row of sub-pixels are located.

[0017] Furthermore, no sub-pixels are set inside the first region, while sub-pixels are arranged inside the second region.

[0018] Secondly, embodiments of the present invention also provide a display device, including a display substrate as described above.

[0019] In the technical solution provided by this invention, a low-level signal line is used to compensate for the load capacitance of the traces in the first region. This allows the load capacitance of traces with a smaller number of connected sub-pixels due to the cutout area to approach or even equal the load capacitance of other traces. This makes the delays of all traces in the display substrate similar, ensuring the display effect of the display device. Therefore, the technical solution provided by this invention can ensure the display effect of the display device. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a display substrate provided in an embodiment of the present invention;

[0022] Figure 2 for Figure 1 Enlarged view of region I;

[0023] Figure 3 This is a schematic diagram of the structure of a display substrate provided in another embodiment of the present invention;

[0024] Figure 4 This is a partial structural schematic diagram of a display substrate provided in another embodiment of the present invention;

[0025] Figure 5 for Figure 4 A cross-sectional view with thick white lines in the center;

[0026] Figure 6 The diagram shows the load capacitance distribution of the traces provided in another embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] This invention provides a display substrate, such as... Figure 1 and Figure 2 As shown, it includes a display area A and a cutout area B, wherein the cutout area B and the display area A together form a closed shape, and the cutout area B is located at the edge of the closed shape;

[0029] The display area A includes a first area A1 near the grooved area B and a second area A2 excluding the first area;

[0030] The display substrate includes a low-level signal line 210 disposed in the first region A1. The low-level signal line 210 is used to receive a preset signal and form a capacitance with the trace 220 in the first region A1 to increase the load capacitance of the trace 220.

[0031] In this embodiment of the invention, a low-level signal line is used to compensate for the load capacitance of the traces in the first region. This allows the load capacitance of traces with fewer connected sub-pixels due to the cutout area to approach or even equal the load capacitance of other traces. This makes the delays of all traces in the display substrate similar, ensuring the display effect of the display device. Therefore, the technical solution provided by this invention can ensure the display effect of the display device.

[0032] The aforementioned display area A and the cutout area B are two interconnected but non-overlapping areas. The outer contour of the cutout area B can be a quadrilateral, triangle, circle, etc., which is not limited here. The contour shape of the part where display area A and cutout area B meet is adapted to the contour shape of the part where cutout area B and display area A meet. For example, if the contour shape of cutout area B is a rectangle with length a and width b, then the contour of display area A includes a rectangular groove with length a and width b.

[0033] Display area A and cutout area B together form a closed shape, which can be a rectangle (including rounded rectangles), a circle, a triangle (including rounded triangles), etc. Cutout area B is located at the edge of the closed shape. Taking a rectangle as an example, the cutout area is located at the edge of the rectangle, and its shape can be as follows... Figure 1 As shown, it is similar to the "notch screen" on the market.

[0034] Display area A includes a first area A1 near the trench area B, that is, the first area A1 and the edge of the closed graphic together surround the trench area B.

[0035] like Figure 3 As shown, sub-pixels are distributed in the display areas on both sides of the cutout area B in the direction of row B. Sub-pixels located in the same row are connected to the same traces 220 to obtain signals for emitting light. The line segments of these traces 220 between the sub-pixels on both sides are arranged to bypass the cutout area B in the first area. The traces with sub-pixels distributed in the entire row are distributed in the second area A2.

[0036] Because of the presence of the cutout area B, some sub-pixels are removed, resulting in fewer sub-pixels connected to the traces 220 distributed in the first area A1 compared to the number connected to the traces distributed in the second area. This causes the load capacitance of the traces 220 in the first area to be less than that in the second area, leading to a difference in signal delay between the traces 220 in the first and second areas, thus affecting the display performance of the display device.

[0037] In this embodiment of the invention, the low-level signal lines 210 originally distributed in the first region A1 are used to form a capacitor with the traces 220 in the first region A1 to compensate for the missing load capacitance of the traces 220 (due to the fewer sub-pixel load capacitances of the connected sub-pixels compared to the sub-pixels connected by the traces in the second region A2). This makes the overall load capacitance of the traces 220 in the first region A1 the same as or close to the overall load capacitance of the traces in the second region A2, thereby ensuring that the signal delay of the traces 220 in the first region A1 is the same as the signal delay of the traces in the second region A2, and ensuring the display effect of the display device.

[0038] In addition, since the low-level signal line 210 is originally located in the first region A1, there is no need to add an extra structure to compensate for the load capacitance of the trace 220 in the first region A1. This also makes it easier to reduce the bezel of the display substrate, which is beneficial for the narrow bezel design of the display device.

[0039] The low-level signal line 210 forms a capacitor with each trace 220 in the first region A1. Since only one trace 220 in the first region A1 will have a voltage signal change within a certain time period, the low-level signal line 210 is less disturbed in each time period, and the change of trace 220 will not affect the stability of the low-level signal line 210.

[0040] Among them, such as Figure 3 As shown, the first region A1 may not have any sub-pixels, while the second region A2 may have sub-pixels. Since there are no sub-pixels in the first region A1, the traces 220 in the first region A1 will not interfere with the sub-pixels.

[0041] Furthermore, the trace 220 is a gate line located in the first region A1 or a reset line located in the first region A1.

[0042] When trace 220 is a gate line, sub-pixels on both sides of the cutout area B located in the same row are connected to a single gate line. The line segment of the gate line between the sub-pixels on both sides is set to bypass the cutout area B in the first area. When any gate line in the first area is working (transmitting a scan signal), the low-level signal line 210 forms a capacitance with the working gate line, increasing the load capacitance of the working gate line, making the load capacitance of the gate line the same as that of the gate lines in the second area.

[0043] When trace 220 is a reset line, the sub-pixels on both sides of the cutout area B located in the same row are all connected to a reset line. The line segment of the reset line between the two sub-pixels is set to bypass the cutout area B in the first area. When any reset line in the first area is working (transmitting a reset signal), the low-level signal line 210 forms a capacitor with the working reset line, increasing the load capacitance of the working reset line, so that the load capacitance of the reset line is the same as that of the reset lines in the second area.

[0044] Furthermore, the orthographic projection of the trace 220 on the substrate coincides with the orthographic projection of the low-level signal line 210 on the substrate.

[0045] like Figure 2As shown, the orthographic projection of all traces in the first region onto the substrate coincides with the orthographic projection of the low-level signal line 210 onto the substrate. In this embodiment, a capacitor can be formed using the two conductors of the overlapping projection portion of the low-level signal line 210 and the trace 220, and the insulating layer between them, to compensate for the missing load capacitance of the trace 220 in the first region A1.

[0046] Furthermore, the width of the low-level signal line 210 in the column direction is greater than the sum of the widths of the traces 220 in the column direction within the first region A1.

[0047] like Figure 2 As shown, the multiple traces 220 in the first region A1 include a first trace 221 extending along the row direction and two second traces 222 respectively connected to the two ends of the first trace 221. The second trace 222 located on the first side of the first trace 221 is connected to the first end of the first trace 221 and the trace 223 located on the first side of the first trace 221 for connecting the sub-pixel. The second trace 222 located on the second side of the first trace 221 is connected to the second end of the first trace 221 and the trace 223 located on the second side of the first trace 221 for connecting the sub-pixel.

[0048] like Figure 2 As shown, the first segments of multiple traces 220 are distributed in parallel within the first region A1. The sum of the widths of the first segments 221 of the multiple traces 220 in the column direction within the first region A1 is less than the width of the low-level signal line 210 in the column direction.

[0049] Furthermore, such as Figure 4 and Figure 5 As shown, the display substrate includes a polysilicon layer 410, a wiring layer 420, a first insulating layer 430, and a low-level signal line 210 arranged sequentially from the substrate to the encapsulation layer. The first insulating layer 430 includes a first portion 431 located between the low-level signal line 210 and the wiring layer 420, and a second portion 432 located between two adjacent wiring lines 220 in the wiring layer 420.

[0050] Since the traces 220 connected to the sub-pixels on both sides of the cutout area B are all located within the first area A1, the trace density in the first area A1 is greater than that in the second area A2. To improve the insulation between the traces 220 within the first area A1, in this embodiment, the second portion 432 of the first insulating layer 430 is used to ensure that each trace 220 within the first area A1 is mutually insulated, ensuring that each trace 220 within the first area A1 can function normally. Additionally, the first portion 431 of the first insulating layer 430 also ensures that the traces 220 are mutually insulated from the low-level signal line 210.

[0051] Among them, such as Figure 5 As shown, a second insulating layer 440 is provided between the polysilicon layer 410 and the wiring layer 420. A via 450 is formed in the display substrate, penetrating the second portion 432 of the first insulating layer 430 and the second insulating layer 440. The low-level signal line 210 is connected to the polysilicon layer 410 through the via 450.

[0052] The second insulating layer 440 is used to insulate the polysilicon layer 410 from the wiring layer 420. The insulating layer 430 can be a multilayer structure, for example, including two layers of insulating material stacked on top of each other.

[0053] Through via 450, the low-level signal line 210 is electrically connected to the polysilicon layer 410, thereby forming a three-layer capacitor structure of low-level signal line-trace-polysilicon. The low-level signal line 210 and the polysilicon layer 410 are the first plate of the capacitor, and the trace 220 is the second plate of the capacitor. In this embodiment, since the shape of the low-level signal line 210 is basically fixed, the size of the polysilicon layer 410 overlapping with the trace 220 can be adjusted according to the amount of compensation capacitor that needs to be added to each trace 220, so as to achieve the effect of targeted compensation for the trace 220.

[0054] The specific manufacturing process can be as follows: First, a polysilicon layer 410 is formed on the substrate. Then, a second insulating layer 440 is formed covering the polysilicon layer 410. Next, a wiring layer 420 is formed on the side of the second inorganic layer 440 away from the polysilicon layer 410. Then, a first insulating layer 430 is formed on the side of the wiring layer 420 away from the polysilicon layer 410. The first insulating layer 430 covers the wiring layer 420 (i.e., covers the gap between the wiring 220 in the wiring layer 420). Then, vias 450 penetrating the second part and the second insulating layer 440 are opened between the wirings 220. Finally, a low-level signal line 220 is formed on the side of the first insulating layer 430 away from the polysilicon layer 410. At this time, the low-level signal line 220 can be connected to the polysilicon layer 410 through the via.

[0055] Furthermore, such as Figure 1 and Figure 3 As shown, the outer contour of the trench area B is an isosceles trapezoid, the first base of the isosceles trapezoid is located at the edge of the closed shape, and the length of the first base is greater than the length of the second base.

[0056] like Figure 3As shown, since the outer contour of the cutout region B is an isosceles trapezoid, the number of sub-pixels in each row on both sides of the row direction of the cutout region B is different, that is, the number of sub-pixels connected by the routing line 220 in the first region A1 is also different. Specifically, routing lines 1, 2, ..., n-1, n are arranged sequentially from the first base to the second base of the isosceles trapezoid. Among the routing lines in the first region A1, routing line 1 connects the fewest sub-pixels, and routing line n connects the most sub-pixels.

[0057] At this time, the overlap area between the polysilicon layer 410 and the low-level signal line 210 and each trace 220 in the first region A1 is different, and the resulting capacitance for load compensation is also different. Specifically, the fewer sub-pixels connected by the trace 220, the greater its overlap area with the polysilicon layer 410 and the low-level signal line 210, and thus the larger the compensation capacitance.

[0058] Furthermore, a first row of sub-pixels and a second row of sub-pixels are arranged sequentially from the first bottom edge to the second bottom edge of the cutout area B. The display brightness of the first row of sub-pixels is greater than that of the second row of sub-pixels. The cutout area B is located on the straight line where the first row of sub-pixels is located and the straight line where the second row of sub-pixels is located.

[0059] In this embodiment, the low-level signal line 210 and the polysilicon layer 410 are used to compensate for the load capacitance of each trace 220 in the first region A1, ultimately resulting in the following trend in the change of the total capacitance load of each trace: Figure 6 As shown, Figure 6 The x-coordinate in the figure is Figure 3 Different wiring within the first area A1, Figure 6 The vertical axis represents the percentage of the load capacitance relative to the traces located in the second region A2. That is, with the second region A2 as a reference, the load capacitance of each trace 220 in the first region A1 decreases as the number of sub-pixels it connects decreases. This also causes the display brightness of each row of sub-pixels to decrease as the number of sub-pixels in that row decreases. This gradual change in display brightness is not easily perceived by the human eye and also reduces the energy lost when the low-level signal line 210 compensates for the load capacitance of the trace 220, thus saving energy without affecting the display effect of the display device.

[0060] This invention also provides a display device, including a display substrate as described above.

[0061] Display devices can be monitors, mobile phones, tablets, televisions, wearable electronic devices, navigation display devices, etc.

[0062] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0063] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0064] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. A display substrate, characterized in that, It includes a display area and a cutout area, the cutout area and the display area together forming a closed shape, wherein the cutout area is located at the edge of the closed shape; The display area includes a first area adjacent to the grooved area and a second area other than the first area; The display substrate includes a low-level signal line disposed in the first area. The low-level signal line is used to receive a preset signal and form a capacitance with the traces in the first area to increase the load capacitance of the traces. The trace includes a first line segment, a second line segment, and a third line segment connected in sequence. The first line segment and the third line segment extend along the row direction, and the second line segment intersects the row direction. The first line segments are distributed parallel to each other in the first region. The orthographic projection of the first line segment on the substrate coincides with the orthographic projection of the low-level signal line on the substrate. The overlap area between the low-level signal line and each first line segment in the first region is different. The display substrate includes a polysilicon layer, a wiring layer, a first insulating layer, and a low-level signal line, sequentially disposed from the substrate to the encapsulation layer. The polysilicon layer is stepped from the direction away from the first bottom edge of the trench region, and the overlap area between the polysilicon layer and the wiring layer gradually decreases. The first insulating layer includes a first portion located between the low-level signal line and the wiring layer, and a second portion located between two adjacent wirings in the wiring layer. A second insulating layer is also provided between the polysilicon layer and the wiring layer. A via is formed in the display substrate, penetrating the second portion of the first insulating layer and the second insulating layer. The low-level signal line is connected to the polysilicon layer through the via. The overlap area between the polysilicon layer and the low-level signal line and each wiring in the first region is different, and the load capacitance of each wiring in the first region decreases as the number of sub-pixels it connects to decreases.

2. The display substrate according to claim 1, characterized in that, The trace is a gate line located in the first region or a reset line located in the first region.

3. The display substrate according to claim 1, characterized in that, The orthographic projection of the trace on the substrate coincides with the orthographic projection of the low-level signal line on the substrate.

4. The display substrate according to claim 1, characterized in that, The width of the low-level signal line in the column direction is greater than the sum of the widths of the traces in the column direction within the first region.

5. The display substrate according to claim 1, characterized in that, The outer contour of the excavated area is a quadrilateral, a triangle, or a circle.

6. The display substrate according to claim 1, characterized in that, The outer contour of the trench area is an isosceles trapezoid, the first base of the isosceles trapezoid is located at the edge of the closed shape, and the length of the first base is greater than the length of the second base.

7. The display substrate according to claim 6, characterized in that, A first row of sub-pixels and a second row of sub-pixels are arranged sequentially from the first bottom edge to the second bottom edge of the cutout area. The display brightness of the first row of sub-pixels is greater than that of the second row of sub-pixels. The cutout area is located on the straight line where the first row of sub-pixels and the second row of sub-pixels are located.

8. The display substrate according to claim 1, characterized in that, The first region has no sub-pixels, while the second region has sub-pixels arranged inside.

9. A display device, characterized in that, Includes the display substrate as described in any one of claims 1-8.

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