Memory cell and method for forming same, and memory device

Abstract

Various embodiments of the present invention are directed to a memory cell including a high electron affinity dielectric layer at the bottom electrode. The high electron affinity dielectric layer is one of a plurality of different dielectric layers vertically stacked between the bottom electrode and the top electrode above the bottom electrode. In addition, the high electrode electron affinity dielectric layer has the highest electron affinity among the plurality of different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and / or material components. It should be understood that by arranging the high electron affinity dielectric layer closest to the bottom electrode, at least when the memory cell is an RRAM, the possibility of the memory cell being stuck during cycling is reduced. Therefore, the possibility of a hard reset / failure bit is reduced. Embodiments of the present invention also relate to a memory cell, a method for forming the same, and a memory device.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory cell and a method for forming the same, and a memory device. Background Art

[0002] Many modern electronic devices include nonvolatile memory. Nonvolatile memory is electronic memory that can store data when power is removed. Some promising candidates for the next generation of nonvolatile memory include oxygen ion resistive random access memory (RRAM) and metal ion RRAM. Both types of RRAM have relatively simple structures and are compatible with complementary metal oxide semiconductor (CMOS) logic manufacturing processes. Summary of the invention

[0003] An embodiment of the present invention provides a memory cell, comprising: a bottom electrode; a top electrode located above the bottom electrode; and a dielectric stack, comprising a plurality of dielectric layers stacked between the bottom electrode and the top electrode; wherein the plurality of dielectric layers include a first dielectric layer, and the first dielectric layer is one of the plurality of dielectric layers closest to the bottom electrode and has the highest electron affinity among the plurality of dielectric layers.

[0004] Another embodiment of the present invention provides a memory device, comprising a memory cell, wherein the memory cell comprises: a bottom electrode; a dielectric structure located above the bottom electrode and comprising a plurality of different dielectric materials from top to bottom; and a top electrode located above the dielectric structure; wherein the plurality of different dielectric materials include a first dielectric material located at the bottom electrode, and the first dielectric material has the lowest bottom conductive band edge among the plurality of different dielectric materials.

[0005] Yet another embodiment of the present invention provides a method for forming a memory cell, comprising: depositing a bottom electrode layer over a substrate; depositing a dielectric film over and directly on the bottom electrode layer, wherein the dielectric film comprises a plurality of different dielectric layers stacked vertically, wherein the plurality of different dielectric layers comprises a first dielectric layer located at the bottom electrode layer, and wherein the first dielectric layer has a highest electron affinity among the plurality of different dielectric layers; depositing a top electrode layer over the dielectric film; and patterning the bottom electrode layer, the dielectric film, and the top electrode layer into a memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A cross-sectional view of some embodiments of a memory cell is shown in which a high electron affinity (HEA) dielectric layer is located at the bottom electrode.

[0008] Figure 2 Shows Figure 1 Graph of some embodiments of the electron affinity of a dielectric layer including a HEA dielectric layer in a memory cell.

[0009] Figure 3 A table listing the electron affinities of various materials is shown.

[0010] Figure 4A and Figure 4B The following diagrams show the current during the set operation and reset operation. Figure 1 Cross-sectional views of some embodiments of memory cells.

[0011] Figure 5 Shows Figure 1 Cross-sectional views of some optional embodiments of a memory cell, wherein the memory cell further comprises a capping layer.

[0012] Figure 6 Shows Figure 1 Cross-sectional views of some alternative embodiments of a memory cell, wherein the memory cell comprises three or more dielectric layers.

[0013] Figure 7 Shows Figure 6 Cross-sectional views of some embodiments of a memory cell, wherein the memory cell is limited to three dielectric layers.

[0014] Fig. 8A and Figure 8B Shows Figure 7 Graphs of different embodiments of the electron affinity of a dielectric layer including a HEA dielectric layer in a memory cell.

[0015] Fig. 9 Shows Figure 6 Cross-sectional views of some optional embodiments of a memory cell, wherein the memory cell further comprises a capping layer.

[0016] Fig.10 Shows Figure 1 Cross-sectional views of some embodiments of a memory cell, wherein the memory cell is integrated into an interconnect structure of an integrated circuit (IC) chip.

[0017] Fig.11A and Fig. 11B Shows Fig.10 Cross-sectional views of different alternative embodiments of a memory cell.

[0018] Fig. 12A and Fig. 12B 1 shows a cross-sectional view of some embodiments of an IC chip including a plurality of memory cells integrated into a single one-transistor one-resistor (1T1R) cell, and each memory cell as shown in FIG. Fig.10 Configure as shown.

[0019] Fig.13 Shows Fig. 12A and Fig. 12B Top layout of some embodiments of IC chips.

[0020] Fig.14 Shows Fig. 12A and Fig. 12B Schematic diagram of some embodiments of the 1T1R unit in FIG.

[0021] FIG. 15A to FIG. 15C Shows Fig.14 Schematic diagram of different alternative embodiments of a 1T1R cell, where the access transistors are different.

[0022] Figures 16 to 23 A series of cross-sectional views of some embodiments of methods for forming a memory cell integrated with a 1T1R cell and including a separate HEA dielectric layer at a corresponding bottom electrode are shown.

[0023] Fig.24 Shows Figures 16 to 23 A block diagram of some embodiments of the method.

[0024] Figure 25 to Figure 29 Shows Figures 16 to 23 A series of cross-sectional views of some alternative embodiments of a method in which a memory cell is formed using planarization patterning.

[0025] Fig.30 Shows Figure 25 to Figure 29 A block diagram of some embodiments of the method. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0027] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or process of operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0028] Some resistive random access memory (RRAM) cells include a bottom electrode, a top electrode located above the bottom electrode, and a single dielectric layer located between the bottom electrode and the top electrode. The single dielectric layer includes a metal oxide and has a single material component throughout. During a set operation, a set voltage with a positive polarity is applied from the top electrode to the bottom electrode to form a conductive filament in the single dielectric layer. The conductive filament electrically couples the bottom electrode to the top electrode so that the RRAM cell is in a low resistance state (LRS). During a reset operation, a reset voltage with a negative polarity is applied from the top electrode to the bottom electrode to at least partially dissolve the conductive filament. In this way, the RRAM cell is in a high resistance state (HRS). Because the resistance of the RRAM cell changes during the set and reset operations, the resistance can be used to represent a data bit. For example, LRS can represent a binary "1", while HRS can represent a binary "0", and vice versa.

[0029] The challenge with RRAM cells is that when the RRAM cell is cycled, the RRAM cell may get stuck at the LRS. In this case, it usually occurs after many cycles of the RRAM cell. When the RRAM cell is stuck, the RRAM cell can be referred to as a hard reset bit. In addition, the read current through the RRAM cell can be greater than or about the same as the current when the RRAM cell is in the LRS. The RRAM cell typically remains stuck for many cycles and may therefore be considered a hard failure bit. In this way, when the RRAM cell is one of many similar RRAM cells that define an RRAM array, the RRAM cell can be error correcting code (ECC) corrected by an ECC device. However, the ECC device can be designed to correct random soft failure bits, not hard failure bits, so that the hard failure bits can use the ECC capacity intended for random soft failure bits. In terms of using too much ECC capacity for hard failure bits, the ECC device may become overwhelmed and may not be able to correct the random soft failure bits. This may in turn lead to failure of the RRAM array.

[0030] Various embodiments of the present invention are directed to a memory cell including a high electron affinity (HEA) dielectric layer at a bottom electrode, and a method for forming the memory cell. The memory cell may be, for example, an RRAM cell or some other suitable type of memory cell. The HEA dielectric layer is one of a plurality of different dielectric layers vertically stacked between a bottom electrode and a top electrode above the bottom electrode. In addition, among the different dielectric layers, the HEA dielectric layer has the highest electron affinity and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and / or material compositions. For the same set of elements, different material systems correspond to different sets of elements, and different material compositions correspond to different element ratios.

[0031] It can be appreciated that by arranging the HEA dielectric layer closest to the bottom electrode, at least when the memory cell is RRAM, the likelihood of the memory cell getting stuck during cycling is reduced. Thus, the likelihood of a hard reset / failure bit is reduced. Because the likelihood of a hard reset / failure bit is reduced, the hard reset / failure bit is less likely to use the ECC capacity of the memory array to which the memory cell belongs. Since the hard reset / failure bit is less likely to use the ECC capacity, the hard reset / failure bit is less likely to overwhelm the ECC capacity of the memory array. Thus, the memory array is less likely to fail. Since the HEA dielectric layer reduces the likelihood of a memory array failure, no additional ECC capacity is required. This in turn saves integrated circuit (IC) chip area, which can be used for additional ECC capacity.

[0032] As will be seen below, the HEA dielectric layer can be integrated into the memory process flow by additional deposition. In this way, the HEA dielectric layer adds almost no additional cost to the memory process flow. In addition, the integration is compatible with process nodes of 40 nanometers or less.

[0033] refer to Figure 1 , a cross-sectional view 100 of some embodiments of a memory cell 102 is provided, wherein a HEA dielectric layer 104h is located on a bottom electrode 106. The memory cell 102 can be, for example, an oxygen ion RRAM cell, a metal ion RRAM cell, or some other suitable type of memory cell. Note that a metal ion RRAM cell can also be referred to as a conductive bridge RAM (CBRAM).

[0034] The HEA dielectric layer 104h is one of the plurality of dielectric layers 104 that are vertically stacked above the bottom electrode 106 and separate the bottom electrode 106 from the top electrode 108 above the bottom electrode 106. In addition, among the plurality of dielectric layers 104, the HEA dielectric layer 104h has the highest electron affinity and is closest to the bottom electrode 106. Therefore, relative to the rest of the plurality of dielectric layers 104, the HEA dielectric layer 104h has a “high” electron affinity.

[0035] The electron affinity of the dielectric layer is the energy difference between the bottom conduction band edge of the dielectric layer and the vacuum energy level. The vacuum energy level is the same for the plurality of dielectric layers 104, and may be, for example, about 4.05 electron volts (eV). Because the vacuum energy level of the plurality of dielectric layers 104 is the same, the bottom conduction band edges of the plurality of dielectric layers 104 respectively define the electron affinity of the plurality of dielectric layers 104. In addition, the bottom conduction band edge of the HEA dielectric layer 104h is the lowest among the plurality of dielectric layers 104.

[0036] It has been appreciated that by arranging the HEA dielectric layer 104h closest to the bottom electrode 106, at least when the memory cell 102 is an RRAM, the likelihood of the memory cell 102 getting stuck during cycling is reduced. For example, when transitioning from LRS to HRS, the memory cell 102 is most likely to get stuck during a reset operation. Because the HEA dielectric layer 104h has the highest electron affinity among the multiple dielectric layers 104 and is located at the bottom electrode 106, electrons can more easily pass through the multiple dielectric layers 104 during a reset operation. Therefore, the likelihood of the memory cell 102 getting stuck during cycling is reduced.

[0037] Because the likelihood of the memory cell 102 getting stuck during cycling is reduced, the likelihood of a hard reset / fail bit is reduced. Because the likelihood of a hard reset / fail bit is reduced, the hard reset / fail bit is less likely to use ECC capacity for a memory array (not shown) containing the memory cell 102. Therefore, the memory array is less likely to fail. Because the HEA dielectric layer 104h reduces the likelihood of a memory array failure, no additional ECC capacity is required, and therefore no additional IC chip area is required.

[0038] Continue to refer Figure 1 , the plurality of dielectric layers 104 are stacked vertically and define a dielectric structure extending from a bottom electrode 106 to a top electrode 108. In addition, the plurality of dielectric layers 104 have two dielectric layers: 1) a HEA dielectric layer 104h; and 2) a low electron affinity (LEA) dielectric layer 104l. The LEA dielectric layer 104l is located above and adjacent to the HEA dielectric layer 104h and has a "low" electron affinity relative to the HEA dielectric layer 104h. In an alternative embodiment, the plurality of dielectric layers 104 have three or more different dielectric layers.

[0039] Each of the HEA and LEA dielectric layers 104h, 104l may be, for example, a metal oxide, a metal oxynitride, a component metal oxide, some other suitable dielectric, or any combination of the foregoing. In addition, each of the HEA and LEA dielectric layers 104h, 104l may be, for example, titanium oxide (e.g., TiO2), hafnium oxide (e.g., HfO2), hafnium aluminum oxide (e.g., Hf x Al 1-x O2), tantalum oxide (e.g., Ta2O5), hafnium tantalum oxide (e.g., Hf x Ta 1-x In some embodiments, the HEA dielectric layer 104h is a high-k dielectric, and / or the LEA dielectric layer 104l is a high-k dielectric. The high-k dielectric may be, for example, a dielectric having a dielectric constant k greater than about 3.9, 10.0, or some other suitable value.

[0040] The HEA and LEA dielectric layers 104h, 104l have different material systems or different material compositions. Different material systems correspond to different groups of elements. For the same group of elements (eg, the same material system), different material compositions correspond to different ratios of the elements.

[0041] In embodiments where the HEA and LEA dielectric layers 104h, 104l have different material systems, the HEA dielectric layer 104h consists of or consists essentially of a first set of elements, while the LEA dielectric layer 104l consists of or consists essentially of a second set of elements that is different from the first set of elements. For example, the HEA dielectric layer 104h may be aluminum oxide (e.g., Al2O3), while the LEA dielectric layer 104l may be silicon oxide (e.g., SiO2). However, other suitable materials are also possible.

[0042] In embodiments where the HEA and LEA dielectric layers 104h, 104l have different material compositions, the HEA dielectric layer 104h consists of or consists essentially of a group of elements. Additionally, the LEA dielectric layer 104l consists of or consists essentially of the group of elements, but in a different ratio of elements compared to the HEA dielectric layer 104h. For example, the HEA dielectric layer 104h may be aluminum oxide (e.g., Al2O3), while the LEA dielectric layer 104l may be aluminum oxide having a different ratio of aluminum to oxide (e.g., Al x O y , where x≠2 and y≠3). However, other suitable materials are also possible.

[0043] The HEA and LEA dielectric layers 104h, 104l have separate thicknesses T d In some embodiments, the thickness T d is about 1-50 nm, about 1-25 nm, about 25-50 nm, or some other suitable value. If the thickness T of the HEA or LEA dielectric layer 104h, 104l is d If the thickness T of the HEA dielectric layer 104h is too small (e.g., less than about 1 nanometer or some other suitable value), the benefits of the material properties of the dielectric layer may not be obtained. d If the thickness T of the HEA or LEA dielectric layer 104h, 104l is too small, the HEA dielectric layer 104h may not be able to reduce the possibility of the memory cell 102 being stuck. d If the TFT is too large (e.g., greater than about 50 nanometers or some other suitable value), the operating voltage of the memory cell 102 may be too high. High voltage can, for example, increase power consumption, reduce the life of the memory cell 102, and increase the risk of device failure.

[0044] The top electrode 106 and the bottom electrode 108 are conductive and are adjacent to the plurality of dielectric layers 104. The bottom electrode 106 may be, for example, or include a metal, a metal nitride, a metal oxide, doped polysilicon, some other suitable conductive material, or any combination of the foregoing. The top electrode 108 may be, for example, or include a metal, a metal nitride, doped polysilicon, some other suitable conductive material, or any combination of the foregoing. The top and bottom electrodes 106, 108 may, for example, each be or include aluminum (e.g., Al), titanium (e.g., Ti), tantalum (e.g., Ta), gold (e.g., Au), platinum (e.g., Pt), tungsten (e.g., W), nickel (e.g., Ni), iridium (e.g., Ir), titanium nitride (e.g., TiN), tantalum nitride (e.g., TaN), N-doped polysilicon, P-doped polysilicon, some other suitable conductive material, or any combination of the foregoing.

[0045] refer to Figure 2 , provides a Figure 1 Graph 200 of some embodiments of the electron affinities of HEA and LEA dielectric layers 104h, 104l. The vertical axis corresponds to energy, and the horizontal axis corresponds to Figure 1 The first band gap 202 of the HEA dielectric layer 104h is related to the vacuum energy level E vac The first electron affinity X1 is separated and adjacent to the first Fermi level 204 of the bottom electrode 106. The second band gap 206 of the LEA dielectric layer 1041 is adjacent to the vacuum energy level E vac A second electron affinity X2 is spaced apart that is less than the first electron affinity X1. In addition, the second band gap 206 is adjacent to a second Fermi level 208 of the top electrode 108. The first Fermi level 204 and the second Fermi level 208 are the same, but may alternatively be different.

[0046] Note that the top edge of the first band gap 202 corresponds to the bottom conductive band edge of the HEA dielectric layer 104h, while the top edge of the second band gap 206 corresponds to the bottom conductive band edge of the LEA dielectric layer 104l. Therefore, the bottom conductive band edge of the HEA dielectric layer 104h is lower than the bottom conductive band edge of the LEA dielectric layer 104l.

[0047] As described above, it has been recognized that, at least when the memory cell is an RRAM, placing the HEA dielectric layer 104h closest to the bottom electrode 106 can reduce the likelihood that the memory cell 102 will get stuck during cycling. Thus, the likelihood of a hard reset / failure bit is reduced. Because the likelihood of a hard reset / failure bit is reduced, the hard reset / failure bit is less likely to use the ECC capacity of a memory array (not shown) containing the memory cell 102. Therefore, the memory array is less likely to fail.

[0048] To determine the first and second electron affinities X1, X2 of the HEA and LEA dielectric layers 104h, 104l, respectively, the first and second electron affinities X1, X2 may be measured by X-ray photoelectron spectroscopy (XPS) or by other suitable methods. Figure 3 The materials of the HEA and LEA dielectric layers 104h and 104l are found in the table of which the materials and the corresponding electron affinities are listed. For example, assuming that the HEA dielectric layer 104h is Al2O3 and the LEA dielectric layer 104l is SiO2, by referring to Figure 3 As can be seen from the table, the first and second electron affinities X1 and X2 are approximately 1.25 eV and approximately 0.55 eV, respectively.

[0049] If in Figure 3 The material of HEA or LEA dielectric layers 104h, 104l cannot be found in the table, but is Figure 3 In particular, the electron affinity of a material can be calculated as the weighted sum of the electron affinities of the two or more materials using the atomic percentages of the two or more materials as weights of the electron affinities. For example, assuming that the HEA or LEA dielectric layer 104h, 104l is ZrTiO4, ZrTiO4 in Figure 3 It is not found in the table, but it is a mixture of TiO2 and ZrO2. The atomic percentages of TiO2 and ZrO2 in ZrTiO4 are approximately 50 respectively. In addition, as shown in reference Figure 3 As can be seen from the table, the electron affinities of ZrO2 and TiO2 are approximately 2.65 eV and 2.85 eV, respectively. Therefore, the electron affinity of ZrTiO4 is approximately equal to 2.65 eV*0.5+2.85 eV*0.5, which is approximately equal to 2.75 eV. Although the determination of electron affinity is described using ZrTiO4, other suitable materials are also possible.

[0050] refer to Figure 4A and Figure 4B , providing the setting and reset operation respectively. Figure 1 400A, 400B of some embodiments of the memory cell 102. Figure 4A In the embodiment, a set voltage with a positive polarity (e.g., V+ to V- or to GND) is applied from the top electrode 108 to the bottom electrode 106 to form a conductive filament 402 in the plurality of dielectric layers 104. The conductive filament 402 electrically couples the top electrode 108 to the bottom electrode 106, so the memory cell 102 is in LRS. Figure 4BIn the embodiment of the present invention, a reset voltage having a negative polarity (e.g., V- to V+ or GND to V+) is applied from the top electrode 108 to the bottom electrode 106 to at least partially dissolve the conductive filament 402. Since the conductive filament 402 is at least partially dissolved, the memory cell 102 is in HRS. Because the resistance of the memory cell 102 changes during the set and reset operations, the resistance can be used to represent a data bit. For example, LRS can represent a binary "1", while HRS can represent a binary "0", and vice versa.

[0051] In some embodiments, the memory cell 102 is an oxygen ion type RRAM cell. During a set operation of at least some embodiments of the oxygen ion type RRAM cell, oxygen ions move from the plurality of dielectric layers 104 to a storage region (not shown) between the plurality of dielectric layers 104 and the top electrode 108. The movement of oxygen ions away from the oxygen vacancies constitutes a conductive filament 402 in the plurality of dielectric layers 104. During a reset operation of at least some embodiments of the oxygen ion type RRAM cell, oxygen ions move from the storage region to the plurality of dielectric layers 104 to fill the oxygen vacancies and destroy the conductive filament 402.

[0052] In some embodiments, the memory cell 102 is a metal ion RRAM cell. During a set operation of at least some embodiments of the metal ion RRAM cell, the top electrode 108 is oxidized to form metal ions. In addition, the metal ions migrate to the plurality of dielectric layers 104 and are reduced to the conductive filament 402. During a reset operation of at least some embodiments of the metal ion RRAM cell, the conductive filament 402 is oxidized to form metal ions. In addition, the metal ions migrate to the top electrode 108 and are reduced to the top electrode 108. This in turn destroys the conductive filament 402. In some embodiments where the memory cell 102 is a metal ion RRAM cell, the conductive filament 402 is Figure 4A and Figure 4B Flip vertically and from Figure 4A and Figure 4B The bottom electrode 106 in the embodiment extends upward.

[0053] refer to Figure 5 , provides Figure 1 5 , wherein the memory cell 102 further comprises a capping layer 502. The capping layer 502 is located between the top electrode 108 and the plurality of dielectric layers 104 and has a high affinity for oxygen compared to the bottom and top electrodes 106, 108. In other words, the capping layer 502 relies on less energy to react with oxygen than the bottom and top electrodes 106, 108.

[0054] In at least some embodiments where the memory cell 102 is an oxygen ion RRAM cell, a storage region (not shown) is located between the plurality of dielectric layers 104 and the capping layer 502. In addition, since the capping layer 502 has a high affinity for oxygen, the capping layer 502 increases the size of the storage region. Thus, more oxygen ions can be stored when the memory cell 102 is set and therefore in the LRS. Because more oxygen ions can be stored, the conductive filament 402 (e.g., see Figure 4A and Figure 4B ) may have a greater oxygen vacancy density, and thus the LRS may have a lower resistance. This in turn may increase the difference between the resistances of the memory cells 102 in the LRS and HRS, respectively, and thus may increase the switching window.

[0055] In at least some embodiments where the memory cell 102 is a metal ion RRAM cell, during a set operation, the capping layer 502 is oxidized instead of the top electrode 108. In addition, because the capping layer 502 has a high affinity for oxygen relative to the top electrode 108, the capping layer 502 is more easily oxidized than the top electrode 108. In this way, a smaller set voltage can be used for the set operation, which can improve power efficiency and / or can increase the life of the memory cell 102. In addition, the density of metal ions can be higher, and therefore the metal density in the conductive filament 402 can be higher. This in turn can increase the difference between the resistances of the memory cell 102 in the LRS and HRS, respectively, and thus can increase the switching window.

[0056] The capping layer 502 may be, for example, or include aluminum, titanium, tantalum, hafnium, titanium oxide, hafnium oxide, zirconium oxide, germanium oxide, cerium oxide, some other suitable material, or any combination of the foregoing. In some embodiments, the capping layer 502 is conductive and / or metallic. For example, in an embodiment where the memory cell 102 is a metal-ion RRAM cell, the capping layer 502 is conductive and includes a metal. In an alternative embodiment, the capping layer 502 is a dielectric. In an embodiment where the capping layer 502 is a dielectric, the capping layer 502 has a lower electron affinity and a higher bottom conduction band edge than the HEA dielectric layer 104h.

[0057] refer to Figure 6 , provides Figure 1 600 of some alternative embodiments of a memory cell 102, wherein the plurality of dielectric layers 104 include three or more dielectric layers: 1) a HEA dielectric layer 104h; and 2) two or more LEA dielectric layers (labeled 104l1 to 104l n , where n is an integer greater than 1).

[0058] Each of the two or more LEA dielectric layers 10411, ..., 1041n is as follows: Figure 1 As described above, the two or more LEA dielectric layers 10411, ..., 104ln each have a lower electron affinity than the HEA dielectric layer 104h. In addition, each of the two or more LEA dielectric layers 10411, ..., 104ln has a different material system or a different material composition than the HEA dielectric layer 104h. In some embodiments, each of the two or more LEA dielectric layers 10411, ..., 104ln is different from each adjacent LEA dielectric layer and / or each other LEA dielectric layer.

[0059] refer to Figure 7 , provides Figure 6 700 of some embodiments of a memory cell 102, wherein the memory cell 102 is limited to two LEA dielectric layers: a first LEA dielectric layer 10411; and a second LEA dielectric layer 10412. In other words, Figure 6 The integer n in is equal to 2.

[0060] refer to Fig. 8A and Figure 8B , provides Figure 7 HEA dielectric layer 104h and Figure 7 800A and 800B of different embodiments of the electron affinity of the first LEA dielectric layer 10411 and the second LEA dielectric layer 10412. The vertical axis corresponds to energy, and the horizontal axis corresponds to the electron affinity of the first LEA dielectric layer 10411 and the second LEA dielectric layer 10412. Figure 7 The position of line B in .

[0061] The first band gap 802 of the HEA dielectric layer 104h is related to the vacuum energy level E vac The first electron affinity X1 is separated from the first LEA dielectric layer 10411 and is adjacent to the first Fermi level 204 of the bottom electrode 106. The second band gap 804 of the first LEA dielectric layer 10411 is adjacent to the vacuum energy level E vac The third band gap 806 of the second LEA dielectric layer 10412 is spaced apart from the vacuum energy level E vac The third electron affinity X3 is spaced apart and abuts the second Fermi level 208 of the top electrode 108. As described above, the second and third electron affinities X2, X3 are less than the first electron affinity X1 to prevent the memory cell 102 from getting stuck during cycling, at least when the memory cell is an RRAM.

[0062] Note that the top edge of the first band gap 802 corresponds to the bottom conductive band edge of the HEA dielectric layer 104h, and the top edges of the second and third band gaps 804, 806 correspond to the bottom conductive band edges of the first and second LEA dielectric layers 104l1, 104l2. Therefore, the bottom conductive band edge of the HEA dielectric layer 104h is lower than the bottom conductive band edges of the first and second LEA dielectric layers 104l1, 104l2.

[0063] Specific reference Fig. 8A , the first electron affinity X1 is greater than the second electron affinity X2, and the second electron affinity X2 is greater than the third electron affinity X3. Therefore, Figure 7 The electron affinity of the dielectric structure defined by the plurality of dielectric layers 104 decreases discretely from the bottom electrode 106 to the top electrode 108. In addition, the bottom conductive strip edge of the dielectric structure has a stepped profile that steps upward from the bottom electrode 106 to the top electrode 108.

[0064] Specific reference Figure 8B , the first electron affinity X1 is greater than the second electron affinity X2, and the third electron affinity X3 is between the first and second electron affinities X1 and X2. Figure 7 The electron affinity of the dielectric structure defined by the plurality of dielectric layers 104 decreases discretely from the bottom electrode 106 to the top electrode 108 and then increases discretely. In addition, the bottom conductive band edge of the dielectric structure rises in steps from the bottom electrode 106 to the top electrode 108 and then falls in steps. In alternative embodiments, the dielectric structure has other suitable electron affinity profiles and / or bottom conductive band edge profiles.

[0065] refer to Fig. 9 , provides Figure 6 900 of some optional embodiments of the memory cell 102, wherein the memory cell 102 further includes a capping layer 502. The capping layer 502 may include, for example, Figure 5 Thus, the overlay 502 can, for example, provide an expanded switching window, reduced power consumption, other suitable benefits, or any combination of the foregoing.

[0066] refer to Fig.10 , provides Figure 1 1000 of some embodiments of memory cells 102 of an IC chip, wherein the memory cells 102 are located in an interconnect structure 1002 of an IC chip. The memory cells 102 are located below the top electrode line 1004t and the top electrode via 1006t. In addition, the memory cells 102 are located above the bottom electrode line 1004b and the bottom electrode via 1008.

[0067] The top electrode via 1006t extends from the top electrode line 1004t downward to the top electrode 108. In addition, the top electrode via 1006t extends through the hard mask 1010 on top of the top electrode 108. In an alternative embodiment, the hard mask 1010 is omitted. The hard mask 1010 can be or include, for example, silicon nitride and / or some other suitable dielectric. The top electrode line 1004t and the top electrode via 1006t can be or include, for example, copper, aluminum, aluminum copper, some other suitable metal, or any combination of the foregoing.

[0068] Bottom electrode via 1008 extends upward from bottom electrode line 1004b to bottom electrode 106 and includes via plug 1008p and via liner 1008l. In an optional embodiment, via liner 1008l is omitted. Bottom electrode line 1004b can be or include, for example, copper, aluminum, aluminum copper, some other suitable metal, or any combination of the foregoing.

[0069] The via liner 10081 cups the bottom side of the via plug 1008p to separate the via plug 1008p from the bottom electrode line 1004b. In some embodiments, the via liner 10081 is an adhesion layer to enhance the deposition of the layers forming the via plug 1008p. In some embodiments, the via liner 10081 is a diffusion barrier to prevent the material of the bottom electrode line 1004b from diffusing upward to the via plug 1008p and / or the bottom electrode 106. The via liner 10081 can be or include, for example, tantalum nitride and / or some other suitable conductive barrier material. The via plug 1008p can be or include, for example, titanium nitride, aluminum, titanium, tantalum, gold, platinum, tungsten, some other suitable conductive material, or any combination of the foregoing. In some embodiments, the via plug 1008 p is integrated with and / or is the same material as the bottom electrode 106 , such that there is no boundary between the bottom electrode 106 and the via plug 1008 p .

[0070] The dielectric structure surrounds the memory cell 102 and the top electrode line 1004t, the top electrode via 1006t, the bottom electrode line 1004b, and the bottom electrode via 1008. The dielectric structure includes a hard mask 1010 and also includes a sidewall spacer structure 1012 located at the sidewall of the top electrode 108. The sidewall spacer structure 1012 can be or include, for example, silicon nitride and / or some other suitable dielectric. In addition, the dielectric structure includes a plurality of intermetallic dielectric (IMD) layers 1014, a via dielectric layer 1016, and an etch stop layer 1018.

[0071] The IMD layer 1014 surrounds the bottom electrode line 1004b and the top electrode line 1004t, respectively. The IMD layer 1014 may be or include, for example, an extremely low-k dielectric and / or some other suitable dielectric.

[0072] A through-hole dielectric layer 1016 and an etch stop layer 1018 are stacked between the IMD layers 1014. The through-hole dielectric layer 1016 surrounds the bottom electrode through hole 1008 and is located between the memory cell 102 and the bottom electrode line 1004b. The through-hole dielectric layer 1016 can be, for example, or include silicon carbide, silicon-rich oxide, some other suitable dielectric, or any combination of the foregoing. The etch stop layer 1018 covers the through-hole dielectric layer 1016 and wraps around the top of the memory cell 102. The etch stop layer 1018 can be, for example, or include silicon carbide and / or some other suitable dielectric.

[0073] refer to Fig.11A and Fig. 11B , provides Fig.10 Cross-sectional views 1100A, 1100B of different alternative embodiments of the memory cell 102. Fig.11A In the embodiment, the memory unit 102 also includes the following Figure 5 The cover layer 502 is described. In addition, the sidewall spacer structure 1012 is located on the sidewall of the cover layer 502. Fig. 11B 1004b, and each individual layer of the memory cell 102, except for the top electrode 108, has a U-shaped or V-shaped profile. However, in alternative embodiments, other suitable profiles are possible. In addition, the relative positions between the components have been rearranged, and the bottom electrode via 1008, the sidewall spacer structure 1012, and the hard mask 1010 are omitted.

[0074] Fig. 11B The memory cell 102 of the embodiment can be formed by a single lithography / etching process. For example, a contiguous one of the through-hole dielectric layer 1016 and the IMD layer 1014 can be deposited above the bottom electrode line 1004b. The through-hole dielectric layer 1016 and the IMD layer can then be patterned to define a memory cell opening that exposes the bottom electrode line 1004b. In addition, a separate layer forming the memory cell 102 can be conformally deposited in the memory cell opening and cover the IMD layer. With the deposited layers, planarization can be performed to expose the IMD layer and pattern the layer into the memory cell 102. Since lithography is expensive, the memory cell 102 formed by a single lithography / etching process is Fig. 11B The memory unit 102 can save a lot of cost.

[0075] refer to Fig. 12A , a cross-sectional view 1200A of some embodiments of an IC chip including a plurality of memory cells 102 is provided, wherein the memory cells 102 are integrated into separate single transistor single resistor (1T1R) cells 1202, and each of the memory cells 102 is connected to a single transistor single resistor (1T1R) cell 1202. Fig.10The 1T1R cell 1202 includes a separate drain region 1204 and a separate drain-side conductive path 1206 .

[0076] The drain regions 1204 are doped regions of the substrate 1208 and each have a doping type opposite to that of an adjacent region of the substrate 1208. In addition, the drain regions 1204 are electrically isolated from each other by trench isolation structures 1210 and partially define access transistors 1212 (partially shown) for individually selecting the memory cells 102. The trench isolation structures 1210 extend to the top of the substrate 1208 and include silicon oxide and / or some other suitable dielectric material. The trench isolation structures 1210 may be, for example, shallow trench isolation (STI) structures or some other suitable trench isolation structures. The substrate 1208 may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or some other suitable semiconductor substrate.

[0077] Drain side conductive paths 1206 electrically couple drain regions 1204 to memory cells 102 and are defined by interconnect structure 1002. Interconnect structure 1002 includes a plurality of lines 1004 and a plurality of vias 1006. The plurality of lines 1004 include top electrode lines 1004t and bottom electrode lines 1004b. In some embodiments, top electrode lines 1004t correspond to bit lines BL. The plurality of vias 1006 include top electrode vias 1006t. The level of vias 1006 closest to substrate 1208 is in interlayer dielectric (ILD) layer 1214, while the remaining levels of vias 1006 and lines 1004 are in IMD layer 1014. Lines 1004 and vias 1006 are conductive and may be or include, for example, copper, aluminum, aluminum copper, some other suitable conductive material, or any combination of the foregoing.

[0078] A peripheral region 1216 to one side of the 1T1R cell 1202 accommodates a peripheral device 1218 (only partially shown). The peripheral device 1218 includes a pair of source / drain regions 1220 (only one of which is shown) located in the substrate 1208, and also includes a gate structure (not shown) located between the source / drain regions 1220. The source / drain regions 1220 are doped regions of the substrate 1208, and each has a doping type opposite to that of an adjacent region of the substrate 1208. The peripheral device 1218 can be, for example, a metal oxide semiconductor field effect transistor (MOSFET) or other suitable type of semiconductor device. In an optional embodiment, the peripheral device 1218 is a fin field effect transistor (FinFET), a full-all-around gate field effect transistor (GAA FET), a nanowire field effect transistor, a nanosheet field effect transistor, or some other suitable type of semiconductor device.

[0079] refer to Fig. 12B , provides Fig. 12AA cross-sectional view 1200B of some embodiments of an IC chip, taken along the Fig. 12A The cross-sectional view 1200A of FIG. 1T1R cell 1202 includes a separate memory cell 102 , a separate drain-side conductive path 1206 , a separate access transistor 1212 , and a separate source-side conductive path 1222 .

[0080] The access transistor 1212 is located on the substrate 1208, between the substrate 1208 and the interconnect structure 1002. In addition, the access transistors 1212 are electrically isolated from each other by the trench isolation structure 1210. The access transistor 1212 includes a separate drain region 1204, a separate source region 1224, a separate gate dielectric layer 1226, and a separate gate electrode 1228. The gate electrode 1228 is respectively located above the gate dielectric layer 1226, and in some embodiments, defines a word line WL. The drain region 1204 and the source region 1224 are doped regions of the substrate 1208, and each has a doping type opposite to an adjacent region (e.g., body) of the substrate 1208. The drain region 1204 is respectively adjacent to the drain side of the gate electrode 1228, and the source region 1224 is respectively adjacent to the source side of the gate electrode 1228. The access transistor 1212 can be, for example, a MOSFET or some other suitable type of semiconductor device.

[0081] Drain side conductive paths 1206 electrically couple drain region 1204 to memory cell 102 and source side conductive paths 1222 electrically couple source region 1224 to source line SL. Drain side and source side conductive paths 1206, 1222 are defined by the plurality of lines 1004 and the plurality of vias 1006.

[0082] refer to Fig.13 , provides Fig. 12A and Fig. 12B FIG. 1300 is a top view of some embodiments of an IC chip. Fig. 12A and Fig. 12B The cross-sectional views 1200A and 1200B can be taken along lines C and D, respectively, or other suitable locations. The IC chip includes a plurality of memory cells 102 in a plurality of rows and columns, thereby defining a memory array 1302. The memory cells 102 can be, for example, Figure 1 , Figure 4A , Figure 4B , Figures 5 to 7 , Fig. 9 , Fig.10 , Fig.11A , Fig. 11B , Fig. 12A or Fig. 12B any one of the following.

[0083] The peripheral device 1218 surrounds the memory array 1302 at the peripheral area 1216 of the IC chip. The peripheral device 1218 can be, for example, or include a transistor and / or other suitable semiconductor device. In addition, the peripheral device 1218 can, for example, adopt an ECC circuit, a read / write circuit, other suitable circuits for operating the memory cell 102, or any combination of the foregoing.

[0084] As described above, the memory cell 102 includes a separate HEA dielectric layer disposed proximate to the separate bottom electrode to reduce the likelihood of the memory cell 102 being stuck during cycling, at least when the memory cell 102 is an RRAM cell. Thus, the likelihood of a hard reset / failure bit is reduced. Because the likelihood of a hard reset / failure bit is reduced, the hard reset / failure bit is less likely to use ECC capacity in an ECC circuit for the memory array 1302. In some embodiments, the ECC circuit is defined in whole or in part by a portion 1304 of the peripheral area 1216. Since the hard reset / failure bit is less likely to use ECC capacity, the memory array 1302 is less likely to fail. Because the HEA dielectric layer reduces the likelihood of the memory array 1302 failing, no additional ECC capacity is required, and therefore no additional IC chip area is required.

[0085] refer to Fig.14 , provides Fig. 12A and Fig. 12B 1400 is a schematic diagram of some embodiments of the 1T1R unit 1202. The 1T1R unit 1202 represents Fig. 12A and Fig. 12B Each other 1T1R cell 1202 in the memory cell 102 includes a memory cell 102 and an access transistor 1212 electrically coupled in series from a bit line BL to a source line SL. As described above, the memory cell 102 includes a HEA dielectric layer 104h to prevent the memory cell 102 from being stuck during cycling, at least when the memory cell 102 is an RRAM. The access transistor 1212 is selected by the word line WL and selectively couples the memory cell 102 to the source line SL according to a signal carried on the word line WL. The access transistor 1212 is shown as a MOSFET, but may be some other suitable type of semiconductor device.

[0086] refer to FIG. 15A to FIG. 15C , provides Fig.14 Schematic diagrams 1500A-1500C of some different alternative embodiments of the 1T1R cell 1202, wherein the access transistor 1212 is a different type of semiconductor device. Fig.15A In , access transistor 1212 is a bipolar junction transistor (BJT). Fig. 15BIn , access transistor 1212 is a HEMT with a Schottky gate contact. Fig. 15C In the embodiment, access transistor 1212 is a metal oxide semiconductor (MOS) high electron mobility transistor (HEMT). In alternative embodiments, access transistor 1212 is some other suitable type of semiconductor device.

[0087] Although Fig.10 , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.14 and FIG. 15A to FIG. 15C The memory cell 102 is shown as having a single LEA dielectric layer 1041, but in alternative embodiments, Fig.10 , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.14 and FIG. 15A to FIG. 15C The memory cell 102 may have two or more LEA dielectrics. Figure 5 and Figure 6 Although Fig. 11B , Fig. 12A , Fig. 12B , Fig.14 and FIG. 15A to FIG. 15C The memory cell 102 is shown without Figure 5 The cover layer 502, but in an alternative embodiment, Fig. 11B , Fig. 12A , Fig. 12B , Fig.14 and FIG. 15A to FIG. 15C The memory cell 102 may have a capping layer 502. Although Fig. 12A and Fig. 12B Each memory cell 102 in the IC chip is based on Fig.10 Embodiment configuration, but may alternatively adopt Fig.11A and Fig. 11B Although Fig.14 and FIG. 15A to FIG. 15C The 1T1R unit 1202 includes Figure 1 Memory cell 102, but in an alternative embodiment, Fig.14 and FIG. 15A to FIG. 15C The 1T1R unit 1202 may alternatively include Figure 4A , Figure 4B , Figures 5 to 7 , Fig. 9 , Fig.10 , Fig.11A , Fig. 11B , Fig. 12A or Fig. 12BMemory cell 102 in any one of.

[0088] refer to Figures 16 to 23 , a series of cross-sectional views 1600-2300 of some embodiments of a method for forming a memory cell integrated with a 1T1R cell and including a separate HEA dielectric layer at a corresponding bottom electrode are provided. The cross-sectional views 1600-2300 can be taken, for example, along Fig.13 Line C or Fig.13 In addition, the cross-sectional views 1600-2300 may, for example, show the addition of a cover layer. Fig. 12A and Fig. 12B The formation of IC chips.

[0089] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 16 , the trench isolation structure 1210 is formed to extend to the top of the substrate 1208. The trench isolation structure 1210 surrounds and divides the region of the substrate 1208 where the 1T1R cell 1202 is formed. In addition, the trench isolation structure 1210 surrounds and divides the peripheral region 1216 of the IC chip.

[0090] Also through Fig.16 The cross-sectional view 1600 of 1208 shows that a plurality of semiconductor devices are formed on a substrate 1208. The plurality of semiconductor devices include access transistors 1212 (only partially shown) that are independent of and respectively located at the 1T1R cell 1202 being formed. In addition, the plurality of semiconductor devices include a peripheral device 1218 (only partially shown) located at a peripheral region 1216 of the IC chip. The access transistor 1212 includes a separate drain region 1204 and a separate source region (not shown) located in the substrate 1208. In addition, the access transistor 1212 includes a separate gate structure (not shown). The gate structure has separate drain sides that are respectively adjacent to the drain regions 1204, and also has separate source sides that are respectively adjacent to the source regions. The peripheral device 1218 includes a pair of source / drain regions 1220 (only one of which is shown) located in the substrate 1208, and also includes a gate structure (not shown) located between and adjacent to the source / drain regions 1220.

[0091] like Fig.17As shown in the cross-sectional view 1700 of , the interconnect structure 1002 is partially formed above the semiconductor device (e.g., the access transistor 1212 and the peripheral device 1218) and is electrically coupled to the semiconductor device. The interconnect structure 1002 includes a plurality of lines 1004 and a plurality of through holes 1006 stacked in a dielectric structure. The dielectric structure includes an ILD layer 1214 and a plurality of IMD layers 1014 located above the ILD layer 1214. The plurality of lines 1004 include a plurality of bottom electrode lines 1004b along the top surface of the interconnect structure 1002. The bottom electrode lines 1004b are independent of the 1T1R unit 1202 and are respectively located at the formed 1T1R unit 1202. In addition, the bottom electrode lines 1004b are respectively electrically connected to the drain region 1204 of the access transistor 1212 through the lines 1004 and the through holes 1006.

[0092] Also through Fig.17 The cross-sectional view 1700 of illustrative embodiment shows that a through-hole dielectric layer 1016 is deposited on the interconnect structure 1002 .

[0093] like Fig.18 As shown in the cross-sectional view 1800 of FIG. 18 , a bottom electrode via 1008 is formed in the through-hole dielectric layer 1016. Note that, in order to achieve compactness, the lower portion of the interconnect structure 1002 and the structure located below the lower portion are omitted in this figure and the subsequent figures. The bottom electrode via 1008 is independent of the formed 1T1R unit 1202, and extends to the bottom electrode line 1004b through the through-hole dielectric layer 1016 respectively. In addition, the bottom electrode via 1008 includes a separate through-hole plug 1008p and a separate through-hole liner 1008l. In an optional embodiment, the through-hole liner 1008l is omitted. The through-hole liner 1008l cups the bottom side of the through-hole plug 1008p to separate the through-hole plug 1008p from the bottom electrode line 1004b.

[0094] The process for forming the bottom electrode via 1008 may include, for example: 1) patterning the through-hole dielectric layer 1016 to form openings that are independent of the bottom electrode line 1004b and expose the bottom electrode line 1004b, respectively; 2) depositing a liner layer and a plug layer to fill the opening and cover the through-hole dielectric layer 1016; and 3) performing planarization on the plug and liner layers to expose the through-hole dielectric layer 1016. However, other suitable processes are also possible.

[0095] Also through Fig.181800 shows that a bottom electrode layer 1802 is deposited to cover the through-hole dielectric layer 1016 and the bottom electrode through-hole 1008. The bottom electrode layer 1802 is conductive and electrically coupled to the bottom electrode line 1004b through the bottom electrode through-hole 1008. The bottom electrode layer 1802 may be, for example, or include a metal, a metal nitride, a metal oxide, doped polysilicon, some other suitable conductive material, or any combination of the foregoing. In addition, the bottom electrode layer 1802 may be, for example, or include aluminum, titanium, tantalum, gold, platinum, tungsten, nickel, iridium, titanium nitride, tantalum nitride, N-doped polysilicon, P-doped polysilicon, some other suitable material, or any combination of the foregoing. In some embodiments, the bottom electrode layer 1802 is the same material as the through-hole plug 1008p.

[0096] Although the bottom electrode layer 1802 and the bottom electrode via 1008 are described as being formed separately, in alternative embodiments, the bottom electrode layer 1802 and the bottom electrode via 1008 may be formed together. In at least some of these alternative embodiments, the via plug 1008p is part of the bottom electrode layer 1802, and there is no boundary between the via plug 1008p and the bottom electrode layer 1802.

[0097] like Fig.19 As shown in the cross-sectional view 1900 of , the plurality of dielectric layers 104 are deposited to be stacked vertically above the bottom electrode layer 1802. In addition, the dielectric layer 104h (i.e., the HEA dielectric layer 104h) having the highest electron affinity among the plurality of dielectric layers 104 and therefore closest to the bottom electrode layer 1802 is deposited first. As will be seen below, the plurality of dielectric layers 104 are divided into a plurality of segments that are independent of the formed memory cells and serve as switching layers for the memory cells. In addition, it has been appreciated that by arranging the HEA dielectric layer 104h closest to the bottom electrode layer 1802, at least when the memory cell is an RRAM cell, the likelihood of the memory cell being stuck during cycling is reduced.

[0098] The plurality of dielectric layers 104 include a HEA dielectric layer 104h, and further include a dielectric layer 104l (i.e., LEA dielectric layer 104l) having a low electron affinity compared to the HEA dielectric layer 104h. The LEA dielectric layer 104l is located above the HEA dielectric layer 104h and is therefore further away from the bottom electrode layer 1802 than the HEA dielectric layer 104h. In an alternative embodiment, the plurality of dielectric layers 104 include two or more LEA dielectric layers vertically stacked above the HEA dielectric layer 104h, and each is described as a LEA dielectric layer 104l.

[0099] The HEA dielectric layer 104h is a different dielectric material than the LEA dielectric layer 104l. Each of the HEA and LEA dielectric layers 104h, 104l can be, for example, a metal oxide, a metal oxynitride, a component metal oxide, some other suitable dielectric, or any combination of the foregoing. In addition, each of the HEA and LEA dielectric layers 104h, 104l can be, for example, titanium oxide (e.g., TiO2), hafnium oxide (e.g., HfO2), hafnium aluminum oxide (e.g., Hf x Al 1-x O2), tantalum oxide (e.g., Ta2O5), hafnium tantalum oxide (e.g., Hf x Ta 1-x O2), tungsten oxide (e.g., WO2), zirconium oxide (e.g., ZrO2), aluminum oxide (e.g., Al2O3), sulfated tin oxide (e.g., STO), some other suitable dielectric, or any combination of the foregoing. In some embodiments, the HEA dielectric layer 104h is a high-k dielectric, and / or the LEA dielectric layer 104l is a high-k dielectric.

[0100] The HEA and LEA dielectric layers 104h, 104l have different material systems or different material compositions. Different material systems correspond to different groups of elements. For example, the HEA dielectric layer 104h may be tantalum oxide (e.g., Ta2O5) and the LEA dielectric layer 104l may be aluminum oxide (e.g., Al2O3). For the same group of elements (e.g., the same material system), different material compositions correspond to different ratios of the elements. For example, the HEA dielectric layer 104h may be aluminum oxide (e.g., Al2O3) and the LEA dielectric layer 104l may be aluminum oxide with different ratios of aluminum and oxide (e.g., Al x O y , where x≠2 and y≠3). Although the first two examples provide specific materials, other suitable materials are possible.

[0101] The HEA and LEA dielectric layers 104h, 104l have separate thicknesses T d In some embodiments, the thickness T d is about 1-50 nm, about 1-25 nm, about 25-50 nm, or some other suitable value. If the thickness T of the HEA or LEA dielectric layer 104h, 104l is d If the thickness T of the HEA dielectric layer 104h is too small (e.g., less than about 1 nanometer or some other suitable value), the benefits of the material properties of the dielectric layer may not be obtained. d If the thickness T of the HEA or LEA dielectric layer 104h, 104l is too small, then at least when the memory cell is an RRAM cell, the HEA dielectric layer 104h may not prevent the formed memory cell from getting stuck during cycling.d If the thickness of the memory cell is too large (eg, greater than about 50 nanometers or some other suitable value), the operating voltage of the formed memory cell may be too high. High voltage may, for example, increase power consumption, reduce the useful life of the memory cell and increase the risk of device failure.

[0102] The process for depositing the plurality of dielectric layers 104 may, for example, include sequentially depositing the plurality of dielectric layers 104 by chemical vapor deposition (CVD), physical vapor deposition (PVD), some other suitable deposition process, or any combination of the foregoing. In some embodiments, the HEA dielectric layer 104h is deposited by thermal oxidation of the bottom electrode layer 1802, and then the LEA dielectric layer 104l is deposited by CVD, PVD, or some other suitable deposition process.

[0103] As described above, the HEA and LEA dielectric layers 104h, 104l have different material systems or different material compositions. In some embodiments where the HEA and LEA dielectric layers 104h, 104l have different material systems, the HEA and LEA dielectric layers 104h, 104l are deposited by vapor deposition using different sets of precursors, respectively. In some embodiments where the HEA and LEA dielectric layers 104h, 104l have different material compositions, the HEA and LEA dielectric layers 104h, 104l are deposited by vapor deposition using the same set of precursors but different ratios of precursors. In addition, in some embodiments where the HEA and LEA dielectric layers 104h, 104l have different material compositions, the HEA and LEA dielectric layers 104h, 104l are deposited in situ in a common process chamber.

[0104] Also by Fig.19 The cross-sectional view 1900 of EMBODIMENT 1 shows that a vertically stacked capping layer 502 and a top electrode layer 1902 are deposited on the plurality of dielectric layers 104. In an alternative embodiment, the capping layer 502 is omitted and therefore not deposited.

[0105] The capping layer 502 has a high affinity for oxygen compared to the bottom and top electrode layers 1802, 1902. In other words, the capping layer 502 relies on less energy to react with oxygen than the bottom and top electrode layers 1802, 1902. At least when the formed memory cell is a metal ion RRAM cell and an oxygen ion RRAM cell, the capping layer 502 can enhance the performance of the memory cell. For example, the capping layer 502 can increase the switching window and / or reduce the operating voltage. The capping layer 502 can, for example, be or include aluminum, titanium, tantalum, hafnium, titanium oxide, hafnium oxide, zirconium oxide, germanium oxide, cerium oxide, some other suitable material, or any combination of the foregoing. In some embodiments, the capping layer 502 is conductive and / or metallic. For example, in an embodiment in which the formed memory cell is a metal ion RRAM cell, the capping layer 502 is a metal. In an optional embodiment, the capping layer 502 is a dielectric. In embodiments where the capping layer 502 is a dielectric, the capping layer 502 has a lower electron affinity than the HEA dielectric layer 104h.

[0106] The top electrode layer 1902 may be, for example, or include metal, metal nitride, doped polysilicon, some other suitable conductive material, or any combination thereof. In addition, the top electrode layer 1902 may be, for example, or include aluminum, titanium, tantalum, gold, platinum, tungsten, nickel, iridium, titanium nitride, tantalum nitride, N-doped polysilicon, P-doped polysilicon, some other suitable material, or any combination thereof.

[0107] like Fig. 20 As shown in the cross-sectional view 2000 of FIG. 1 , a hard mask 1010 is formed, which is independent of the 1T1R cell 1202 and is respectively located at the formed 1T1R cell 1202. As will be seen below, the hard mask 1010 has a pattern for the memory cell of the 1T1R cell 1202. For example, the hard mask 1010 can be formed by forming a top electrode layer 1902 (e.g., see Fig.19 ) and then patterning the hard mask layer into the hard mask 1010 to form the hard mask 1010. For example, the patterning may be performed by a photolithography / etching process or some other suitable patterning process.

[0108] Also through Fig. 20The cross-sectional view 2000 of illustrative embodiments shows that with the hard mask 1010 in place, a first etch is performed on the top electrode layer 1902 (see, e.g., 19) and the capping layer 502 (see, e.g., 19). The first etch stops on the plurality of dielectric layers 104 and transfers the pattern of the hard mask 1010 to the top electrode layer 1902 and the capping layer 502. By transferring the pattern to the top electrode layer 1902, the first etch divides the top electrode layer 1902 into top electrodes 108, which are independent of the memory cells being formed. By transferring the pattern to the capping layer 502, the first etch divides the capping layer 502 into capping segments that are independent of the memory cells.

[0109] like Fig.21 As shown in the cross-sectional view 2100 of FIG. 2 , a sidewall spacer structure 1012 is formed on a common sidewall defined by the hard mask 1010, the top electrode 108, and the capping layer 502. The sidewall spacer structure 1012 may be, for example, or include silicon nitride and / or some other suitable dielectric. The process for forming the sidewall spacer structure 1012 may, for example, include: 1) Depositing a covering and conformally lining Fig. 20 and 2) etching back the spacer layer. However, other suitable processes are also possible.

[0110] Also through Fig.21 The cross-sectional view 2100 of 2100 shows that with the hard mask 1010 and the sidewall spacer structure 1012 in place, a second etch is performed on the plurality of dielectric layers 104 and the bottom electrode layer 1802. The second etch stops on the through-hole dielectric layer 1016 and transfers the pattern defined by the hard mask 1010 and the sidewall spacer structure 1012 to the dielectric layer 104 and the bottom electrode layer 1802. By transferring the pattern to the plurality of dielectric layers 104, the second etch divides the plurality of dielectric layers 104 into dielectric segments that are independent of the memory cells to be formed. By transferring the pattern to the bottom electrode layer 1802, the second etch divides the bottom electrode layer 1802 into bottom electrodes 106 that are independent of the memory cells.

[0111] After the second etch is completed, the memory cell 102 is retained independently of the formed 1T1R cell 1202. The individual bottom electrodes 106 of the memory cell 102 are respectively located on the bottom electrode through-holes 1008 and electrically coupled to the bottom electrode through-holes 1008. The individual dielectric segments of the plurality of dielectric layers 104 are respectively located on the bottom electrodes 106. The individual covering segments of the covering layer 502 are respectively located on the dielectric segments. The individual top electrodes 108 are respectively located on the covering segments. The memory cell 102 can be, for example, an oxygen ion RRAM cell, a metal ion RRAM cell, or some other suitable type of memory cell.

[0112] During operation of the memory cell 102, the separate dielectric segments serve as a switching layer that changes between the HRS and the LRS. In addition, because the HEA dielectric layer 104h is closest to the bottom electrode 106 among the multiple dielectric layers 104, the likelihood of the memory cell 102 getting stuck during cycling is reduced, at least when the memory cell is an RRAM cell. Therefore, the likelihood of a hard reset / failure bit is reduced. Because the likelihood of a hard reset / failure bit is reduced, the hard reset / failure bit is less likely to use the ECC capacity of the memory array (not shown) containing the memory cell 102. Therefore, the memory array is less likely to fail. Because the HEA dielectric layer 104h reduces the likelihood of a memory array failure, no additional ECC capacity is required, and therefore no additional IC chip area is required.

[0113] Because the possibility of the memory cell 102 getting stuck during cycling is reduced by the HEA dielectric layer 104h, this possibility can be reduced by additional deposition processes during the method. In this way, the HEA dielectric layer 104h adds almost no additional cost and is compatible with 40 nm or smaller process nodes.

[0114] like Fig. 22 As shown in the cross-sectional view 2200 of FIG. 2 , the interconnect structure 1002 is completed around the memory cell 102. This includes depositing an etch stop layer 1018 and an additional IMD layer 1014 covering the memory cell 102, and then forming a plurality of additional lines 1004 and a plurality of additional vias 1006 in the etch stop layer 1018 and the additional IMD layer 1014. The plurality of additional lines 1004 include top electrode lines 1004t respectively located above the memory cells 102, and the plurality of additional vias 1006 include top electrode vias 1006t respectively extending from the top electrode lines 1004t to the top electrodes 108 of the memory cells 102.

[0115] like Fig.23 As shown in the cross-sectional view 2300 of FIG. 2 , at the memory cell 102, conductive filaments 402 independent of the memory cell 102 are formed in the plurality of dielectric layers 104, respectively. The formation may include, for example, applying a forming voltage to each memory cell 102. For example, when the top electrode 108 of the memory cell 102 is biased, the bottom electrode 106 of the memory cell 102 may be grounded. However, other processes for forming the conductive filaments 402 are possible.

[0116] Although the reference method describes Figures 16 to 23 , it should be understood that Figures 16 to 23 The structure shown in is not limited to this method, but can be independently independent of this method. Figures 16 to 23Described as a series of acts, it will be appreciated that in other embodiments, the order of the acts may be varied. Figures 16 to 23 What is shown and described is a particular set of actions, but some of the actions shown and / or described may be omitted in other embodiments. In addition, actions not shown and / or described may be included in other embodiments.

[0117] refer to Fig.24 , provides Figures 16 to 23 Block diagram 2400 of some embodiments of the method.

[0118] At 2402, an access transistor is formed on a substrate. See, e.g. Fig.16 .

[0119] At 2404, an interconnect structure is partially formed over the substrate and the access transistor, wherein the interconnect structure includes a bottom electrode line located above the access transistor and electrically coupled to the access transistor. See, e.g. Fig.17 .

[0120] At 2406, a through-hole dielectric layer is formed over the interconnect structure. See, e.g. Fig.17 .

[0121] At 2408, a bottom electrode via is formed that extends through the via dielectric layer to the bottom electrode line. See, e.g. Fig.18 .

[0122] At 2410, a bottom electrode layer is deposited over the via dielectric layer and the bottom electrode via. See e.g. Fig.18 .

[0123] At 2412, a plurality of dielectric layers are deposited to be vertically stacked above the bottom electrode layer, wherein the dielectric layer having the highest electron affinity among the plurality of dielectric layers and closest to the bottom electrode layer is deposited first. See, e.g. Fig.19 .

[0124] At 2414, a capping layer is deposited over the plurality of dielectric layers. See, e.g. Fig.19 .

[0125] At 2416, a top electrode layer is deposited over the capping layer. See e.g. Fig.19 .

[0126] At 2418, the top and bottom electrode layers, the capping layer, and the plurality of dielectric layers are patterned to form a memory cell that is located above the bottom electrode line and electrically coupled to the bottom electrode line through the bottom electrode via. See, e.g. Fig. 20 and Fig.21 .

[0127] At 2420, an interconnect structure is completed around the memory cell. See e.g. Fig. 22 .

[0128] At 2422, a forming voltage is applied across the memory cell to form a conductive filament in the plurality of dielectric layers. See, e.g. Fig.23 .

[0129] Although here Fig.24 The block diagram 2400 is shown and described as a series of actions or events, but it will be understood that the order in which such actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in different orders and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, all of the actions shown may not be required to implement one or more aspects or embodiments described herein, and one or more actions described herein may be performed in one or more separate actions and / or stages.

[0130] refer to Figure 25 to Figure 29 , provides Figures 16 to 23 A series of cross-sectional views 2500-2900 of some optional embodiments of a method of forming a layer of a memory cell using planarization patterning. The cross-sectional views 2500-2900 may be taken, for example, along Fig.13 Line C in or Fig.13 In addition, the cross-sectional views 2500-2900 may, for example, show the addition of a cover layer. Fig. 11B The memory cell 102 is formed.

[0131] like Fig.25 As shown in the cross-sectional view 2500, the execution Fig.16 and Fig.17 A trench isolation structure 1210 is formed, and the trench isolation structure 1210 extends to Fig.16 The top of the substrate 1208 shown and described. In addition, as with respect to Fig.16 As shown and described, a plurality of semiconductor devices are formed on substrate 1208. The plurality of semiconductor devices include access transistor 1212 (only partially shown) and peripheral device 1218 (only partially shown). Fig.17 As shown and described, the interconnect structure 1002 is partially formed over and electrically coupled to the semiconductor device. Fig.17 As shown and described, a through-via dielectric layer 1016 is deposited over the interconnect structure 1002 .

[0132] Also through Fig.25 The cross-sectional view 2500 shows that an additional IMD layer 1014 is deposited overlying the through-hole dielectric layer 1016 .

[0133] like Fig.26 As shown in the cross-sectional view 2600 of FIG. 26 , the through-hole dielectric layer 1016 and the additional IMD layer 1014 on top of the through-hole dielectric layer 1016 are patterned to form memory cell openings 2602 that are independent of the 1T1R cells 1202 and are respectively located at the formed 1T1R cells 1202. Note that for compactness, the lower portion of the interconnect structure 1002 and the structure located below the lower portion are omitted in this and subsequent drawings. The patterning can be performed, for example, by a photolithography / etching process or some other suitable patterning process.

[0134] like Fig. 27 As shown in the cross-sectional view 2700 of FIG. 27 , the bottom electrode layer 1802, the plurality of dielectric layers 104, the capping layer 502, and the top electrode layer 1902 are deposited to line and fill the memory cell opening 2602 (see, for example, FIG. 27 ). Fig.26 ). In an alternative embodiment, the cover layer 502 is omitted and thus not formed. In an alternative embodiment, the plurality of dielectric layers 104 includes three or more dielectric layers. The bottom electrode layer 1802, the plurality of dielectric layers 104, the cover layer 502, and the top electrode layer 1902 are as described with reference to Fig.18 and Fig.19 As described above. Therefore, the dielectric layer 104h (i.e., the HEA dielectric layer 104h) having the highest electron affinity among the plurality of dielectric layers 104 and thus closest to the bottom electrode layer 1802 is deposited first. It should be understood that arranging the HEA dielectric layer 104h closest to the bottom electrode layer 1802 reduces the possibility of the memory cell being stuck during cycling. The bottom electrode layer 1802, the plurality of dielectric layers 104, the capping layer 502, and the top electrode layer 1902 are as described above. Fig.18 and Fig.19 The above-mentioned ground is formed.

[0135] like Fig.28 As shown in the cross-sectional view 2800, the bottom electrode layer 1802 (see for example Fig. 27 ), multiple dielectric layers 104, capping layer 502 and top electrode layer 1902 (see, for example, Fig. 27 ) is performed. The planarization stops on the additional IMD layer 1014 on top of the through-hole dielectric layer 1016 and the memory cell opening 2602 (see, e.g. Fig.26 ) pattern is transferred to the bottom electrode layer 1802, multiple dielectric layers 104, the covering layer 502 and the top electrode layer 1902.

[0136] The memory cell 102 is formed by transferring the pattern and planarizing. The memory cell 102 is independent of the 1T1R cell 1202 and is located at the 1T1R cell 1202. The pattern is transferred to the bottom and top electrode layers 1802 and 1902, and the bottom and top electrode layers 1802 and 1902 are respectively divided into a bottom electrode 106 independent of the memory cell 102 and a top electrode 108 independent of the memory cell 102. The pattern is transferred to the plurality of dielectric layers 104, and the plurality of dielectric layers 104 are divided into dielectric segments independent of the memory cell 102. The pattern is transferred to the capping layer 502, and the capping layer 502 is divided into capping segments independent of the memory cell 102. After the patterning is completed, the bottom electrode 106, the dielectric segment, and the capping segment have a U-shaped profile. However, a V-shape and other suitable profiles are also possible.

[0137] Because planarization changes the pattern from Fig.26 The patterning at the memory cell 102 is transferred to the various layers of the memory cell 102, so the memory cell 102 can be formed by a single lithography / etching process. This is similar to the Figures 16 to 23 The multiple lithography / etching processes of the memory cell 102 at Fig.18 and Fig. 20 Because photolithography is expensive, reducing the number of photolithography / etching processes can significantly reduce costs.

[0138] like Fig.29 As shown in the cross-sectional view 2900, the execution Fig. 22 and Fig.23 Such as the action of Fig. 22 As shown and described, an interconnect structure 1002 is completed around the memory cell 102. Fig.23 As shown and described, conductive filaments 402 are formed in the plurality of dielectric layers 104 at the memory cells 102 , respectively, independent of the memory cells 102 .

[0139] Although the reference method describes Figure 25 to Figure 29 , it should be understood that Figure 25 to Figure 29 The structure shown is not limited to this method, but can be independently independent of this method. Figure 25 to Figure 29 Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. Figure 25 to Figure 29 Where a particular set of actions is shown and described, some of the actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0140] refer to Fig.30 , provides Figure 25 to Figure 29 Block diagram 3000 of some embodiments of the method.

[0141] At 3002, an access transistor is formed on a substrate. See, e.g. Fig.16 and Fig.25 .

[0142] At 3004, an interconnect structure is partially formed over the substrate and the access transistor, wherein the interconnect structure includes a bottom electrode line located above the access transistor and electrically coupled to the access transistor. See, e.g. Fig.17 and Fig.25 .

[0143] At 3006, a through-hole dielectric layer is formed over the interconnect structure. See, e.g. Fig.17 and Fig.25 .

[0144] At 3008, an IMD layer is formed over the through-hole dielectric layer. See, e.g. Fig.25 .

[0145] At 3010, the through-hole dielectric layer and the IMD layer are patterned to form a memory cell opening located above and exposing the bottom electrode line. See, e.g. Fig.26 .

[0146] At 3012, a bottom electrode layer is deposited, covering the IMD layer and lining the memory cell opening. See, e.g. Fig. 27 .

[0147] At 3014, a plurality of dielectric layers are deposited in a vertical stack, the plurality of dielectric layers covering the bottom electrode layer and lining the memory cell opening, wherein the dielectric layer having the highest electron affinity and closest to the bottom electrode layer is deposited first. See, e.g. Fig. 27 .

[0148] At 3016, a capping layer is deposited that covers the plurality of dielectric layers and lines the memory cell openings. See, e.g. Fig. 27 .

[0149] At 3018, a top electrode layer is deposited that covers the capping layer and lines the memory cell opening. See, e.g. Fig. 27 .

[0150] At 3020, planarization is performed on the top and bottom electrode layers, the capping layer, and the plurality of dielectric layers to form memory cells that are located above and electrically coupled to the lines in the memory cell openings. See, e.g. Fig.28 .

[0151] At 3022, an interconnect structure is completed around the memory cell. See e.g. Fig.29 .

[0152] At 3024, a forming voltage is applied across the memory cell to form a conductive filament in the plurality of dielectric layers. See, e.g. Fig.29 .

[0153] Although in this article Fig.30 The block diagram 3000 is shown and described as a series of actions or events, but it will be understood that the order in which such actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in different orders and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, all of the actions shown may not be required to implement one or more aspects or embodiments described herein, and one or more actions described herein may be performed in one or more separate actions and / or stages.

[0154] In some embodiments, the present invention provides a memory cell, comprising: a bottom electrode; a top electrode, located above the bottom electrode; and a dielectric stack, comprising a plurality of dielectric layers stacked between the bottom electrode and the top electrode; wherein the plurality of dielectric layers comprises a first dielectric layer, and the first dielectric layer is one of the plurality of dielectric layers closest to the bottom electrode and has the highest electron affinity among the plurality of dielectric layers. In some embodiments, the plurality of dielectric layers comprises a second dielectric layer located above the first dielectric layer, wherein the second dielectric layer has a different element group from the first dielectric layer. In some embodiments, the plurality of dielectric layers comprises a second dielectric layer located above the first dielectric layer, wherein the second dielectric layer has the same element group as the first dielectric layer and also has a different element ratio from the first dielectric layer. In some embodiments, the dielectric stack consists of two dielectric layers. In some embodiments, the memory cell further comprises a capping layer located above the dielectric stack, between the dielectric stack and the top electrode, wherein the capping layer has a higher affinity for oxygen than the top electrode and the bottom electrode. In some embodiments, the plurality of dielectric layers include a second dielectric layer and a third dielectric layer, wherein the second dielectric layer is located between the first dielectric layer and the third dielectric layer and has an electron affinity between the electron affinity of the first dielectric layer and the electron affinity of the third dielectric layer. In some embodiments, the plurality of dielectric layers include a second dielectric layer and a third dielectric layer, wherein the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and wherein the third dielectric layer has an electron affinity between the electron affinity of the first dielectric layer and the electron affinity of the second dielectric layer. In some embodiments, the memory cell further includes a conductive filament located in the dielectric stack, wherein the conductive filament includes an oxygen vacancy. In some embodiments, the memory cell further includes a conductive filament located in the dielectric stack, wherein the conductive filament includes a metal.

[0155] In some embodiments, the present invention provides a memory device, comprising: a memory cell, wherein the memory cell comprises: a bottom electrode; a dielectric structure located above the bottom electrode and including a plurality of different dielectric materials from top to bottom; and a top electrode located above the dielectric structure; wherein the plurality of different dielectric materials include a first dielectric material at the bottom electrode, and the first dielectric material has the lowest bottom conductive band edge among the plurality of different dielectric materials. In some embodiments, the bottom conductive band edge of the dielectric structure gradually rises from the bottom electrode to the top surface of the dielectric structure. In some embodiments, the bottom conductive band edge of the dielectric structure gradually rises from the bottom electrode to the midpoint between the bottom electrode and the top surface of the dielectric structure, and wherein the bottom conductive band edge gradually decreases from the midpoint to the top surface. In some embodiments, the memory cell further comprises: a capping layer located between the top electrode and the dielectric structure and in direct contact with the top electrode and the dielectric structure, wherein the capping layer relies on less energy to react with oxygen than the top electrode. In some embodiments, the memory device further comprises a conductive filament located in the dielectric structure, wherein the conductive filament extends from the top surface of the dielectric structure to the bottom surface of the dielectric structure and terminates before the bottom surface.

[0156] In some embodiments, the present invention provides a method comprising: depositing a bottom electrode layer over a substrate; depositing a dielectric film over and directly on the bottom electrode layer, wherein the dielectric film comprises a plurality of different dielectric layers stacked vertically, wherein the plurality of different dielectric layers comprises a first dielectric layer located at the bottom electrode layer, and wherein the first dielectric layer has the highest electron affinity among the plurality of different dielectric layers; depositing a top electrode layer over the dielectric film; and patterning the bottom electrode layer, the dielectric film, and the top electrode layer into a memory cell. In some embodiments, the method further comprises depositing a capping layer over the dielectric film, wherein the top electrode layer is deposited over the capping layer and has a lower affinity for oxygen than the capping layer. In some embodiments, the dielectric film comprises a second dielectric layer, and wherein the deposition of the dielectric film comprises: depositing the first dielectric layer by vapor deposition; and depositing the second dielectric layer over the first dielectric layer by vapor deposition, wherein the deposition of the first dielectric layer and the deposition of the second dielectric layer are performed using the same precursor set but different proportions of precursors. In some embodiments, the dielectric film includes a second dielectric layer, and wherein the deposition of the dielectric film includes: depositing the first dielectric layer by vapor deposition using a first precursor group; and depositing the second dielectric layer over the first dielectric layer by vapor deposition using a second precursor group different from the first precursor group. In some embodiments, the method further includes applying a forming voltage having a positive polarity from a top electrode of the memory cell to a bottom electrode of the memory cell to form a conductive filament in the dielectric structure separating the top electrode and the bottom electrode. In some embodiments, the electron affinity of the dielectric film decreases discretely and uninterruptedly from the bottom surface of the dielectric film to the top surface of the dielectric film.

[0157] The present invention summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a substrate to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that this equivalent configuration is not directed away from the spirit and scope of the present invention, and in the case of not directed away from the spirit and scope of the present invention, they can make multiple changes, replacements and changes herein.

Claims

1. A memory cell, comprising: Bottom electrode; a top electrode, located above the bottom electrode; as well as a dielectric stack comprising a plurality of dielectric layers stacked between the bottom electrode and the top electrode; wherein the plurality of dielectric layers include a first dielectric layer, and The first dielectric layer is one of the plurality of dielectric layers that is closest to the bottom electrode and has the highest electron affinity among the plurality of dielectric layers, Wherein, the multiple dielectric layers also include a second dielectric layer, the first dielectric layer includes a first compound having a first number of atoms of a metal element and a second number of atoms of a non-metal element, the second dielectric layer includes a second compound having a third number of atoms of a metal element and a fourth number of atoms of a non-metal element, the first number of atoms is different from the third number of atoms, and the second number of atoms is different from the fourth number of atoms.

2. The memory cell according to claim 1, wherein: The bottom electrode and the top electrode include metal, metal nitride, metal oxide, doped polysilicon, some other suitable conductive material, or any combination of the foregoing.

3. The memory cell according to claim 1, wherein: The bottom electrode includes aluminum.

4. The memory cell according to claim 1, wherein: The dielectric stack consists of two dielectric layers.

5. The memory cell according to claim 1, further comprising: A capping layer is located on the dielectric stack and between the dielectric stack and the top electrode, wherein the capping layer has a higher affinity for oxygen than the top electrode and the bottom electrode.

6. The memory cell according to claim 1, wherein: The plurality of dielectric layers includes a third dielectric layer, and wherein the second dielectric layer is located between the first dielectric layer and the third dielectric layer and has an electron affinity between an electron affinity of the first dielectric layer and an electron affinity of the third dielectric layer.

7. The memory cell according to claim 1, wherein: The plurality of dielectric layers includes a third dielectric layer, wherein the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and wherein the third dielectric layer has an electron affinity between an electron affinity of the first dielectric layer and an electron affinity of the second dielectric layer.

8. The memory cell according to claim 1, further comprising: A conductive filament is disposed in the dielectric stack, wherein the conductive filament comprises an oxygen vacancy.

9. The memory cell according to claim 1, further comprising: A conductive filament is located in the dielectric stack, wherein the conductive filament comprises metal.

10. A memory device comprising a memory cell, wherein: The memory unit comprises: Bottom electrode; a dielectric structure located above the bottom electrode and comprising a plurality of different dielectric materials from top to bottom; and a top electrode disposed on the dielectric structure; wherein the plurality of different dielectric materials include a first dielectric material located at the bottom electrode, and The first dielectric material has a lowest bottom conductive strip edge among the plurality of different dielectric materials, The plurality of different dielectric materials further include a second dielectric material, the first dielectric material including a first compound of a metal element having a first number of atoms and a second number of atoms of a non-metal element, the second dielectric material including a second compound of a metal element having a third number of atoms and a fourth number of atoms of a non-metal element, the first number of atoms being different from the third number of atoms, and the second number of atoms being different from the fourth number of atoms.

11. The memory device according to claim 10, wherein: The bottom conductive strip edge of the dielectric structure gradually rises from the bottom electrode to the top surface of the dielectric structure.

12. The memory device according to claim 10, wherein: A bottom conductive strip edge of the dielectric structure steps up from the bottom electrode to a midpoint between the bottom electrode and a top surface of the dielectric structure, and wherein the bottom conductive strip edge steps down from the midpoint to the top surface.

13. The memory device according to claim 10, wherein: The memory unit further comprises: A capping layer is located between and in direct contact with the top electrode and the dielectric structure, wherein the capping layer reacts with oxygen with less energy than the top electrode.

14. The memory device according to claim 10, further comprising: A conductive filament is located in the dielectric structure, wherein the conductive filament extends from the top surface of the dielectric structure to the bottom surface of the dielectric structure and terminates before the bottom surface.

15. A method of forming a memory cell, comprising: depositing a bottom electrode layer over the substrate; depositing a dielectric film over and directly on the bottom electrode layer, wherein the dielectric film comprises a plurality of different dielectric layers stacked vertically, wherein the plurality of different dielectric layers comprises a first dielectric layer located at the bottom electrode layer, and wherein the first dielectric layer has a highest electron affinity among the plurality of different dielectric layers; depositing a top electrode layer over the dielectric film; and patterning the bottom electrode layer, the dielectric film, and the top electrode layer into memory cells, Wherein, the multiple different dielectric layers also include a second dielectric layer, the first dielectric layer includes a first compound of a metal element having a first number of atoms and a second number of atoms of a non-metal element, the second dielectric layer includes a second compound of a metal element having a third number of atoms and a fourth number of atoms of a non-metal element, the first number of atoms is different from the third number of atoms, and the second number of atoms is different from the fourth number of atoms.

16. The method according to claim 15, further comprising: A capping layer is deposited over the dielectric film, wherein the top electrode layer is deposited over the capping layer and has a lower affinity for oxygen than the capping layer.

17. The method according to claim 15, wherein: The deposition of the dielectric film comprises: depositing the first dielectric layer by vapor deposition; and The second dielectric layer is deposited over the first dielectric layer by vapor deposition, wherein the deposition of the first dielectric layer and the deposition of the second dielectric layer are performed using the same set of precursors but different ratios of the precursors.

18. The method according to claim 15, wherein: The deposition of the dielectric film comprises: depositing the first dielectric layer by vapor deposition using a first precursor set; and The second dielectric layer is deposited over the first dielectric layer by vapor deposition using a second precursor set different from the first precursor set.

19. The method according to claim 15, further comprising: A forming voltage having a positive polarity is applied from a top electrode of the memory cell to a bottom electrode of the memory cell to form a conductive filament in a dielectric structure separating the top electrode and the bottom electrode.

20. The method according to claim 15, wherein: The electron affinity of the dielectric film decreases discretely and continuously from a bottom surface of the dielectric film to a top surface of the dielectric film.

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