RF amplifier with input-side fractional harmonic resonator circuit

Abstract

This invention relates to an RF amplifier having an input-side fractional harmonic resonator circuit. An RF amplifier includes a transistor, an input impedance matching circuit (e.g., a single-segment T-matching circuit and a multi-segment bandpass circuit), and a fractional harmonic resonator circuit. The input impedance matching circuit is coupled between an amplification path input and a transistor input. The input of the fractional harmonic resonator circuit is coupled to the amplification path input, and the output of the fractional harmonic resonator circuit is coupled to the transistor input. The fractional harmonic resonator circuit is configured to resonate at a resonant frequency between the fundamental operating frequency of the RF amplifier and a second harmonic of the fundamental frequency. According to another embodiment, the fractional harmonic resonator circuit resonates at a fraction x of the fundamental frequency, wherein the fraction is between about 1.25 and about 1.9 (e.g., x ≈ 1.5).

Description

Technical Field

[0001] The embodiments of the subject matter described herein generally relate to radio frequency (RF) amplifiers, and more specifically, to broadband power amplifier devices and packaging devices. Background Technology

[0002] Wireless communication systems employ power amplifiers to amplify the power of radio frequency (RF) signals. For example, in a cellular base station, a Doherty power amplifier can form part of the final amplification stage in the transmission chain before the amplified signal is provided to the antenna for radiation through the air interface. High gain, high linearity, stability, and high levels of power-added efficiency are desirable characteristics of power amplifiers in such wireless communication systems.

[0003] In the field of power amplifier device design, achieving concurrent multi-band, broadband amplification is becoming increasingly desirable. For example, to successfully design a broadband power amplifier device for concurrent multi-band, broadband operation in a Dougherty power amplifier circuit, it is desirable to achieve good broadband fundamental matching (e.g., more than 20% fractional bandwidth) to properly handle harmonic frequency interactions, while also achieving a wide video bandwidth. However, achieving these goals continues to present challenges for power amplifier device designers. Summary of the Invention

[0004] According to one aspect of the present invention, a radio frequency (RF) amplifier is provided, comprising: a transistor having a transistor input terminal; an input impedance matching circuit coupled between a first input of a first amplification path and the transistor input terminal; and a fractional harmonic resonator circuit having an input and an output, wherein the input of the fractional harmonic resonator circuit is coupled to the first input of the first amplification path, wherein the output of the fractional harmonic resonator circuit is coupled to the transistor input terminal, and wherein the fractional harmonic resonator circuit is configured to resonate at a resonant frequency between the fundamental operating frequency of the RF amplifier and a second harmonic of the fundamental frequency.

[0005] According to one or more embodiments, the fractional harmonic resonator circuit resonates at a fraction x of the fundamental frequency, wherein the fraction is between 1.25 and 1.9.

[0006] According to one or more embodiments, the score is between 1.4 and 1.6.

[0007] According to one or more embodiments, the fractional harmonic resonator circuit is a parallel inductor / capacitor (LC) circuit, the parallel inductor / capacitor circuit comprising: a first inductor having a first terminal electrically connected to the first input and a second terminal electrically connected to the transistor input; and a first capacitor connected in parallel with the first inductor.

[0008] According to one or more embodiments, the fractional harmonic resonator circuit is coupled within the input impedance matching circuit.

[0009] According to one or more embodiments, the input impedance matching circuit has a single-segment T-matching topology, the single-segment T-matching topology including: a first connection node; a second connection node; a second capacitor coupled between the first connection node and the ground reference node; and a second inductor coupled between the second connection node and the transistor input terminal, wherein the fractional harmonic resonator circuit is electrically coupled between the first connection node and the second connection node.

[0010] According to one or more embodiments, the RF amplifier further includes:

[0011] A third inductor element is coupled between the first input and the first connection node.

[0012] According to one or more embodiments, the third inductor element includes a first plurality of bonding wires connected between the first input and the first connection node; and the second inductor element includes a second plurality of bonding wires connected between the second connection node and the transistor input terminal.

[0013] According to one or more embodiments, the input impedance matching circuit has a multi-segment bandpass topology, the multi-segment bandpass topology including: a first connection node; a second connection node; a third connection node; a second inductor coupled between the first connection node and a ground reference node; a second capacitor coupled between the first connection node and the second connection node; a third capacitor coupled between the second connection node and the ground reference node; and a third inductor coupled between the third connection node and the transistor input terminal, wherein the fractional harmonic resonator circuit is electrically coupled between the second connection node and the third connection node.

[0014] According to one or more embodiments, the RF amplifier further includes a fourth inductor element coupled between the first input and the first connection node.

[0015] According to one or more embodiments, the fourth inductor element includes a first plurality of bonding wires connected between the first input and the first connection node; and the third inductor element includes a second plurality of bonding wires connected between the third connection node and the transistor input terminal.

[0016] According to one or more embodiments, the input circuit further includes: a resistor coupled in parallel with the second capacitor between the first connection node and the second connection node; and a DC blocking capacitor coupled in series with the second inductor between the first connection node and the ground reference node.

[0017] According to one or more embodiments, the RF amplifier further includes: a baseband termination circuit coupled between the input impedance matching circuit and a ground reference node, wherein the baseband termination circuit includes a plurality of components, wherein the plurality of components include an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the input impedance matching circuit and the ground reference node.

[0018] According to one or more embodiments, the RF amplifier is a Dougherty power amplifier, the RF amplifier further comprising: a second amplification path; a power divider having a power divider input configured to receive an RF signal, a first output coupled to the first input of the first amplification path, and a second output coupled to a second input of the second amplification path, wherein the power divider is configured to split the RF signal into a first RF signal provided to the first amplification path via the first output and a second RF signal provided to the second amplification path via the second output; and

[0019] A combining node configured to receive and combine amplified RF signals generated by the first amplification path and the second amplification path.

[0020] According to another aspect of the present invention, a packaged radio frequency (RF) amplifier device is provided, comprising: a device substrate; an input lead coupled to the device substrate; an output lead coupled to the device substrate; a transistor die coupled to the device substrate, wherein the transistor die includes a transistor, a transistor input terminal, and a transistor output terminal coupled to the output lead; an input impedance matching circuit coupled between the input lead and the transistor input terminal; and a fractional harmonic resonator circuit having an input and an output, wherein the input of the fractional harmonic resonator circuit is coupled to the input lead, wherein the output of the fractional harmonic resonator circuit is coupled to the transistor input terminal, and wherein the fractional harmonic resonator circuit is configured to resonate at a resonant frequency of a fraction x as a fundamental frequency, wherein the fraction is between 1.25 and 1.9.

[0021] According to one or more embodiments, the fractional harmonic resonator circuit is a parallel inductor / capacitor (LC) circuit, the parallel inductor / capacitor circuit comprising: a first inductor having a first terminal electrically connected to the first input and a second terminal electrically connected to the transistor input; and a first capacitor connected in parallel with the first inductor.

[0022] According to one or more embodiments, the input impedance matching circuit has a single-segment T-matching topology, the single-segment T-matching topology including: a first connection node; a second connection node; a second capacitor coupled between the first connection node and the ground reference node; and a second inductor coupled between the second connection node and the transistor input terminal, wherein the fractional harmonic resonator circuit is electrically coupled between the first connection node and the second connection node.

[0023] According to one or more embodiments, the packaged RF amplifier device further includes: an integrated passive device assembly coupled to the device substrate, wherein the first connection node and the second connection node, the fractional harmonic resonator circuit, and the second capacitor form a portion of the integrated passive device assembly.

[0024] According to one or more embodiments, the input impedance matching circuit has a multi-segment bandpass topology, the multi-segment bandpass topology including: a first connection node; a second connection node; a third connection node; a second inductor coupled between the first connection node and a ground reference node; a second capacitor coupled between the first connection node and the second connection node; a third capacitor coupled between the second connection node and the ground reference node; and a third inductor coupled between the third connection node and the transistor input terminal, wherein the fractional harmonic resonator circuit is electrically coupled between the second connection node and the third connection node.

[0025] According to one or more embodiments, an integrated passive device assembly is included, the integrated passive device assembly being coupled to the device substrate, wherein the first connection node, the second connection node, the third connection node, the fractional harmonic resonator circuit, the second inductor element, the second capacitor, and the third capacitor form a portion of the integrated passive device assembly. Attached Figure Description

[0026] A more complete understanding of the subject matter can be derived by referring to the detailed embodiments and claims when considered in conjunction with the following figures, wherein the same reference numerals refer to similar elements throughout the figures.

[0027] Figure 1 This is a schematic circuit diagram of a power amplifier circuit with a single-segment input T-matched topology and a fractional harmonic resonator, according to one or more example embodiments.

[0028] Figure 2 This is a schematic circuit diagram of a power amplifier circuit with a two-stage input bandpass topology and a fractional harmonic resonator, according to one or more other example embodiments.

[0029] Figure 3A , 3B Figures 3C, 3D, 3E, and 3F illustrate various example embodiments of the baseband termination circuit;

[0030] Figure 4 This is a simplified schematic diagram of a Dougherty power amplifier according to one or more example embodiments;

[0031] Figure 5 This is a top view of a packaged RF power amplifier device including two parallel amplification paths according to one or more example embodiments;

[0032] Figure 6This is a top view of a packaged RF power amplifier device including a portion of a power transistor and an input impedance matching circuit according to one or more example embodiments;

[0033] Figure 7 It is a cut along line 7-7 based on one or more example embodiments. Figure 6 A cross-sectional side view of a portion of an RF power amplifier device;

[0034] Figure 8 This is a top view of a packaged RF power amplifier device including a portion of a power transistor and an input impedance matching circuit according to one or more other example embodiments;

[0035] Figure 9 It is a cut along line 9-9 based on one or more example embodiments. Figure 8 A cross-sectional side view of a portion of an RF power amplifier device; and

[0036] Figure 10 This is a flowchart of a method for manufacturing a packaged RF power amplifier device including an input impedance matching circuit, according to one or more example embodiments. Detailed Implementation

[0037] In the field of high-power radio frequency (RF) power amplification for cellular base stations and other applications (e.g., where "RF" in this application includes frequencies in the range of 1 MHz to 100 GHz), broadband power amplification using silicon-based devices (e.g., laterally diffused metal-oxide-semiconductor (LDMOS) power transistor devices with output matching networks) has been successfully achieved. However, such silicon-based devices exhibit relatively low efficiency and power density compared to gallium nitride (GaN)-based power amplifier devices. Therefore, GaN-based power amplifier devices are increasingly being considered for high-power broadband applications. However, achieving broadband power amplification (e.g., fractional bandwidth exceeding 20%, where "fractional bandwidth" is the amplifier's bandwidth divided by its center operating frequency) using GaN technology presents challenges.

[0038] For example, it is known that the nonlinear input capacitance of RF power devices, including GaN transistors (e.g., GaN field-effect transistors (FETs)), generates harmonic and intermodulation distortions that can impair efficiency and linearity. Additionally, the source second harmonic impedance can significantly affect drain efficiency. Without information about the second harmonic impedance at the current source termination plane, it is very difficult to tune the power amplifier (e.g., using digital predistortion or DPD) to achieve a relatively high fractional bandwidth with good performance (e.g., high efficiency and linearity).

[0039] To overcome these and other challenges in designing broadband power amplifiers (including those using GaN-based devices), the embodiments disclosed herein can achieve broadband input impedance matching at the fundamental frequency f0 using an input-side impedance matching circuit with a single-segment T-matching topology or a multi-segment (e.g., two-segment) bandpass topology. Additionally, to generate a low-impedance condition (simulating a short circuit) near the second harmonic frequency 2f0, a fractional harmonic resonator circuit (also simply referred to as a "harmonic resonator") is added near the input of the RF power device. According to various embodiments, the harmonic resonator is "fractional" because it resonates at a fractional frequency of harmonic frequencies below the second harmonic frequency band but above the fundamental frequency band (i.e., the harmonic resonator resonates at a frequency between the fundamental frequency and the second harmonic frequency).

[0040] According to embodiments, the fractional harmonic resonator circuit is a parallel inductor-capacitor (LC) resonator circuit. For example, some specific embodiments of the subject matter of this invention include a fractional harmonic resonator comprising a capacitor (e.g., an integrated metal-insulator-metal (MIM) capacitor) and an inductor (e.g., in the form of a bonded wire array or an integrated spiral inductor) coupled in parallel between the amplifier input and the input (e.g., the gate terminal) of the RF power device. The fractional harmonic resonator can be placed within an input-side impedance matching circuit (e.g., including T-matching topologies and bandpass topologies). The component values ​​of the fractional harmonic resonator are chosen such that below the resonant frequency of the fractional harmonic resonator, the fractional harmonic resonator will simulate an inductor, making the input matching circuit topology appear as a typical matching circuit (e.g., a T-matching topology) in the fundamental frequency band. However, in the second harmonic band, the fractional harmonic resonator will simulate a capacitor, which, when properly designed, can provide a low-impedance termination at the input of the RF power device. The fractional harmonic resonator embodiments described herein can be used to control the second harmonic impedance across a wide (e.g., over 20%) fractional bandwidth with relatively low impedance (e.g., near short circuit). This can be useful for achieving relatively high efficiency in broadband applications.

[0041] Figure 1 This is a schematic diagram of an RF power amplifier circuit 100 having a single-stage input T-matching topology 110 and a fractional harmonic resonator (FHR) circuit 130, according to an example embodiment. In this embodiment, the amplifier circuit 100 includes an input 102 (e.g., a first conductive package lead), an input impedance matching circuit 110, an FHR circuit 130, a transistor 140, an output impedance matching circuit 150, and an output 104 (e.g., a second conductive package lead). Each of the inputs 102 and the outputs 104 may be more generally referred to as an "RF input / output (I / O)".

[0042] The input impedance matching circuit 110 and the FHR circuit 130 can be collectively referred to as the "input circuit". Similarly, the output impedance matching circuit 150 can be referred to as the "output circuit". (The last sentence appears to be incomplete and possibly refers to a different circuit.) Figure 5-7 In more detail, many of the components that make up the input impedance matching circuit 110 and the FHR circuit 130, and specifically those components covered by the dashed box 180, may be included in the integrated passive device (IPD) (such as...). Figure 5-7 In and / or on IPD 580, 581, or on another type of substrate (e.g., small PCB or other types of substrate).

[0043] Although the individual elements of transistor 140, input impedance matching circuit 110, output impedance matching circuit 150, and FHR circuit 130 are shown as singular components, this depiction is for ease of explanation only. Based on the description herein, those skilled in the art will understand that certain elements of transistor 140 and / or input impedance matching circuit 110, FHR circuit 130, and output impedance matching circuit 150 may each be implemented as multiple components (e.g., connected in parallel or series with each other). Therefore, the following description of the individual elements of transistor 140 and input impedance matching circuit 110, FHR circuit 130, and output impedance matching circuit 150 is not intended to limit the scope of the invention to the illustrated embodiments.

[0044] Input 102 and output 104 may each include a conductor configured to electrically couple amplifier circuit 100 to an external circuitry (not shown). More specifically, in this embodiment, input 102 and output 104 are physically positioned across the exterior and interior of the device package. Input impedance matching circuitry 110 and FHR circuitry 130 are electrically coupled between input 102 and a first terminal 142 (e.g., gate terminal) of transistor 140. Similarly, output impedance matching circuitry 150 is electrically coupled between a second terminal 144 (e.g., drain terminal) of transistor 140 and output 104. A third terminal 145 (e.g., source terminal) of transistor 140 is coupled to a ground reference node.

[0045] According to an embodiment, transistor 140 is the primary active component of amplifier circuit 100. Transistor 140 includes a control terminal 142 and two current conduction terminals 144 and 145, wherein the current conduction terminals 144 and 145 are spatially and electrically separated by a variable conductivity channel. For example, transistor 140 may be a field-effect transistor (FET) including a gate terminal (control terminal 142), a drain terminal (first current conduction terminal 144), and a source terminal (second current conduction terminal 145). According to an embodiment and using the nomenclature generally applied to FETs in a non-limiting manner, the input terminal 142 of transistor 140 is coupled to input impedance matching circuit 110 and FHR circuit 130, the drain terminal 144 of transistor 140 is coupled to output impedance matching circuit 150, and the source terminal 145 of transistor 140 is coupled to ground (or another voltage reference). The current between the current conduction terminals of transistor 140 can be modulated by changing the control signal provided to the gate terminal of transistor 140.

[0046] According to various embodiments, transistor 140 is a III-V field-effect transistor (e.g., a high electron mobility transistor (HEMT)) that has a relatively low drain-source capacitance Cds compared to a silicon-based FET (e.g., an LDMOS FET). For example, in some embodiments, transistor 140 may be a GaN FET, but in other embodiments, transistor 140 may be another type of III-V transistor (e.g., gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), or indium antimonide (InSb)) or another type of transistor with a relatively low drain-source capacitance. Figure 1 In this document, the drain-source capacitance of transistor 140 is represented by a parallel capacitor 146 connected between the drain terminal of transistor 140 and the output terminal 144 of transistor 140. Based on the description herein, those skilled in the art will understand that capacitor 146 is not a physical component, but rather a model of the drain-source capacitance of transistor 140. According to embodiments, the drain-source capacitance of transistor 140 may be less than approximately 0.2 picofarads per watt (pF / W).

[0047] As described above, the input impedance matching circuit 110 and the FHR circuit 130 are electrically coupled between the input 102 and the input terminal 142 (e.g., the gate terminal) of the transistor 140. The input impedance matching circuit 110 is configured to transform (e.g., raise) the gate impedance of the transistor 140 at node 102 to a higher (e.g., intermediate or higher) impedance level (e.g., in the range of about 2 ohms to about 10 ohms or higher). This is advantageous because it allows the printed circuit board (PCB) level matching interface from the driver stage to have an impedance that can be achieved in high-volume manufacturing with minimal loss and variation (e.g., a “user-friendly” matching interface).

[0048] According to an embodiment, the input impedance matching circuit 110 is a single-segment T-matching circuit, which includes a first inductor 112, a parallel capacitor 114, and a second inductor 116. For example... Figure 1 As shown, the FHR circuit 130, which will be described in more detail later, is implemented within the input impedance matching circuit 110, and more specifically between the first inductor element 112 and the second inductor element 116.

[0049] In the input impedance matching circuit 110, a first inductor 112 (e.g., a first set of bond wires) is coupled between input 102 and node 113 (also referred to as the "connection node"). More specifically, a first end of inductor 112 (e.g., a first end of the first set of bond wires) is connected to input 102, and a second end of inductor 112 (e.g., a second end of the first set of bond wires) is connected to node 113. A second inductor 116 (e.g., a second set of bond wires) is coupled between node 113 and input terminal 142 of transistor 140. More specifically, a first end of inductor 116 (e.g., a first end of the second set of bond wires) is (indirectly) coupled to node 113, and a second end of inductor 116 (e.g., a second end of the second set of bond wires) is connected to control terminal 142. Finally, a parallel capacitor 114 is coupled between node 113 and ground (or another voltage reference). More specifically, the first end of the parallel capacitor 114 is coupled to node 113, and the second end of the parallel capacitor 114 is coupled to ground.

[0050] Figure 1 The input impedance matching circuit 110 described in the figure is a single-stage T-matching circuit. However, as mentioned above, in alternative embodiments, the single-stage T-matching circuit can be replaced by an impedance matching circuit in the form of a two-stage bandpass circuit. For example, Figure 2 This is a schematic circuit diagram of a power amplifier circuit 200 according to another example embodiment, having an impedance matching circuit in the form of a two-stage bandpass circuit 210 and a fractional harmonic resonator (FHR) circuit 130. To a certain extent, Figure 1 and 2 The various components are substantially similar or identical, and these references utilize the same reference numerals. For the sake of brevity, in Figure 2 In the context of the description, descriptions of substantially similar or identical elements are not repeated (i.e., in...). Figure 1 and 2 (those elements with the same reference numerals in the figures), but these descriptions are intended to be incorporated into the following... Figure 2 The description.

[0051] Essentially, amplifier circuit 100 ( Figure 1) and amplifier circuit 200 ( Figure 2 The differences between them can be found in the input impedance matching circuits 110 and 210. According to... Figure 2 In the illustrated embodiment, the input impedance matching circuit 210 has a two-stage bandpass filter configuration, which includes a first series inductor 112, a series capacitor 220, a second series inductor 116, a parallel inductor 218, and a parallel capacitor 114. According to the embodiment, the series inductor 116 and the parallel capacitor 114 form a low-pass filter in the bandpass filter configuration, and the parallel inductor 218 and the series capacitor 220 form a high-pass filter in the bandpass filter configuration. This bandpass configuration allows for wideband operation at RF frequencies, which is not easily achieved using simpler matching networks.

[0052] like Figure 2 As shown, the FHR circuit 130 described previously in conjunction with 1 is implemented within the input impedance matching circuit 210. More specifically, the FHR circuit 130 is coupled between the first inductor element 112 and the second inductor element 116, and even more specifically, the FHR circuit 130 is connected between the second terminal of the series capacitor 220 and the first terminal of the second series inductor element 116 (i.e., between nodes 113 and 115).

[0053] Furthermore, the input impedance matching circuit 210 and the FHR circuit 130 can be collectively referred to as the "input circuit". (The last sentence appears to be incomplete and possibly refers to a different topic.) Figure 5 , 8 As described in more detail in section 9, many of the components that make up the input impedance matching circuit 210 and the FHR circuit 130, and specifically those components covered by the dashed box 280, may be included in the IPD assembly (such as... Figure 5 , 8 In and / or on IPD assemblies 580', 581' in 9, or in and / or on another type of substrate.

[0054] In the input impedance matching circuit 210, a first inductor 112 (e.g., a first set of bond wires) is coupled between input 102 and node 213. More specifically, a first end of inductor 112 (e.g., a first end of the first set of bond wires) is connected to input 102, and a second end of inductor 112 (e.g., a second end of the first set of bond wires) is connected to node 213. A series capacitor 220 is coupled between node 213 and node 113. More specifically, a first end of series capacitor 220 is coupled to node 213, and a second end of series capacitor 220 is coupled to node 113. A second inductor 116 (e.g., a second set of bond wires) is coupled between node 113 and input terminal 142 of transistor 140. More specifically, a first end of inductor 116 (e.g., a first end of the second set of bond wires) (e.g., indirectly) is coupled to node 113, and a second end of inductor 116 (e.g., a second end of the second set of bond wires) is connected to control terminal 142. A parallel inductor 218 is coupled between node 213 and ground (or another voltage reference). More specifically, a first end of the parallel inductor 218 is coupled to node 213, and a second end of the parallel inductor 218 is coupled to ground. Finally, a parallel capacitor 114 is coupled between node 113 and ground (or another voltage reference). More specifically, a first end of the parallel capacitor 114 is coupled to node 113, and a second end of the parallel capacitor 114 is coupled to ground.

[0055] According to an embodiment, in the two input matching networks 110 and 210, the inductance value of inductor 112 can be in the range of approximately 150 picrohenries (pH) to approximately 500 pH, the inductance value of inductor 116 can be in the range of approximately 50 pH to approximately 250 pH, and the capacitance value of parallel capacitor 114 can be in the range of approximately 10 picofarads (pF) to approximately 200 pF. Finally, in input matching network 210, the capacitance value of series capacitor 220 can be in the range of approximately 10 pF to approximately 100 pF. In other embodiments, the component values ​​of some or all of the above components can be less than or greater than the ranges given above.

[0056] Desiredly, the parallel capacitor 114 has a relatively large capacitance (e.g., greater than about 60 pF) to provide an RF low-impedance point at node 113 (e.g., to provide an “RF cold point” or “pseudo-RF cold point” at node 113). In other words, node 113 represents a low-impedance point in the circuit for RF signals. According to embodiments, amplifier circuits 100, 200 also include an input-side baseband termination (BBT) circuit 160 coupled between node 113 (e.g., at or coupled to node 113) and a ground reference node. The input-side baseband termination circuit 160, which may be located in the same device package as transistor 140 (and is therefore considered as a baseband termination circuit within the package), can be used to improve the low-frequency resonance (LFR) of amplifier circuits 100, 200 caused by the interaction between the input matching circuits 110, 210 and the bias feed (e.g., bias feed 191, described later) by presenting low impedance at the envelope frequency and / or high impedance at the RF frequency. From an RF matching perspective, the input-side baseband termination circuit 160 can essentially be considered "invisible" because it primarily provides impedance at the envelope frequency (i.e., the baseband termination circuit 160 provides termination for the envelope frequencies of amplifier circuits 100 and 200). As will be discussed later... Figures 3A-3F In more detail, in various embodiments, the input-side baseband termination circuit 160 may have any of a variety of different circuit configurations. In other embodiments, as shown by the dashed connection between node 113 and baseband termination circuit 160, the input-side baseband termination circuit 160 may be excluded from amplifier circuits 100, 200.

[0057] refer to Figure 1 and 2 Both, and as previously stated, each of the amplifier circuits 100 and 200 includes a fractional harmonic resonator (FHR) circuit 130 coupled between input 102 and control terminal 142 of transistor 140. Figure 1 and 2 In the illustrated embodiment, the FHR circuit 130 is coupled between node 113 and the control terminal 142 of the transistor, and more specifically, between node 113 and node 115 (or the first terminal of inductor 116). Node 113 can be considered as an "input" or "input terminal" of the FHR circuit 130, and node 115 can be considered as an "output" or "output terminal" of the FHR circuit 130. Figure 1 and 2 In this embodiment, the FHR circuit 130 is positioned "within" the input impedance matching circuits 110, 210, meaning that components of the input impedance matching circuits 110, 210 are coupled to both the input and output of the FHR circuit 130. More specifically, in Figure 1In this circuit, capacitor 114 is coupled to the input (node ​​113) of FHR circuit 130, and inductor 116 is coupled to the output (node ​​115) of FHR circuit 130. Similarly, in Figure 2 In the process, capacitors 114 and 220 are coupled to the input (node ​​113) of FHR circuit 130, and inductor 116 is coupled to the output (node ​​115) of FHR circuit 130.

[0058] The FHR circuit 130 includes an inductor 132 (e.g., a third set of bond wires or an integrated spiral inductor) and a capacitor 134 coupled in parallel between nodes 113 and 115, wherein node 115 is coupled to the control terminal 142 of transistor 140 via inductor 116. The inductance and capacitance values ​​of inductor 132 and capacitor 134 are selected such that the parallel combination of inductor 132 and capacitor 134 produces a high impedance condition (simulating a short circuit) between the fundamental frequency f0 and the second harmonic frequency 2f0, and a low impedance condition close to 2f0. More specifically, the inductance and capacitance values ​​of inductor 132 and capacitor 134 are selected such that the FHR circuit 130 resonates at a resonant frequency fr below the second harmonic frequency band but above the fundamental frequency band (i.e., the harmonic resonator resonates at a resonant frequency between the fundamental frequency and the second harmonic frequency). In other words, the FHR circuit 130 resonates at a resonant frequency fr that is a fraction x of the fundamental frequency f0, wherein the fraction is greater than 1 but less than 2. In other words, the fraction x is an improper fraction between 1 and 2. For example, but not by any limitation, the FHR circuit 130 can resonate at a resonant frequency fr within a first range between about 1.25f0 and about 1.9f0 (i.e., 1.25 ≤ x ≤ 1.9) or within a second range between about 1.4f0 and about 1.6f0 (i.e., 1.4 ≤ x ≤ 1.6). In some embodiments, the FHR circuit 130 can resonate at a resonant frequency fr of about 1.5f0 (i.e., x ≈ 1.5). According to an embodiment, the inductance value (L) of the inductor element 132 is... 132 ) and the capacitance value of capacitor 134 (C 134 The following equation can be used to select:

[0059]

[0060] Where x is a fraction of the fundamental frequency f0, the FHR circuit 130 is designed to resonate at the fundamental frequency (i.e., fr = xf0).

[0061] As a non-limiting example, when the FHR circuit 130 is designed to resonate at a frequency of 1.5f0 (i.e., x = 1.5) and the fundamental operating frequency is 2.0 GHz (its second harmonic is at 4.0 GHz), the inductance value of inductor 132 can be about 141 pH, and the capacitance value of capacitor 134 can be about 20 pF. In other embodiments, the fundamental frequency can be lower or higher than 2.0 GHz, and the fraction x of the fundamental frequency at which the FHR circuit 130 is designed to resonate can be less than or greater than 1.5. In such cases, the inductance value of inductor 132 and the capacitance value of capacitor 134 will be selected to have appropriately different values. According to embodiments, the inductance value of inductor 132 can be in the range of about 20 pH to about 1 nanohenry (nH), and the capacitance value of capacitor 134 can be in the range of about 1 pF to about 300 pF, but the values ​​of these components can also be outside these ranges.

[0062] As previously described, the FHR circuit 130 is designed to resonate at a frequency fr higher than the fundamental frequency f0 and lower than the second harmonic frequency 2f0. The FHR circuit 130, comprising the parallel-coupled inductor 132 and capacitor 134, will generate a high impedance between nodes 113 and 115 when resonating at fr. Therefore, the control terminal 142 (e.g., the gate terminal) of transistor 140 will terminate with a high impedance at frequency fr. At frequencies just above fr, the FHR circuit 130 will behave like a capacitor, and the control terminal 142 of transistor 140 will terminate with a negative reactance. In passive lossless networks, reactance tends to increase with frequency, which will ensure that the reactance seen at control terminal 142 at 2f0 will be higher than that at fr. Since the reactance at the terminating control terminal 142 is just negative above fr and will be even higher at 2f0, a near-zero reactance value (i.e., simulating a short circuit) can be achieved at control terminal 142 at 2f0 when properly designed. Even with losses in the circuit elements at RF frequencies, low impedance (i.e., impedance close to that of a short circuit compared to the device's Ropt) can be achieved. This 2f0 termination is desirable for efficient operation.

[0063] In embodiments, each amplifier circuit in amplifier circuits 100, 200 (as shown by the dashed bias feed 191) may optionally include a gate bias circuit 190 coupled to node 113, which may act as a second (outside the package) baseband termination circuit substantially coupled in parallel with the first baseband termination circuit 160. A drain bias circuit (not shown) configured in a similar (or different) manner may be coupled to the output 144 of transistor 140. The bias circuit 190 includes a bias feed 191 (e.g., a microstrip line), a series-coupled inductor element 192 (e.g., with...). Figure 5 The bias lead 592 is series coupled. Figure 6 One or more bonding lines 692) and capacitor 196, wherein an intermediate node 193 is located between the inductor / capacitor combination. According to an embodiment, the inductance value of the inductor element 192 can be in the range of about 1500 pH to about 2500 pH, and the capacitance value of the capacitor 196 can be in the range of about 8,000 nanofarads (nF) to about 12,000 nF, but the inductance and / or capacitance values ​​can also be lower or higher.

[0064] To provide a gate bias voltage to input 142 of transistor 140, an external bias circuit (not shown) can be connected to node 193 (e.g., the distal end of a bias lead), and the bias voltage can be provided through this node. A drain bias voltage can be provided to node 158 in a similar manner through an output-side bias circuit (not shown). In other embodiments, either or both of the input-side or output-side bias circuits may be omitted. In such other embodiments, instead, an external bias circuit can be connected to input 102 or output 104, and one or more bias voltages can be provided through input 102 and / or output 104.

[0065] refer to Figure 2 In an embodiment where gate bias is provided via input 102 instead of gate bias circuit 190, circuit 200 may further include a resistor 122 coupled in parallel with capacitor 220 between nodes 213 and 113, and a DC blocking capacitor 219 connected in series with inductor 218. When resistor 222 and DC blocking capacitor 219 are included, each is configured to provide high impedance at RF frequencies. According to embodiments, the resistance value of resistor 222 may be in the range of about 50 ohms to about 150 ohms, the inductance value of inductor 218 may be in the range of about 100 pH to about 350 pH, and the capacitance value of DC blocking capacitor 219 may be in the range of about 50 pF to about 300 pF, but the resistance and capacitance values ​​of these components may also be lower or higher. Although Figure 2 The third inductor 218 and the DC blocking capacitor 219 are shown in a specific series arrangement (e.g., the third inductor 218 is directly connected to node 213), but in other embodiments, the order of the third inductor 218 and the DC blocking capacitor 219 may be reversed (e.g., the DC blocking capacitor 219 is directly connected to node 213, and the third inductor 218 is coupled between the DC blocking capacitor 219 and ground). Again, and as indicated by the dashed lines depicting the resistor 222 and the DC blocking capacitor 219, the resistor 222 and the DC blocking capacitor 219 may be excluded from circuit 200, for example, in embodiments where a gate bias voltage is provided via the gate bias circuit 190.

[0066] On the output side of amplifier circuits 100 and 200, an output impedance matching circuit 150 is coupled between the first current-conducting terminal 144 (e.g., the drain terminal) of transistor 140 and output 104. The output impedance matching circuit 150 is configured to match the output impedance of amplifier circuits 100 and 200 with the input impedance of external circuitry or components (not shown) that can be coupled to output 104. The output impedance matching circuit 150 can have any of a variety of different circuit configurations, and Figure 1 , 2 Only one example is shown. More specifically, in Figure 1 , 2 In the non-limiting example shown, the output impedance matching circuit 150 includes two inductor elements 152 and 154 and a parallel capacitor 156. The first inductor element 152 (e.g., a fourth set of bond wires) is coupled between a first current-conducting terminal 144 (e.g., the drain terminal) of transistor 140 and output 104. In an embodiment, the second inductor element 154 (e.g., a fifth set of bond wires) is coupled between the first current-conducting terminal 144 of transistor 140 and node 158, which corresponds to another RF low-impedance point. In an embodiment, a second terminal of the parallel capacitor 156 is coupled to ground (or another voltage reference).

[0067] Secondly, RF low impedance point 158 ​​represents the low impedance point in the circuit used for RF signals. According to an embodiment, another (output-side) baseband termination (BBT) circuit 162 is coupled between RF low impedance point 158 ​​and the ground reference node. Again, baseband termination circuit 162 can be used to further improve the LFR of amplifier circuits 100, 200 caused by the interaction between the output impedance matching circuit 150 and the bias feed (not shown) by presenting low impedance at the envelope frequency and / or high impedance at the RF frequency. From an RF matching perspective, baseband termination circuit 162 can also be considered "invisible".

[0068] As now, we will combine Figures 3A-3F As described, in the various embodiments, the baseband termination circuits 160, 162 can have any of a variety of different circuit configurations. For example, Figures 3A-3F The baseband termination circuit is shown (e.g., Figure 1 , 2 Six example embodiments of the baseband termination circuits 160, 162). Figures 3A-3F In each of the figures, baseband termination circuits 300, 301, 302, 303, 304, and 305 are coupled to connection node 313 (e.g., Figure 1 , 2Between node 113 and / or node 158 and ground (or another voltage reference). Additionally, each baseband termination circuit 300-305 includes an envelope inductor 362L series coupled between node 313 and ground. env Envelope resistor 364R env Envelope capacitor 366C env .exist Figures 3A-3E In each diagram, the first end of the envelope inductor 362 is coupled to node 313, and the second end of the envelope inductor 362 is coupled to node 380. The first end of the envelope resistor 364 is coupled to node 380, and the second end of the envelope resistor 364 is coupled to node 382. The first end of the envelope capacitor 366 is coupled to node 382, ​​and the second end of the envelope capacitor 366 is coupled to ground (or another voltage reference). Although in Figures 3A-3E In this embodiment, the order of the components between node 313 and the ground reference node is envelope inductor 362, envelope resistor 364, and envelope capacitor 366; however, in other embodiments, the order of components in the series circuit may be different. For example, in Figure 3F In the above, the envelope resistor 364 is coupled between node 313 and node 384, the envelope inductor 362 is coupled between node 384 and node 386, and the envelope capacitor 366 is coupled between node 386 and ground (or another voltage reference).

[0069] refer to Figures 3A-3F Furthermore, according to an embodiment, the envelope inductor 362 can be implemented as an integrated inductor (e.g., Figure 6 , 8 The inductor 662), implemented as a discrete inductor and / or implemented as a set of bond wires coupling connection node 313 to envelope resistor 364 (e.g., through node 380). For example, and as will be described in detail later, envelope inductor 362 may be integrally formed as an IPD (such as...). Figure 5-9 This is a portion of IPDs 580, 580', 581, 581'. For example, the inductance value of the envelope inductor 362 can be in the range of about 5 pH to about 2000 pH. Desiredly, the inductance value of the envelope inductor 362 is less than about 500 pH (e.g., as low as 50 pH or possibly even lower in this embodiment). In other embodiments, the value of the envelope inductor 362 can be lower or higher than the range given above.

[0070] In an embodiment, the envelope resistor 364 can be implemented as an integrated resistor (e.g., Figure 6 , 8 Resistor 664) or in another embodiment, is implemented as a discrete resistor. For example, envelope resistor 364 can be integrally formed as an IPD (such as...). Figure 5-9This is part of IPDs 580, 580', 581, and 581'. In some instances, the envelope capacitor 366 and envelope inductor 362 may provide additional parasitic resistance, which may be considered as part of the overall resistance forming the envelope resistor 364. In embodiments, the resistance value of the envelope resistor 364 may be in the range of about 0.1 ohms to about 5.0 ohms, but the resistance value of the envelope resistor 364 may also be outside this range.

[0071] In an embodiment, the envelope capacitor 366 can be implemented as an integrated capacitor (e.g., Figure 6 , 8 The capacitor 366 (or in another embodiment, is implemented as a discrete capacitor, such as a "chip capacitor"), may be integrally formed as an IPD (e.g., a capacitor 666). Figure 5-9 This is part of IPD 580, 580', 581, 581'. In this embodiment, the capacitance value of the envelope capacitor 366 may be in the range of about 1 nF to about 1 microfarad (μF), but the capacitance value of the envelope capacitor 366 may also be outside this range.

[0072] Figure 3A The first embodiment of the baseband termination circuit 300 shown includes a simple series combination of an envelope inductor 362, an envelope resistor 364, and an envelope capacitor 366. Conversely, in Figure 3B-3F In some embodiments, the baseband termination circuits 301-305 may include one or more “bypass” or “parallel” capacitors 368, 370, 372, 374, 376, 378, C para The capacitor is coupled in parallel with the envelope inductor 362 and / or the envelope resistor 364. In some embodiments, each of the bypass capacitors 368, 370, 372, 374, 376, and 378 can be implemented as a discrete capacitor (e.g., Figure 6 , 8 The capacitor 678, or in other embodiments, is implemented as an integrated capacitor. In each of these embodiments, the capacitance value of the bypass capacitors 368, 370, 372, 374, 376, and 378 can be in the range of about 3.0 pF to about 1400 pF. In other embodiments, the value of any one of the bypass capacitors 368, 370, 372, 374, 376, and 378 can be lower or higher than the range given above.

[0073] exist Figure 3B In the baseband termination circuit 301, bypass capacitor 368, C paraIt is coupled in parallel with the envelope inductor 362. More specifically, the first end of the envelope inductor 362 and the bypass capacitor 368 is coupled to node 313, and the second end of the envelope inductor 362 and the bypass capacitor 368 is coupled to node 380.

[0074] exist Figure 3C In the baseband termination circuit 302, the bypass capacitor 370, C para It is coupled in parallel with the envelope resistor 364. More specifically, the first end of the envelope resistor 364 and the bypass capacitor 370 is coupled to node 380, and the second end of the envelope resistor 364 and the bypass capacitor 370 is coupled to node 382.

[0075] exist Figure 3D In the baseband termination circuit 303, bypass capacitor 372, C para It is coupled in parallel with envelope inductor 362 and envelope resistor 364. More specifically, bypass capacitor 372 is coupled across nodes 313 and 382.

[0076] exist Figure 3E In the baseband termination circuit 304, the first bypass capacitor 374, C para1 Coupled in parallel with envelope inductor 362, and with second bypass capacitor 376, C para2 It is coupled in parallel with the envelope resistor 364. More specifically, the first end of the envelope inductor 362 and the first bypass capacitor 374 is coupled to node 313, and the second end of the envelope inductor 362 and the first bypass capacitor 374 is coupled to node 380. In addition, the first end of the envelope resistor 364 and the second bypass capacitor 376 is coupled to node 380, and the second end of the envelope resistor 364 and the second bypass capacitor 376 is coupled to node 382.

[0077] refer to Figure 3B , 3E The device or circuit in which the baseband termination circuits 301, 304, and 305 of 3F are combined, along with the parallel-coupled inductor 362 and capacitor 368, 374, or 378 to form frequency proximity circuits 301, 304, or 305 (e.g., Figure 1 , 2The amplifier circuits 100 and 200 are parallel resonant circuits with a center operating frequency. As used herein and according to embodiments, the term "near the center operating frequency" means "within 20% of the center operating frequency." Thus, for example, when the device has a center operating frequency of 2.0 GHz, the frequency "near the center operating frequency" corresponds to a frequency falling within the range of 1.8 GHz to 2.2 GHz. While 2.0 GHz is given as an example center operating frequency, the device may also have a center operating frequency different from 2.0 GHz. In alternative embodiments, the term "near the center operating frequency" may mean "within 10% of the center operating frequency" or "within 5% of the center operating frequency."

[0078] Because of L env / / C para A parallel resonant circuit is formed at a frequency close to the center operating frequency of the device; therefore, the parallel resonant circuit L... env / / C para Essentially, this manifests as an open circuit at this frequency. Therefore, RF energy near the center operating frequency, which may exist at node 313 coupled to circuits 301, 304, or 305, will be transmitted through the parallel resonant circuit L. env / / C para Deflection. This deflection can be provided even with a relatively low inductance value for inductor 362. For these reasons, circuits 301, 304, and 305 can significantly improve the devices or circuits incorporating them (e.g., by presenting low impedance at the envelope frequency and high impedance at the RF frequency) by presenting low impedance at the envelope frequency and high impedance at the RF frequency. Figure 1 , 2 LFR of amplifier circuits 100 and 200.

[0079] exist Figure 3C , 3D In each embodiment of the baseband termination circuits 302, 303, and 304 of 3E, bypass capacitors 370, 372, or 376 are coupled in parallel with envelope resistor 364. Because capacitors 370, 372, or 376 can be used to route RF current around envelope resistor 364, circuits 302, 303, and 304 may result in a reduction in the RF current dissipated by envelope resistor 364. This characteristic of circuits 302, 303, and 304 can also be used to better protect envelope resistor 364 from potential damage due to excessive current that might otherwise flow through envelope resistor 364 without bypass capacitors 370, 372, or 376.

[0080] Compared to circuit 300, each of circuits 301-305 can improve device efficiency because circuits 301-305 allow less RF current to flow through (and be dissipated by) the envelope resistor 364. Additionally, since circuits 301-305 present high impedance to RF frequencies close to the center operating frequency of the device where the baseband termination circuitry is combined, connecting circuits 301-305 to a low RF impedance point (e.g., ...) is beneficial. Figure 1 , 2 The RF low impedance point (113 or 158) is not important, but circuits 301-305 can be connected to that RF low impedance point. Conversely, the benefits of circuits 301-305 can be achieved even when they are coupled to nodes exhibiting higher RF impedance. This situation includes other nodes in input impedance matching circuits and output impedance matching circuits.

[0081] Refer again Figure 1 and 2 And as will be combined later Figure 5-9 In more detail, various embodiments of the RF amplifier device may include at least one input-side integrated passive device (IPD) assembly (e.g., Figure 5-9 IPD assemblies 580, 580', 581, 581') and at least one output-side IPD assembly (e.g., Figure 5 IPD assemblies 582, 583). One or more input-side IPD assemblies (e.g., Figure 5-9 The IPD assemblies 580, 580', 581, 581' include portions of input circuits 110, 210, fractional harmonic resonator circuit 130, and baseband termination circuit 160. For example, as previously described, by... Figure 1 , 2 Some or all of the components covered by the dashed boxes 180, 280 may be included in or on the output-side IPD assembly. Similarly, the one or more output-side IPD assemblies (e.g., Figure 5 The IPD assemblies 582, 583 include portions of output circuitry 150 and baseband termination circuitry 162. More specifically, each IPD assembly may include a semiconductor substrate having one or more integrated passive components. In several specific embodiments, each input-side IPD assembly may include a parallel capacitor 114, a parallel inductor 218, a parallel capacitor 219, a series capacitor 220, a resistor 222, an FHR circuit inductor 132, an FHR circuit capacitor 134, and a component of baseband termination circuitry 160 (e.g., Figures 3A-3FComponents 362, 364, 366, 368, 370, 372, 374, 376, 378). In other specific embodiments, each output-side IPD assembly may include a parallel capacitor 156 and a component of the baseband termination circuit 162 (e.g., Figures 3A-3F Components 362, 364, 366, 368, 370, 372, 374, 376, 378.

[0082] In other embodiments, portions of the input impedance matching circuits 110, 210 and the output impedance matching circuit 150, as well as the baseband termination circuits 160, 162, may be implemented as different / discrete components or as portions of other types of assemblies (e.g., low-temperature co-fired ceramic (LTCC) devices, small PCB assemblies, etc.). In still other embodiments, portions of the input impedance matching circuits 110, 210 and / or the output impedance matching circuit 150 may be coupled to and / or integrated within a semiconductor die including the transistor 140. The following detailed description of embodiments including IPD assemblies should not be construed as limiting the subject matter of the invention, and the terms "passive device substrate" or "IPD substrate" refer to any type of structure including passive devices, including IPDs, LTCC devices, transistor dies, PCB assemblies, etc.

[0083] Figure 1 and 2 Each of the amplifier circuits 100 and 200 can be implemented as a single-path amplifier, which receives an RF signal at input 102, amplifies the signal through transistor 140, and generates an amplified RF signal at output 104. Alternatively, multiple instances of amplifier circuits 100 and 200 can be implemented together to provide a multipath amplifier, such as a Dougherty power amplifier or another type of multipath amplifier circuit.

[0084] For example, Figure 4 This is a simplified schematic diagram of a Dougherty power amplifier (DPA) 400, which may implement an embodiment of amplifier circuit 100 or 200. The DPA 400 includes an input node 402, an output node 404, a power divider 406 (or splitter), a main amplifier path 420, a peaking amplifier path 421, and a combination node 480. A load 490 may be coupled to the combination node 480 (e.g., via an impedance transformer, not shown) to receive amplified RF signals from the amplifier 400.

[0085] Power divider 406 is configured to divide the power of the input RF signal received at input node 402 into a main portion and a peaked portion of the input signal. The main input signal is provided to the main amplifier path 420 at power divider output 408, and the peaked input signal is provided to the peaked amplifier path 421 at power divider output 409. During full-power mode operation, when both the main amplifier 440 and the peaked amplifier 441 supply current to the load 490, power divider 406 distributes the input signal power between amplifier paths 420, 421. For example, power divider 406 may distribute the power equally, such that approximately half of the input signal power is provided to each path 420, 421 (e.g., for a symmetrical Dougherty amplifier configuration). Alternatively, power divider 406 may distribute the power unequally (e.g., for an asymmetrical Dougherty amplifier configuration).

[0086] Essentially, power divider 406 distributes the input RF signal supplied at input node 402 and amplifies the distributed signal along main amplifier path 420 and peaking amplifier path 421, respectively. The amplified signals are then combined in phase at combination node 480. Importantly, maintaining phase coherence between main amplifier path 420 and peaking amplifier path 421 across the band of interest ensures that the amplified main signal and peaking signal arrive in phase at combination node 480, and thus ensures proper Dougherty amplifier operation.

[0087] An input impedance matching network 410 (input MNm) can be implemented at the input of the main amplifier 440 (e.g., Figure 1 , 2 The input impedance matching circuits 110 and 210). Similarly, an input impedance matching network 411 (input MNp) can be implemented at the input of the peaking amplifier 441 (e.g., Figure 1 , 2 The input impedance matching circuits 110 and 210 are used. Matching networks 410 and 411 can be used to transform the gate impedances of the main amplifier 440 and the peaking amplifier 441 to more desirable system-level impedances and manipulate the signal phase to ensure proper Dougherty amplifier operation. All or part of the input matching networks 410 and 411 can be implemented within the power transistor package that includes the main amplifier 440 and / or the peaking amplifier 441, or some portions of the input impedance matching networks 410 and 411 can be implemented on a PCB or other substrate on which the power transistor package is mounted.

[0088] According to various embodiments of the subject matter of the invention, the DPA 400 also includes fractional harmonic resonator (FHR) circuits 430, 431 coupled between the inputs of amplifiers 440, 441 and the inputs of the main amplifier and peaking amplifiers 440, 441 (e.g., Figure 1 , 2 The FHR circuit 430, 431 is configured to generate a low impedance condition (simulating a short circuit) near the second harmonic frequency 2f0 of the DPA 400.

[0089] Each of the main amplifier 440 and the peaking amplifier 441 includes one or more single-stage power transistor integrated circuits (ICs) or multi-stage power transistor ICs (or power transistor dies) for amplifying RF signals conducted through amplifiers 440, 441. According to various embodiments, all amplifier stages or the final amplifier stage of either or both of the main amplifier 440 and / or the peaking amplifier 441 may be implemented, for example, using III-V field-effect transistors (e.g., HEMTs), such as GaN FETs (or another type of III-V transistor, including GaAs FETs, GaP FETs, InP FETs, or InSb FETs). In some embodiments, where only one of the main amplifier 440 or the peaking amplifier 441 is implemented as a III-V FET, the other amplifiers may be implemented as silicon-based FETs (e.g., LDMOS FETs).

[0090] According to one embodiment, carrier amplifier 440 and peaking amplifier 441 each include a single-stage amplifier (i.e., an amplifier having a single amplification stage or power transistor). In other embodiments, carrier amplifier 440 is a two-stage amplifier comprising a relatively low-power driver amplifier (not shown) and a relatively high-power final-stage amplifier (not shown) arranged in a cascaded (or series) configuration between the input and output of the carrier amplifier. In the cascaded carrier amplifier configuration, the output (e.g., the drain terminal) of the driver amplifier is electrically coupled to the input (e.g., the gate terminal) of the final-stage amplifier. Similarly, peaking amplifier 441 may include a two-stage amplifier comprising a relatively low-power driver amplifier (not shown) and a relatively high-power final-stage amplifier (not shown) arranged in a cascaded configuration between the input and output of the peaking amplifier. In the cascaded peaking amplifier configuration, the output (e.g., the drain terminal) of the driver amplifier is electrically coupled to the input (e.g., the gate terminal) of the final-stage amplifier. In other embodiments, each of carrier amplifier 440 and peaking amplifier 441 may include more than two cascaded-coupled amplification stages.

[0091] While the main power transistor IC and the peaking power transistor IC can have the same size (e.g., in a symmetric Dougherty configuration), they can alternatively have unequal sizes (e.g., in various asymmetric Dougherty configurations). As used herein, the term "size" relating to a power transistor IC refers to the peripheral / current carrying capacity of the power transistor embodied in the IC. In an asymmetric Dougherty configuration, one or more peaking power transistor ICs are typically larger than one or more main power transistor ICs by a multiplier. For example, the size of the one or more peaking power transistor ICs can be twice that of the one or more main power transistor ICs, such that the current carrying capacity of the one or more peaking power transistor ICs is twice that of the one or more main power transistor ICs (i.e., the size ratio of the peaking amplifier IC to the main amplifier IC is 2:1). Size ratios of the peaking amplifier IC to the main amplifier IC other than a 2:1 ratio can also be implemented.

[0092] An output impedance matching network 450 (output MNm) can be implemented at the output of the main amplifier 440 (e.g., Figure 1 , 2 The output impedance matching circuit 150). Similarly, an output impedance matching network 451 (output MNp) can be implemented at the output of the peaking amplifier 441 (e.g., Figure 1 , 2 The output impedance matching circuit 150 is used. In each case, matching networks 450, 451 can be used to transform the drain impedance of the main amplifier 440 and the peaking amplifier 441 to a more desirable system-level impedance and manipulate the signal phase to ensure proper Dougherty amplifier operation. All or part of the output impedance matching networks 450, 451 can be implemented within a power transistor package including the main amplifier 440 and / or the peaking amplifier 441, or some portions of the output impedance matching networks 450, 451 can be implemented on a PCB or other substrate on which the power transistor package is mounted.

[0093] During operation of DPA 400, main amplifier 440 is biased to operate in Class AB mode (or deep Class AB mode), and peaking amplifier 441 is biased to operate in Class C mode (or deep Class C mode). In some configurations, peaking amplifier 156 may be biased to operate in Class B or deep Class B mode. Main amplifier 440 and peaking amplifier 441 are coupled to combination node 480 via carrier output circuit 450 and peaking output circuit 451, respectively. At low to medium input signal power levels (i.e., when the power of the input signal at RF input 402 is below the turn-on threshold level of peaking amplifier 441), DPA 400 operates in low-power mode, in which main amplifier 440 operates to amplify the input signal, and peaking amplifier 441 conducts minimally (e.g., peaking amplifier 441 is essentially off). During this operational phase, main output circuit 450 determines the maximum VSWR (voltage standing wave ratio) that main amplifier 440 will be exposed to. Conversely, when the input signal power increases to the level at which the main amplifier 440 reaches voltage saturation, the power splitter 406 divides the energy of the input signal between the main amplification path 420 and the peaking amplifier path 421, and both amplifiers 440 and 441 operate to amplify the corresponding portions of their input signals.

[0094] When the input signal level increases beyond the point where the main amplifier 440 operates in compression, the conduction of the peaking amplifier 441 also increases, thereby supplying more current to the load 490. In response, the load line impedance of the main amplifier output decreases. In fact, an impedance modulation effect occurs when the load line impedance of the main amplifier 440 changes dynamically in response to the input signal power (i.e., the peaking amplifier 441 provides an active load pull to the main amplifier 440). The main output circuit 450, coupled between the output of the main amplifier 440 and the combination node 480, transforms the main amplifier load line impedance to a high value during backoff, thereby allowing the main amplifier 440 to efficiently supply power to the load 490 over an extended output power range.

[0095] The DPA 400 features a “non-inverting” load network configuration. In this configuration, the input circuitry is configured such that, at the center operating frequency f0 of amplifier 400, the input signal supplied to peaking amplifier 441 is delayed by 90 degrees relative to the input signal supplied to main amplifier 440. To ensure that the main input RF signal and the peaked input RF signal arrive at main amplifier 440 and peaking amplifier 441 with a phase difference of approximately 90 degrees, as is fundamental for Dougherty amplifier operation, a phase delay element 482 applies a phase delay of approximately 90 degrees to the peaked input signal. For example, phase delay element 482 may comprise a quarter-wave transmission line or another suitable type of delay element having an electrical length of approximately 90 degrees.

[0096] Essentially, the phase delay element 482 compensates for the 90-degree phase delay implemented by the phase shift and impedance transformation element 484 between the output of the main amplifier 440 and the combination node 480. For example, the phase shift and impedance transformation element 484 may include a transmission line coupled between the output of the main amplifier 440 and the combination node 480. In essence, the phase delay element 482 and the phase shift and impedance transformation element 484 make the phase shift applied to the RF signal along the main amplifier path 420 and the peaking amplifier path 421 equal, ensuring that the amplified signal arrives at the combination node 480 in phase.

[0097] Alternative embodiments of the Dougherty amplifier may have an "inverting" load network configuration. In this configuration, the input circuitry is configured such that, at the center operating frequency f0 of amplifier 400, the input signal supplied to the main amplifier 440 is delayed by approximately 90 degrees relative to the input signal supplied to the peaking amplifier 441, and the output circuitry is configured to apply a phase delay of approximately 90 degrees to the signal between the output of the peaking amplifier 441 and the combination node 480.

[0098] Amplifiers 440 and 441, along with portions of fractional harmonic resonator circuits 430 and 431 and matching networks 410, 411, 450, and 451, can be implemented in a discrete packaged power amplifier device. In such a device, input and output leads are coupled to a substrate, and each amplifier 440, 441 may include a single-stage or multi-stage power transistor also coupled to the substrate. Portions of the fractional harmonic resonator circuits 430 and 431, as well as input matching networks 410 and 411 and output matching networks 450 and 451, can be implemented as additional components within the package. Additionally, as described in detail below, the baseband termination circuit (e.g., in...) Figures 3A-3F As shown Figure 1 , 2 The BBT circuits 160 and 162 (in embodiments) can also be implemented as additional components within the packaging device.

[0099] For example, Figure 5 This is a top view of an embodiment of a packaged RF amplifier device 500, which embodies... Figure 1 , 2 Two parallel examples of circuit 100 or 200 can be used to provide a Dougherty amplifier (e.g., Figure 4 The amplifier in the DPA400 (e.g., Figure 4 Amplifiers 440, 441), FHR circuits (e.g., Figure 1 , 2 The FHR circuit 130) and the matching network (e.g., Figure 4All or part of the matching networks 410, 411, 450, 451. Additionally, as will be described in more detail below, the device 500 includes two input-side IPD assemblies 580, 580', 581, 581', each of the two output-side IPD assemblies 580, 580', 581, 581' including input impedance matching circuits 510, 510', 511, 511' (e.g., ...). Figure 1 , 2 Circuits 110, 210, 410, 411; baseband termination circuits 560, 561 (e.g., Figure 1 , 2 Circuit 160) and fractional harmonic resonator (FHR) circuits 530, 531 (e.g., Figure 1 , 2 The circuits 130, 430, and 431 of the 4th generation are included. Additionally, the device 500 includes two output-side IPD assemblies 582 and 583, each of which includes output impedance matching circuits 550 and 551 (e.g., ...). Figure 1 , 2 Circuits 150, 450, 451) and baseband termination circuits 562, 563 (e.g., Figure 1 , 2 The circuit 162) part.

[0100] In an embodiment, device 500 includes a flange 506 (or "device substrate"), said flange 506 comprising a rigid conductive substrate of sufficient thickness to provide structural support for various electrical components and elements of device 500. Additionally, flange 506 can serve as a heat sink for transistor dies 540, 541 and other devices mounted on flange 506. Flange 506 has a top surface and a bottom surface (in... Figure 5 (Only the central part of the top surface is visible) and the roughly rectangular perimeter corresponding to the perimeter of the device 500.

[0101] Flange 506 is formed of a conductive material and can be used to provide a ground reference node for device 500. For example, various components and elements may have ends electrically coupled to flange 506, and flange 506 may be electrically coupled to system ground when device 500 is integrated into a larger electrical system. At least the top surface of flange 506 is formed of a layer of conductive material, and all flanges 506 may be formed of bulk conductive material.

[0102] In one embodiment, the isolation structure 508 is attached to the top surface of the flange 506. The isolation structure 508, formed of a rigid electrically insulating material, provides electrical isolation between conductive features of the device (e.g., between leads 502-505, 592-595 and flange 506). In another embodiment, the isolation structure 508 has a frame shape comprising a substantially closed quadrilateral structure with a central opening. Figure 5 As shown, the isolation structure 508 may have a substantially rectangular shape, or the isolation structure 508 may have another shape (e.g., ring, ellipse, etc.).

[0103] A portion of the top surface of the flange 506 exposed through the opening in the isolation structure 508 is referred to herein as the “active region” of the device 500. Transistor dies 540 and 541, together with IPD assemblies 580 (or 580'), 581 (or 581'), 582, and 583, are located within the active device region of the device 500, as will be described in more detail later. For example, transistor dies 540 and 541 and IPD assemblies 580-583 may be coupled to the top surface of the flange 506 using conductive epoxy, solder, solder bumps, sintering, and / or eutectic bonding.

[0104] Device 500 accommodates two amplification paths (indicated by arrows 520 and 521), where each amplification path 520 or 521 represents circuit 100 or 200. Figure 1 , 2 The physical implementation scheme of ). When combined with a Dougherty amplifier (e.g., Figure 4 In the DPA 400, amplification path 520 can correspond to the main amplifier path (e.g., Figure 4 The main amplifier path 420), and the amplification path 521 can correspond to the peaking amplifier path (e.g., Figure 4 Peaking amplifier path 421). In some instances, the order can be switched, where amplification path 520 can correspond to the peaking amplifier path and amplification path 521 can correspond to the main amplifier path.

[0105] Each path 520, 521 includes input leads 502, 503 (e.g., Figure 1 , 2 Input 102), output leads 504, 505 (e.g., Figure 1 , 2 Output 104), one or more transistor dies 540, 541 (e.g., Figure 1 , 2 transistor 140 or Figure 4 Amplifiers 440, 441), input impedance matching circuits 510 (or 510'), 511 (511') (e.g., Figure 1 , 2 Input impedance matching circuit 110, 210 or Figure 4 The input matching networks 410 and 411 (parts of the input impedance matching networks), and the output impedance matching circuits 550 and 551 (e.g., Figure 1 , 2 Output impedance matching circuit 150 or Figure 4 The output matching networks 450, 451 (parts of the output matching networks), and the input-side baseband termination circuits 560, 561 (e.g., Figure 1 , 2 Baseband termination circuit 160), output-side baseband termination circuits 562, 563 (e.g., Figure 1 , 2 Baseband termination circuit 162), FHR circuits 530, 531 (e.g., Figure 1 , 2 FHR circuits 130, 430, and 431 (4).

[0106] Input and output leads 502-505 are mounted on the top surface of the isolation structure 508 on opposite sides of the central opening, and thus the input and output leads 502-505 rise above the top surface of the flange 506 and are electrically isolated from the flange 506. Typically, the input and output leads 502-505 are oriented to allow for the attachment of bonding wires between the input and output leads 502-505 and components and elements within the central opening of the isolation structure 508.

[0107] Each transistor die 540, 541 includes an integrated power FET, wherein each FET has a control terminal (e.g., a gate terminal) and two current-conducting terminals (e.g., a drain terminal and a source terminal). The control terminal of the FET within each transistor die 540, 541 is coupled to input leads 502, 503 via input impedance matching circuits 510 (or 510'), 511 (or 511') and FHR circuits 530, 531. Additionally, one current-conducting terminal (e.g., the drain terminal) of the FET within each transistor die 540, 541 is coupled to output leads 504, 505 via output impedance matching circuits 550, 551. In an embodiment, the other current-conducting terminal (e.g., the source terminal) of the FET within each transistor die 540, 541 is electrically coupled to flange 506 (e.g., to ground) via die 540, 541.

[0108] Combining later Figure 6-9 The embodiments of the input impedance matching circuits 510, 510', 511, 511', baseband termination circuits 560, 561, and FHR circuits 530, 531 are described in more detail below. Figure 6-9The components of these circuits 510, 510', 511, 511', 530, 531, 560, and 561 are shown in more detail. (As will be combined...) Figure 6-9 As can be seen, some components of these circuits can be implemented within IPD assemblies 580 (or 580'), 581 (or 581'). In short, each input impedance matching circuit 510 (or 510'), 511 (or 511') is series-coupled with FHR circuits 530, 531 between input leads 502, 503 and the control terminals of the FETs within transistor dies 540, 541. Each input-side baseband termination circuit 560, 561 is coupled to nodes 513, 514 within IPD assemblies 580 (or 580'), 581 (or 581') (e.g., Figure 1 , 2 Between node 113 (e.g., conductive bonding pad) and ground reference (e.g., flange 506). Each FHR circuit 530, 531 is coupled between the control terminal (e.g., gate terminal) of the FET within transistor dies 540, 541 and input leads 502, 503. Within IPD assembly 580 (or 580'), each FHR circuit 530, 531 is more specifically coupled to first nodes 513, 514 (e.g., ... Figure 1 Node 113 or Figure 2 Node 213) and second nodes 515, 516 (for example, Figure 1 , 2 Between nodes 115), each of the first node 513 and the second node 515 (or the first node 514, the second node 516) can be physically implemented as a conductive bonding pad of the IPD assembly 580 (or 580').

[0109] Some components of the output impedance matching circuits 550, 551, FHR circuits 530, 531, and baseband termination circuits 562, 563 can be implemented within IPD assemblies 582, 583. In short, each output impedance matching circuit 550, 551 is coupled between the current-conducting terminal (e.g., drain terminal) of the FET within transistor dies 540, 541 and the output leads 504, 505. Each baseband termination circuit 562, 563 is coupled between nodes 558, 559 (e.g., ...) within IPD assemblies 582, 583. Figure 1 , 2 Between node 158 (or another RF low impedance point) and ground reference (e.g., flange 506).

[0110] In addition to the input and output leads 502-505, the device 500 may also include a bias circuit system (e.g., including...). Figure 1 , 2 Bias circuit 190). In Figure 5In the embodiments, each bias circuit in the bias circuit includes an inductive element (e.g., Figure 1 , 2 The inductor element 192), and each bias circuit in the input-side (gate) bias circuit further includes capacitors 596, 597 (e.g., Figure 1 , 2 (e.g., capacitor 196). For example, each capacitor 596, 597 may be a discrete capacitor (or "chip capacitor"), with a first end coupled to the far end of bias leads 592, 593, and a second end coupled to a ground reference node (e.g., on a PCB connected to device 500).

[0111] The inductor element of each bias circuit may include, for example, bias leads 592, 593, 594, 595 and one or more bond wires (e.g., bias leads 592-595) indirectly coupling each bias lead 592-595 to the control terminal (e.g., gate terminal) or current conduction terminal (e.g., drain terminal) of the FET within each transistor die 540, 541. Figure 6 , 8 The bonding wires 692 are arranged in series. The distal ends of each bias lead 592-595 (corresponding to) Figure 1 , 2 Node 193 can be electrically coupled to an external bias circuit (not shown) that provides a bias voltage to the control or current conduction terminal of each FET via bias leads 592-595. When the gate bias voltage is provided via bias leads 592, 593, resistor 622 (described below) can be excluded from device 500 (e.g., Figure 2 Resistor 222) and capacitor 619 (e.g., Figure 2 (Capacitor 219). In other embodiments, either or both of the input-side or output-side bias circuitry may be omitted. Instead, in such embodiments, external bias circuitry may be connected to input leads 502, 503 or output leads 504, 505, and one or more bias voltages may be provided through input leads 502, 503 and / or output leads 504, 505.

[0112] exist Figure 5 In this example, device 500 includes two transistor dies 540 and 541 that operate substantially in parallel; however, another semiconductor device may also include a single transistor die or more than two transistor dies. Additionally, device 500 includes two input-side IPD assemblies 580 (or 580') and 581 (or 581') that also operate substantially in parallel, and two output-side IPD assemblies 582 and 583. It should be understood that more or fewer IPD assemblies 580-583 may also be implemented.

[0113] According to an embodiment, device 500 is incorporated within an air-cavity package, wherein transistor dies 540, 541, IPD assemblies 580-583, and various other components are positioned within a closed air cavity. Essentially, the air cavity is defined by a flange 506, an isolation structure 508, and a cap (not shown) covering and contacting the isolation structure 508 and leads 502-505, 592-595. Figure 5 In this configuration, the outer perimeter will be substantially aligned with the outer perimeter of flange 506. In other embodiments, components of device 500 may be incorporated into an overmolded package (i.e., a package in which electrical components within the active device region are encapsulated with a non-conductive molding compound and portions of leads 502-505, 592-595 may also be surrounded by a molding compound). The overmolded package may not include the isolation structure 508.

[0114] The reference now includes device 500 ( Figure 5 A magnified view of part of the () Figure 6-9 The portion includes two embodiments of the input impedance matching circuits 510 and 510', the baseband termination circuit 560, and the FHR circuit 530. More specifically, Figure 6 and 7 The diagram depicts a single-stage input impedance matching circuit 510 (e.g., Figure 1 , 5 Examples of input impedance matching circuits 110 and 510, and Figure 8 and 9 The diagram depicts a two-stage input impedance matching circuit 510' (e.g., Figure 2 , 5 Examples of input impedance matching circuits 210 and 510'.

[0115] In terms of the degree of basic similarity, single-segment input impedance matching circuit embodiments (e.g., Figure 1 The input impedance matching circuit 110) and the two-stage input impedance matching circuit embodiments (e.g., Figure 2 The input impedance matching circuit 210) and the two will be combined Figure 6-9 Describe them together. More specifically, Figure 6 and 8 These are top views of the lower left input-side portions 600 and 600' of the packaged RF power amplifier device 500 along the amplifier path 520, representing the first and second embodiments, respectively. Portions 600 and 600' ( Figure 6 , 8This includes a portion of a power transistor die 540, a portion of an input lead 502, and an input-side IPD assembly 580 or 580', in which a single-stage input impedance matching circuit is implemented ( ) Figure 6 , 7 ) or a two-stage input impedance matching circuit ( Figure 8 , 9 ), FHR circuit 530 and baseband termination circuit 560. To enhance understanding, Figure 7 and 9 These include sections taken along lines 7-7 and 9-9 respectively. Figure 6 and 8 A cross-sectional side view of portions 600 and 600' of the RF power amplifier device. More specifically, Figure 7 and 9 This is a cross-sectional view through the input lead 502, IPD assembly 580 or 580', a portion of flange 506, and transistor die 540. (See also...) Figure 7 and 9 As shown, the power transistor die 540 and IPD assembly 580 or 580' are coupled to conductive flange 506, and the input lead 502 is electrically isolated from conductive flange 506 (e.g., using isolation structure 508). It should be noted that the input-side portion of device 500 along amplifier path 521 can be coupled to… Figure 6-9 The portions shown in the figure, 600 or 600', are essentially the same.

[0116] The power transistor die 540 includes a transistor input terminal 642 (e.g., a conductive bonding pad), which is electrically connected within the power transistor die 540 to a single-stage or final-stage FET 730 integrated within the die 540. Figure 7 , 9The FET 730 may include a control terminal (e.g., a gate terminal). As previously discussed, each FET 730 may include a III-V field-effect transistor (e.g., a HEMT) such as a GaN FET (or another type of III-V transistor, including GaAs FET, GaP FET, InP FET, or InSb FET). More specifically, each FET 730 may be integrally formed in and on a substrate semiconductor substrate 732 (e.g., a GaN substrate, a GaN-on-silicon substrate, a GaN-on-silicon carbide substrate, etc.). The conductive connection between the control terminal (e.g., the gate terminal) of the FET 730 and the input terminal 642 of the die 540 may be formed by a stacked structure 734 of alternating dielectric layers and patterned conductive layers, wherein portions of the patterned conductive layers are electrically connected using conductive vias. A conductive layer 736 on the bottom surface of the die 540 may provide a ground node (e.g., for the source end), which may be connected to the conductive layer 736 (and thus to the conductive flange 506) using through-substrate vias or doped sink regions (not shown).

[0117] IPD Assembly 580 ( Figure 6 , 7 ), 580' Figure 8 , 9 Each IPD assembly in the assembly may also include a substrate semiconductor substrate 782 (e.g., a silicon substrate, silicon carbide substrate, GaN substrate, or another type of semiconductor substrate, which may be referred to herein as an "IPD substrate") and a stacked structure 784 of alternating dielectric layers and patterned conductive layers, wherein portions of the patterned conductive layers are electrically connected using conductive vias. As will be discussed in more detail below, an input impedance matching circuit 510 or 510' (e.g., Figure 1 , 2 Impedance matching circuit 110 or 210), baseband termination circuit 560 (e.g., Figure 1 , 2 The baseband termination circuit 160) and the FHR circuit 530 (e.g., Figure 1 , 2 The various electrical components of the FHR circuit 130 are integrally formed within and / or connected to the IPD assemblies 580, 580'. These electrical components may be electrically connected to conductive bonding pads (e.g., bonding pads 513, 515, 811) on the top surface of the IPD assemblies 580, 580', and may also be electrically connected to ground (or another voltage reference) (e.g., using conductive through-substrate vias extending through the semiconductor substrate 782 to the bottom surface of the IPD assemblies 580, 580').

[0118] exist Figure 6-9 In the two embodiments shown, the input lead 502 (e.g., Figure 1 , 2 The electrical connection between input 102) and IPD assembly 580 or 580' includes a first inductor element 612 (e.g., Figure 1 , 2 The first inductor element 612 can be implemented as a first set of bonding wires, with its first end coupled to the input lead 502 and its second end coupled to the conductive bonding pad 513 on the top surface of the IPD assembly 580, 580' (e.g., corresponding to the conductive bonding pad 513 on the top surface of the IPD assembly 580, 580'). Figure 1 Connection node 113 or Figure 2 (Connection node 213). Similarly, in Figure 6-9 In the two embodiments shown, the electrical connection between the IPD assembly 580 or 580' and the input terminal 642 (e.g., the gate terminal) of the transistor die 540 includes a second inductor element 616 (e.g., Figure 1 , 2 The second inductor element 616 can be implemented as a second set of bonding wires, wherein the first end is coupled to a conductive bonding pad 515 on the top surface of the IPD assembly 580, 580' (e.g., corresponding to the inductor element 116), the second inductor element 616 can be implemented as a second set of bonding wires, wherein the first end is coupled to a conductive bonding pad 515 on the top surface of the IPD assembly 580, 580' (e.g., corresponding to the conductive bonding pad 515 on the top surface of the IPD assembly 580, 580'). Figure 1 , 2 The second end is coupled to the input terminal 642 of the transistor die 540.

[0119] Now for reference Figure 6 and 7 The following will now describe a single-stage input impedance matching circuit 510 (e.g., Figure 1 An embodiment of the IPD assembly 580 is a portion of the input impedance matching circuit 110. The input impedance matching circuit 510 is a single-stage T-matching circuit, which includes a first inductor element 612 (e.g., Figure 1 Inductor 112), parallel capacitor 614 (e.g., Figure 1 Parallel capacitor 114), second inductor element 616 (e.g., Figure 1 (Inductor element 116).

[0120] As described above, the first inductor 612 and the second inductor 616 can each be implemented as a set of bonding wires. The IPD assembly 580 includes conductive bonding pads 513, 515 exposed on the top surface of the IPD assembly 580 (corresponding to...). Figure 1The nodes 113 and 115 are connected, and the ends of the bond wires associated with inductor elements 612 and 616 are respectively connected to bond pads 513 and 515. According to an embodiment, the inductance value of inductor element 612 can be in the range of about 150 pH to about 500 pH, and the inductance value of inductor element 616 can be in the range of about 50 pH to about 250 pH. In other embodiments, the inductance value of one or both of the inductor elements 612 and 616 can be less than or greater than the ranges given above.

[0121] Parallel capacitor 614 (e.g., Figure 1 The parallel capacitor 114) is coupled to the bonding pad 513 (e.g., Figure 1 The node 113 is connected to ground (or another voltage reference) via a conductive through-substrate via extending through the semiconductor substrate 782 to the conductive layer 786 and the flange 506 (e.g., using a conductive through-substrate via extending through the semiconductor substrate 782 to the conductive layer 786 on the bottom surface of the IPD assembly 580). More specifically, a first end of the parallel capacitor 614 is coupled to the bonding pad 513, and a second end of the parallel capacitor 614 (e.g., using a conductive through-substrate via extending through the semiconductor substrate 782 to the conductive layer 786 on the bottom surface of the IPD assembly 580) is electrically coupled to the conductive flange 506. The parallel capacitor 614 may be implemented as a metal-insulator-metal (MIM) capacitor (or a set of parallel-coupled MIM capacitors) integrally formed as part of the IPD assembly 580. The MIM capacitor includes a first conductive electrode and a second conductive electrode (formed by a patterned portion of the conductive layer of the stacked structure 784) aligned with each other and electrically separated by the dielectric material of the stacked structure 784. In a more specific embodiment, the first electrode of the parallel capacitor 614 is “directly connected” to the bonding pad 513, where “directly connected” means that it may be electrically connected using one or more conductive traces and / or conductive vias, without using intermediate circuit elements (i.e., circuit elements having more than one trace inductance, where the “trace inductance” is an inductance less than about 100 pH). Because the parallel capacitor 614 and the bonding pad 513 are “directly connected,” and the bonding pad 513 also has only one trace inductance, in this embodiment, the bonding line 612 and the parallel capacitor 614 can also be considered “directly connected.” In an alternative embodiment, the parallel capacitor 614 may be implemented using one or more discrete capacitors coupled to the top surface of the IPD assembly 580 or using another type of capacitor. According to embodiments, the capacitance value of the parallel capacitor 614 may be in the range of about 10 pF to about 200 pF, but the parallel capacitor 614 may also have a lower or higher capacitance value.

[0122] Now for reference Figure 8 and 9 The following will now be described, including a two-stage input impedance matching circuit 510' (e.g., Figure 2An embodiment of the IPD assembly 580' is a portion of the input impedance matching circuit 210. The input impedance matching circuit 510' has a two-stage input bandpass topology, which includes a first inductor element 612 (e.g., Figure 2 Inductor 112), one or more parallel capacitors 614 (e.g., Figure 2 Parallel capacitor 114), second inductor element 616 (e.g., Figure 2 Inductor 116), parallel inductor 818 (e.g., Figure 2 Parallel inductor 218), series capacitor 820 (e.g., Figure 2 (e.g., series capacitor 220), optional resistor 822 (e.g., Figure 2 The resistor 222) and an optional capacitor 819 connected in series with the parallel inductor 818 (e.g., Figure 2 Capacitor 219).

[0123] Again, as described above, the first inductor 612 and the second inductor 616 can each be implemented as a set of bonding wires. The IPD assembly 580' includes conductive bonding pads 513, 515 exposed on the top surface of the IPD assembly 580' (corresponding to...). Figure 2 The nodes 213 and 115 are connected, and the ends of the bond wires associated with inductor elements 612 and 616 are respectively connected to bond pads 513 and 515. According to an embodiment, the inductance value of inductor element 612 can be in the range of about 150 pH to about 500 pH, and the inductance value of inductor element 616 can be in the range of about 50 pH to about 250 pH. In other embodiments, the inductance value of one or both of the inductor elements 612 and 616 can be less than or greater than the ranges given above.

[0124] One or more parallel inductors 818 (e.g., Figure 2 The inductor element 218 is electrically coupled between the bonding pad 513 and ground (or another voltage reference) (e.g., using a conductive through-substrate via extending through the semiconductor substrate 782 to the conductive layer 786 and flange 506). According to an embodiment, each parallel inductor 818 may be implemented as an integrated spiral inductor formed of a conductive coil integrally formed as part of the IPD assembly 580'. According to an embodiment, the inductance value of one or more parallel inductors 818 may be in the range of about 100 pH to about 350 pH, but the inductance value may also be lower or higher.

[0125] In the illustrated embodiment, the optional DC blocking capacitor 819 (e.g., Figure 2The DC blocking capacitor 219 is coupled in series with each parallel inductor 818 (e.g., coupled between each parallel inductor 818 and ground (or another voltage reference)). However, as mentioned above, the DC blocking capacitor 819 can be excluded when the gate bias voltage is provided via separate gate bias circuitry (e.g., via bias leads 592 and 593). When included, each DC blocking capacitor 819 can be implemented as a MIM capacitor (or multiple parallel-coupled MIM capacitors) integrally formed as part of the IPD assembly 580'. Alternatively, each DC blocking capacitor 819 can be implemented as one or more discrete capacitors connected to the top surface of the IPD assembly 580. According to embodiments, the capacitance value of the DC blocking capacitor 819 can be in the range of about 50 pF to about 300 pF, but the inductance value can also be lower or higher.

[0126] Series capacitor 820 (e.g., Figure 2 The first end of the series capacitor 220 is directly or indirectly coupled to the bonding pad 513 (e.g., Figure 2 Node 213), and the second end of the series capacitor 820 is directly or indirectly coupled to the conductive node 813 (e.g., Figure 2 Node 113). Series capacitor 820 (e.g., Figure 2 The series capacitor 220 can be implemented as a discrete capacitor (or multiple discrete capacitors coupled in parallel, such as...) connected to the top surface of the IPD assembly 580'. Figure 8 (As shown). Alternatively, the series capacitor 820 can be implemented as a MIM capacitor (or multiple parallel-coupled MIM capacitors) integrally formed as part of the IPD assembly 580'. According to embodiments, the capacitance value of the series capacitor 820 can be in the range of about 10 pF to about 100 pF, but the capacitance value can also be lower or higher.

[0127] In the illustrated embodiment, a plurality of resistors 822 (e.g., Figure 2 Resistor 222 is coupled in parallel with one or more capacitors 820 between bonding pad 513 and conductive node 813. However, as mentioned above, resistor 822 can be excluded when the gate bias voltage is provided via separate gate bias circuitry (e.g., via bias leads 592 and 593). According to embodiments, when resistors 822 are included, each resistor 822 can be integrally formed as part of IPD assembly 580'. For example, each resistor 822 can be a polysilicon resistor formed from a polysilicon layer on or within stacked structure 784. According to embodiments, the resistance value of one or more resistors 822 can be in the range of about 50 ohms to about 150 ohms, but the resistance value can also be lower or higher.

[0128] According to an embodiment, each parallel capacitor 614 (e.g., Figure 2 The first electrode (or end) of each parallel capacitor 614 is electrically coupled to a conductive node 813, and the second electrode (or end) of each parallel capacitor 614 is electrically coupled to ground (or another voltage reference) (e.g., using a conductive through-substrate via extending through the semiconductor substrate 782 to the conductive layer 786 and flange 506). Each parallel capacitor 614 may be implemented as a MIM capacitor (or a set of parallel-coupled MIM capacitors) integrally formed as part of the IPD assembly 580'. In alternative embodiments, each parallel capacitor 614 may be implemented using one or more discrete capacitors coupled to the top surface of the IPD assembly 580' or using another type of capacitor. According to embodiments, the capacitance value of one or more parallel capacitors 614 may be in the range of about 10 pF to about 200 pF, but the capacitance value may also be lower or higher.

[0129] Now for reference Figure 6-9 In the two embodiments depicted, each IPD assembly in IPD assemblies 580 and 580' further includes an FHR circuit 530 (e.g., Figure 1 , 2 The FHR circuit 130). As previously combined Figure 1-4 The FHR circuit 530 discussed is connected to the input lead 502 within the transistor die 540 (e.g., Figure 1 , 2 The input 102) is between the control terminal (e.g., the gate terminal) of the FET 730. Figure 6-9 In embodiments, the FHR circuit 530 includes one or more inductors 632 (e.g., Figure 1 , 2 The inductor 132) and one or more capacitors 634 (e.g., Figure 1 , 2 The parallel combination of one or more inductors 632 and one or more capacitors 634, wherein the inductance and capacitance values ​​of one or more inductors 632 and one or more capacitors 634 are selected such that the parallel combination of one or more inductors 632 and one or more capacitors 634 produces a low impedance condition (simulating a short circuit) close to the second harmonic frequency 2f0. More specifically, the inductance and capacitance values ​​of one or more inductors 632 and one or more capacitors 634 are selected such that the FHR circuit 530 resonates at a frequency band below the second harmonic frequency but above the fundamental frequency band (i.e., the harmonic resonator resonates at a frequency between the fundamental frequency and the second harmonic frequency).

[0130] According to an embodiment, each of the one or more inductors 632 can be implemented as an integrated spiral inductor formed of a conductive coil, which is integrally formed as part of the IPD assembly 580, 580'. Figure 6 and 7 In the embodiment, a first end (or end portion) of each inductor 632 is coupled to a bonding pad 513 (e.g., Figure 1 Node 113), and the second end (or end) of each inductor 632 is coupled to bonding pad 515 (e.g., Figure 1 Node 115). Additionally, the first end of each capacitor 634 is coupled to bonding pad 513 (e.g., ). Figure 1 Node 113), and the second end of each capacitor 634 is coupled to bonding pad 515 (e.g., Figure 1 (Node 115). Therefore, in the IPD assembly 580, the inductor 632 and the capacitor 634 are coupled in parallel to each other between bonding pads 513 and 515.

[0131] exist Figure 8 and 9 In the embodiment, a first end (or end point) of each inductor 632 is coupled to a conductive node 813 (e.g., Figure 2 Node 113), and the second end (or end) of each inductor 632 is coupled to bonding pad 515 (e.g., Figure 2 Node 115). Additionally, the first end of each capacitor 634 is coupled to a conductive node 813 (e.g., ). Figure 2 Node 113), and the second end of each capacitor 634 is coupled to bonding pad 515 (e.g., Figure 2 (node ​​115). Therefore, in IPD assembly 580', inductor 632 and capacitor 634 are coupled in parallel to each other between conductive node 813 and bonding pad 515.

[0132] Despite Figure 6-9 In the inductor 632, the inductor 632 is depicted as an integrated spiral inductor, but in other embodiments, the inductor 632 may be a discrete component, or the inductor 632 may be replaced by one or more bond wires 632' (dashed lines indicate alternative embodiments), wherein a first end is electrically coupled to a bond pad 515 and a second end is electrically coupled to a bond pad 513. Figure 6 ) or conductive node 813 ( Figure 8According to an embodiment, one or more capacitors 634 of the FHR circuit 530 may be implemented as capacitors integrally formed with the IPD substrate of the IPD assemblies 580, 580'. For example, each capacitor 634 may be implemented as an integrated MIM capacitor, the integrated MIM capacitor comprising a first conductive electrode and a second conductive electrode (formed by a patterned portion of the conductive layer of the stacked structure 784) aligned with each other and electrically separated by the dielectric material of the stacked structure 784. In an alternative embodiment, one or more capacitors 634 may be implemented using discrete capacitors coupled to the top surface of the IPD assemblies 580, 580' or using another type of capacitor. According to an embodiment, the inductance value of one or more inductors 632 may be in the range of about 20 pH to about 1 nH, and the capacitance value of one or more capacitors 634 may be in the range of about 1 pF to about 300 nF, but the inductance and / or capacitance values ​​may also be lower or higher.

[0133] IPD assemblies 580, 580' may also include baseband termination circuitry 560 (e.g., Figure 1 , 2 The baseband termination circuit 560). In various embodiments, the baseband termination circuit 560 may have any of a variety of configurations, such as, but not limited to, those described above. Figures 3A-3F One of the configurations shown. In Figure 6-9 In the illustrated embodiment, each of the baseband termination circuits 560 has Figure 3F The topology of the baseband termination circuit 305. More specifically, in Figure 6 and 7 In one embodiment, the baseband termination circuit 560 includes components electrically connected to the bonding pad 513 (e.g., Figure 1 , 3F An envelope resistor 664 (e.g., which may correspond to or be coupled to nodes 113, 313 at the RF low impedance point) and a ground reference (e.g., flange 506) between the nodes and the ground reference (e.g., flange 506). Figure 3F Resistor 364), envelope inductor 662 (e.g., Figure 3F Inductor 362) and envelope capacitor 666 (e.g., Figure 3F A series combination of capacitors (366). Figure 8 and 9 In one embodiment, the baseband termination circuit 560 includes components electrically connected to the conductive node 813 (e.g., Figure 2 , 3F An envelope resistor 664 (e.g., which may correspond to or be coupled to nodes 113, 313 at the RF low impedance point) and a ground reference (e.g., flange 506) between the nodes and the ground reference (e.g., flange 506). Figure 3F Resistor 364), envelope inductor 662 (e.g., Figure 3FInductor 362) and envelope capacitor 666 (e.g., Figure 3F A series combination of capacitors (366).

[0134] Additionally, each baseband termination circuit 560 includes a bypass capacitor 678 connected in parallel with the envelope inductor 662 (e.g., Figure 3F Bypass capacitor 378). In Figure 6 and 8 In the embodiments, two instances of the parallel combination of envelope inductor 662 and bypass capacitor 678 are implemented on opposite sides of IPD assemblies 580, 580'. More specifically, in the illustrated embodiment, the parallel combination of envelope inductor 662 and capacitor 678 is connected in parallel between envelope resistor 664 and envelope capacitor 666. In alternative embodiments, baseband termination circuit 560 may include only one instance of the combination of envelope inductor 662 and capacitor 678 or more than two instances of the combination of envelope inductor 662 and capacitor 678.

[0135] exist Figure 6-9 In some embodiments, the envelope resistor 664 is integrally formed as part of the IPD assemblies 580, 580'. For example, each envelope resistor 664 may be a polysilicon resistor formed from or within a polysilicon layer on or within the stacked structure 784 and electrically coupled to the bonding pad 513. Figure 6 and 7 ) or conductive node 813 ( Figure 8 and 9 This is between the enveloping inductor 662 and the bypass capacitor 678 in parallel combination. In other alternative embodiments, the enveloping resistor 664 may be formed of tungsten silicide or another material, and may be a thick-film resistor or a thin-film resistor, or may be a discrete component coupled to the top surface of the IPD assembly 580, 580'.

[0136] Envelope inductor 662 can also be integrally formed as part of IPD assemblies 580, 580', such as Figure 6-9 As shown in the embodiments. For example, each envelope inductor 662 may be a patterned conductor formed from one or more portions of one or more conductive layers of a stacked structure 784, wherein a first end of the conductor is electrically coupled to an envelope resistor 664, and a second end of the conductor is electrically coupled to a first end of an envelope capacitor 666. In alternative embodiments, each envelope inductor 662 may be implemented as multiple bond wires or as a spiral inductor (e.g., on or near the top surface of IPD assemblies 580, 580') or as a discrete inductor coupled to the top surface of IPD assemblies 580, 580'.

[0137] In this embodiment, each bypass capacitor 678 is coupled in parallel with each envelope inductor 662. Each of the bypass capacitors 678 may be a discrete capacitor connected to the top surface of the IPD assemblies 580, 580', for example (e.g., using solder, conductive epoxy, or other means). More specifically, a first terminal of each bypass capacitor 678 may be electrically coupled to an envelope resistor 664 and to a first terminal of an envelope inductor 662, and a second terminal of each bypass capacitor 678 may be electrically coupled to a second terminal of an envelope inductor 662 and to a first terminal of an envelope capacitor 666.

[0138] For example, each bypass capacitor 678 may be a multilayer capacitor (e.g., a multilayer ceramic capacitor) with parallel interleaved electrodes and a surrounding terminal. Alternatively, each bypass capacitor 678 may be formed as part of a separate IPD (e.g., a MIM capacitor formed on a semiconductor substrate) or may be a capacitor integrally formed with the semiconductor substrate of the IPD assemblies 580, 580' (e.g., a MIM capacitor). Alternatively, each bypass capacitor 678 may be implemented as some other type of capacitor capable of providing the desired capacitance to the baseband termination circuit 560.

[0139] Envelope capacitor 666 is electrically coupled between a ground reference node (e.g., a conductive layer 786 at the bottom surface of each IPD assembly 580, 580') and a parallel combination of envelope inductor 662 and bypass capacitor 678. For example, capacitor 666 may be a MIM capacitor integrally formed with the IPD substrate of IPD assemblies 580, 580'. In some embodiments, capacitor 666 may be formed in a stacked structure 784 completely above semiconductor substrate 782, or capacitor 666 may have portions extending into or otherwise coupled to or in contact with semiconductor substrate 782. According to embodiments, capacitor 666 may be formed of a first electrode, a second electrode, and a dielectric material between the first and second electrodes. The dielectric material of capacitor 666 may include one or more layers of polysilicon, various oxides, nitrides, or other suitable materials. In various embodiments, the first and second electrodes of capacitor 666 may include horizontal portions of a conductive layer (e.g., portions parallel to the top and bottom surfaces of IPD assemblies 580, 580') and / or vertical portions of interconnects of the conductive layers (e.g., portions parallel to the sides of IPD assemblies 580, 580'). Additionally, the first and second electrodes of capacitor 666 may be formed of a metal layer and / or of a conductive semiconductor material (e.g., polysilicon). Alternatively, the enveloping capacitor 666 may be a discrete capacitor (e.g., using solder, conductive epoxy, or other means) connected to the top surface of IPD assemblies 580, 580'. As those skilled in the art will understand based on the description herein, although... Figure 7 , 9 The diagram shows specific double-plate capacitor structures for capacitors 614, 634, and 666, but various other capacitor structures can be used instead.

[0140] Moreover, as discussed above, the bias circuit (e.g., Figure 1 , 2 The bias circuit 190 can also be coupled to the control terminal (e.g., the gate terminal) of the transistor 730, and in one embodiment, this connection is made via IPD assemblies 580, 580'. More specifically, in an embodiment, at least one first end of a bonding wire 692 can also be connected to the conductive bonding pad 513. Figure 6 ) or conductive node 813 ( Figure 8 ), and the second end of the bonding wire 692 is connected to the bias lead (e.g., Figure 5The bias lead 592). When a bias voltage is provided to the bias lead via an external bias circuit, the bias voltage can be delivered to the gate of the FET 730 within the transistor die 540 via the bonding wire 692, conductive bonding pad 513 or conductive node 813, FHR circuit 530, bonding wire 616, and conductive bonding pad 642. According to an embodiment, the bonding wire 692 and the bias lead (e.g., Figure 5 The inductance of the series combination of bias leads 592 can be in the range of about 500 pH to about 3000 pH, but the inductance can also be lower or higher.

[0141] Figure 5-9 An embodiment of an RF amplifier device is shown, comprising input and output leads coupled to a substrate (e.g., using intermediate electrical isolation) and a transistor die coupled to the substrate between the input and output leads. Such an RF amplifier device may be particularly suitable for high-power amplification. Those skilled in the art will understand, based on the description herein, that various embodiments can also be implemented using different packages or constructions. For example, one or more amplification paths including embodiments of the subject matter of this invention may be coupled to a substrate such as a PCB, a leadless package (e.g., a quad flat no-lead (QFN) package), or another type of package. In such embodiments, the inputs and outputs of one or more amplification paths may be implemented using conductive solder pads or other input / output (I / O) structures. This implementation may be particularly suitable for low-power amplification systems, such as relatively low-power Dougherty amplifiers, where the main amplification path and peaking amplification path (including bare transistor dies, IPDs, bias circuitry, etc.), power dividers, delay and impedance inverting elements, combiners, and other components may be coupled to the substrate. It should be understood that embodiments of the subject matter of this invention are not limited to the embodiments shown.

[0142] Figure 10 This is according to various example embodiments for manufacturing packaged RF power amplifier devices (e.g., Figure 5 The flowchart of a method for a packaged RF power amplifier device (500) is shown, wherein the packaged RF power amplifier device includes an input impedance matching circuit and an output impedance matching circuit, an input-side baseband termination circuit and an output-side baseband termination circuit, and an input-side fractional harmonic resonator circuit (e.g., Figures 3A-3F Embodiments of circuits 300-305, 510, 510', 511, 511', 530, 531, 550, 551, 560-563 (5). The method may begin in blocks 1002-1004 with the formation of one or more IPD assemblies. More specifically, in block 1002, one or more input and output IPDs (e.g., Figure 5-9(IPDs 580, 580', 581, 581', 582, 583). According to an embodiment, each input IPD (e.g., IPDs 580, 580', 581, 581') includes components of an impedance matching circuit, a baseband termination circuit, and a fractional harmonic resonator circuit, such as in combination. Figure 6-9 Detailed description.

[0143] In addition to forming the passive components of each IPD, forming each IPD also includes forming various conductive features (e.g., conductive layers and vias) that facilitate electrical connections between the various components of each circuit. For example, forming an IPD may also include forming various accessible connection nodes on the surface of the substrate of each IPD. As previously discussed, connection nodes may include conductive bonding pads that can accept inductive elements (e.g., Figure 6-9 The attachment of bonding lines 612, 616. Additionally, in block 1004, some components corresponding to various circuit elements (e.g., Figure 6-9 When capacitors 614, 634, 666, 678, 820 are implemented as discrete components (rather than integrated components), these discrete components can be coupled to conductors exposed on the surface of each IPD to form one or more IPD assemblies.

[0144] In block 1006, for the air cavity embodiment, an isolation structure (e.g., Figure 5 An isolation structure 508) is coupled to a device substrate (e.g., flange 506). Additionally, one or more active devices (e.g., transistor dies 540, 541) and an IPD assembly (e.g., Figure 5-9 IPD assemblies 580, 580', 581, 581', 582, 583 are coupled to a portion of the top surface of the substrate, said portion being exposed through an opening in the isolation structure. Leads (e.g., input and output leads 502-505 and bias leads 592-595, if included) are coupled to the top surface of the isolation structure. For overmolded (e.g., encapsulated) device embodiments, the isolation structure may be omitted, and the substrate and leads may form a portion of a lead frame.

[0145] In block 1008, one or more input leads, one or more transistors, one or more IPD assemblies, and one or more output leads are electrically coupled together. For example, as previously discussed, electrical connections can be made using bond wires between the various device components and elements. For example, some of the bond wires correspond to inductor components of the input matching circuit or output matching circuit (e.g., Figure 5-9(The bonding lines 612, 616). Finally, in block 1010, the device is capped (e.g., for an air cavity package) or encapsulated (e.g., for a molded package, using a molding compound). The device can then be integrated into a larger electrical system (e.g., a Dougherty amplifier or other type of electrical system).

[0146] One embodiment of an RF amplifier includes a transistor, an input impedance matching circuit (e.g., a single-segment T-matching circuit and a multi-segment bandpass circuit), and a fractional harmonic resonator circuit. The input impedance matching circuit is coupled between an amplification path input and a transistor input. The input of the fractional harmonic resonator circuit is coupled to the amplification path input, and the output of the fractional harmonic resonator circuit is coupled to the transistor input. The fractional harmonic resonator circuit is configured to resonate at a resonant frequency between the fundamental operating frequency and the second harmonic frequency of the RF amplifier. According to another embodiment, the fractional harmonic resonator circuit resonates at a fraction x of the fundamental frequency, wherein the fraction is between 1.25 and 1.9 (e.g., x ≈ 1.5).

[0147] An embodiment of a packaged radio frequency (RF) amplifier device includes a device substrate, input and output leads coupled to the device substrate, a transistor die coupled to the device substrate, an input impedance matching circuit, and a fractional harmonic resonator circuit. The transistor die includes a transistor, a transistor input, and a transistor output coupled to the output lead. The input impedance matching circuit is coupled between the input lead and the transistor input. The fractional harmonic resonator circuit has an input and an output, wherein the input of the fractional harmonic resonator circuit is coupled to the input lead, and the output of the fractional harmonic resonator circuit is coupled to the transistor input. The fractional harmonic resonator circuit is configured to resonate at a resonant frequency between the fundamental operating frequency and the second harmonic frequency of the RF amplifier. According to another embodiment, the fractional harmonic resonator circuit resonates at a fraction x of the fundamental frequency, wherein the fraction is between 1.25 and 1.9 (e.g., x ≈ 1.5).

[0148] The preceding specific embodiments are merely illustrative in nature and are not intended to limit the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as exemplary is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, it is not intended to be limited by any express or implied theory presented in the preceding technical field, background art, and specific embodiments.

[0149] The connecting lines shown in the various figures included herein are intended to illustrate exemplary functional relationships and / or physical couplings between various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in embodiments of this subject matter. Furthermore, certain terms may be used herein for reference only and are therefore not intended to be limiting, and the terms “first,” “second,” and other such numerical terms relating to structures do not imply a sequence or order unless the context clearly indicates otherwise.

[0150] As used herein, "node" means any internal or external reference point, connection point, junction, signal line, conductive element, etc., where a given signal, logic level, voltage, data pattern, current, or quantity exists. Furthermore, two or more nodes can be implemented by a single physical element (and even when receiving or outputting at a common node, two or more signals can be multiplexed, modulated, or otherwise distinguished).

[0151] The foregoing description refers to elements, nodes, or features being "connected" or "coupled" together. As used herein, unless explicitly stated otherwise, "connected" means that one element is directly and not necessarily mechanically linked to (or directly connected to) another element. Similarly, unless explicitly stated otherwise, "coupled" means that one element is directly or indirectly and not necessarily mechanically connected to (or directly or indirectly connected to) another element via electrical or other means. Therefore, although the schematic diagrams shown in the accompanying drawings depict an exemplary arrangement of elements, additional intermediate elements, devices, features, or components may be present in embodiments of the depicted subject matter.

[0152] While at least one exemplary embodiment has been presented in the foregoing detailed descriptions, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed descriptions will provide those skilled in the art with a convenient roadmap for implementing one or more of the described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, including equivalents known or foreseeable at the time of filing this patent application.

Claims

1. A radio frequency (RF) amplifier, characterized in that, include: A transistor having a transistor input terminal; An input impedance matching circuit is coupled between the first input of the first amplification path and the input terminal of the transistor. as well as A fractional harmonic resonator circuit has an input and an output, wherein the input of the fractional harmonic resonator circuit is coupled to a first input of a first amplification path, wherein the output of the fractional harmonic resonator circuit is coupled to an input of a transistor, and wherein the fractional harmonic resonator circuit is configured to resonate at a resonant frequency between the fundamental operating frequency of the RF amplifier and the second harmonic of the fundamental operating frequency. The input impedance matching circuit has a single-segment T-matching topology, which includes: First connection node; Second connection node; A second capacitor, coupled between the first connection node and the ground reference node; and A second inductor element is coupled between the second connection node and the transistor input terminal, and The fractional harmonic resonator circuit is electrically coupled between the first connection node and the second connection node.

2. The RF amplifier according to claim 1, characterized in that, The fractional harmonic resonator circuit resonates at a fraction x of the fundamental operating frequency, wherein the fraction is between 1.25 and 1.

9.

3. The RF amplifier according to claim 2, characterized in that, The score is between 1.4 and 1.

6.

4. The RF amplifier according to claim 1, characterized in that, The fractional harmonic resonator circuit is a parallel inductor-capacitor (LC) circuit, which includes: A first inductor element, the first inductor element having a first terminal electrically connected to the first input and a second terminal electrically connected to the transistor input terminal; and The first capacitor is connected in parallel with the first inductor.

5. The RF amplifier according to claim 1, characterized in that, The fractional harmonic resonator circuit is coupled within the input impedance matching circuit.

6. The RF amplifier according to claim 1, characterized in that, In addition, including: A third inductor element is coupled between the first input and the first connection node.

7. The RF amplifier according to claim 6, characterized in that: The third inductor element includes a first plurality of bonding wires connecting the first input and the first connection node; and The second inductor element includes a second plurality of bonding wires connected between the second connection node and the transistor input terminal.

8. A radio frequency (RF) amplifier, characterized in that, include: A transistor having a transistor input terminal; An input impedance matching circuit is coupled between the first input of the first amplification path and the input terminal of the transistor. as well as A fractional harmonic resonator circuit has an input and an output, wherein the input of the fractional harmonic resonator circuit is coupled to a first input of a first amplification path, wherein the output of the fractional harmonic resonator circuit is coupled to an input of a transistor, and wherein the fractional harmonic resonator circuit is configured to resonate at a resonant frequency between the fundamental operating frequency of the RF amplifier and the second harmonic of the fundamental operating frequency. The input impedance matching circuit has a multi-segment bandpass topology, which includes: First connection node; Second connection node; Third connection node; A second inductor element is coupled between the first connection node and the ground reference node; A second capacitor is coupled between the first connection node and the second connection node; A third capacitor, coupled between the second connection node and the ground reference node; and A third inductor element, the third inductor element being coupled between the third connection node and the transistor input terminal, and The fractional harmonic resonator circuit is electrically coupled between the second connection node and the third connection node.

9. A packaged radio frequency (RF) amplifier device, characterized in that, include: Device substrate; An input lead is coupled to the device substrate; An output lead, the output lead being coupled to the device substrate; A transistor die coupled to the device substrate, wherein the transistor die includes a transistor, a transistor input terminal, and a transistor output terminal coupled to the output lead; An input impedance matching circuit is coupled between the input lead and the transistor input terminal. as well as A fractional harmonic resonator circuit has an input and an output, wherein the input of the fractional harmonic resonator circuit is coupled to an input lead, and the output of the fractional harmonic resonator circuit is coupled to an input terminal of a transistor, and wherein the fractional harmonic resonator circuit is configured to resonate at a resonant frequency of a fraction x, which is a fundamental operating frequency, wherein the fraction is between 1.25 and 1.

9. The input impedance matching circuit has a single-segment T-matching topology, which includes: a first connection node; a second connection node; a second capacitor coupled between the first connection node and a ground reference node; and a second inductor coupled between the second connection node and the transistor input terminal, wherein the fractional harmonic resonator circuit is electrically coupled between the first connection node and the second connection node.

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