Method and apparatus for estimating sampling clock phase mismatch error

Abstract

The application provides a sampling clock phase mismatch error estimation method and device, which comprises the following steps: dividing the proportional relationship between the modulo square subtraction estimator and the TIADC sampling clock phase mismatch error into several intervals according to frequency; counting the slope and bias value of the proportional line segment corresponding to the sampling clock phase mismatch error and the estimation value at each interval frequency boundary point; in real-time estimation of the sampling clock phase mismatch error, the slope of the proportional line segment corresponding to the real-time estimation frequency is obtained by converting the error estimation value obtained by the modulo square subtraction estimator, the bias value of the frequency is estimated by linear interpolation, and the actual error value of the sampling clock phase mismatch is estimated by the slope and the bias value. In the application, the slope and the bias value of the proportional line segment of the frequency point are counted and stored offline, the real-time slope and bias value are obtained by linear interpolation in actual estimation, the estimation accuracy is improved, and the processing complexity is not excessively increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication, in particular to a sampling clock phase mismatch error estimation method and device. BACKGROUND

[0002] In the 5G mobile communication system, the system rate has been greatly improved compared with the 4G, and the base station and the terminal have higher performance requirements for the ADC. Time-interleaved ADC (TIADC) is the mainstream technology of high-speed and high-performance ADC, and TIADC is usually the first choice for ADC in the 5G system.

[0003] TIADC is composed of multiple sub-ADCs with the same resolution, each ADC alternately samples and converts the input signal, and finally a multiplexer (MUX) alternately outputs the outputs of each sub-ADC to multiply the sampling rate. As shown in Figure 1 , an M-channel TIADC composed of M parallel sub-ADCs, the sampling rate of each sub-ADC is f S / M, each sub-ADC samples the analog input signal periodically through its own sample-and-hold circuit (S / H), and the sampling time of the mth sub-channel is t m =nMT s +mT s , where n=0, 1, 2,..., m=0, 1, 2,..., M-1, T s is the sampling period, and then the output of the sub-ADC is reconstructed by the MUX to obtain the overall sampling frequency f s which is M times the sampling frequency of the sub-ADC.

[0004] Due to the difficulty in achieving complete symmetry and matching in the layout design of multiple channels, and due to the changes in temperature, voltage and other environmental conditions during chip manufacturing, mismatch will occur between the sub-channels of the TIADC. In order to achieve high-speed and high-performance TIADC and meet the ADC requirements of the 5G mobile communication system, it is necessary to estimate and compensate for these mismatches, otherwise the overall system performance will be seriously affected. The mismatch in the TIADC system usually includes three types: bias mismatch, gain mismatch, and sampling clock phase mismatch. Among the three types of mismatch errors, the introduction of bias and gain errors will cause regular changes in the output signal, while the sampling clock phase mismatch error is mainly caused by aperture jitter and inconsistent time delay between sub-channels. Even if the sampling clock phase mismatch error of each channel is fixed, as the input signal frequency increases, the final sampling clock phase mismatch error will also increase, and this characteristic of changing with the input signal frequency cannot be directly identified from the output result, so its influence on the system performance is much greater than that of the bias error and the gain error.

[0005] For the sampling clock phase mismatch error estimation, generally practical is a full-digital blind adaptive estimation, and a modulus square subtraction method is a commonly used method for the full-digital blind adaptive estimation, which considers that the modulus square subtraction estimation element and the estimation of the sampling clock phase mismatch error present a certain linear proportional relationship, and the specific error value is estimated therefrom. However, with the increase of the number of sub-ADCs, the linear proportion is not very strict, and the estimation error also becomes large. SUMMARY

[0006] Embodiments of the present application provide a sampling clock phase mismatch error estimation method and device, to at least solve the problem in the modulus square subtraction method for the sampling clock phase mismatch error estimation in the related art, that with the increase of the number of sub-ADCs, the estimation error also becomes large.

[0007] According to an embodiment of the present application, a sampling clock phase mismatch error estimation method is provided, comprising: dividing the proportional relationship corresponding to the TIADC sampling clock phase mismatch error of the modulus square subtraction estimation element into several intervals according to frequency; statistically calculating the slope and bias value of the proportional line segment corresponding to the actual sampling clock phase mismatch error and the estimation value at the frequency division point of each interval; in the real-time estimation of the TIADC sampling clock phase mismatch error, the slope of the proportional line segment corresponding to the frequency is calculated according to the error estimation value obtained by the modulus square subtraction estimation element, the bias value of the frequency is estimated by interpolation according to the statistically calculated slope and bias value, and the actual error value of the sampling clock phase mismatch is estimated according to the slope and bias value.

[0008] Optionally, dividing the proportional relationship corresponding to the TIADC sampling clock phase mismatch error of the modulus square subtraction estimation element into several intervals according to frequency comprises: dividing the range of the actual sampling clock phase mismatch error of the TIADC according to equal intervals according to frequency, wherein the corresponding proportion of each interval is approximately linear.

[0009] Optionally, statistically calculating the slope and bias value of the proportional line segment corresponding to the actual sampling clock phase mismatch error and the estimation value at the frequency division point of each interval comprises: statistically calculating the estimation value of each sampling clock phase mismatch error point according to the estimation element line of the modulus square subtraction method; linearly fitting each actual sampling clock phase mismatch error point and the corresponding estimation value to obtain the slope and bias value of the sampling clock phase mismatch error line segment at each frequency point; and storing the corresponding slope and bias value of each frequency point.

[0010] Optionally, the error estimation value obtained by the modulus square subtraction estimation algorithm is used to convert the slope of the proportional line segment corresponding to the frequency, and the bias value is estimated by interpolation according to the statistical slope and the bias value, including: the estimation value obtained by the modulus square subtraction estimation algorithm is used to convert the slope of the proportional line segment corresponding to the frequency; the slope range corresponding to the frequency is queried in the statistical slope, and the bias value of the range boundary point is obtained; the bias value of the frequency is estimated by interpolation according to the linear relationship between the slope and the bias value.

[0011] Optionally, the proportional relationship between the modulus square subtraction estimation algorithm and the TIADC sampling clock phase mismatch error is divided into several intervals according to the frequency, including: the frequencies corresponding to the boundary points of the (M+1) intervals are: f0, f1,..., f i , f i+1 ,..., f M-1 . i For frequency f s , the actual sampling clock phase mismatch error range is divided into 2N equal intervals, and each actual sampling clock phase mismatch error point is: Where T -N is the system sampling period, and a is a constant.

[0012] Optionally, the slope and bias value of the proportional line segment corresponding to the actual sampling clock phase mismatch error and the estimation value at the frequency boundary point of each interval are statistically obtained offline, and the statistical slope and bias value are stored, including: the estimation value of the modulus square subtraction estimation algorithm is obtained by statistics, and the estimation value of each sampling clock phase mismatch error point is s -(N-1) , s -1 ,..., s (N-1) , 0, s1,..., s N ; each actual sampling clock phase mismatch error point and the corresponding estimation value s -N , s -(N-1) ,..., s -1 , 0, s1,..., s (N-1) , s N are linearly fitted to obtain the slope k i of the sampling clock phase mismatch error line segment at frequency f i and the bias value b i when the sampling clock phase mismatch error is 0; the same operation is performed on other frequencies to obtain the slope of the sampling clock phase mismatch error line segment at different frequencies and the bias value when the sampling clock phase mismatch error is 0; the slopes k0, k1,..., k i corresponding to each frequency point f0, f1,..., f i+1 , f M-1 are obtained.i , k i+1 ,..., k M-1 and bias values b0, b1,..., b i , b i+1 ,..., b M-1 are stored.

[0013] Optionally, before the error estimate value obtained by the modulus square subtraction estimator is converted into the slope of the corresponding proportional line segment at the frequency, the corresponding slope range is found in the offline statistical slope, and the bias value of the range boundary point is obtained, the bias value of the frequency is estimated by interpolation, comprising: the estimate value obtained by the modulus square subtraction estimator is converted into the slope k of the corresponding proportional line segment at the frequency; the obtained slope k is inquired in k0, k1,..., k i , k i+1 ,..., k M-1 , to find that the corresponding slope range is located between k i , k i+1 ; the bias value b of the frequency is estimated by interpolation as follows:

[0014]

[0015] Optionally, before the error estimate value obtained by the modulus square subtraction estimator is converted into the slope of the corresponding proportional line segment at the frequency, the input signal is sampled by the TIADC, and the modulus square subtraction method is used to calculate the error estimate value.

[0016] Optionally, after the actual error value of the sampling clock phase mismatch is estimated by the slope and the bias value, the estimated actual error value of the sampling clock phase mismatch is output to the compensator for error compensation.

[0017] According to another embodiment of the application, a sampling clock phase mismatch error estimation device is provided, comprising: a partition module for partitioning the proportional relationship between the modulus square subtraction estimator and the TIADC sampling clock phase mismatch error according to frequency into several intervals, wherein the corresponding proportion of each interval is approximately linear; a statistical module for offline statistics of the slope and bias value of the actual sampling clock phase mismatch error and the estimate value corresponding to the proportional line segment at the frequency boundary point of each interval, and storing the offline statistical slope and bias value; an estimation module for real-time estimation of the TIADC sampling clock phase mismatch error, wherein the error estimate value obtained by the modulus square subtraction estimator is converted into the slope of the corresponding proportional line segment at the frequency, the corresponding slope range is found in the offline statistical slope, the bias value of the range boundary point is obtained, the bias value of the frequency is estimated by interpolation, and the actual error value of the sampling clock phase mismatch is estimated by the slope and the bias value.

[0018] Optionally, the partitioning module includes: a partitioning unit, used for dividing the (M+1) intervals into intervals with corresponding frequencies of: f0, f1, ..., f i f i+1 , ..., f M-1 For frequency point f i The actual sampling clock phase mismatch error range is divided into 2N equal intervals, and the phase mismatch error points of each actual sampling clock are as follows: Where T s Let be the system sampling period, and 'a' be a constant.

[0019] Optionally, the statistical module includes: a statistical unit for estimating the modulus subtraction method. The estimated value of each sampling clock phase mismatch error point was obtained through statistical analysis, and the value was s. -N s -(N-1) , ..., s -1 ,0,s1,...,s (N-1) s N The fitting unit is used to match the phase mismatch error points of each actual sampling clock. and the corresponding estimated value s -N s -(N-1) , ..., s -1 ,0,s1,...,s (N-1) s N Perform linear fitting to obtain the frequency point f i The slope k of the downsampling clock phase mismatch error segment i And the bias value b when the sampling clock phase mismatch error is 0 i The acquisition unit performs the same operation on other frequency points to obtain the slope of the sampling clock phase mismatch error line segment at different frequency points and the offset value when the sampling clock phase mismatch error is 0; the storage unit is used to store f0, f1, ..., f i f i+1 , ..., f M-1 The slopes k0, k1, ..., k corresponding to each frequency point i k i+1 , ..., k M-1 and bias values ​​b0, b1, ..., b i b i+1 , ..., b M-1 Store it.

[0020] Optionally, the estimation module includes: a conversion module, used to convert the estimated value obtained by the modulus-square subtraction estimation operator to the slope k of the corresponding proportional line segment at that frequency; and a query module, used to query the obtained slope k in k0, k1, ..., k i ki+1 , ..., k M-1 The query found the corresponding slope range located at k. i k i+1 Between; the interpolation module is used to estimate the offset value b at this frequency through the following interpolation:

[0021]

[0022] Optionally, the device further includes: a sampling module, used to sample the input signal before calculating the slope of the corresponding proportional line segment at the frequency based on the error estimate, and to calculate the error estimate using the modulus-square subtraction method.

[0023] Optionally, the device further includes an output module for outputting the estimated actual error value of the sampling clock phase mismatch to a compensator for error compensation.

[0024] According to yet another embodiment of the present invention, a storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

[0025] According to yet another embodiment of the present invention, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0026] In the above embodiments of the present invention, the slope and bias of the proportional line segment of the frequency point are statistically stored offline, and the real-time slope and bias values ​​are obtained by linear interpolation in actual estimation. This improves the estimation accuracy to meet the system's high-speed and high-performance requirements for the ADC without excessively increasing the processing complexity. Attached Figure Description

[0027] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0028] Figure 1 This is a schematic diagram of the TIADC architecture based on existing technology;

[0029] Figure 2 This is a flowchart of a sampling clock phase mismatch error estimation method according to an embodiment of the present invention;

[0030] Figure 3 This is a flowchart of blind adaptive processing according to an embodiment of the present invention;

[0031] Figure 4is a flow chart of offline slope and bias of a line according to an embodiment of the present application;

[0032] Figure 5 is a schematic diagram of two-channel TIADC clock sampling point position according to an embodiment of the present application;

[0033] Figure 6 is a schematic diagram of a sampling clock phase mismatch error estimation device structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] Hereinafter, the present application will be described in detail with reference to the accompanying drawings and embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0035] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0036] In the present embodiment, a sampling clock phase mismatch error estimation method is provided, Figure 2 is a method flow chart according to an embodiment of the present application, as Figure 2 shown, the flow includes the following steps:

[0037] Step S202, divide the proportional relationship corresponding to the TIADC sampling clock phase mismatch error estimation value into several intervals according to the frequency, wherein the corresponding proportion of each interval is approximately linear;

[0038] Step S204, offline statistics of the slope and bias value of the actual sampling clock phase mismatch error and the estimation value corresponding to the proportional line segment at the frequency division point of each interval, and store the offline statistics of the slope and bias value;

[0039] Step S206, in the real-time estimation of the TIADC sampling clock phase mismatch error, the slope of the corresponding proportional line segment at this frequency is obtained according to the error estimation value obtained by the estimation value of the modulus square subtraction, the corresponding slope range is found in the offline statistics of the slope, and the bias value of the range division point is obtained, the bias value of this frequency is estimated by interpolation, and the actual error value of the sampling clock phase mismatch is estimated by the slope and bias value.

[0040] In step S202 of the present embodiment, the frequencies corresponding to the division points of the (M+1) intervals are assumed to be: f0, f1,..., f i , f i+1 ,..., f M-1 , for the frequency f iThe actual sampling clock phase mismatch error range is divided into 2N equal intervals, and the phase mismatch error points of each actual sampling clock are as follows: Where T s Let be the system sampling period, and 'a' be a constant.

[0041] In step S204 of this embodiment, the estimation operator is based on the modulus subtraction method. The estimated value of each sampling clock phase mismatch error point was obtained through statistical analysis, and the value was s. -N s -(N-1) , ..., s -1 ,0,s1,...,s (N-1) s N ; to identify the phase mismatch error points of each actual sampling clock and the corresponding estimated value s -N s -(N-1) , ..., s -1 ,0,s1,...,s (N-1) s N Perform linear fitting to obtain the frequency point f i The slope k of the downsampling clock phase mismatch error segment i And the bias value b when the sampling clock phase mismatch error is 0 i Perform the same operation on other frequencies to obtain the slope of the sampling clock phase mismatch error line segment at different frequencies and the offset value when the sampling clock phase mismatch error is 0; then set f0, f1, ..., f i f i+1 , ..., f M-1 The slopes k0, k1, ..., k corresponding to each frequency point i k i+1 , ..., k M-1 and bias values ​​b0, b1, ..., b i b i+1 , ..., b M-1 Store it.

[0042] In step S206 of this embodiment, the slope k of the corresponding proportional line segment at that frequency is calculated based on the estimated value obtained from the modulus-square subtraction estimation operator; the obtained slope k is then used in k0, k1, ..., k i k i+1 , ..., k M-1 The query found the corresponding slope range located at k. i k i+1 Between; the offset value b at this frequency is estimated by the following interpolation:

[0043]

[0044] Before step S106 of the embodiment, the TIADC can also sample the input signal and calculate the error estimation value by using the modulus square subtraction method.

[0045] After step S106 of the embodiment, the actual error value of the estimated sampling clock phase mismatch can be output to a compensator for error compensation.

[0046] In the above embodiment of the application, the problem that the estimation error increases with the increase of the number of sub-ADCs is solved by the above steps, the estimation precision is improved to meet the high-speed and high-performance requirements of the system on the ADC, and the processing complexity is not excessively increased.

[0047] In order to facilitate the understanding of the embodiments of the application, the following will be described in combination with specific application embodiments.

[0048] In the embodiment, a new sampling clock phase mismatch error estimation method is provided, as shown in Figure 3 The method of the embodiment mainly includes the following steps:

[0049] Step S301, sampling the input signal, the sampling points are x1, x2 and x3, and the first error estimation value is calculated by using the modulus square subtraction method

[0050] Step S302, based on the initial slope k0 and the bias b0 of the corresponding proportional line segment of the calculation error value and the actual error value, the first actual error estimation value e=(c1-b0) / k0 is calculated;

[0051] Step S303, output to the compensator for the first error compensation;

[0052] Step S304, for the compensated sampling signal, the second error estimation value is calculated by using the modulus square subtraction method

[0053] Step S305, based on the estimation value, the slope k of the second estimation is calculated k=1-(c2-b0) / (c1-b0);

[0054] Step S306, the bias b of the second estimation is calculated by interpolation b=(b i+1 +Ab i ) / (1+A);

[0055] Step S307, the second actual error estimation value e=(c2-b) / k is calculated;

[0056] Step S308, output to the compensator for the second error compensation.

[0057] Wherein, the initial slope and bias of the proportional line segment corresponding to the error value and the actual error value are obtained by line statistics, see Figure 4 As shown, it is necessary to segment long time statistics of the slope and bias value of each frequency point. Specifically, it includes the following steps:

[0058] Step S401, select M frequency points to be counted, assuming that the demarcation points of (M+1) intervals correspond to frequencies: f0, f1,..., fM. i , f i+1 ,..., f M-1 , the required sampling clock phase mismatch error range [-aT s , aT s ] of the system, wherein T s is the sampling period of the system, and a is a constant. For each frequency point, the bias value of each sampling clock phase mismatch error point is scanned and counted within the required sampling clock phase mismatch error range of the system.

[0059] Step S402, for example, for f i , the actual sampling clock phase mismatch error range is divided into 2N equal intervals, and each actual sampling clock phase mismatch error point is:

[0060] Step S403, the estimation value of the modulo square subtraction method After long-term statistics, the estimation value of each sampling clock phase mismatch error point is s -N , s -(N-1) ,..., s -1 , 0, s1,..., s (N-1) , s N .

[0061] Step 404, linear fitting is performed on each actual sampling clock phase mismatch error point and the corresponding estimation value s -N , s -(N-1) ,..., s -1 , 0, s1,..., s (N-1) , s N , so that the slope k i of the sampling clock phase mismatch error line segment of f i and the bias value b i when the sampling clock phase mismatch error is 0 can be obtained.

[0062] Step S405, similar operations are performed on other frequency points to obtain the slope of the sampling clock phase mismatch error line segment of different frequency points and the bias value when the sampling clock phase mismatch error is 0.

[0063] Step S406, finally f0, f1, ..., f i f i+1 , ..., f M-1 The slopes k0, k1, ..., k corresponding to each frequency point i k i+1 , ..., k M-1 and bias values ​​b0, b1, ..., b i b i+1 , ..., b M-1 Store it.

[0064] In this embodiment, the proportional relationship between the modulus-square subtraction estimation operator and the sampling clock phase mismatch error is divided into several intervals according to frequency, with the corresponding proportion in each interval being approximately linear. For an extended period offline, the slope and offset values ​​of the proportional line segment corresponding to the actual sampling clock phase mismatch error and the estimated value at each interval's frequency boundary are statistically analyzed and stored for subsequent real-time estimation. In real-time estimation, the slope of the corresponding proportional line segment at that frequency is first calculated based on the estimated value obtained from the modulus-square subtraction estimation operator. Then, the corresponding slope range is found from the previously stored slopes, and the offset value at the boundary of that range is obtained. Next, the offset value at that frequency is estimated through interpolation. Finally, the actual error value of the sampling clock phase mismatch is estimated using the slope and offset value.

[0065] The technical solution provided in this embodiment is particularly suitable for scenarios with a large number of sub-ADC channels. The actual estimated frequency is not limited to a single audio point, but is also applicable to comprehensive frequency scenarios with multiple audio points.

[0066] The following section will describe in detail the specific implementation process of this embodiment, combining the modular subtraction method and its blind adaptive processing in the existing technology.

[0067] I. Modular Square Subtraction Method

[0068] The following uses a two-channel TIADC as an example to illustrate the modulus-square subtraction method. Figure 5 As shown, assuming the system's bias mismatch and gain mismatch are corrected, when there is no sampling time phase mismatch between the two channels, the sampling points for the input signal in channel 1 and channel 2 are x1 and x'2, respectively. When the system has a sampling clock phase mismatch error Δτ (much smaller than the sampling clock period T),... s When the sampling time is Δτ, the actual sampling points of channels 1 and 2 are x1 and x2, respectively. In the figure, x3 is the sampling point of channel 1 in the next cycle. If channel 1 is taken as the reference channel, the actual sampling time point x2 of channel 2 deviates from the ideal sampling time point x'2 by a time value of Δτ. For an input signal whose amplitude varies with time, the existence and magnitude of Δτ cause the value of the sampling point of channel 2 to change.

[0069] To find the relationship between Δτ and the sampling points x1 and x2, the difference (x2-x1) and (x3-x2) of the outputs of channel 1 and channel 2 is made respectively, and the mathematical expectation of the square of the two items is taken, that is, formula (1):

[0070]

[0071] where σ 2 represents the average power of each sampling point, assuming that each path is the same, x(t1) represents the sampling at t1, and T s represents the sampling period. The last term is the expectation of the cross-correlation function of adjacent sampling points, denoted as R(T s + Δτ),

[0072] Then formula (1) can be written as:

[0073]

[0074] Similarly,

[0075]

[0076] Subtracting formula (2) from formula (3), when Δτ is very small, the cross-correlation function can be expanded by Taylor series, and only the first derivative term is retained, to obtain

[0077]

[0078] where R'(T S + Δτ) is the first derivative of R(T s + Δτ). From a statistical point of view, when the sample size is large enough, R'(T S + Δτ) can be regarded as a certain value for a certain input frequency of a TIADC system. Thus, there is a fixed proportional relationship between the measure on the left side of the equation and Δτ, which is the basic estimator of the modulus square subtraction method.

[0079] In an embodiment of the present application, taking the multi-channel scenario with a large number of ADCs as an example, the above-mentioned 2-channel TIADC is expanded to 8 channels, the 0th channel is taken as the reference, the error of the 4th channel is estimated first, after calibration, the errors of the 2nd and 6th channels are estimated, and finally the errors of the 1st, 3rd, 5th and 7th channels are estimated, and then the estimator of the modulus square subtraction method can be written as:

[0080]

[0081] II. Blind adaptive processing

[0082] In actual system, the input signal frequency cannot be known, and blind adaptive estimation is needed. Because of the formula (4) of the modulus subtraction method, although the input signal frequency and the error estimation mean value are linearly proportional, the error value cannot be directly obtained. Because the slope of the proportional line segment increases with the increase of the frequency, and the value of the line segment at different frequencies is also different when there is no error, blind adaptive estimation is needed.

[0083] Based on the modulus subtraction method, it is assumed that the first estimation value of the left side of the formula (4) after multiple averaging is c1=E[(x2-x1) 2 ]-E[(x3-x2) 2 ], and then the first compensation is performed, and the second estimation value after multiple averaging is c2=E[(x2-x1) 2 ]-E[(x3-x2) 2 ], and the actual sampling clock phase mismatch error value is e. If the formula (4) is linearly proportional, the estimation value and the error value are respectively taken as the ordinate and the abscissa of the proportional line segment, the slope of the proportional line segment is k, and the bias is b. For blind processing, the initial value of the slope k0 and the initial value of the bias b0 in the first estimation are respectively obtained by offline statistics and set, and then the actual sampling clock phase mismatch error value output by the first estimation is:

[0084] e=(c1-b0) / k0 (6)

[0085] After the e is sent to the error compensator after the error estimation, the first compensation is performed, and then the actual sampling clock phase mismatch error value output by the second estimation is:

[0086] e-c1=(c2-b0) / k0 (7)

[0087] The slope of the proportional line segment can be obtained by (6) and (7):

[0088] k=1-(c2-b0) / (c1-b0) (8)

[0089] After the slope k is obtained, the bias b is set according to the method in section 3.3, and then the actual sampling clock phase mismatch error value in the second error estimation is:

[0090] e=(c2-b) / k (9)

[0091] This achieves blind adaptive estimation, allowing error estimation even when the input signal frequency is unknown. A second compensation is then performed. Next, the error converges after several consecutive operations using the third estimation and compensation using formula (6) and the fourth estimation and compensation using formula (9). For an 8-channel TIADC, the estimation of channel 4 converges, followed by error estimation and compensation for channels 2 and 6, and finally, error estimation and compensation for channels 1, 3, 5, and 7.

[0092] III. Statistics and Setting of the Correspondence between Slope and Bias

[0093] As in this embodiment Figure 4 As described below, the ratio corresponding to the modulus-square subtraction estimation operator and the sampling clock phase mismatch error is divided into several intervals according to frequency, and the corresponding ratio of each interval is approximately linear. Assume that the frequencies corresponding to the boundary points of each (M+1) interval are: f0, f1, ..., f... i f i+1 , ..., f M-1 The system requires a sampling clock phase mismatch error range of [-aT]. s aT s ], where T s Let be the system sampling period, and 'a' be a constant. For each frequency point, the bias values ​​of each sampling clock phase mismatch error point are scanned and statistically analyzed at equal intervals within the system's required sampling clock phase mismatch error range.

[0094] For example, for f i The actual sampling clock phase mismatch error range is divided into 2N equal intervals, and the phase mismatch error points of each actual sampling clock are as follows: Estimation operator based on the method of subtraction of modulo squares Based on long-term statistical analysis, the estimated value of each sampling clock phase mismatch error point is s. -N s -(N-1) , ..., s -1 ,0,s1,...,s (N-1) s N The phase mismatch error points of each actual sampling clock are identified. and the corresponding estimated value s -N s -(N-1) , ..., s -1 ,0,s1,...,s (N-1) s N By performing a linear fit, f can be obtained. i The slope k of the downsampling clock phase mismatch error segment i And the bias value b when the sampling clock phase mismatch error is 0 iSimilar operations are performed on other frequencies to obtain the slope of the sampling clock phase mismatch error line segment at different frequencies and the offset value when the sampling clock phase mismatch error is 0. Finally, f0, f1, ..., f i f i+1 , ..., f M-1 The slopes k0, k1, ..., k corresponding to each frequency point i k i+1 , ..., k M-1 and bias values ​​b0, b1, ..., b i b i+1 , ..., b M-1 Then store the data. This concludes the offline statistical process.

[0095] In real-time estimation, k obtained from formula (8) is in the range of k0, k1, ..., k i k i+1 , ..., k M-1 In the query, assuming it is located at k i k i+1 Between these, the bias b used in formula (9) can be considered to have the following correspondence:

[0096]

[0097] The value on the left side of the above equation is known, denoted as A. Then, the value of the bias b can be obtained through formula (10):

[0098] b = (b i+1 +Ab i ) / (1+A) (11)

[0099] This is the process of interpolating and estimating the bias value. Substituting b into formula (9) will give the actual sampling clock phase mismatch error value.

[0100] In this embodiment, segmentation and interpolation techniques are introduced, while conventional processing methods do not segment and average the biases corresponding to the two endpoints as the bias values ​​used in the calculation. Obviously, the estimation accuracy is not as high as that of this embodiment.

[0101] In another practical application embodiment of the present application, the performance of the method is evaluated taking an 8-way TIADC as an example. The parameter settings are as follows: sampling rate 2GHz, channel number M=8, offset mismatch error [0 0 0 0 0 0 0 0], gain mismatch error [1 1 1 1 1 1 1], sampling clock phase mismatch error [0 0.03 -0.03 0.03 0.03 -0.03 0.03 -0.03]Ts, AWGN channel, signal-to-noise ratio 100dB, the sampling clock phase mismatch error is estimated using the modulus square subtraction method, the statistical data length is 65536*256 sampling points each time, the error estimation is performed 8000 times, and the effective number of bits (ENOB) of the TIADC is scanned from 1MHz to 200MHz. After compensation, the ENOB of the conventional average method cannot reach 12bit at many frequency points, while the ENOB of the segmented interpolation method of the embodiment of the present application can reach more than 12bit, meeting the sampling requirements of the 5G system.

[0102] Meanwhile, the embodiment of the present application is offline statistics of the slope and offset of the proportional line segment of some frequency points, and in actual estimation, only the real-time slope and offset values are obtained through linear interpolation, so the processing is simple and does not cause excessive increase in complexity.

[0103] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and a necessary general hardware platform, and of course, it can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disc), and includes a plurality of instructions for causing a terminal device (which can be a mobile phone, a computer, a server, or a network device) to execute the method described in each embodiment of the present application.

[0104] In the present embodiment, a sampling clock phase mismatch error estimation device is also provided, which is used to implement the above embodiments and preferred embodiments, and will not be described again. As used below, the term "module" or "unit" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably realized in software, hardware, or a combination of software and hardware is also possible and is contemplated.

[0105] Figure 6 is a structural block diagram of the sampling clock phase mismatch error estimation device according to the embodiment of the present application, as shown in Figure 6 The device includes a partition module 10, a statistics module 20, and an estimation module 30.

[0106] The partitioning module 10 is used to divide the proportional relationship between the estimation operator of the modulus-square subtraction and the phase mismatch error of the TIADC sampling clock into several intervals according to the frequency, wherein the corresponding proportion of each interval is approximately linear.

[0107] The statistics module 20 is used to offline statistically analyze the slope and offset values ​​of the proportional line segments corresponding to the actual sampling clock phase mismatch error and the estimated value at each interval frequency boundary point, and to store the slope and offset values ​​of the offline statistics.

[0108] The estimation module 30 is used in the real-time estimation of the sampling clock phase mismatch error of TIADC to calculate the slope of the corresponding proportional line segment at the frequency based on the error estimate obtained by the estimation operator of modulus-square subtraction, find the corresponding slope range in the slope statistics of the line segment, obtain the offset value of the boundary point of the range, estimate the offset value of the frequency by interpolation, and estimate the actual error value of the sampling clock phase mismatch by the slope and the offset value.

[0109] In one embodiment, the partitioning module 10 further includes: a division unit 11, used for dividing the (M+1) intervals at each boundary point with frequencies of: f0, f1, ..., f i f i+1 , ..., f M-1 For frequency point f i The actual sampling clock phase mismatch error range is divided into 2N equal intervals, and the phase mismatch error points of each actual sampling clock are as follows: Where T s Let be the system sampling period, and 'a' be a constant.

[0110] In one embodiment, the statistical module 20 includes a statistical unit 21, a fitting unit 22, an acquisition unit 23, and a storage unit 24.

[0111] Statistical unit 21 is used for the estimation operator of the modulus subtraction method. The estimated value of each sampling clock phase mismatch error point was obtained through statistical analysis, and the value was s. -N s -(N-1) , ..., s -1 ,0,s1,...,s (N-1 ), s N .

[0112] Fitting unit 22 is used to fit the phase mismatch error points of each actual sampling clock. and the corresponding estimated value s -N s -(N-1) , ..., s -1 ,0,s1,...,s (N-1) s N Perform linear fitting to obtain the frequency point fi slope k of the line segment of the down-sampling clock phase mismatch error i and the bias value b when the sampling clock phase mismatch error is 0 i .

[0113] The acquisition unit 23 performs the same operation on other frequencies to obtain the slope of the line segment of the sampling clock phase mismatch error and the bias value b when the sampling clock phase mismatch error is 0 for different frequencies.

[0114] The storage unit 24 is configured to store f0, f1,..., f i , f i+1 ,..., f M-1 , the slope k0, k1,..., k i , k i+1 ,..., k M-1 and the bias value b0, b1,..., b i , b i+1 ,..., b M-1 corresponding to each frequency.

[0115] In an embodiment, the estimation module 30 comprises a conversion module 31, a query module 32 and an interpolation module 33.

[0116] The conversion module 31 is configured to convert the slope k of the corresponding proportional line segment at the frequency according to the estimation value obtained by the modulus subtraction estimation algorithm.

[0117] The query module 32 is configured to query the obtained slope k in k0, k1,..., k i , k i+1 ,..., k M-1 to find the corresponding slope range located between k i , k i+1 .

[0118] The interpolation module 33 is configured to estimate the bias value b of the frequency by interpolation as follows:

[0119]

[0120] In an embodiment, the device further comprises a sampling module 40 and an output module 50.

[0121] The sampling module 40 is configured to sample the input signal before converting the slope k of the corresponding proportional line segment at the frequency according to the error estimation value, and calculate the error estimation value by using the modulus subtraction method.

[0122] The output module 50 is configured to output the actual error value of the sampling clock phase mismatch estimated to the compensator for error compensation.

[0123] It should be noted that the above modules can be implemented by software or hardware, and the hardware can be implemented by the following manners, but is not limited to: all the modules are located in the same processor; or the modules are located in different processors in any combination.

[0124] Embodiments of the present application also provide a storage medium, which stores a computer program, and the computer program is configured to execute the steps in any of the above method embodiments when running.

[0125] Optionally, in the embodiment, the storage medium can include, but is not limited to: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various storage media that can store computer programs.

[0126] Embodiments of the present application also provide an electronic device, which includes a memory storing a computer program and a processor configured to execute the computer program to perform the steps in any of the above method embodiments.

[0127] Optionally, the electronic device can further include a transmission device connected with the processor and an input / output device connected with the processor.

[0128] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented by general computing devices, which can be concentrated on a single computing device or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by program codes executable by computing devices, so that they can be stored in storage devices and executed by computing devices, and in some cases, the steps shown or described can be executed in different order, or they can be manufactured into individual integrated circuit modules, or multiple modules or steps can be manufactured into a single integrated circuit module. Therefore, the present application is not limited to any specific combination of hardware and software.

[0129] The above only describes the preferred embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method of sampling clock phase mismatch error estimation, the method comprising: The method comprises: The proportional relationship between the modulus-square subtraction estimation operator and the phase mismatch error of the TIADC sampling clock is divided into several intervals according to frequency, including: (M+1) intervals, with the boundary points corresponding to the frequencies: f0, f1, ..., f i ,f i+1 ,...,f M-1 For frequency point f i The actual sampling clock phase mismatch error range is divided into 2N equal intervals, and the phase mismatch error points of each actual sampling clock are as follows: Where T s Let be the system sampling period, 'a' be a constant, 'm' be the corresponding ratio of each interval be approximately linear, 'M' be an integer greater than 1, and 'N' be a positive integer. The statistical frequency demarcation point of each interval, the down-sampling clock phase mismatch error and the corresponding proportional line segment slope and bias value are estimated, including: the modulo subtraction method estimation E The statistical estimation value of each sampling clock phase mismatch error point is s -N ,s -(N-1) ,...,s -1 ,0,s1,...,s (N-1) ,s N ; x1, x2, x3 are sampling points; E is a mathematical expectation symbol; Each sampling clock phase mismatch error point And the corresponding estimated value s -N , -(N-1) ... -1 , 0, s1,... (N-1) , s N Linear fitting to get the frequency f i The slope k of the down-sampling clock phase mismatch error line segment i And the bias value b when the sampling clock phase mismatch error is 0 i ; The same operation is performed on other frequency points to obtain the slope of the sampling clock phase mismatch error line segment and the bias value when the sampling clock phase mismatch error is 0 for different frequency points; f0, f1,..., f i i+1 f0, f1,..., f M-1 i k0, k1,..., k i+1 M-1 b0, b1,..., b i i+1 b0, b1,..., b M-1 are stored;​​​​ In real-time estimation of the sampling clock phase mismatch error of the TIADC, The estimated value obtained by the modulus square subtraction estimation is converted into the slope k of the corresponding proportional line segment at the frequency; The obtained slope k is inquired in k0, k1,..., k i , k i+1 , ..., k M-1 to find the corresponding slope range located between k i , k i+1 ; The bias value b of the frequency is estimated by interpolation as follows: b = (b i+1 + Ab i ) / (1 + A) The actual error value of the sampling clock phase mismatch is estimated according to the slope and the bias value; wherein A is the slope of the proportional line segment at the real-time estimation frequency converted from the error estimated value obtained by the modulus square subtraction estimation.

2. The method of claim 1, wherein, After the actual error value of the sampling clock phase mismatch is estimated by the slope and the bias value, the method further comprises: The estimated actual error value of the sampling clock phase mismatch is output to a compensator for error compensation.

3. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the method in any one of claims 1 to 2 when running. 4.An electronic device comprising a memory and a processor, the electronic device characterized by, The memory stores a computer program, and the processor is configured to execute the computer program to execute the method in any one of claims 1 to 2.

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