System and method for synchronizing communications between multiple processors

Abstract

The present invention relates to systems and methods for synchronizing communications between multiple processors, and more particularly to a system, method, and computer program product for synchronizing multiple processes of one or more applications executed by the multiple processors. In addition to the processors, the system includes multiple memories, each memory being associated with a respective process and configured to maintain a local count of messages representing the respective process associated with the memory and at least one remote count of messages representing the corresponding process executed by another processor. The system also includes a mapper configured to map the local count of the respective process to the remote count of the respective process. To synchronize, a first process of a first application executed by a first processor is configured to enter a delay period if the local count and the at least one remote count maintained by the memory associated with the first process fail to match.

Description

Technical Field

[0001] The present disclosure generally relates to a system, method, and computer program product for synchronizing communications between multiple processors, eg, providing improved synchronization of inbound and / or outbound message processing by parallel processes or applications executed by the multiple processors. Background Art

[0002] For any of a variety of purposes, multiple processors can execute the same application in parallel, each application comprising one or more processes. For example, multiple processors can execute the same application to provide enhanced fault tolerance. Alternatively, the results of multiple processors executing the application in parallel can be considered for purposes such as integrity monitoring. Furthermore, parallel execution of the same application by multiple processors can also be utilized where application availability is critical.

[0003] The execution of the same application (and therefore the same process) by multiple processors is advantageously synchronized so that different instances of the same process utilize the same data even when the processes are executed by different processors. Therefore, the inbound and outbound message processing associated with the execution of a process by multiple processors should be synchronized. One method for synchronizing the inbound and outbound message processing associated with the execution of the same process by multiple processors employs network switch loopback. However, this method introduces significant data latency and the requirement for external hardware in the form of a network switch. Another method for synchronizing the inbound and outbound message processing during the execution of the same process by multiple processors relies on additional memory shared by the multiple processors. Additional memory also requires additional hardware and correspondingly increases the power requirements associated with the execution of the same process by multiple processors. Furthermore, additional software is typically required to provide mutual access to the shared memory by the multiple processors executing the same process, thereby increasing the complexity of the system. In this approach, the additional memory is typically sized to accommodate the worst-case skew between messages processed during the execution of the same process by the multiple processors, resulting in the additional memory being larger than desired. Summary of the Invention

[0004] According to examples of the present disclosure, a system, method, and computer program product are provided for improving synchronization between multiple processors executing applications that include the same process, including improved synchronization for inbound and / or outbound message processing performed by multiple processors in conjunction with executing the same process. As a result, the system, method, and computer program product of the examples of the present disclosure ensure that the same data is synchronously provided to and consumed by the processes executed by the multiple processors even when the execution of the processes by the multiple processors is skewed in time. In addition, the system, method, and computer program product of the examples of the present disclosure require only limited memory and limited or no external hardware to synchronize inbound and outbound message processing associated with the processes executed by the multiple processors.

[0005] In an example of the present disclosure, a system configured to synchronize communications is provided. The system includes multiple processors, each processor configured to execute one or more applications, at least one of which includes one or more processes. The system also includes multiple memories, each associated with a corresponding process of the application executed by the corresponding processor. Each memory is configured to maintain a local count and at least one remote count, the local count representing messages transmitted to or from the corresponding process associated with the corresponding memory, and the remote count representing messages transmitted to or from the corresponding process of the application executed by another processor among the multiple processors. The system also includes a mapper configured to map the local count of the corresponding process to the remote count of the corresponding process on multiple other processors. To maintain synchronization, a first process of a first application executed by a first processor is configured to enter a delay period if the local count maintained by the memory associated with the first process and the at least one remote count do not match.

[0006] In one embodiment, a first process of the present invention is configured to enter a delay period when a local count exceeds at least one remote count, and is further configured to continue execution when the local count matches the remote count of the corresponding process. In one embodiment, a memory location associated with a corresponding process of an application executed by another processor that maintains a remote count is identified by hardware addressing. In another embodiment, a memory location associated with a corresponding process of an application executed by another processor that maintains a remote count is identified by a Peripheral Component Interconnect Express (PCIe) address. As used herein, PCIe is an interface standard for connecting high-speed components, as defined by PCI-SIG (Beaverton, OR 97003, USA).

[0007] The plurality of processors may operate asynchronously due to clock or operational differences. The plurality of processors may include a plurality of different processors that operate independently due to architectural or clock differences. In an example, the plurality of processors include a plurality of multi-core processors, each core of the multi-core processor being configured to execute one or more applications, at least one of the applications including one or more processes. When a first process of a first application executed by a first processor enters a delay period, one or more other processes of the first application executed by the first processor continue without delay.

[0008] In another example of the present disclosure, a method for synchronizing communications is provided. The method includes processing multiple messages using each of one or more processes of one or more applications executed by each of a plurality of processors. For a respective process of an application executed by a respective processor, the method includes maintaining a local count and at least one remote count in a memory associated with the respective process. The local count represents messages transmitted to or from the respective process associated with the respective memory. The at least one remote count represents messages transmitted to or from a corresponding process of an application executed by another processor of the plurality of processors. The method also includes mapping the local count of the respective process to the remote count of the respective process. The method also includes causing the first process to enter a delay period if the local count and the at least one remote count maintained in the memory associated with a first process of a first application executed by a first processor fail to match.

[0009] The example method causes the first process to enter a delay period by causing the first process to enter a delay period if the local count exceeds at least one remote count. In this example, the method also includes continuing to process the multiple messages using the first process if the local count matches the remote count of the corresponding process. In the example, the method maps the local count by identifying a memory location that maintains the remote count in memory associated with the corresponding process of an application executed by another processor via hardware addressing. In this example, the method identifies a memory location by hardware addressing by identifying a memory location that maintains the remote count in memory associated with the corresponding process of an application executed by another processor via a PCIe address. The method may process the multiple messages by operating the multiple processors asynchronously due to clock or operational differences. In the example, the method maps the local count by mapping the local count in an asynchronous manner.

[0010] In another example of the present disclosure, a computer program product configured to synchronize communications is provided. The computer program product includes a non-transitory computer-readable medium storing program code, the program code including program code instructions that, when executed, are configured to process multiple messages using each of one or more processes of one or more applications executed by each of a plurality of processors. The program code also includes program code instructions configured to maintain a local count and at least one remote count in a memory associated with a corresponding process of the application executed by the corresponding processor. The local count represents messages transmitted to or from the corresponding process associated with the corresponding memory, while the at least one remote count represents messages transmitted to or from a corresponding process of the application executed by another processor of the plurality of processors. The program code also includes program code instructions configured to map the local count of the corresponding process to the remote count of the corresponding process, and program code instructions configured to cause a first process of a first application executed by a first processor to enter a delay period if the local count and the at least one remote count maintained in a memory associated with the first process do not match.

[0011] According to an example, the program code instructions configured to cause the first process to enter a delay period include program code instructions configured to cause the first process to enter a delay period if a local count exceeds at least one remote count. In this example, the program code also includes program code instructions configured to continue processing the multiple messages using the first process if the local count matches the remote count of the corresponding process. In an example, the program code including program code instructions configured to map the local count includes program code instructions configured to identify, via hardware addressing, a memory location associated with a corresponding process of an application executed by another processor that maintains the remote count. In this example, the program code instructions configured to identify, via hardware addressing, a memory location associated with a corresponding process of an application executed by another processor that maintains the remote count, includes program code instructions configured to identify, via a PCIe address, a memory location associated with a corresponding process of an application executed by another processor that maintains the remote count. The program code instructions configured to process the multiple messages may include program code instructions configured to process the multiple messages asynchronously relative to processing of the multiple messages by other processors in the multiple processors due to clock or operational differences. The program code instructions configured to map the local count may include program code instructions configured to map the local count asynchronously. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Having generally described above certain examples of the present disclosure, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0013] Figure 1 is a block diagram of a system configured to synchronize communications between multiple processors according to an example of the present disclosure;

[0014] Figure 2 is a more detailed block diagram of a system configured to synchronize communications between multiple processors according to an example of the present disclosure;

[0015] Figure 3 is an example according to the present disclosure, for example, Figure 1 or Figure 2 A flowchart of the operations performed by the system;

[0016] Figure 4 is a diagram representing local remote counts maintained by two different processors and illustrating a delay period entered by one of the processors in response to a mismatch between the local count and the remote count according to an example of the present disclosure. DETAILED DESCRIPTION

[0017] Some examples of the present disclosure will now be described more fully below with reference to the accompanying drawings, in which some, but not all, examples of the present disclosure are shown. Indeed, these examples may be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these examples are provided so that the present disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout. As used herein, the terms "data," "content," "information," and similar terms are used interchangeably to refer to data that can be sent, received, and / or stored according to examples of the present disclosure. Accordingly, none of these terms should be used to limit the spirit and scope of the examples of the present disclosure.

[0018] According to examples of the present disclosure, a system, method, and computer program product are provided to synchronize communications (e.g., communications between multiple processors). As used herein, reference to synchronization refers to time synchronization. For example, for fault tolerance purposes, for integrity purposes, and / or to increase the availability of an application, multiple processors may be executing the same application. At least some of the applications executed by the multiple processors may include multiple processes (e.g., tasks or threads) that are executed in parallel and can run at different rates. Therefore, multiple processors may be executing one or more of the same processes in parallel. For various reasons (including, for example, drift in the clock source of one or more processors), multiple processors executed by different processors may become asynchronous. In this case, due to different data inputs, the same process executed by multiple processors may no longer generate the same results. For example, the time difference between multiple processors executing the same process may cause the process to operate on different instances of the same data element, thereby generating different results. In order to reduce this asynchronous operation of multiple processes, the system, method, and computer program product of examples of the present disclosure promote synchronous communication between multiple processors and, accordingly, the synchronous execution of the application's processes by multiple processors. When the processes are no longer synchronized, the method, device, and computer program product return the processors to synchronization with respect to the processor execution of the processes.

[0019] Now refer to Figure 1 , depicts a system 10 configured to synchronize communications between a plurality of processors 12. The system 10 includes the plurality of processors 12 and a plurality of memories 14, wherein at least one memory is associated with each of the plurality of processors. Figure 1 The system 10 is shown as including two processors 12 (referred to as a first processor and a second processor), but other example systems may include other numbers of processors (e.g., three or more processors). Figure 1 As shown, the plurality of processors 12 may include or embody respective memories 14, or one or more of the memories may be external to the respective processors while maintaining communication therewith. As described below, the exemplary system 10 includes at least two memory locations (e.g., registers) associated with each of the plurality of processors 12, one of which is configured to maintain a local count 16 and the other is configured to maintain a remote count 18. Figure 1 As shown, the two memory locations for maintaining the local count 16 and the remote count 18 for the respective processors 12 may be provided by a single memory device 14. However, another example processor 12 may include or be in communication with separate memory devices 14, one of which is configured to store the local count 16 and the other of which is configured to store the remote count 18.

[0020] The multiple processors 12 of the example are configured to operate synchronously, and therefore can be provided with clocks by the same clock source. However, in other examples, the multiple processors 12 are configured to operate asynchronously (for example, provided with clocks by different clock sources). The multiple processors 12 may include multiple processors of the same type. Alternatively, the multiple processors 12 may be specifically implemented by multiple different types of processors, that is, the processors may be different processors (with different internal hardware architectures). In one example, the multiple processors 12 include multiple multi-core processors. Each of the processors 12 is configured to execute one or more applications, at least some of which are to be synchronized. At least some of the applications may include one or more processes (for example, tasks or threads). In an example, two or more processes of an application may be executed in parallel, even if these processes may be running at different periodic rates or even non-periodically. In the case where the system 10 includes multiple multi-core processors, each application may be executed in a partition on a specific core of the corresponding processor. As a result, the corresponding cores of the two or more multi-core processors of this example may execute the same application (and then, the same process).

[0021] like Figure 1 As shown, the system 10 also includes a mapper 20. The mapper 20 can be specifically implemented by a hardware component. In the illustrated example where a plurality of processors 12 include a first and a second processor, the mapper is configured to map the local count 16 of the first processor to the remote count 18 of the second processor, and accordingly map the local count of the second processor to the remote count of the first processor. In an alternative example where the system 10 includes three or more processors 12, the processor is configured to maintain the remote count 18 of each of the plurality of other processors, and the mapper 20 is correspondingly configured to map the local count 16 of the first processor to the corresponding remote count associated with the first processor stored by the memory 14 associated with each other processor (e.g., the remote count of the first processor stored by the second processor, the remote count of the first processor stored by the third processor, the remote count of the first processor stored by the fourth processor, etc.). The mapper 20 can be configured in various ways. In an example, the mapper 20 is specifically implemented as a network controller, such as a synchronous interface network controller (SINC). In this example, SINC can be specifically implemented by an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA).

[0022] In the case where the mapper 20 is specifically implemented as a SINC 22, Figure 2A more detailed diagram of a system 10 for synchronizing communications between multiple processors 12 (e.g., in this illustrated example, between a first and second processor) is provided. As described above, each processor 12 includes or is associated with memory 14, which in turn maintains a local count 16 and a remote count 18 in corresponding memory locations. The illustrated sets of local counts 16 and remote counts 18 are associated with corresponding processes of applications executed by the processors 12. Because processors 12 may execute multiple processes of one or more applications, the memory 14 associated with the processors may include multiple sets of local counts 16 and remote counts 18, one of which is associated with each process. The local count 16 for a corresponding process serves as a transaction counter, identifying the number of messages currently being sent to or from the process, or the most recently sent to or from the process. For example, after sending or receiving the first message by the corresponding process, the processor 12 may set the local count 16 to a value of 1. After sending or receiving the tenth message by the corresponding process, the processor 12 may correspondingly set the local count 16 to a value of 10, and so on. Similarly, remote count 18 maintained by processor 12 is a representation of messages executed by another process (i.e., the corresponding process) of an application executed by another processor (e.g., in this example, the second processor). Since processors 12 are executing the same application (and, therefore, the same process), local count 16 and remote count 18 should be identical if the processors are synchronized. However, if processors 12 are not synchronized, local count 16 and remote count 18 will contain different values, causing system 10 of this example to take action to restore the processors (and, more specifically, the processors' processes) to synchronization.

[0023] Figure 2 The example mapper 20 depicted in FIGURE 2 (e.g., as embodied in SINC 22) maps local counts 16 of corresponding processes of an application executed by a first processor 12 to remote counts 18 of the same process of the same application executed by a second processor, and conversely, maps local counts of corresponding processes of an application executed by the second processor to remote counts of the same process of the same application executed by the first processor. Thus, the set of local counts 16 and remote counts 18 represents corresponding counts of messages sent to and from the same process of the same application executed by different processors. The example mapper 20 is configured to perform this mapping in real time or near real time to allow meaningful comparison between the local counts 16 and the remote counts 18 maintained by the corresponding processors 12, without the remote counts being time-delayed or time-shifted to a significant extent due to the time required for the mapping process.

[0024] Although the mapper 20 can be implemented in various ways, Figure 2The SINC 22 of the illustrated example includes multiple sets of registers, where one set of registers is associated with each process of an application of multiple processors 12. Thus, each set of registers is associated with a corresponding set of local counts 16 and remote counts 18 for a corresponding process of an application executed by a processor 12. For example, a first set of registers is associated with a corresponding process of an application executed by a first processor, and a second set of registers is associated with a corresponding process of an application executed by a second processor (i.e., the same process of the same application). Although Figure 2 The SINC 22 of FIG. 1 includes only two sets of registers, but the mapper may include any number of sets of registers, where each set of registers is associated with a different corresponding process of the application executed by the processor 12. Each set of registers may include status / configuration registers 24, outbound registers 26, and inbound registers 28, where the outbound and inbound registers are used to transmit data to and from other external devices. The register sets also include a mapper in the form of at least one mapper register 20 as described below. In this regard, the register set associated with a process of an application executed by one processor 12 may include one mapper register 20 that is configured to communicate with each other processor that is executing the same application and, in turn, the corresponding (e.g., the same) process.

[0025] exist Figure 2 In an example, for example, the mapper registers 20 associated with a process of an application executed by a first processor 12 are configured to communicate with a second processor executing the same application, and then a corresponding process, and the mapper registers associated with the corresponding process of the same application executed by the second processor are configured to communicate with the first processor. In other examples including three or more processors 12, the register set associated with a process of an application executed by one processor may include multiple mapper registers 20, one of which is configured to communicate with each other processor executing the same application, and then a corresponding (e.g., the same) process. As an example of a system 10 including three processors 12, in the case where both the second and third processors execute the same application (and then a corresponding process), the register set associated with the process of the application executed by the first processor may include a first mapper register 20 configured to communicate with the second processor and a second mapper register configured to communicate with the third processor. Similarly, the register group associated with the corresponding process of the same application executed by the second processor may include a first mapper register configured to communicate with the first processor and a second mapper register configured to communicate with the third processor, and the register group associated with the corresponding process of the same application executed by the third processor may include a first mapper register configured to communicate with the first processor and a second mapper register configured to communicate with the second processor.

[0026] Each mapper register 20 is configured to receive a local count 16 maintained by the memory 14 of the processor 12 that is executing the application (and hence the process) associated with the corresponding mapper register. Figure 2 As shown, each mapper register 20 is also in communication (eg, hardware communication) with a remote count 18 maintained by the memory 14 of another processor 12 with which the mapper register is configured to communicate. Figure 2 In the example depicted in FIG, the value of a mapper register 20 associated with a process of an application executed by a first processor 12 (i.e., the local count 16 stored by the memory 14 of the first processor) is provided to a memory location of a memory of a second processor that maintains a remote count 18, thereby providing memory-mapped input / output (which may be dynamically allocated in one example). Conversely, the value of a mapper register 20 associated with a corresponding process of the same application executed by a second processor 12 (i.e., the local count 16 stored by the memory 14 of the second processor) is provided to a memory location of the memory of the first processor that maintains a remote count 18. In other words, the first processor 12 of this example writes the value of the local count 16 from the memory 14 associated with the first processor to the mapper register 20 associated with the corresponding process, which in turn passes the value to the memory associated with the corresponding process of the same application executed by the second processor for storage as the value of the remote count 18. In other examples including three or more processors 12, the local count of one processor is mapped to the corresponding remote count of each of the other processors executing the same application (and, in turn, the same process) via the corresponding mapper register 20.

[0027] Regardless of the number of processors 12, the mapper 20 can be configured to operate asynchronously so that the local count 16 provided by a corresponding processor 12 can be transferred and mapped to the remote count 18 of another processor in real time with minimal latency, so that a clock does not need to be provided to the example mapper. In this regard, the memory location where the remote count 18 is maintained in the memory 14 associated with the processor 12 can be identified (e.g., by the mapper 20) through hardware addressing. Although various hardware addressing techniques can be used, the mapper 20 (e.g., the example network controller) uses PCIe addressing 30 (e.g., Figure 2 ) shown with respect to processor 12 and mapper 20 in order to identify the memory location where the other processor maintains the remote count 18, thereby minimizing latency in conjunction with mapping the value of the local count 16 to the remote count.

[0028] The mapping of the value of the local counter 16 of one processor 12 to the remote counter 18 of one or more other processors can be defined or controlled by one or more parameters. These parameters can be predefined as a result of static configuration, can be defined on the fly in conjunction with message transmission to and from the mapper 20, or some combination thereof, with some parameters predefined (e.g., as a result of static configuration) and other parameters defined in conjunction with message transmission to and from the mapper. The parameters can include the identifier of the mapper register 20, the address of the other processor 12, and / or the number of words that one processor wants to write to the other processor. Another parameter can be an offset parameter that defines an offset (e.g., a PCIe address offset) relative to a fixed address of a memory location associated with the other processor and configured to store the remote counter 18. An additional parameter can be a timeout value that defines the length of time the other processor is allowed to increment its counter, wherein action is taken if the other processor fails to increment its counter within the time period defined by the timeout value, thereby allowing the processor stuck in the delay period to be identified and appropriate remedial action to be taken. The example system 10, method, and computer program product provide flexibility with respect to multiple processors 12 and communications therebetween by allowing various parameters to be defined statically in advance or dynamically (written on the fly) in conjunction with message exchanges.

[0029] Now refer to Figure 3 , method 38 is shown as follows, for example, Figure 1 (In some examples, Figure 2) is performed by a system 10. As shown in block 40, the system 10 (e.g., a plurality of processors 12) is configured to process a plurality of messages for the same process with each of the plurality of processors. In this regard, each of the plurality of processors is configured to execute the same application (and, in turn, the same process of the same application) in parallel. For the same process executed by each processor 12 in the plurality of processors, a local count 16 and at least one remote count 18 are maintained in memory 14 associated with the respective processor. In this regard, the local count 16 may be maintained to count, for example, the number of messages communicated with the process by the respective processor 12 (or, more generally, the number of messages processed, which may be measured, for example, by the number of instructions executed or some other metric based on the degree of processing of the application's process), and the remote count 18 may be maintained for corresponding processes of the same application executed by one or more other processors (e.g., by maintaining a separate remote count value for the corresponding process of the same application executed by each of the other processors). Similar to the local count 16, the remote count 18 may be configured to count, for example, the number of messages transmitted (or more generally, processed, for example, in terms of the number of instructions executed or some other measure of the degree of processing of the application) by a corresponding process of another processor 12. For a corresponding process of an application, a processor 12 may maintain a number of local counts 16 and remote counts 18 equal to the number of instances of the process of the application executed by the processor. Thus, the number of remote counts 18 maintained by a processor 12 is typically one less than the total number of instances of the corresponding process of the application executed by the processor. In conjunction with the corresponding processes, for example, in a system 10 including three processors 12 each executing the same application (and, in turn, the same corresponding process), each processor will maintain a local count 16 and two remote counts 18, each remote count value representing a local count associated with the corresponding process of the application executed by a corresponding one of the other processors. As described above and as Figure 3 As shown in block 42 of , the method 38 includes maintaining 42 , for a respective process of an application executed by a respective processor, a local count 16 and at least one remote count 18 in a memory 14 associated with the respective process, wherein the local count represents messages transmitted to or from the respective process associated with the respective memory, and wherein the at least one remote count represents messages transmitted to or from the corresponding process of an application executed by another processor of the plurality of processors.

[0030] like Figure 3As shown in block 44 of FIG. 1 , the system 10 (e.g., the mapper 20) is configured to map the local count 16 of the process of the application executed by one processor 12 to the corresponding remote count 18 of another processor that is executing the same application (and, in turn, the corresponding (i.e., the same) process). In the case where the system 10 includes three or more processors 12, the local count 16 of the process of the application executed by one processor is mapped to the corresponding remote count 18 maintained by each other processor that is executing the same application (including the corresponding process). Figure 3 As shown in decision block 46 of , the system 10 (e.g., each respective processor 12) determines whether the local count 16 maintained by the processor is greater than the remote count 18 maintained by the same processor, or, in an example including three or more processors, whether the local count of the processor is greater than any of a plurality of remote counts maintained by the same processor. In the event that the local count 16 maintained by the processor 12 is equal to or less than the remote count 18 maintained by the same processor, or in the event that the system 10 includes three or more processors and the local count maintained by the processor is equal to or less than each of a plurality of remote counts maintained by the same processor for the other processors, the processor continues to process the next message (e.g., by providing a message transfer from or to the processor), the decision is yes, and the flow of method 38 returns to Figure 3 Box 40.

[0031] However, in the event that the local count 16 maintained by a processor 12 exceeds the remote count maintained by the same processor, or in the example of a system 10 including three or more processors and the local count maintained by a processor exceeds the remote count maintained by the same processor for any other processor, the decision is no and the process executed by the corresponding processor whose local count exceeds the remote count is caused to enter a delay period, as shown. Figure 3 As shown in block 48 of . Upon entering the delay period, the corresponding processor 12 does not process the next message of the process (e.g., by preventing the transmission of the next message from or to the corresponding processor), but instead enters an idle state, while one or more other processors (i.e., other processors whose remote count 18 maintained by the corresponding processor is less than the local count 16 maintained by the same processor) continue to execute the application (more specifically, the process) by processing the next message of the process (e.g., by providing the transmission of the next message from or to the one or more other processors), as shown in FIG. Figure 350. While the particular process of the respective processor is in the delay period, other processes running in parallel on the respective processor (e.g., other processes executed by other cores of a multi-core processor) are not delayed and continue to execute. After one or more other processors 12 process the next message for the process and map the local count 16 of the other processor to the corresponding remote count 18 maintained by the respective processor, the comparison of the local count maintained by the respective processor with the remote count maintained by the same processor, or in the example including three or more processors, the comparison of the local count maintained by the respective processor with the remote count maintained by the same processor for each of the other processors, is repeated to determine whether the local count is still greater than the remote count, or greater than at least one remote count in the case of a system including three or more processors. If the local count 16 maintained by the corresponding processor 12 is still greater than at least one remote count 18 maintained by the same processor, the corresponding processor remains in a delay period while one or more other processors (those associated with the remote count maintained by the corresponding processor that exceeds the local count maintained by the same processor) continue to execute the application by processing the next message (e.g., by providing for the delivery of the next message from or to the one or more other processors). However, if the other processors 12 have caught up with the corresponding processor, such that the remote count 18 maintained by the corresponding processor is equal to the local count 16 maintained by the same processor, the delay period for the corresponding processor ends, and the corresponding processor and the other processors continue to execute the application by processing the next message (e.g., by providing for the delivery of the next message from or to the processor).

[0032] Combined with the above Figure 3 The described operations are performed, by way of example, by each processor 12. In other words, although described above in connection with a delay period being established in connection with one of the processors 12, the local count 16 and the remote count 18 maintained by the memory 14 associated with each processor are compared by each respective processor such that, in the event that the local count maintained by the respective processor exceeds the remote count maintained by the same processor for the other processors, any one or more of the plurality of processors is configured to enter a delay period.

[0033] As an example of entering a delay period to allow the multiple processors 12 to return to synchronization with respect to message processing associated with the execution of the same process of the same application, Figure 4Depicted are operations performed by first and second processors executing the same application (more specifically, the same process of the same application) for multiple consecutive time slices, along with the values of the local count 16 and remote count 18 maintained by each of the first and second processors during each time slice. In time slice 1, each of the first and second processors processes a first message in conjunction with execution of the same application (and, in turn, the same process). The initial values of the local and remote counts maintained by each of the first and second processors match each other, as both are 0 during time slice 1. After processing the first message, the local counts maintained by the first and second processors are updated to 1 in time slice 2, and the values of each processor's local count are mapped to the remote counts of the other processors, such that the remote counts of the first and second processors are now also 1. During time slice 2 of the process, each of the first and second processors then processes the next message, as the values of the local and remote counts for each of the first and second processors continue to be equal. The local and remote counts are then updated to 2 in time slice 3, and the first and second processors process the next message in conjunction with execution of the same application (and, in turn, the same process) during time slice 3, as the local and remote counts for each of the first and second processors continue to remain the same.

[0034] As shown in time slice 4 of the process, the first processor has processed the third message, resulting in a local count of 3, which is mapped to the remote count of the second processor. However, the second processor has not yet processed the third message of the process, resulting in the second processor's local count remaining at 2, which continues to be mapped to the remote count maintained by the first processor. Because the first processor's local count exceeds the remote count maintained by the first processor in time slice 4 of the process, the first processor enters a delay period and does not process the next message during time slice 4. Although the first processor enters the delay period, other processes running in parallel on the first processor (e.g., other processes executed by other cores of a multi-core processor) are not delayed and continue execution. However, because the second processor's local count is not greater than the remote count maintained by the second processor (but is smaller than the remote count maintained by the second processor), the second processor processes the next message during time slice 4 of the process. Having processed the next message of the process, the local count maintained by the second processor increases to 3 in time slice 5, which is then mapped to the remote count maintained by the first processor. Since the local and remote counts maintained by each of the first and second processors are again equal to each other, the delay period for the first processor ends, and both the first and second processors process the next message in time slice 5 of the process, resulting in the local and remote counts being increased to 4 for each of the first and second processors in time slice 6 of the process, thereby allowing both the first and second processors to continue processing the next message (e.g., by providing transmission of the next message from or to the processor).

[0035] like Figure 4 As shown in the example depicted in , the example system 10, method, and computer program product allow multiple processors 12 to maintain synchronization with respect to inbound and / or outbound message processing (e.g., the sending or receiving of messages) performed by the multiple processors in conjunction with executing the same application (and, in turn, the same process), even when the processors operate asynchronously or become out of sync with respect to a common clock. By ensuring synchronous communication among the multiple processors 12, the execution of the same application (including the same process) by the multiple processors should generate the same results, thereby providing improved fault tolerance, integrity, and availability of the application. Furthermore, the example system 10, method, and computer program product require only limited memory and limited or no external hardware to synchronize inbound and outbound message processing associated with the processes executed by the multiple processors, thereby reducing the complexity and power requirements of the system. In this regard, the example system 10 can limit the amount of memory required by each processor 12 to store the messages being processed to the amount required to store two messages, compared to existing approaches that must be larger to accommodate worst-case skew.

[0036] Figure 3A flow chart describing the operation of the system, method and computer program product according to the present disclosure is shown. It will be understood that the individual blocks of the flow chart and the combination of the blocks in the flow chart can be implemented by various means, specifically implemented as hardware, firmware, circuits and / or other devices associated with the software that executes the one or more software instructions. For example, the one or more operations described above can be specifically implemented by software instructions. In this regard, the software instructions that specifically implement the above-mentioned process can be stored by memory 14 and executed by corresponding processor 12. It will be understood that any of these software instructions can be loaded onto a computer or other programmable device (e.g., hardware) to generate a machine so that the resulting computer or other programmable device implements the function specified in the flow chart box. These software instructions can also be stored in a computer-readable memory, which can guide a computer or other programmable device to work in a particular way so that the software instructions stored in the computer-readable memory generate a product that performs the function specified in the flow chart box. The software instructions can also be loaded onto a computer or other programmable device so that a series of operations are performed on the computer or other programmable device to generate a computer-implemented process so that the software instructions executed on the computer or other programmable device provide the operation for implementing the function specified in the flow chart box.

[0037] Furthermore, the present disclosure includes the following clauses, and it is noted that the scope of protection is provided by the claims rather than by these clauses:

[0038] Item 1. A system configured to synchronize communications, the system comprising: a plurality of processors, each processor configured to execute one or more applications, at least one of the applications comprising one or more processes; a plurality of memories, each memory associated with a corresponding process of the application executed by the corresponding processor, wherein each memory is configured to maintain a local count representing messages transmitted to or from the corresponding process associated with the corresponding memory and at least one remote count representing messages transmitted to or from the corresponding process of the application executed by another processor of the plurality of processors; and a mapper configured to map the local count of the corresponding process to the remote count of the corresponding process, wherein a first process of a first application executed by a first processor is configured to enter a delay period if the local count and the at least one remote count maintained by the memory associated with the first process fail to match.

[0039] Clause 2. The system of clause 1, wherein the first process is configured to enter a delay period if the local count exceeds at least one remote count, and further configured to continue execution if the local count matches the remote count of the corresponding process.

[0040] Clause 3. The system of any one of clauses 1 to 2, wherein a memory location associated with a corresponding process of an application executed by another processor that maintains a remote count is identified by hardware addressing.

[0041] Clause 4. The system of clause 3, wherein the memory location associated with the corresponding process of the application executed by the other processor that maintains the remote count is identified by a PCIe address.

[0042] Clause 5. The system of any one of clauses 1 to 4, wherein the plurality of processors operate asynchronously due to clock or operational differences.

[0043] Clause 6. The system of any one of clauses 1 to 5, wherein the plurality of processors comprises a plurality of distinct processors that operate independently due to architectural or clock differences.

[0044] Clause 7. The system of any one of clauses 1 to 6, wherein the plurality of processors comprises a plurality of multi-core processors, each core of the multi-core processor being configured to execute one or more applications, at least one of the applications comprising one or more processes.

[0045] Clause 8. The system of any one of clauses 1 to 7, wherein, if a first process of a first application executed by a first processor enters a delay period, one or more other processes of the first application executed by the first processor continue without delay.

[0046] Item 9. A method for synchronizing communications, the method comprising the following steps: processing multiple messages using each of one or more processes of one or more applications executed by each of a plurality of processors; maintaining a local count and at least one remote count in a memory associated with a corresponding process of an application executed by a corresponding processor, wherein the local count represents messages transmitted to or from the corresponding process associated with the corresponding memory, and wherein the at least one remote count represents messages transmitted to or from a corresponding process of an application executed by another processor of the plurality of processors; mapping the local count of the corresponding process to the remote count of the corresponding process; and causing a first process of a first application executed by a first processor to enter a delay period if the local count and the at least one remote count maintained in the memory associated with the first process of the application executed by the first processor fail to match.

[0047] Clause 10. A method according to Clause 9, wherein the step of causing the first process to enter a delay period includes causing the first process to enter a delay period when the local count exceeds at least one remote count, and wherein the method further includes continuing to process the multiple messages using the first process when the local count matches the remote count of the corresponding process.

[0048] Clause 11. The method of any one of clauses 9 to 10, wherein mapping the local count comprises identifying, by hardware addressing, a memory location associated with a corresponding process of an application executed by another processor that maintains the remote count.

[0049] Clause 12. The method of clause 11, wherein identifying the memory location by hardware addressing comprises identifying, by a PCIe address, a memory location that maintains a remote count of memory associated with a corresponding process of an application executed by another processor.

[0050] Clause 13. The method of any one of clauses 9 to 12, wherein processing the plurality of messages comprises operating the plurality of processors asynchronously due to clock or operational differences.

[0051] Clause 14. The method of any one of clauses 9 to 13, wherein the step of mapping the local count comprises mapping the local count in an asynchronous manner.

[0052] Clause 15. A computer program product configured to synchronize communications, the computer program product comprising a non-transitory computer-readable medium storing program code, the program code comprising program code instructions that, when executed, are configured to: process a plurality of messages using each of one or more processes of one or more applications executed by each of a plurality of processors; maintain a local count and at least one remote count in a memory associated with a respective process of an application executed by the respective processor, wherein the local count represents messages transmitted to or from the respective process associated with the respective memory, and wherein the at least one remote count represents messages transmitted to or from a corresponding process of an application executed by another of the plurality of processors; map the local count of the respective process to the remote count of the respective process; and if the local count and the at least one remote count maintained in a memory associated with a first process of a first application executed by a first processor fail to match, cause the first process to enter a delay period.

[0053] Clause 16. A computer program product according to clause 15, wherein the program code instructions configured to cause the first process to enter a delay period include program code instructions configured to cause the first process to enter a delay period if the local count exceeds at least one remote count, and wherein the program code also includes program code instructions configured to continue processing the multiple messages using the first process if the local count matches the remote count of the corresponding process.

[0054] Clause 17. A computer program product according to any one of clauses 15 to 16, wherein the program code instructions configured to map the local count include program code instructions configured to identify, by hardware addressing, a memory location that maintains the remote count in a memory associated with a corresponding process of an application executed by another processor.

[0055] Clause 18. A computer program product according to clause 17, wherein the program code instructions configured to identify a memory location by hardware addressing include program code instructions configured to identify a memory location that maintains a remote count of memory associated with a corresponding process of an application executed by another processor by a PCIe address.

[0056] Clause 19. A computer program product according to any one of clauses 15 to 18, wherein the program code instructions configured to process the multiple messages include program code instructions configured to process the multiple messages asynchronously relative to processing of the multiple messages by other processors in the multiple processors due to clock or operational differences.

[0057] Clause 20. The computer program product of any of clauses 15 to 19, wherein the program code instructions configured to map the local count include program code instructions configured to map the local count in an asynchronous manner.

[0058] The flowchart blocks support combinations of means for performing the specified functions and combinations of operations for performing the specified functions. It will be understood that one or more blocks of the flowchart and combinations of blocks in the flowchart can be implemented by a computer system based on dedicated hardware that performs the specified functions or a combination of dedicated hardware and software instructions.

[0059] In some examples, some of the operations described above may be modified or further amplified. Furthermore, in some examples, additional optional operations may be included. Modifications, amplifications, or additions to the operations described above may be performed in any order and in any combination.

[0060] With the benefit of the teachings presented in the above description and the associated drawings, those skilled in the art to which the present disclosure belongs will recognize many modifications and other examples of the present disclosure set forth herein. Therefore, it should be understood that the present disclosure is not limited to the specific examples disclosed, and modifications and other examples are intended to be included within the scope of the appended claims. In addition, although the above description and the associated drawings describe examples in the context of certain example combinations of elements and / or functions, it should be understood that different combinations of elements and / or functions may be provided by alternative examples without departing from the scope of the appended claims. In this regard, for example, as may be described in some of the appended claims, combinations of elements and / or functions that are different from those explicitly described above are also conceivable. Although specific terms are used herein, they are used only in a general and descriptive sense and not for limitation. With the benefit of the teachings presented in the above description and the associated drawings, those skilled in the art to which the present disclosure belongs will recognize many modifications and other examples of the present disclosure set forth herein. Therefore, it will be understood that the present disclosure is not limited to the specific examples disclosed, and modifications and other examples are intended to be included within the scope of the appended claims. Furthermore, although the above description and the associated drawings describe examples in the context of certain example combinations of elements and / or functions, it should be understood that different combinations of elements and / or functions may be provided by alternative examples without departing from the scope of the appended claims. In this regard, for example, as set forth in some of the appended claims, combinations of elements and / or functions different from those explicitly described above are also contemplated. Although specific terms are employed herein, they are used in a general descriptive sense only and not for purposes of limitation.

Claims

1. A system (10) configured to synchronize communications, the system comprising: a plurality of processors (12), each processor configured to execute one or more applications, at least one of the applications comprising one or more processes; a plurality of memories (14), each memory being associated with a respective process of an application executed by a respective processor, wherein each memory is configured to maintain a local count (16) representing messages transmitted to or from the respective process associated with the respective memory and at least one remote count (18) representing messages transmitted to or from a corresponding process of an application executed by another processor of the plurality of processors; and a mapper (20) configured to map the local count of the respective process to a remote count of the respective process, The first process of the first application executed by the first processor is configured to enter a delay period if the local count maintained by the memory associated with the first process and at least one remote count fail to match.

2. The system (10) according to claim 1, wherein The first process is configured to enter the delay period if the local count (16) exceeds at least one remote count (18) and is further configured to continue execution if the local count matches the remote count of the corresponding process.

3. The system (10) according to any one of claims 1 to 2, wherein: A memory location of the memory (14) associated with the corresponding process of the application executed by the other processor (12) maintaining the remote count (18) is identified by hardware addressing.

4. The system (10) according to claim 3, wherein: The memory location of the memory (14) associated with the corresponding process of the application executed by the other processor (12) maintaining the remote count (18) is identified by a PCIe address.

5. The system (10) according to any one of claims 1 to 2, wherein: The plurality of processors (12) operate asynchronously due to clock or operation differences.

6. The system (10) according to any one of claims 1 to 2, wherein: The plurality of processors (12) includes a plurality of distinct processors that operate independently due to architectural or clock differences.

7. The system (10) according to any one of claims 1 to 2, wherein: The plurality of processors (12) include a plurality of multi-core processors, each core of the multi-core processor being configured to execute one or more applications, at least one of the applications including one or more processes.

8. The system (10) according to any one of claims 1 to 2, wherein: In the event that the first process of the first application executed by the first processor (12) enters the delay period, one or more other processes of the first application executed by the first processor continue without delay.

9. A method (38) for synchronizing communications, the method comprising the steps of: processing (40) a plurality of messages using each of one or more processes of one or more applications executed by each of a plurality of processors (12); maintaining (42) a local count (16) and at least one remote count (18) in a memory (14) associated with a respective process of an application executed by a respective processor, wherein the local count represents messages transmitted to or from the respective process associated with the respective memory, and wherein the at least one remote count represents messages transmitted to or from the corresponding process of an application executed by another processor of the plurality of processors; mapping (44) the local count of the respective process to a remote count of the corresponding process; and In the event that the local count and at least one remote count maintained by the memory associated with a first process of a first application executed by a first processor fail to match, causing (48) the first process to enter a delay period.

10. The method (38) of claim 9, wherein: The step of causing (48) the first process to enter the delay period includes causing the first process to enter the delay period when the local count (16) exceeds at least one remote count (18), and wherein the method also includes continuing to process (40) the multiple messages using the first process when the local count matches the remote count of the corresponding process.

11. The method (38) according to any one of claims 9 to 10, wherein: The step of mapping (44) the local count (16) includes identifying, by hardware addressing, a memory location in the memory (14) associated with the corresponding process of the application executed by the other processor (12) where the remote count (18) is maintained.

12. The method (38) of claim 11, wherein: The step of identifying the memory location by hardware addressing includes identifying the memory location where the remote count (18) is maintained in the memory (14) associated with the corresponding process of the application executed by the other processor (12) by a PCIe address.

13. The method (38) according to any one of claims 9 to 10, wherein: The step of processing (40) the plurality of messages includes operating the plurality of processors (12) asynchronously due to clock or operational differences.

14. The method (38) according to any one of claims 9 to 10, wherein: The step of mapping (44) the local count (16) includes mapping the local count in an asynchronous manner.

15. The method (38) according to any one of claims 9 to 10, wherein: The method includes program code stored on a non-transitory computer readable medium.

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