Semiconductor memory devices

Abstract

A semiconductor memory device is provided, the semiconductor memory device comprising: a plurality of bit line structures including bit lines extending parallel to each other along a first lateral direction on a substrate; a plurality of buried contacts and a plurality of bonding pads. The plurality of buried contacts fill the lower portion of the space between the plurality of bit line structures on the substrate, and the plurality of bonding pads fill the upper portion of the space between the plurality of bit line structures and extend on the plurality of bit line structures. The plurality of bonding pads have a hexagonal array structure, and the center points of the top surfaces of a first bonding pad, a second bonding pad, and a third bonding pad that are adjacent to each other among the plurality of bonding pads are connected by an isosceles triangle.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0130820, filed on October 21, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a semiconductor memory device, and more specifically, to a semiconductor memory device having a bonding pad configured to electrically connect an active region to a lower electrode. Background Technology

[0003] Driven by the rapid development of the electronics industry and user demands, electronic devices are being manufactured to be smaller and lighter. Consequently, high integration density is required for semiconductor memory devices used in these devices, and design rules for their fabrication are becoming increasingly complex. As a result, the process of connecting the components included in a semiconductor memory device is becoming more challenging. Summary of the Invention

[0004] The inventive concept provides a semiconductor memory device that can reduce the process difficulty during the manufacturing process of the semiconductor memory device and can ensure the reliability of the connection between components.

[0005] According to one aspect of the inventive concept, a semiconductor memory device is provided. The semiconductor memory device includes: a plurality of bit line structures, including bit lines extending parallel to each other in a first lateral direction on a substrate; a plurality of buried contacts and a plurality of bonding pads. The plurality of buried contacts fill the lower portion of the space between the plurality of bit line structures on the substrate, and the plurality of bonding pads fill the upper portion of the space between the plurality of bit line structures and extend on the plurality of bit line structures. The plurality of bonding pads have a hexagonal array structure, and the center points of the respective top surfaces of a first bonding pad, a second bonding pad, and a third bonding pad that are adjacent to each other among the plurality of bonding pads are connected by an isosceles triangle.

[0006] According to another aspect of the inventive concept, a semiconductor memory device is provided. The semiconductor memory device includes: a substrate, in which a plurality of active regions are defined; a plurality of word lines intersecting the plurality of active regions and extending parallel to each other in a first lateral direction; a plurality of bit line structures including bit lines on the substrate, the bit lines extending parallel to each other in a second lateral direction perpendicular to the first lateral direction; a plurality of buried contacts and a plurality of bonding pads, wherein the plurality of buried contacts fill the lower portion of the space between the plurality of bit line structures on the substrate, and the plurality of bonding pads fill the upper portion of the space between the plurality of bit line structures and extend on the plurality of bit line structures; and a plurality of memory nodes located on the plurality of bonding pads. The plurality of bonding pads have a hexagonal array structure, and the center points of the respective top surfaces of three adjacent bonding pads are connected by an unequal-sided triangle. The plurality of memory nodes have a hexagonal array structure, and the center points of the respective top surfaces of three adjacent memory nodes are connected by an equilateral triangle.

[0007] According to another aspect of the inventive concept, a semiconductor memory device is provided. The semiconductor memory device includes: a substrate, in which a plurality of active regions are defined by a device isolation film; a plurality of word lines intersecting the plurality of active regions and extending parallel in a first lateral direction; a plurality of bit line structures located on the substrate, the plurality of bit line structures having bit lines extending parallel in a second lateral direction perpendicular to the first lateral direction; a plurality of buried contacts filling the lower portion of the space between the plurality of bit line structures on the substrate, the plurality of buried contacts being connected to the plurality of active regions; a plurality of bonding pads connected to the plurality of buried contacts, the plurality of bonding pads filling the upper portion of the space between the plurality of bit line structures and extending onto the plurality of bit line structures, wherein the top surface of each of the plurality of bonding pads has a disk-shaped form; and a plurality of memory nodes located on the plurality of bit line structures and connected to the plurality of bonding pads. A first side, a second side, and a third side of a triangle connecting the center points of the respective top surfaces of three adjacent bonding pads among the plurality of bonding pads have lengths of 3F (F represents a feature size), less than 3F, and greater than 3F, respectively. Each of the first, second, and third sides of the triangle connecting the center points of the top surfaces of three adjacent storage nodes among the plurality of storage nodes has a length of 3F. Attached Figure Description

[0008] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which the same reference numerals consistently denote the same elements. In the drawings:

[0009] Figure 1 This is a schematic planar layout of the main components of a semiconductor memory device according to an example embodiment;

[0010] Figures 2A to 2C This is a schematic planar layout illustrating the arrangement of bonding pads included in a semiconductor memory device according to an example embodiment;

[0011] Figures 3A to 3D , Figures 4A to 4D , Figures 5A to 5D and Figures 6A to 6D This is a cross-sectional view of the process sequence of a method for manufacturing a semiconductor memory device according to an example embodiment;

[0012] Figure 7A This is a plan view of the operations for forming a mask pattern for forming a bonding pad included in a semiconductor memory device, according to an example embodiment.

[0013] Figure 7B It is shown Figure 7A A schematic planar layout of the mask pattern arrangement; and

[0014] Figures 8A to 8D , Figures 9A to 9D and Figures 10A to 10D This is a cross-sectional view of the process sequence of a method for manufacturing a semiconductor memory device according to an example embodiment. Detailed Implementation

[0015] Figure 1 This is a schematic planar layout of the main components of a semiconductor memory device 1 according to an example embodiment.

[0016] Reference Figure 1 The semiconductor memory device 1 may include a plurality of active regions ACT. In some embodiments, each of the plurality of active regions ACT may be arranged to have a long axis that is inclined in a direction relative to a first lateral direction (X direction) and a second lateral direction (Y direction) perpendicular to each other.

[0017] Multiple word lines (WL) can intersect with multiple active regions (ACT) and extend parallel to each other in the first lateral direction (X direction). Multiple bit lines (BL) can be arranged on multiple word lines (WL) and extend parallel to each other in the second lateral direction (Y direction) that intersects with the first lateral direction (X direction).

[0018] Multiple bit lines (BL) can be connected to multiple active regions (ACT) via direct contact (DC).

[0019] In some embodiments, a plurality of buried contacts BC may be formed between two adjacent bit lines in a plurality of bit lines BL. In some embodiments, the plurality of buried contacts BC may be arranged in a straight line in each of a first lateral direction (X direction) and a second lateral direction (Y direction).

[0020] Multiple landing pads (LPs) may be formed on multiple buried contacts (BCs). The multiple landing pads (LPs) may be arranged to at least partially overlap with the multiple buried contacts (BCs). In some embodiments, each of the multiple landing pads (LPs) may extend onto either of two adjacent bit lines (BLs). When viewed from above, the multiple landing pads (LPs) may have a hexagonal array structure. For example, when viewed from above, the multiple landing pads (LPs) may be arranged in a straight line in a first lateral direction (X direction) and in a zigzag pattern in a second lateral direction (Y direction) to form a honeycomb shape. For example, when viewed from above, the honeycomb shape may consist of a group of six landing pads (LPs) arranged in a hexagonal array structure and a seventh landing pad (LP), each of the six landing pads (LPs) located at a corresponding corner of the hexagon, with the seventh landing pad (LP) located inside the hexagon formed by the group of six landing pads (LPs).

[0021] Multiple bonding pads (LPs) can be formed using, for example, extreme ultraviolet (EUV) lithography. In some embodiments, multiple bonding pads (LPs) can be formed without using pattern density enhancement techniques (such as dual patterning technique (DPT) or quadruple patterning technique (QPT)) that include a lithography process. The top surface of each of the multiple bonding pads (LPs) can have a disk shape whose edges are not elliptical but substantially circular.

[0022] Multiple memory nodes (SNs) can be formed on multiple bonding pads (LPs). Multiple memory nodes (SNs) can be formed on multiple bit lines (BLs). Each of the multiple memory nodes (SNs) can be the lower electrode of multiple capacitors. The memory nodes (SNs) can be connected to the active region (ACT) via bonding pads (LPs) and buried contacts (BCs). When viewed from above, the multiple memory nodes (SNs) can have a hexagonal array structure. For example, when viewed from above, the multiple memory nodes (SNs) can be arranged in a straight line in a first lateral direction (X direction) and in a zigzag pattern in a second lateral direction (Y direction) to form a honeycomb shape. For example, when viewed from above, the honeycomb shape can consist of a group of six memory nodes (SNs) arranged in a hexagonal array structure and a seventh memory node (SN), each of the six memory nodes (SNs) located at a corresponding corner of the hexagon, with the seventh memory node (SN) located inside the hexagon formed by the group of the six memory nodes (SNs).

[0023] The cell shape containing multiple bonding pads (LPs) can differ slightly from the cell shape containing multiple storage nodes (SNs). For example, the center points of three adjacent bonding pads (LPs) can be connected by a scalene triangle, while the center points of three adjacent storage nodes (SNs) can be connected by an isosceles triangle or an equilateral triangle (or a regular triangle). (See reference...) Figures 2A to 2CThe arrangement is described in detail. The three adjacent bonding pads LP in a plurality of bonding pads LP may include two bonding pads LP located at adjacent corners of a hexagonal structure and one bonding pad LP located inside a hexagon formed by a group of the six bonding pads LP. Similarly, the three adjacent bonding pads LP in a plurality of storage nodes SN may include two storage nodes SN located at adjacent corners of a hexagonal structure and one storage node SN located inside a hexagon formed by a group of the six storage nodes SN.

[0024] As used here, the center point of the bonding pad LP and the center point of the storage node SN can be represented as the center point of the top surface of the bonding pad LP and the center point of the top surface of the storage node SN when viewed from above (from the XY plane), respectively.

[0025] Figures 2A to 2C This is a schematic planar layout illustrating the arrangement of bonding pads included in a semiconductor memory device according to an embodiment.

[0026] Reference Figure 2A When viewed from above, the multiple bonding pads LP can have a hexagonal array structure. For example, the multiple bonding pads LP can be arranged in a straight line in a first lateral direction (X direction) and in a zigzag pattern in a second lateral direction (Y direction) to form a honeycomb shape.

[0027] exist Figure 2A The diagram also illustrates the bonding pad LP and a hypothetical reference bonding pad LPR to explain the arrangement of multiple bonding pads LP. In the multiple reference bonding pads LPR, the center points LPR-C of three adjacent reference bonding pads LPR can be connected by an isosceles triangle or an equilateral triangle, where at least two of the three interior angles of the triangle connecting the center points LPR-C of these three adjacent reference bonding pads LPR can have the same value. The diameter DI-R of the reference bonding pad LPR can be equal to the diameter DI-L of the bonding pad LP. In some embodiments, the multiple reference bonding pads LPR can be formed using a pattern density enhancement technique (such as DPT or QPT) including a photolithography process.

[0028] For example, the first reference interior angle θ1-R and the second reference interior angle θ2-R can be the interior angle between the base and the two sides, wherein the base connects the center points LPR-C of two adjacent reference mating pads LPR in the first lateral direction (X direction), and the two sides connect the center points LPR-C of the two adjacent reference mating pads LPR in the first lateral direction (X direction) to the center point LPR-C of a reference mating pad LPR adjacent to the two adjacent reference mating pads LPR in the second lateral direction (Y direction). The first reference interior angle θ1-R can be equal to the second reference interior angle θ2-R. In some embodiments, the third reference interior angle θ3-R can be the interior angle between the two sides connecting the center points LPR-C of the two adjacent reference mating pads LPR in the first lateral direction (X direction) to the center point LPR-C of the reference mating pad LPR adjacent to the two adjacent reference mating pads LPR in the second lateral direction (Y direction). The third reference interior angle θ3-R can be equal to each of the first reference interior angle θ1-R and the second reference interior angle θ2-R. For example, each of the first reference interior angle θ1-R, the second reference interior angle θ2-R, and the third reference interior angle θ3-R can be 60°.

[0029] In three adjacent reference mating pads (LPRs), the distance between the center points LPR-C of two adjacent reference mating pads (LPRs) in the first lateral direction (X direction) can be called the reference base distance (hereinafter referred to as the reference base side length) LB-R. The distance from the center points LPR-C of the two adjacent reference mating pads (LPRs) in the first lateral direction (X direction) to the center point LPR-C of a reference mating pad (LPR) adjacent to the two aforementioned reference mating pads (LPRs) in the second lateral direction (Y direction) can be called the first reference side distance (hereinafter referred to as the first reference side length) LS-R1 and the second reference side distance (hereinafter referred to as the second reference side length) LS-R2, respectively.

[0030] The first reference side length LS-R1 can be equal to the second reference side length LS-R2. For example, the first reference side length LS-R1 and the second reference side length LS-R2 can have a value of 3F (where F represents the feature size). For example, 3F can be approximately 25.6 nm, but is not limited thereto. In some embodiments, the first reference side length LS-R1, the second reference side length LS-R2, and the reference bottom side length LB-R can have the same value as the reference distance. For example, each of the first reference side length LS-R1, the second reference side length LS-R2, and the reference bottom side length LB-R, which is equal to the reference distance, can have a value of 3F. In some other embodiments, the reference bottom side length LB-R can be the reference distance, and the first reference side length LS-R1 and the second reference side length LS-R2 can have the same value that can be larger or smaller than the reference distance.

[0031] In a plurality of mating pads LP, three adjacent mating pads LP, for example, the center points LP-C of two mating pads LP that are adjacent to each other in the first lateral direction (X direction) and the center point LP-C of a mating pad LP that is adjacent to the two adjacent mating pads LP in the second lateral direction (Y direction) can be connected by an isosceles triangle.

[0032] For simplicity, among multiple bonding pads LP, the three bonding pads LP that are adjacent to each other so that the line connecting the center points LP-C of the three bonding pads LP forms a triangle can be referred to as the first bonding pad LP1, the second bonding pad LP2, and the third bonding pad LP3, respectively. For example, two bonding pads LP that are adjacent to each other in the first lateral direction (X direction) can be referred to as the first bonding pad LP1 and the second bonding pad LP2, respectively. The bonding pad LP that is adjacent to the first bonding pad LP1 and the second bonding pad LP2 in the second lateral direction (Y direction) between the first bonding pad LP1 and the second bonding pad LP2 can be referred to as the third bonding pad LP3.

[0033] The three interior angles of the triangle connecting the center points LP-C of the first, second, and third mating pads LP1, LP2, and LP3 can be distinct from each other. For example, the first interior angle θ1 can be the interior angle between the base of the center point LP-C connecting the first and second mating pads LP1 and LP2 and the side connecting the first and third mating pads LP1 and LP3. The second interior angle θ2 can be the interior angle between the base of the center point LP-C connecting the first and second mating pads LP1 and LP2 and the side connecting the second and third mating pads LP2 and LP3. The third interior angle θ3 can be the interior angle between the side connecting the first and third mating pads LP1 and the side connecting the second and third mating pads LP2 and LP3. The first interior angle θ1, the second interior angle θ2, and the third interior angle θ3 can be distinct from each other. The first interior angle θ1 can be different from the second interior angle θ2. For example, the first interior angle θ1 can be greater than 60°, and the second interior angle θ2 can be less than 60°. The third interior angle θ3 can have a value obtained by subtracting the first interior angle θ1 and the second interior angle θ2 from 180°.

[0034] The distance between the center points LP-C of the first bonding pad LP1 and the second bonding pad LP2 can be called the base distance (hereinafter referred to as the base side length) LB. The distance between the center points LP-C of the first bonding pad LP1 and the third bonding pad LP3 can be called the first side distance (hereinafter referred to as the first side length) LS1. In addition, the distance between the center points LP-C of the second bonding pad LP2 and the third bonding pad LP3 can be called the second side distance (hereinafter referred to as the second side length) LS2.

[0035] The base length LB and the reference base length LB-R can have the same value (i.e., the reference distance). For example, the base length LB can have the value 3F.

[0036] The first side length LS1 may be different from the second side length LS2. In some embodiments, the first side length LS1 may be smaller than the base side length LB (i.e., the reference distance), and the second side length LS2 may be larger than the base side length LB (i.e., the reference distance). For example, the first side length LS1 may be less than 3F, and the second side length LS2 may be greater than 3F.

[0037] Multiple bonding pads LP can be arranged in a straight line in a first lateral direction (X direction) and in a zigzag pattern in a second lateral direction (Y direction). Additionally, multiple reference bonding pads LPR can be arranged in a straight line in the first lateral direction (X direction) and in a zigzag pattern in the second lateral direction (Y direction). Each of the multiple bonding pads LP and the multiple reference bonding pads LPR can extend along its corresponding one of two adjacent bit lines BL. In some embodiments, the multiple bonding pads LP may not extend along the bit lines BL. For example, only a portion of the multiple bonding pads LP can extend along one of the two adjacent bit lines BL.

[0038] The center point LP-C of each of the plurality of bonding pads LP can be offset from the center point LPR-C of each of the plurality of reference bonding pads LPR in a direction away from its adjacent bit line BL along a first lateral direction (X direction) or in a direction opposite to the first lateral direction (X direction) (-X direction).

[0039] For example, the center point LP-C of each bonding pad LP arranged in a row in the first lateral direction (X direction) can be offset by a first movement distance CD1 from the center point LPR-C of each reference bonding pad LPR arranged in a row in the first lateral direction (X direction). Additionally, the center point LP-C of each bonding pad LP adjacent to the bonding pad LP arranged in the row in the second lateral direction (Y direction) and arranged in another row in the first lateral direction (X direction) can be offset by a second movement distance CD2 from the center point LPR-C of each reference bonding pad LPR arranged in a row in the first lateral direction (X direction) in the opposite direction (-X direction). In some embodiments, the first movement distance CD1 can be equal to the second movement distance CD2. For example, each of the first movement distance CD1 and the second movement distance CD2 can be greater than 0 and less than 0.75F. In some embodiments, each of the first movement distance CD1 and the second movement distance CD2 can be in the range from about 1 nm to about 6 nm.

[0040] Multiple bonding pads (LPs) can be formed using, for example, EUV lithography. In some embodiments, multiple bonding pads (LPs) can be formed without using pattern density enhancement techniques (such as DPT or QPT) that include a lithography process.

[0041] Therefore, with Figure 2A The multiple reference bonding pads LPR shown are different, and the multiple bonding pads LP can be formed into a twisted honeycomb shape.

[0042] Compared to the reference bonding pad LPR, the center point LP-C of the bonding pad LP can be offset in a direction away from its adjacent bit line BL. Therefore, the width of the bonding pad LP extending in the vertical direction (Z direction) (in the first transverse direction (X direction)) along the side surface of the adjacent bit line BL can be increased. Thus, the corresponding bonding pads LP and buried contacts (e.g., Figure 1 The overlap allowance between the buried contacts BC in the [contact] can be increased. Therefore, the reliability of the electrical connection between the corresponding bonding pads LP and buried contacts BC can be improved. Furthermore, the distance in the first lateral direction (X direction) between a bonding pad LP and the buried contact BC corresponding to its adjacent bonding pad LP can be increased. Therefore, bridging between the bonding pad LP and the adjacent buried contact BC can be prevented.

[0043] When multiple bonding pads LP are formed using a pattern density enhancement technique (such as DPT or QPT) that includes a single photolithography process, the top surface of each of the multiple bonding pads LP can be a rhombus or parallelogram shape with non-circular edges, or a rhombus or parallelogram shape with rounded edges. However, since the multiple bonding pads LP according to this embodiment can be formed using an EUV photolithography process, the top surface of each of the multiple bonding pads LP can be a disk shape with substantially circular edges rather than elliptical edges.

[0044] Therefore, the distance between the corresponding bonding pads LP can be increased. This prevents bridging between adjacent bonding pads LP and improves the insulation structure filling each space between multiple bonding pads LP (e.g., Figures 10A to 10D The gap-filling characteristics of the insulation structure 195 in the middle can be improved. As a result, the reliability of electrical insulation between the corresponding bonding pads LP can be improved.

[0045] Reference Figure 2BMultiple storage nodes (SNs) can be located on multiple bonding pads (LPs). For example, when viewed in a plan view, each storage node (SN) can be completely stacked with its corresponding bonding pad (LP). The diameter (DI-S) of the storage node (SN) can be larger than the diameter (DI-L) of the bonding pad (LP). The multiple bonding pads (LPs) can be arranged as shown in the reference... Figure 2A The described distorted cellular shape. Multiple storage nodes (SNs) can be arranged in a complete cellular shape.

[0046] The center points LP-C of the first bonding pad LP1, the second bonding pad LP2, and the third bonding pad LP3 can be connected by a scalene triangle. For example, the first interior angle θ1 and the second interior angle θ2 of the triangle connecting the center points LP-C of the first bonding pad LP1, the second bonding pad LP2, and the third bonding pad LP3 can be different. For example, the first interior angle θ1 can be greater than 60°, the second interior angle θ2 can be less than 60°, and the third interior angle θ3 can have a value obtained by subtracting the first interior angle θ1 and the second interior angle θ2 from 180°.

[0047] The center points SN-C of the three storage nodes SN corresponding to the first bonding pad LP1, the second bonding pad LP2, and the third bonding pad LP3, respectively, can be connected by an isosceles triangle or an equilateral triangle. For example, the distance between the center point SN-C of the storage node SN corresponding to the first bonding pad LP1 and the center point SN-C of the storage node SN corresponding to the third bonding pad LP3 can be equal to the distance between the center points SN-C of the storage node SN corresponding to the second bonding pad LP2 and the center point SN-C of the storage node SN corresponding to the third bonding pad LP3. In some embodiments, the distances between the center points SN-C of the three storage nodes SN corresponding to the first bonding pad LP1, the second bonding pad LP2, and the third bonding pad LP3 can have the same value as a reference distance. For example, the reference distance can be 3F. In some other embodiments, the distance between the center point SN-C of the storage node SN corresponding to the first bonding pad LP1 and the center point SN-C of the storage node SN corresponding to the second bonding pad LP2 can have the same value as the reference distance. The distance between the center point SN-C of the storage node SN corresponding to the first bonding pad LP1 and the center point SN-C of the storage node SN corresponding to the third bonding pad LP3 can have the same value as the distance between the center point SN-C of the storage node SN corresponding to the second bonding pad LP2 and the center point SN-C of the storage node SN corresponding to the third bonding pad LP3, which is slightly greater or less than the reference distance.

[0048] The triangle connecting the center points SN-C of the three storage nodes SN corresponding to the first bonding pad LP1, the second bonding pad LP2, and the third bonding pad LP3, respectively, can have a first node interior angle θ1-S and a second node interior angle θ2-S with the same value. In some embodiments, the third node interior angle θ3-S can be equal to each of the first node interior angle θ1-S and the second node interior angle θ2-S. For example, each of the first node interior angle θ1-S, the second node interior angle θ2-S, and the third node interior angle θ3-S can be 60°.

[0049] Reference Figure 2C Multiple bonding pads LP can have a hexagonal array structure. For example, multiple bonding pads LP can be arranged in a straight line in a first lateral direction (X direction) and in a zigzag pattern in a second lateral direction (Y direction) to form a honeycomb shape.

[0050] The center points LP-C of three adjacent mating pads LP (i.e., the first mating pad LP1, the second mating pad LP2, and the third mating pad LP3) can be connected by a scalene triangle. The three interior angles of the triangle connecting the center points LP-C of the first mating pad LP1, the second mating pad LP2, and the third mating pad LP3 can be distinct from each other. The first interior angle θ1 can be different from the second interior angle θ2. For example, the first interior angle θ1 can be greater than 60°, and the second interior angle θ2 can be less than 60°. The third interior angle θ3 can have a value obtained by subtracting the first interior angle θ1 and the second interior angle θ2 from 180°.

[0051] The first side length LS1 may be different from the second side length LS2. In some embodiments, the first side length LS1 may be smaller than the base side length LB, and the second side length LS2 may be larger than the base side length LB. For example, the first side length LS1 may be less than 3F, and the second side length LS2 may be greater than 3F.

[0052] The imaginary center extension line HVL can extend in the second lateral direction (Y direction) from the center of the bottom of the respective center point LP-C connecting the first bonding pad LP1 and the second bonding pad LP2. The imaginary center extension line HVL can be perpendicular to the bottom of the respective center point LP-C connecting the first bonding pad LP1 and the second bonding pad LP2. The center point LP-C of the third bonding pad LP3 can be spaced apart from the imaginary center extension line HVL by a center movement distance TCD in the first lateral direction (X direction) along a direction away from the bit line BL. The center movement distance TCD can be equal to... Figure 2AThe first moving distance CD1 and the second moving distance CD2 shown are the sum of the two moving distances. The center moving distance TCD can be greater than 0 and less than half the base length LB. For example, the center moving distance TCD can be greater than 0 and less than 1.5F. In some embodiments, the center moving distance TCD can be in the range of about 2 nm to about 12 nm.

[0053] For reference Figure 2A As described, the reliability of the electrical connection between the bonding pad LP and its corresponding buried contact BC according to this embodiment can be improved, and bridging between the bonding pad LP and another buried contact BC adjacent to its corresponding buried contact BC can be prevented. Furthermore, the reliability of the electrical insulation between the corresponding bonding pads LP can be improved.

[0054] In addition, as referenced Figure 2B As described, according to this embodiment, multiple storage nodes SN can be arranged in a honeycomb shape, such that the center points SN-C of three adjacent storage nodes SN are connected by isosceles or equilateral triangles. Therefore, each of the multiple storage nodes SN can have a diameter DI-S larger than the diameter DI-L of the bonding pad LP, and bridging between adjacent storage nodes SN can also be prevented. Thus, the size of multiple capacitor structures (e.g., Figure 10A and Figure 10C The capacitance of each of the capacitor structures 200 can be increased, thereby improving the data retention reliability of each of the multiple capacitor structures 200.

[0055] Figures 3A to 6D This is a cross-sectional view of the process sequence of a method for manufacturing a semiconductor memory device according to an example embodiment. Figure 7A This is a plan view of the operations for forming a mask pattern for forming a bonding pad included in a semiconductor memory device, according to an example embodiment. Figure 7B It is shown Figure 7A The diagram shows a schematic planar layout of the mask pattern arrangement. Figures 8A to 10D This is a cross-sectional view showing the process sequence of a method for manufacturing a semiconductor memory device according to an example embodiment. Specifically, Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 8A , Figure 9A and Figure 10A It is along Figure 1 or Figure 7A A sectional view taken by line A-A'. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 8B , Figure 9B and Figure 10B It is along Figure 1 or Figure 7A The sectional view taken by line B-B'. Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 8C , Figure 9C and Figure 10C It is along Figure 1 or Figure 7A A sectional view taken by line C-C'. Figure 3D , Figure 4D , Figure 5D , Figure 6D , Figure 8D , Figure 9D and Figure 10D It is along Figure 1 or Figure 7A A sectional view taken by line D-D'.

[0056] Reference Figures 3A to 3D Device isolation trenches 116T can be formed in the substrate 110, and device isolation films 116 can be formed to fill the device isolation trenches 116T respectively. Multiple active regions 118 can be defined in the substrate 110 by the device isolation films 116. Like... Figure 1 Like the active region ACT shown, each of the active regions 118 can be in the shape of a relatively long island with a short axis and a long axis.

[0057] For example, substrate 110 may include silicon (Si), such as crystalline Si, polycrystalline Si, or amorphous Si. Optionally, substrate 110 may include a semiconductor element such as germanium (Ge), or at least one compound semiconductor selected from silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Optionally, substrate 110 may have a silicon-on-insulator (SOI) structure. For example, substrate 110 may include a buried oxide layer (BOX). Substrate 110 may include conductive regions, such as doped wells or doped structures.

[0058] The device isolation film 116 may comprise, for example, a material comprising at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The device isolation film 116 may comprise a single layer comprising one insulating film, a double layer comprising two insulating films, or a multilayer structure comprising a combination of at least three insulating films. For example, the device isolation film 116 may comprise a double-layer or multilayer structure comprising an oxide film and a nitride film. However, according to the inventive concept, the construction of the device isolation film 116 is not limited to the above description.

[0059] Multiple word line grooves 120T can be formed in the substrate 110. The multiple word line grooves 120T can extend parallel to each other in a first lateral direction (X direction) and have a straight shape that intersects the active region 118 and is arranged approximately equidistantly in a second lateral direction (Y direction). For example, along... Figure 3B As shown in the cross-sectional portion taken along line B-B', steps may be formed at the bottom of the plurality of word line trenches 120T. For example, bumps may be formed above the substrate 110 along the bottom of the plurality of word line trenches 120T. In some embodiments, during the formation of the plurality of word line trenches 120T, separate etching processes may be used to etch the device isolation film 116 and the substrate 110, such that the etching depth of the device isolation film 116 is different from the etching depth of the substrate 110. For example, at the bottom of the plurality of word line trenches 120T, multiple upper surfaces of the substrate 110 may be higher than multiple upper surfaces of the device isolation film 116. In some embodiments, during the formation of the plurality of word line trenches 120T, the device isolation film 116 and the substrate 110 may be etched together, such that the etching depth of the device isolation film 116 is different from the etching depth of the substrate 110 due to the difference in etching rates between the device isolation film 116 and the substrate 110.

[0060] The resulting structure, including multiple word line trenches 120T, can be cleaned, and then multiple gate dielectric films 122, multiple word lines 120, and multiple buried insulating films 124 can be sequentially formed within the multiple word line trenches 120T. The multiple word lines 120 can constitute... Figure 1 The multiple word lines WL shown.

[0061] Multiple word lines 120 can fill the lower portion of multiple word line trenches 120T, and multiple buried insulating films 124 can cover the multiple word lines 120 and fill the upper portion of the multiple word line trenches 120T. Multiple gate dielectric films 122 can be formed between the multiple word lines 120, the device isolation film 116, and the substrate 110. Therefore, the multiple word lines 120 can extend parallel in the first lateral direction (X direction) and have a straight shape that intersects the active region 118 and is arranged at approximately equal intervals in the second lateral direction (Y direction). Similarly, the multiple buried insulating films 124 can extend parallel in the first lateral direction (X direction) and have a straight shape that intersects the active region 118 and is arranged at approximately equal intervals in the second lateral direction (Y direction).

[0062] For example, the multiple word lines 120 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), or combinations thereof. In some embodiments, each of the multiple word lines 120 may include a core layer and a barrier layer located between the core layer and the gate dielectric film 122. For example, the core layer may include a metallic material or a conductive metal nitride such as W, WN, TiSiN, or WSiN, and the barrier layer may include a metallic material or a conductive metal nitride such as Ti, TiN, Ta, or TaN.

[0063] The gate dielectric film 122 may include at least one selected from silicon oxide film, silicon nitride film, silicon oxynitride film, oxide / nitride / oxide (ONO) film, and high-k dielectric film having a higher dielectric constant than silicon oxide film. For example, the gate dielectric film 122 may have a dielectric constant of about 10 to about 25. In some embodiments, the gate dielectric film 122 may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxysilane (HfSiON), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, the gate dielectric film 122 may include HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2.

[0064] The top surfaces of the plurality of buried insulating films 124 may be located at substantially the same level as the top surface of the substrate 110. The buried insulating films 124 may include a material film selected from silicon oxide films, silicon nitride films, silicon oxynitride films, and combinations thereof.

[0065] The top surface of each of the multiple word lines 120 may be located at a lower level than the top surface of the substrate 110. The bottom surface of the multiple word lines 120 may have an uneven shape, and saddle-shaped fin field-effect transistors (FinFETs) may be formed in multiple active regions 118.

[0066] As used herein, the term "horizontal" refers to the height measured in the vertical direction (Z-direction) to the main surface of the substrate 110. That is, it will be understood that when two elements are referred to as being at the same or predetermined level, the two elements may have the same or predetermined height in the vertical direction (Z-direction) relative to the main surface of the substrate 110. Additionally, unless otherwise stated, it will be understood that when an element is referred to as being at a lower / higher level, the element may have a smaller / larger height in the vertical direction (Z-direction) relative to the main surface of the substrate 110. Terms such as "same," "equal," "planar," or "coplanar" as used herein include close similarity, including variations that may occur due to manufacturing processes. Unless the context or other statement otherwise indicates otherwise, the term "substantially" may be used herein to emphasize this meaning.

[0067] In some embodiments, after the multiple word lines 120 are formed, impurity ions can be implanted into portions of the active regions 118 of the substrate 110 located on either side of the multiple word lines 120, thus forming source and drain regions in the multiple active regions 118. In some other embodiments, ion implantation processes for forming source and drain regions can be performed prior to the formation of the multiple word lines 120.

[0068] Reference Figures 4A to 4D Insulating patterns 112 and 114 can be formed to cover the device isolation film 116, multiple active regions 118, and multiple buried insulating films 124. For example, insulating patterns 112 and 114 may include silicon oxide films, silicon nitride films, silicon oxynitride films, metal-based dielectric films, or combinations thereof.

[0069] In some embodiments, insulating patterns 112 and 114 may include a plurality of insulating films comprising stacked first insulating pattern 112 and second insulating pattern 114 (e.g., the second insulating pattern 114 is formed on the first insulating pattern 112). For example, the second insulating pattern 114 may have a higher dielectric constant than the first insulating pattern 112.

[0070] In some embodiments, the first insulating pattern 112 may include a silicon oxide film, and the second insulating pattern 114 may include a silicon oxynitride film.

[0071] In some other embodiments, the first insulating pattern 112 may include a non-metallic dielectric film, and the second insulating pattern 114 may include a metallic dielectric film. For example, the first insulating pattern 112 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. For example, the second insulating pattern 114 may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0072] Subsequently, a direct contact hole 134H can be formed to pass through insulating patterns 112 and 114. The direct contact hole 134H can be formed to expose the source region in the active region 118. In some embodiments, the direct contact hole 134H can extend into the active region 118, that is, into the source region.

[0073] Reference Figures 5A to 5D A direct contact conductive layer can be formed to fill the direct contact via 134H and cover the insulating patterns 112 and 114. The direct contact conductive layer may include, for example, silicon (Si), germanium (Ge), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or combinations thereof. In some embodiments, the direct contact conductive layer may include an epitaxial silicon layer. In some embodiments, the direct contact conductive layer may include doped polycrystalline silicon.

[0074] Subsequently, a metal-based conductive layer and an insulating capping layer can be sequentially formed to cover the insulating patterns 112 and 114, as well as the directly contacting conductive layer and the bit line structure 140.

[0075] In some embodiments, the metal-based conductive layer may have a stacked structure of a first metal-based conductive layer and a second metal-based conductive layer. The metal-based conductive layer may have, for example, a stacked structure of two layers, but the inventive concept is not limited thereto. For example, the metal-based conductive layer may include a single-layer or a stacked structure of at least three layers.

[0076] In some embodiments, the first metal-based conductive layer may include titanium nitride (TiN) or Ti-Si-N (TSN), and the second metal-based conductive layer may include tungsten (W) or a mixture of tungsten and tungsten silicide (WSi). xIn some embodiments, the first metal-based conductive layer may serve as a diffusion barrier. In some embodiments, the insulating capping layer may include a silicon nitride film.

[0077] A first metal-based conductive layer, a second metal-based conductive layer, and an insulating capping layer can be etched to form multiple bit lines 147 and multiple insulating capping lines 148. Each of the multiple bit lines 147 may include a first metal-based conductive pattern 145 and a second metal-based conductive pattern 146, each having a straight line shape. The side surfaces of the first metal-based conductive pattern 145, the second metal-based conductive pattern 146, and the multiple insulating capping lines 148 can be aligned with each other. A bit line 147 and an insulating capping line 148 covering the bit line 147 can constitute a bit line structure 140.

[0078] In some embodiments, the bit line structure 140 may further include a conductive semiconductor pattern 132 disposed between the insulating patterns 112 and 114 and the first metal-based conductive pattern 145. The conductive semiconductor pattern 132 may include doped polysilicon. In some embodiments, the conductive semiconductor pattern 132 may be omitted.

[0079] Multiple bit line structures 140, including multiple bit lines 147 and multiple insulating cover lines 148, can extend parallel to each other in a second transverse direction (Y direction) parallel to the main surface of the substrate 110. The multiple bit lines 147 can constitute... Figure 1 The multiple bit lines BL shown.

[0080] During the etching process used to form multiple bit lines 147, the portion of the direct contact conductive layer that is not vertically stacked with the bit lines 147 can be removed together with the etching process to form multiple direct contact conductive patterns 134. In this case, insulating patterns 112 and 114 can be used as etching stop films during the etching process forming the multiple bit lines 147 and the multiple direct contact conductive patterns 134. The multiple direct contact conductive patterns 134 can constitute Figure 1 The diagram shows multiple direct contact DCs. Multiple bit lines 147 can be electrically connected to multiple active regions 118 via multiple direct contact conductive patterns 134.

[0081] In some embodiments, the conductive semiconductor pattern 132 may be formed concurrently with the process of removing the portion of the direct contact conductive layer to form the direct contact conductive pattern 134. For example, in the portion of the direct contact conductive layer vertically superimposed with the bit line 147, the conductive semiconductor pattern 132 may be a portion located on the insulating patterns 112 and 114 without being vertically superimposed with the direct contact hole 134H, while the direct contact conductive pattern 134 may be a portion vertically superimposed with the direct contact hole 134H and in contact with the active region 118.

[0082] Two sidewalls of the plurality of bitline structures 140 may be covered by a plurality of insulating spacer structures 150. Each of the plurality of insulating spacer structures 150 may include a first insulating spacer 152, a second insulating spacer 154, and a third insulating spacer 156. The second insulating spacer 154 may include a material having a lower dielectric constant than the materials of the first insulating spacer 152 and the third insulating spacer 156. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may include a nitride film, and the second insulating spacer 154 may include an oxide film. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may include a nitride film, and the second insulating spacer 154 may include a material having etch selectivity relative to the first insulating spacer 152 and the third insulating spacer 156. For example, when the first insulating spacer 152 and the third insulating spacer 156 include a nitride film, the second insulating spacer 154 may include an oxide film. The second insulating spacer 154 may be removed during a subsequent process to form an air spacer.

[0083] Multiple buried contact holes 170H can be formed between multiple bit lines 147. The internal space of each of the multiple buried contact holes 170H can be defined by an active region 118 and an insulating spacer structure 150 covering the sidewalls of each of two adjacent bit lines among the multiple bit lines 147.

[0084] A plurality of buried contact holes 170Hs can be formed by using an insulating spacer structure 150 covering two sidewalls of each of a plurality of bit line structures 140 including multiple insulating cover lines 148 as an etching mask to remove portions of the insulating patterns 112, 114 and the active region 118. The formation of the plurality of buried contact holes 170Hs may include performing an anisotropic etching process for removing portions of the insulating patterns 112, 114 and the active region 118 by using the insulating spacer structure 150 covering two sidewalls of each of the plurality of bit line structures 140 including multiple insulating cover lines 148 as an etching mask, and then performing an isotropic etching process for further removing other portions of the active region 118 to expand the space defined by the active region 118.

[0085] Reference Figures 6A to 6D Multiple buried contacts 170 and multiple insulating barriers 180 can be formed in the space between multiple insulating spacer structures 150 covering the two sidewalls of the corresponding bit line structure 140. The multiple buried contacts 170 and multiple insulating barriers 180 can be alternately positioned along the space between a pair of insulating spacer structures 150 covering the two sidewalls of the multiple bit line structure 140 (i.e., in the second lateral direction (Y direction)).

[0086] For example, multiple buried contacts 170 may include polysilicon. For example, multiple insulating fences 180 may include nitride films.

[0087] In some embodiments, a plurality of buried contacts 170 may be arranged in a straight line in each of a first lateral direction (X direction) and a second lateral direction (Y direction). Each of the plurality of buried contacts 170 may extend from the active region 118 in a vertical direction (Z direction) perpendicular to the substrate 110. The plurality of buried contacts 170 may constitute Figure 1 The multiple buried contacts BC shown.

[0088] Multiple buried contacts 170 can be arranged in a space defined by multiple insulating fences 180 and multiple insulating spacer structures 150 covering the two sidewalls of multiple bit line structures 140.

[0089] Forming the plurality of buried contacts 170 may include forming an initial buried contact material layer to fill the plurality of buried contact holes 170H and removing the upper portion of the initial buried contact material layer. For example, the initial buried contact material layer may include polysilicon.

[0090] The top surfaces of the plurality of buried contacts 170 may be located at a lower level than the top surfaces of the plurality of insulating cover wires 148. The top surfaces of the plurality of insulating fences 180 may be located at the same level as the top surfaces of the insulating cover wires 148 in the vertical direction (Z direction). Therefore, the top surfaces of the plurality of buried contacts 170 may be located at a lower level than the top surfaces of the plurality of insulating fences 180.

[0091] Multiple mating pad holes 190H may be defined by multiple insulating spacer structures 150 and multiple insulating fences 180. Multiple buried contacts 170 may be exposed at the bottom of the multiple mating pad holes 190H.

[0092] In some embodiments, after forming a plurality of insulating barriers 180, an initial burial contact material layer may be formed. In some other embodiments, after forming the initial burial contact material layer, a plurality of insulating barriers 180 may be formed. In some other embodiments, after forming a plurality of insulating barriers 180, a reference layer may be formed. Figures 5A to 5DThe description includes multiple buried contact holes 170H, and an initial buried contact material layer can be formed to fill the multiple buried contact holes 170H.

[0093] Multiple buried contacts 170 may fill the lower portion of the space between multiple insulating spacer structures 150 that cover the two sidewalls of the respective bit line structure 140. In some embodiments, the top surfaces of the multiple buried contacts 170 may be formed at a level equal to or higher than the level of the top surface of the bit line 147, but the inventive concept is not limited thereto.

[0094] During the formation of multiple buried contacts 170, the upper part of the insulating spacer structure 150 and the insulating cover wire 148 included in the position line structure 140 can be removed, thereby lowering the level of the top surface of the position line structure 140.

[0095] Reference Figures 7A to 8D A bonding pad material layer 190P can be formed to fill multiple bonding pad holes 190H and cover multiple bit line structures 140, and multiple mask patterns MK can be formed on the bonding pad material layer 190P.

[0096] In some embodiments, a metal silicide film may be formed on the plurality of buried contacts 170 prior to forming the bonding pad material layer 190P. The metal silicide film may be located between the plurality of buried contacts 170 and the bonding pad material layer 190P. The metal silicide film may include cobalt silicide (CoSi). x Nickel silicide (NiSi) x ) or manganese silicide (MnSi) x (but not limited to this).

[0097] In some embodiments, the bonding pad material layer 190P may include a conductive barrier film and a conductive pad material layer situated on the conductive barrier film. For example, the conductive barrier film may include a metal, a conductive metal nitride, or a combination thereof. In some embodiments, the conductive barrier film may have a Ti / TiN stacked structure. For example, the conductive pad material layer may include a metal. In some embodiments, the conductive pad material layer may include tungsten (W).

[0098] Multiple mask patterns MK can be formed using, for example, EUV lithography. In some embodiments, multiple mask patterns MK can be formed without using pattern density enhancement techniques (such as DPT or QPT) that include a single lithography process. When viewed from top to bottom, the top surface of each of the multiple mask patterns MK can be formed into a disk shape whose edges are not elliptical but substantially rounded, but the inventive concept is not limited thereto. For example, the top surface of each of the multiple mask patterns MK can be modified to have a disk shape whose edges are substantially rounded by using an optical proximity correction (OPC) method, such that when viewed from top to bottom, it appears as multiple bonding pads (e.g., ...) of the resulting structure obtained by etching the bonding pad material layer 190P using multiple mask patterns MK as etching masks. Figure 9A and Figure 9C Each of the bonding pads 190 has a top surface with a disc shape whose edges are not elliptical but substantially circular. The side surfaces at the edges of each of the multiple mask patterns MK may be substantially perpendicular to the top surface of the bonding pad material layer 190P.

[0099] Multiple mask patterns MK can have a hexagonal array structure. For example, multiple mask patterns MK can be arranged in a straight line in a first lateral direction (X direction) and in a zigzag pattern in a second lateral direction (Y direction) to form a honeycomb shape.

[0100] To illustrate the arrangement of multiple mask patterns MK, in Figure 7B The image shows a mask pattern MK and a hypothetical reference mask pattern MKR. In a plurality of reference mask patterns MKR, the center points MKR-C of three adjacent reference mask patterns MKR can be connected by an isosceles triangle or an equilateral triangle. The diameter DI-MR of the reference mask pattern MKR can be equal to the diameter DI-M of the mask pattern MK. In some embodiments, a pattern density enhancement technique (such as DPT or QPT) including a single photolithography process can be used to form the plurality of reference mask patterns MKR.

[0101] For example, because the three interior angles of the triangle connecting the center point MKR-C of three adjacent reference mask patterns MKR are perpendicular to the reference... Figure 2A The first reference interior angle θ1-R, the second reference interior angle θ2-R, and the third reference interior angle θ3-R are substantially the same, so their detailed description will be omitted. The first reference interior angle θ1-R may be equal to the second reference interior angle θ2-R. In some embodiments, the third reference interior angle θ3-R may be equal to each of the first reference interior angle θ1-R and the second reference interior angle θ2-R. For example, each of the first reference interior angle θ1-R, the second reference interior angle θ2-R, and the third reference interior angle θ3-R may be 60°.

[0102] Since the distance between the center points MKR-C of the three adjacent reference mask patterns MKR is substantially the same as the reference bottom side length LB-R, the first reference side length LS-R1 and the second reference side length LS-R2 shown in Figure 2, a detailed description of them will be omitted.

[0103] Among multiple mask patterns MK, three mask patterns MK that are adjacent to each other, for example, the center points MK-C of two mask patterns MK that are adjacent to each other in the first lateral direction (X direction) and the center point MK-C of a mask pattern MK that is adjacent to the two adjacent mask patterns MK in the second lateral direction (Y direction) can be connected by an isosceles triangle.

[0104] Among multiple mask patterns MK, respectively, and reference... Figure 2A The three adjacent mask patterns MK corresponding to the first bonding pad LP1, the second bonding pad LP2, and the third bonding pad LP3 described can be referred to as the first mask pattern MK1, the second mask pattern MK2, and the third mask pattern MK3, respectively.

[0105] The three interior angles of the triangle connecting the center points MK-C of the first mask pattern MK1, the second mask pattern MK2, and the third mask pattern MK3 can be distinct from each other. Since the three interior angles of the triangle connecting the center points MK-C of the first mask pattern MK1, the second mask pattern MK2, and the third mask pattern MK3 are relative to a reference... Figure 2A The first interior angle θ1, the second interior angle θ2, and the third interior angle θ3 are described as essentially the same, so their detailed descriptions will be omitted. For example, the first interior angle θ1, the second interior angle θ2, and the third interior angle θ3 can be different from each other. The first interior angle θ1 and the second interior angle θ2 can have different values. For example, the first interior angle θ1 can be greater than 60°, and the second interior angle θ2 can be less than 60°. The third interior angle θ3 can have a value obtained by subtracting the first interior angle θ1 and the second interior angle θ2 from 180°.

[0106] The distance between the center points MK-C of the first mask pattern MK1, the second mask pattern MK2, and the third mask pattern MK3 can be... Figure 2A The base length LB, the first side length LS1, and the second side length LS2 shown are substantially the same. The base length LB can be equal to a reference base length LB-R. For example, the base length LB can have a value of 3F. The first side length LS1 can be different from the second side length LS2. In some embodiments, the first side length LS1 can be smaller than the base length LB, and the second side length LS2 can be larger than the base length LB. For example, the first side length LS1 can be less than 3F, and the second side length LS2 can be greater than 3F.

[0107] Multiple mask patterns MK can be arranged in a straight line in the first lateral direction (X direction) and in a zigzag pattern in the second lateral direction (Y direction).

[0108] The center point MK-C of each of the multiple mask patterns MK can be offset from the center point MKR-C of each of the multiple reference mask patterns MKR in a direction away from its adjacent bit line BL along a first lateral direction (X direction) or in a direction opposite to the first lateral direction (X direction) (-X direction).

[0109] For example, the center point MK-C of each of the mask patterns MK arranged in a row in the first lateral direction (X direction) can be offset by a first movement distance CD1 from the center point MKR-C of each of the reference mask patterns MKR arranged in a row in the first lateral direction (X direction). The center point MK-C of each of the mask patterns MK adjacent to each other in the second lateral direction (Y direction) and arranged in another row in the first lateral direction (X direction) can be offset by a second movement distance CD2 from the center point MKR-C of each of the reference mask patterns MKR arranged in a row in the first lateral direction (X direction) in the opposite direction (-X direction). In some embodiments, the first movement distance CD1 can be equal to the second movement distance CD2. For example, each of the first movement distance CD1 and the second movement distance CD2 can be greater than 0 and less than 0.75F. In some embodiments, each of the first movement distance CD1 and the second movement distance CD2 can be in the range from about 1 nm to about 6 nm.

[0110] Multiple mask patterns MK can be formed using, for example, EUV lithography. In some embodiments, multiple mask patterns MK can be formed without using pattern density enhancement techniques (such as DPT or QPT) that include a single lithography process.

[0111] Therefore, unlike multiple reference mask patterns MKR arranged to have a complete honeycomb shape, multiple mask patterns MK can be formed to have a distorted honeycomb shape.

[0112] Reference Figures 9A to 9DA plurality of bonding pads 190 may be formed to fill at least a portion of a plurality of bonding pad holes 190H, and the plurality of bonding pads 190 may extend over a plurality of bit line structures 140. The plurality of bonding pads 190 may be located on a plurality of buried contacts 170 and extend over a plurality of bit line structures 140. In some embodiments, the plurality of bonding pads 190 may extend over a plurality of bit lines 147. The plurality of bonding pads 190 may be located on a plurality of buried contacts 170, thus the plurality of buried contacts 170 may be electrically connected to their corresponding plurality of bonding pads 190. The plurality of bonding pads 190 may be connected to the active region 118 through the plurality of buried contacts 170. The plurality of bonding pads 190 may constitute Figure 1 The multiple bonding pads LP shown.

[0113] A buried contact 170 and a mating pad 190 located on the buried contact 170 can be collectively referred to as a contact structure. The buried contact 170 included in the contact structure can be located between two adjacent bit line structures 140. The mating pad 190 can extend from the space between two adjacent bit line structures 140 having the buried contact 170 to one bit line structure 140. That is, the mating pad 190 can be electrically connected to the buried contact 170 and extends from the space between two adjacent bit line structures 140 having the buried contact 170 to one bit line structure 140 to be vertically stacked with said bit line structure 140.

[0114] The formation of multiple bonding pads 190 may include: forming Figures 7A to 8D The diagram shows a bonding pad material layer 190P; a plurality of mask patterns MK are used as etching masks to form recessed units 190R; and the bonding pad material layer 190P is separated into a plurality of bonding pads 190 to correspond to a plurality of buried contacts 170 respectively. The plurality of bonding pads 190 may be spaced apart from each other and the recessed units 190R are located between the plurality of bonding pads 190. The upper ends of the insulating spacer structures 150, the upper ends of the insulating cover lines 148, and the upper ends of the insulating fences 180 may be exposed inside the recessed units 190R. In some embodiments, during the formation of the recessed units 190R, a portion of the bonding pad material layer 190P, the upper portions of the plurality of insulating spacer structures 150, the upper portions of the plurality of insulating cover lines 148, and the upper portions of the plurality of insulating fences 180 may be removed together.

[0115] Reference Figures 10A to 10DA plurality of lower electrodes 210, a capacitor dielectric film 220, and an upper electrode 230 can be sequentially formed on a plurality of bonding pads 190, thereby forming a semiconductor memory device 1 including a plurality of capacitor structures 200. The plurality of lower electrodes 210 can be electrically connected to the plurality of bonding pads 190 to correspond to the plurality of bonding pads 190 respectively. The capacitor dielectric film 220 can conformally cover the plurality of lower electrodes 210. The upper electrode 230 can cover the capacitor dielectric film 220. The upper electrode 230 can be formed opposite to the lower electrodes 210 and with the capacitor dielectric film 220 located between the upper electrode 230 and the lower electrodes 210. Each of the capacitor dielectric film 220 and the upper electrode 230 can be integrally formed to cover the plurality of lower electrodes 210 in a predetermined region (e.g., in a memory cell region). The plurality of lower electrodes 210 can constitute Figure 1 The multiple storage nodes SN shown are illustrated.

[0116] Each of the plurality of lower electrodes 210 may have a cylindrical shape with its interior filled with a circular horizontal cross-section, but is not limited thereto. In some embodiments, each of the plurality of lower electrodes 210 may have a cylindrical shape with its bottom blocked. In some embodiments, the plurality of lower electrodes 210 may be arranged in a zigzag pattern in a first lateral direction (X direction) or a second lateral direction (Y direction) to form a honeycomb shape. In some other embodiments, the plurality of lower electrodes 210 may be arranged in a straight line in each of the first lateral direction (X direction) and the second lateral direction (Y direction) to form a matrix shape. The plurality of lower electrodes 210 may include, for example, doped silicon, a metal such as tungsten or copper, or a conductive metal compound such as titanium nitride. Although not shown separately, the semiconductor memory device 1 may also include at least one support pattern in contact with the sidewalls of the plurality of lower electrodes 210.

[0117] The capacitor dielectric film 220 may include, for example, TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST ((Ba,Sr)TiO), STO (SrTiO), BTO (BaTiO), PZT (Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O, or combinations thereof.

[0118] The upper electrode 230 may include, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba,Sr)RuO), CRO (CaRuO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or combinations thereof.

[0119] Before forming the plurality of capacitor structures 200, an insulating structure 195 may be formed to fill the recessed units 190R. In some embodiments, the upper surface of the insulating structure 195 may be coplanar with the upper surface of the bonding pad 190 and may contact the bottom surface of the capacitor dielectric film 220. In some embodiments, the insulating structure 195 may include an interlayer insulating layer and an etch stop film. For example, the interlayer insulating layer may include an oxide film, and the etch stop film may include a nitride film. Although Figure 10A and Figure 10C The illustration shows a case where the top surface of the insulating structure 195 and the bottom surface of the lower electrode 210 are at the same level, but the inventive concept is not limited thereto. For example, the top surface of the insulating structure 195 may be at a higher level than the bottom surface of the lower electrode 210, and the lower electrode 210 may extend toward the substrate 110 into the insulating structure 195.

[0120] Since the semiconductor memory device 1 according to this embodiment is formed by offsetting the center point of each of the plurality of bonding pads 190 in a direction away from its adjacent bit line structure 140, the width (in the first lateral direction (X direction)) of the plurality of bonding pads 190 extending in the vertical direction (Z direction) along the side surface of the adjacent bit line structure 140 can be increased. Therefore, the stacking margin between the corresponding bonding pads 190 and the buried contacts 170 can be increased, thereby improving the reliability of the electrical connection between the corresponding bonding pads 190 and the buried contacts 170. In addition, since the distance (in the first lateral direction (X direction)) between a bonding pad 190 and the buried contact 170 connected to another bonding pad 190 adjacent to the bonding pad 190 is increased, bridging between the bonding pad 190 and the buried contact 170 connected to another bonding pad 190 adjacent to the bonding pad 190 can be prevented.

[0121] Furthermore, the top surface of each of the plurality of bonding pads 190 may have a disc shape whose edges are not elliptical but substantially circular. Therefore, by increasing the distance between the respective bonding pads 190, bridging between adjacent bonding pads 190 can be prevented, and the gap-filling characteristics of the insulating structure 195 filling the space between the respective bonding pads 190 can be improved. Thus, the reliability of the electrical insulation between the respective bonding pads 190 can be improved.

[0122] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: Multiple bit line structures, including bit lines extending parallel to a first lateral direction on a substrate; as well as The system includes multiple buried contacts and multiple bonding pads, the buried contacts filling the lower portion of the space between the multiple bit line structures on a substrate, and the bonding pads filling the upper portion of the space between the multiple bit line structures and extending over the multiple bit line structures. The plurality of bonding pads have a hexagonal array structure, and the center points of the top surfaces of the first, second, and third bonding pads that are adjacent to each other are connected by an isosceles triangle.

2. The semiconductor memory device according to claim 1, wherein, The plurality of mating pads are arranged in a straight line in a second lateral direction perpendicular to the first lateral direction, and in a zigzag pattern in the first lateral direction.

3. The semiconductor memory device according to claim 1, in, The first and second bonding pads are arranged along a second transverse direction perpendicular to the first transverse direction. The first interior angle between the two sides connecting the center point of the top surface of the first bonding pad and the center point of the top surface of the second bonding pad and the center point of the top surface of the third bonding pad is different from the second interior angle between the two sides connecting the center point of the top surface of the second bonding pad and the center point of the top surface of the first bonding pad and the center point of the top surface of the third bonding pad.

4. The semiconductor memory device according to claim 3, wherein, The first interior angle is greater than 60° and the second interior angle is less than 60°.

5. The semiconductor memory device according to claim 1, in, The center point of the top surface of the third bonding pad is positioned such that it is separated from the center extension line in a second lateral direction perpendicular to the first lateral direction, and The center extension line extends along a first lateral direction from the center of the side connecting the center point of the respective top surface of the first and second bonding pads.

6. The semiconductor memory device according to claim 5, in, The distance between the center points of the top surfaces of the first and second bonding pads is 3F, and the center point of the top surface of the third bonding pad is located at a distance between 0 and 1.5F from the center extension line in the second lateral direction. Where F represents the feature size.

7. The semiconductor memory device according to claim 5, wherein, The center point of the top surface of the third bonding pad is located at a distance of 2nm to 12nm from the center extension line in the second lateral direction.

8. The semiconductor memory device according to claim 5, wherein, The distance between the center points of the top surfaces of the first and third bonding pads is less than 3F, and the distance between the center points of the top surfaces of the second and third bonding pads is greater than 3F.

9. The semiconductor memory device according to claim 1, wherein, The top surface of each of the plurality of bonding pads has a disc-shaped shape.

10. The semiconductor memory device of claim 1, further comprising: Multiple storage nodes are located on the multiple bonding pads. The plurality of storage nodes have a hexagonal array structure, and the center points of the top surfaces of the first, second and third storage nodes that are adjacent to each other are connected by an equilateral triangle.

11. A semiconductor memory device, the semiconductor memory device comprising: The substrate contains multiple active regions. Multiple word lines intersect with the multiple active regions and extend parallel to each other in the first lateral direction; Multiple bitline structures, including bitlines on a substrate, the bitlines extending parallel in a second lateral direction perpendicular to the first lateral direction; A plurality of buried contacts and a plurality of bonding pads, wherein the plurality of buried contacts fill the lower portion of the space between the plurality of bit line structures on a substrate, and the plurality of bonding pads fill the upper portion of the space between the plurality of bit line structures and extend over the plurality of bit line structures; and Multiple storage nodes are located on the multiple bonding pads. The plurality of bonding pads have a hexagonal array structure, and the center points of the top surfaces of three adjacent bonding pads are connected by a scalene triangle. The plurality of storage nodes have a hexagonal array structure, and the center points of the top surfaces of three adjacent storage nodes are connected by an equilateral triangle.

12. The semiconductor memory device according to claim 11, in, The plurality of mating pads are arranged in a straight line in the first lateral direction and in a zigzag pattern in the second lateral direction, and The plurality of storage nodes are arranged in a straight line in the first horizontal direction and in a zigzag pattern in the second horizontal direction.

13. The semiconductor memory device according to claim 11, wherein, Each of the plurality of bonding pads has a rounded edge on its top surface.

14. The semiconductor memory device of claim 11, wherein, The distance between the center points of the top surfaces of three adjacent storage nodes in the plurality of storage nodes has the same reference distance value.

15. The semiconductor memory device according to claim 14, in, The length of the first side of the triangle connecting the center points of the top surfaces of three adjacent mating pads in the plurality of mating pads is equal to the reference distance, and In this triangle, the second and third sides have lengths less than and greater than the reference distance, respectively.

16. A semiconductor memory device, the semiconductor memory device comprising: The substrate contains multiple active regions confined within it by a device isolation film. Multiple word lines intersect with the multiple active regions and extend parallel to each other in the first lateral direction; Multiple bitline structures are located on a substrate, the multiple bitline structures having bitlines extending parallel to each other in a second lateral direction perpendicular to a first lateral direction; Multiple buried contacts fill the lower portion of the space located between the multiple bit line structures on the substrate, and the multiple buried contacts are connected to the multiple active regions; A plurality of bonding pads are connected to the plurality of buried contacts, the plurality of bonding pads filling the upper portion of the space between the plurality of bit line structures and extending onto the plurality of bit line structures, wherein the top surface of each of the plurality of bonding pads has a disc-shaped shape; and Multiple storage nodes are located on the multiple bit line structures and connected to the multiple bonding pads. Wherein, the first side, second side, and third side of the triangle connecting the center points of the top surfaces of three adjacent mating pads among the plurality of mating pads have lengths of 3F, less than 3F, and greater than 3F, respectively, where F represents the feature dimension, and Each of the first, second, and third sides of the triangle connecting the center points of the top surfaces of three adjacent storage nodes has a length of 3F.

17. The semiconductor memory device of claim 16, wherein, The plurality of bonding pads are arranged in a straight line in the first lateral direction and in a zigzag pattern in the second lateral direction perpendicular to the first lateral direction to form a hexagonal array structure, and the plurality of storage nodes are arranged in a straight line in the first lateral direction and in a zigzag pattern in the second lateral direction to form a hexagonal array structure.

18. The semiconductor memory device according to claim 17, wherein, The center extension line extends in a second lateral direction from the center of the edge connecting the center points of the respective top surfaces of the first and second joint pads, which are positioned adjacent to each other in a first lateral direction, of the plurality of joint pads. The center point of the top surface of the third joint pad is positioned separate from the center extension line in the first lateral direction.

19. The semiconductor memory device of claim 18, wherein, The center point of the top surface of the third bonding pad is located at a distance from the center extension line that is less than half the distance between the center points of the respective top surfaces of the first and second bonding pads, which are adjacent to each other in the first lateral direction, among the plurality of bonding pads.

20. The semiconductor memory device of claim 18, wherein, The center point of the top surface of the third bonding pad is located at a distance of 2 nm to 12 nm from the center extension line in the first lateral direction.

Images