An apparatus and working method for AI chip system architecture verification

Abstract

The application provides a device and working method for AI chip system architecture verification, including a control center for logic control, timing coordination and data interaction of each module. A pulse writing module generates a writing signal with a special pulse form to realize state programming and conduct adjustment of storage or computing devices. A programming selection module accepts the signal of the pulse writing module, supports the structure requirements of various different memory devices of the measured unit, and performs different selective writing according to different array structures. A decoding module accepts the signal of the programming selection module and the feedback signal of the measured unit to be read, and is used for address space mapping, excitation line management and signal on-off control. The measured unit accepts the writing signal of the decoding module and feeds back the reading signal to the decoding module, and is used for storing neural network weights, logic states or continuous conduct grades. The application provides key test support and decision basis for AI chip system architecture research.

Description

Technical Field

[0001] This invention belongs to the field of artificial intelligence technology, and in particular relates to a device and working method for verifying AI chip system architecture. Background Technology

[0002] In recent years, with the rapid development of artificial intelligence technology, especially the significant breakthroughs achieved by various neural networks in fields such as image recognition, speech processing, and natural language understanding, higher demands have been placed on the underlying hardware in terms of computing power and energy efficiency. Traditional computing systems based on the von Neumann architecture physically separate memory from the processor, resulting in a large number of data transfer operations with each calculation, creating the so-called "memory wall" bottleneck, which severely limits the overall computing efficiency and energy consumption of the system.

[0003] To alleviate this problem, computing-in-memory (CIM) architecture has gradually become a research focus for next-generation intelligent computing platforms. This architecture performs computations within or near the memory array, effectively reducing data movement and theoretically significantly improving system energy efficiency. Novel memory types (such as resistive random access memory (RRAM), phase-change memory (PCM), ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM), two-dimensional memory, and analog transistors) are considered crucial technological foundations for key areas such as neuromorphic computing, AI inference chips, and edge intelligent devices due to their non-volatility, high density, multi-level controllability, and resistive computing characteristics naturally compatible with CIM architecture.

[0004] However, current verification methods mostly focus on testing at the SoC level or individual device level, lacking a system-level verification platform that supports functions such as network structure mapping, path configuration, range adjustment, and energy consumption assessment. Especially in the research and development of future computing architectures such as AI chips, IoT chips, and neuromorphic chips, there is an urgent need for a targeted and systematic verification device for novel storage technologies. This device would be used to explore the collaborative mechanisms between novel storage devices and system architectures, support closed-loop evaluation from device behavior to overall performance, and accelerate the architecture selection and deployment of next-generation intelligent computing platforms.

[0005] Existing technology 1 like Figure 1As shown, mainstream automated test equipment (ATE) on the market, such as Advantest's V9300 series, is mainly used in mass production testing processes for SoC chips. Its core objective is to perform large-scale, high-throughput, and high-consistency functional verification, electrical performance testing, and environmental stability assessment of standard chip products. An ATE system typically consists of a controller, signal source, measuring instruments, switching system, adapter, and interfaces for connecting the unit under test (UUT). It supports multi-channel switching and automated control via switching commands, features standardized hardware configuration and programmable test processes, and is widely used in mass production testing lines after chip tape-out.

[0006] SoC chips integrate multiple functional modules, encompassing various types of circuits such as processor cores, memory control, and I / O interfaces. Testing tasks are highly versatile and complex. Therefore, ATE platform design often emphasizes compatibility and process automation rather than in-depth verification of a specific core module. Its testing process is highly closed, with fixed configuration logic, making it difficult to adapt to the flexible path configuration, pulse behavior control, and structural signal mapping required for system architecture exploration. Especially in emerging system architectures built with novel memory technologies, such as in-memory computing, neuromorphic neural network chips, and edge AI acceleration platforms, developers need to explore the impact of different memory structures on system energy efficiency, accuracy, and topology configuration under real-world application conditions. These requirements clearly exceed the intended functional scope of ATE systems. Furthermore, ATE systems are expensive and modular, lacking essential functions for research scenarios such as on-chip control, real-time debugging, path tracing, and energy consumption analysis.

[0007] Therefore, although it is indispensable in traditional SoC product testing, it is not suitable as an emerging memory test platform for AI chip system architecture verification.

[0008] Existing technology 2 like Figure 2 As shown, unlike ATE (Automatic Test Equipment) which is geared towards SoC (System-on-a-Chip) mass production testing, Semiconductor Parameter Analyzers (SPAs) are primarily used for high-precision characterization of the electrical performance and physical mechanism research of individual devices. Typical examples include the Keysight B1500A and Keithley 4200A models, which integrate high-resolution voltage / current sources, pulse waveform modules, and data acquisition channels. They support DC IV measurements, capacitance-voltage scanning (CV), and impulse response analysis, making them core instruments for early material evaluation, electrical modeling, and parameter extraction of novel devices.

[0009] In testing novel memory devices, Spatial Spectrometers (SPAs) can be used to observe the conductance changes of devices under different pulse conditions, plot hysteresis curves for multi-cycle writes, and evaluate physical characteristics such as conduction stability and multi-level adjustability. Their high-resolution current sensing capability (down to the pA level) and precise voltage control capability (down to the μ level) make them an important tool for exploring cell behavior in the early stages of research. However, SPA applications are still concentrated at the cell level, with test objects mostly being single-point devices or finite-scale arrays, making them unsuitable for building system-level test frameworks or executing complex read / write logic flows. Their operation mode is primarily serial, resulting in slow measurement speeds, which cannot meet the needs of large-scale testing or high-throughput evaluation. Furthermore, most SPAs lack functions such as programmable path selection, dynamic weight configuration, analog range adjustment, or online power consumption analysis, and cannot support read / write mapping and application behavior simulation at the neural network level.

[0010] Therefore, although semiconductor parameter analyzers have irreplaceable value in device physics research, their functional dimensions and control capabilities are still significantly limited in testing scenarios for new memory systems applied to system-level applications (such as in-memory computing and neuromorphic computing), and there is an urgent need to supplement them with testing platforms that are systematic, integrated, and application-adaptable. Summary of the Invention

[0011] The purpose of this invention is to address the shortcomings of existing technologies by providing a device and method for verifying AI chip system architecture. This device performs a complete functional process, including write pulse control, data read sampling, path configuration, power consumption monitoring, and structure mapping. It features high-resolution analog stimulation and sampling capabilities, a flexible module combination mechanism, and an open control interface. This allows for broad adaptation to different types of novel memory arrays and supports the rapid construction, debugging, and evaluation of system prototypes in target applications such as neuromorphic computing, neural network inference, and edge intelligent computing. It provides crucial testing support and decision-making basis for AI chip system architecture research.

[0012] The present invention adopts the following technical solution: An apparatus for verifying AI chip system architecture, including The control center, acting as the scheduling center, implements logical control, timing coordination, and data interaction for each module.

[0013] Pulse writing module: Used to generate write signals with special pulse patterns, enabling state programming and conductance adjustment of storage or computing devices. The pulse writing module supports programmable adjustment of parameters such as amplitude, width, and frequency to adapt to the excitation requirements of different device types.

[0014] Programming selection module: Accepts signals from the pulse writing module, supports the structural requirements of various memory devices of the unit under test, and can perform different selective writing according to different array structures.

[0015] The decoding module receives the programming selection module signal and reads the feedback signal from the unit under test. It is used for address space mapping, excitation line management, and signal on / off control. It can act as an intermediary between path configuration and excitation loading, supporting programmable read / write control and structured array access. It also includes an interface selection unit for selecting and switching between multiple voltage excitation interfaces and analog acquisition interfaces, enabling different types of novel memory arrays to perform write and read operations on the same device.

[0016] The unit under test (DUT) receives write pulses and completes state programming under the condition that the decoding module implements row / column gating; during the readout phase, it generates a corresponding electrical response, and the response signal is transmitted to the acquisition module through the read path. The test object can be a memory structure with multiple states, analog behavior, and programmability, including novel non-volatile memories, malleable devices, and synaptic-like devices, used to store neural network weights, logic states, or continuous conductance levels.

[0017] Weight / Range Selection Module: Reads feedback signals from the decoding module, supports different reading paths and mapping methods, supports writing positive and negative weights of the neural network, and can adjust the range size through the range selection module to adapt to different reading voltage output characteristics.

[0018] Acquisition Module: Acquires feedback signals from the weight / range selection module and samples the device output signals. The acquisition module supports analog readings of different signal amplitudes and performs digital conversion.

[0019] Power measurement module: Real-time monitoring of current and voltage during write and read processes, calculation of unit operation energy consumption, and provision of a basis for energy efficiency ratio evaluation.

[0020] The present invention also provides a method for operating a device for verifying AI chip system architecture, comprising: Step 1. The control center controls the operation of each module through digital signals.

[0021] Step 2. The pulse writing module generates a writing signal with the corresponding pulse pattern according to the requirements.

[0022] Step 3. Select modules for selective writing based on the different memory array programming.

[0023] Step 4. The decoding module selects the specific write position of the array through the gating unit.

[0024] Step 5. Write the write signal to the specific storage location of the unit under test to achieve dynamic weight configuration.

[0025] Step 6. Select the specific array to be read through the decoding module.

[0026] Step 7. The weight / range selection module selects the required range to achieve range adjustment, and the network reselection achieves positive and negative weight selection.

[0027] Step 8. The acquisition module converts the acquired voltage and current signals into digital signals.

[0028] Step 9. The read data is finally transmitted back to the control center.

[0029] The beneficial effects of the present invention.

[0030] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention addresses the verification needs of in-memory computing architectures for novel non-volatile memories by providing a system-level functional verification device. This device enables rapid verification and evaluation of in-memory computing chip architectures without the need for complete chip fabrication, significantly reducing R&D costs and time.

[0031] 2. By introducing a programmable read / write path and range configuration mechanism, this invention achieves flexible control of the memory array, which can adapt to different array structures, mapping methods and application requirements, and improves the versatility and scalability of the verification process.

[0032] 3. This invention supports computation mapping and application-level inference testing on real memory arrays, and can simultaneously evaluate accuracy, stability and power consumption performance, realizing closed-loop verification from device behavior to system performance, thereby improving the authenticity and reliability of verification results.

[0033] 4. This invention effectively fills the gap between traditional device-level testing equipment and chip mass production testing equipment in terms of testing dimensions, and provides strong support for the architecture design and technology selection of in-memory computing chips, neuromorphic computing systems and AI inference hardware. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the main structure of the ATE memory test system.

[0035] Figure 2 This is a diagram of the main structure of the SPA testing system.

[0036] Figure 3 This is a schematic diagram of the structure of the present invention.

[0037] Figure 4 This is a flowchart illustrating the main workflow of the present invention.

[0038] Figure 5 This is a schematic diagram of resistance modulation when performing weight mapping on resistive variable memory cells according to the present invention.

[0039] Figure 6 This is a schematic diagram of the conductance mapping and deviation distribution of the 1T1R RRAM array completed by the present invention.

[0040] Figure 7 This is a comparison chart showing the accuracy of the current accumulation results of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention are described clearly and completely below. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0042] This invention supports array-level control of various novel memory cells, including but not limited to resistive random access memory (RRAM), phase-change memory (PCM), magnetoresistive memory (MRAM), ferroelectric memory (FeRAM), two-dimensional material memory, and ion transistors. It features dynamic path configuration and analog behavior measurement, flexible read / write channel configuration, high-precision analog quantity acquisition capabilities, and structure mapping and energy consumption assessment functions. It is suitable for key R&D stages such as architecture deployment, performance exploration, and calculation accuracy analysis of AI in-memory computing chips.

[0043] like Figure 3 As shown, an apparatus for verifying AI chip system architecture according to the present invention includes: The control center, acting as the scheduling center, implements logical control, timing coordination, and data interaction for each module.

[0044] Pulse writing module: Used to generate write signals with special pulse patterns, enabling state programming and conductance adjustment of storage or computing devices. The pulse writing module supports programmable adjustment of parameters such as amplitude, width, and frequency to adapt to the excitation requirements of different device types.

[0045] Programming selection module: Accepts signals from the pulse writing module, supports the structural requirements of various memory devices of the unit under test, and can perform different selective writing according to different array structures.

[0046] Decoding module: Accepts programming selection module signals and reads feedback signals from the unit under test. It is used for address space mapping, excitation line management and signal on / off control. It can act as an intermediary between path configuration and excitation loading, and supports programmable read / write control and structured array access.

[0047] The unit under test (DUT) receives the write pulse and completes state programming under the condition that the decoding module realizes row / column gating; it generates the corresponding electrical response during the readout stage. The response signal is transmitted to the acquisition module through the read path. It is the test object and can be a memory structure with multiple states, simulated behavior and programmability, including novel non-volatile memory, plastic device and synaptic device, etc., used to store neural network weights, logic states or continuous conductance levels.

[0048] Weight / Range Selection Module: Reads feedback signals from the decoding module, supports different reading paths and mapping methods, supports writing positive and negative weights of the neural network, and can adjust the range size through the range selection module to adapt to different reading voltage output characteristics.

[0049] Acquisition Module: Acquires feedback signals from the weight / range selection module and samples the device output signals. The acquisition module supports analog readings of different signal amplitudes and performs digital conversion.

[0050] Power measurement module: Real-time monitoring of current and voltage during write and read processes, calculation of unit operation energy consumption, and provision of a basis for energy efficiency ratio evaluation.

[0051] like Figure 4 As shown, the present invention also provides a method for operating a device for verifying AI chip system architecture, comprising: Step 1. The control center controls the operation of each module through digital signals to achieve flexible path configuration.

[0052] Step 2. The pulse writing module generates a writing signal with the corresponding pulse shape according to the requirements, and supports multiple pulse behavior control.

[0053] Step 3. Select modules for selective writing based on the different memory array programming.

[0054] Step 4. The decoding module selects the specific write position of the array through the gating unit.

[0055] Step 5. Write the write signal to the specific storage location of the unit under test to realize dynamic weight configuration, which is used to explore the impact of different storage structures on system energy efficiency, accuracy and topology configuration.

[0056] Step 6. Select the specific array to be read through the decoding module.

[0057] Step 7. The weight / range selection module selects the desired range to achieve range adjustment. The network weight selection module selects between positive and negative weights.

[0058] Step 8. The acquisition module converts the acquired voltage and current signals into digital signals.

[0059] Step 9. The read data is finally transmitted back to the control center. The entire process realizes the weight mapping and inference verification of the neural network.

[0060] Example A linear mapping is applied between network weights and the conductance of the resistive random access memory (RRAM), which modulates the resistance of the device as follows: Figure 5 As shown, the neural network is deployed on a resistive variable memory array. Figure 6 As shown, the inference deployment effect of the 1T1R RRAM array completed by this test equipment includes the conductivity mapping distribution (G) and accuracy error distribution after writing. This indicates that the system can achieve high-resolution weight mapping control for large-scale arrays. G is mostly distributed in Within the range, at most not exceeding This verified the effectiveness of the system in precision control.

[0061] After completing the neural network weight mapping, the physical implementation of the weighted summation operation in the neural network is verified by performing a pooling calculation on the array readout current. For example... Figure 7 As shown, the theoretical current value corresponding to the weighted summation of the neural network under the same excitation conditions is compared with the array convergence current result measured by the device of the present invention. It can be seen that the measured results are in good agreement with the theoretical calculation results, indicating that the test device of the present invention can accurately complete the current convergence calculation under real array conditions, thereby effectively supporting the realization of the neural network inference process.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A device for verifying AI chip system architecture, characterized in that, include: The control center is responsible for the logical control, timing coordination, and data interaction of each module. Pulse writing module: Generates a write signal with a special pulse pattern to enable state programming and conductance adjustment of storage or computing devices; Programming selection module: Accepts signals from the pulse writing module, supports the structural requirements of various memory devices of the unit under test, and performs different selective writing according to different array structures; Decoding module: Accepts programming selection module signals and reads feedback signals from the unit under test, used for address space mapping, excitation line management and signal on / off control; The unit under test (DUT) receives the write pulse and completes the state programming under the condition that the decoding module implements row / column gating; During the readout phase, a corresponding electrical response is generated. This electrical response is transmitted to the acquisition module via the readout path and is used to store neural network weights, logic states, or continuous conductance levels. Weight / Range Selection Module: Reads feedback signals from the decoding module, supports different reading paths and mapping methods, supports writing positive and negative weights of the neural network, and adjusts the range size through the range selection module to adapt to different reading voltage output characteristics; Acquisition module: Acquires feedback signals from the weight / range selection module and samples the output signal.

2. The device according to claim 1, characterized in that, The pulse writing module supports programmable adjustment of three parameters: amplitude, width, and frequency.

3. The device according to claim 1, characterized in that, The decoding module acts as an intermediary between path configuration and stimulus loading, supporting programmable read / write control and structured array access.

4. The device according to claim 1, characterized in that, The unit under test has a multi-state, analog behavior, and programmable memory structure, including novel non-volatile memory, plastic devices, and synaptic-like devices.

5. The device according to claim 1, characterized in that, The acquisition module supports analog reading of different signal amplitudes and completes digital conversion.

6. The method according to claim 1, characterized in that, It also includes a power measurement module: real-time monitoring of current and voltage during writing and reading processes, calculation of unit operation energy consumption, and providing a basis for energy efficiency ratio evaluation.

7. A method for operating the device for verifying AI chip system architecture as described in any one of claims 1-6, characterized in that, include: Step 1. The control center controls the operation of each module via digital signals; Step 2. The pulse writing module generates a write signal with the corresponding pulse pattern according to the requirements; Step 3. Select modules for selective writing based on the different memory array programming methods; Step 4. The decoding module selects the specific write position of the array through the gating unit; Step 5. Write the write signal to the specific storage location of the unit under test to achieve dynamic weight configuration; Step 6. Select the specific array to be read using the decoding module; Step 7. The range selection module selects the required range to achieve range adjustment, and the network reselection achieves positive and negative weight selection; Step 8. The acquisition module converts the acquired voltage and current signals into digital signals; Step 9. The read data is finally transmitted back to the control center.

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