Managing parity data in a memory system

Abstract

Methods, apparatus, and systems for managing parity data generation are provided. In one aspect, a memory system includes a memory device and a memory controller. The memory device includes N dies, each die including M memory surfaces. Each of the M memory surfaces includes a first memory block, the first memory block including memory pages, each memory page being associated with a word line in a set of sequentially numbered word lines. The memory controller is configured to: generate first parity data for first data to be written to a memory page associated with a k-th word line of the first memory block of each of the M memory surfaces of the N dies; and generate second parity data for second data to be written to memory pages associated with at least the (k-1)-th and (k+1)-th word lines of the first memory block of each of the M memory surfaces of the N dies.

Description

Technical Field

[0001] In general, this disclosure relates to memory devices and memory systems, and more specifically, to managing parity data in memory systems. Background Technology

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash and NAND flash. Various operations (e.g., programming (writing) and erasing operations) can be performed on flash memory to change the threshold voltage of each storage cell to a corresponding level. For NAND flash memory, erasing operations can be performed at the block level, programming operations can be performed at the page level, and reading operations can be performed at the page level. Summary of the Invention

[0003] This disclosure relates to methods, apparatus, and systems for managing parity data in a memory system. One aspect of this disclosure features a memory system including a memory device and a memory controller coupled to the memory device. The memory device includes N dies, each of the N dies including M memory planes, each of the M memory planes including a first memory block, where N and M are positive integers. The first memory block includes memory pages, each memory page being associated with a word line from a set of sequentially numbered word lines. The memory controller is configured to perform operations including: generating first parity data by performing a first encoding operation on first data to be written to a memory page associated with the k-th word line of the first memory block associated with each of the M memory surfaces of each of the N dies, where k is an integer greater than 1; generating second parity data by performing a second encoding operation on second data to be written to a memory page associated with at least the (k-1)-th and (k+1)-th word lines of the first memory block associated with each of the M memory surfaces of each of the N dies; and writing the first data, the first parity data, the second data, and the second parity data to the memory device.

[0004] This disclosure relates to methods, apparatus, and systems for managing parity data in a memory system. One aspect of this disclosure features a memory system including a memory device and a memory controller coupled to the memory device. The memory device includes N dies, each of the N dies including M memory surfaces, each of the M memory surfaces including a first memory block, where N and M are positive integers. The first memory block includes memory pages, each memory page being associated with a word line from a set of sequentially numbered word lines. The memory controller is configured to perform operations including: generating first parity data by performing a first encoding operation on first data to be written to a memory page associated with the k-th word line of the first memory block associated with each of the M memory surfaces of each of the N dies, where k is an integer greater than 1; generating second parity data by performing a second encoding operation on second data to be written to a memory page associated with at least the (k-1)-th and (k+1)-th word lines of the first memory block associated with each of the M memory surfaces of each of the N dies; and writing the first data, the first parity data, the second data, and the second parity data to the memory device.

[0005] In some implementations, the first parity data and the second parity data include redundant array of independent disks (RAID) parity data.

[0006] In some implementations, the second parity data is generated by performing the second encoding operation on the second data to be written to a memory page associated with a set of odd-numbered word lines of the first memory block of each of the M memory faces of each of the N dies.

[0007] In some implementations, the second parity data is generated by performing the second encoding operation on the second data to be written to a memory page associated with a set of even-numbered word lines of the first memory block of each of the M memory faces of each of the N dies.

[0008] In some implementations, a first ratio of the amount of the first parity data to the amount of the first data is greater than a second ratio of the amount of the second parity data to the amount of the second data.

[0009] In some implementations, the first parity data is written to a memory page associated with the k-th word line of the first memory block on the M-th memory face of the N-th die. The second parity data is written to a memory page associated with the (k+1)-th word line of the first memory block on the M-th memory face of the N-th die.

[0010] In some implementations, the memory controller is configured to perform the operation in response to receiving one or more write commands from the host for writing the first data and the second data.

[0011] In some implementations, the first encoding operation and the second encoding operation each include multiple XOR operations. The results of the multiple XOR operations are stored in a buffer of the memory controller.

[0012] In some implementations, the operation includes: recovering the first data using the first parity data in response to detecting a read failure while reading the first data; or recovering the first data using the first parity data in response to detecting a read failure while reading the second data.

[0013] Another aspect of this disclosure features a memory controller. The memory controller includes one or more processors and an interface. The one or more processors are configured to perform operations including: sending one or more first write commands via the interface to write first data and first parity data to a memory device; and sending one or more second write commands via the interface to write second data and second parity data to the memory device. The memory device includes N dies, each of the N dies including M memory surfaces, each of the M memory surfaces including a first memory block, where N and M are positive integers. The first memory block includes memory pages, each memory page being associated with a word line in a set of sequentially numbered word lines. The first parity data is generated by performing a first encoding operation on the first data to be written to a memory page associated with the k-th word line of the first memory block of each of the M memory surfaces of the N dies, where k is a positive integer. The second parity data is generated by performing a second encoding operation on the second data to be written to the memory page associated with at least the (k-1)th word line and the (k+1)th word line of the first memory block of each of the M memory surfaces of each of the N dies.

[0014] In some implementations, the first parity data and the second parity data include redundant array of independent disks (RAID) parity data.

[0015] In some implementations, the second parity data is generated by performing the second encoding operation on the second data to be written to a memory page associated with a set of odd-numbered word lines of the first memory block of each of the M memory faces of each of the N dies.

[0016] In some implementations, the second parity data is generated by performing the second encoding operation on the second data to be written to a memory page associated with a set of even-numbered word lines of the first memory block of each of the M memory faces of each of the N dies.

[0017] In some implementations, a first ratio of the amount of the first parity data to the amount of the first data is greater than a second ratio of the amount of the second parity data to the amount of the second data.

[0018] In some implementations, the first parity data is written to a memory page associated with the k-th word line of the first memory block on the M-th memory face of the N-th die. The second parity data is written to a memory page associated with the (k+1)-th word line of the first memory block on the M-th memory face of the N-th die.

[0019] In some implementations, the memory controller is configured to perform the operation in response to receiving one or more write commands from the host for writing the first data and the second data.

[0020] In some implementations, the first encoding operation and the second encoding operation each include multiple XOR operations. The results of the multiple XOR operations are stored in a buffer of the memory controller.

[0021] In some implementations, the operation includes: recovering the first data using the first parity data in response to detecting a read failure while reading the first data; or recovering the first data using the first parity data in response to detecting a read failure while reading the second data.

[0022] Another aspect of this disclosure is a method of operating a memory system. The method includes: generating first parity data by performing a first encoding operation on first data to be written to a first memory page of a memory device; generating second parity data by performing a second encoding operation on second data to be written to a second memory page associated with at least the (k-1)th word line and the (k+1)th word line of a first memory block associated with each of M memory faces of N dies; and writing the first data, the first parity data, the second data, and the second parity data to the memory device. The memory device includes N dies, each of the N dies includes M memory faces, and each of the M memory faces includes a first memory block, where N and M are positive integers. The first memory block includes memory pages, each memory page being associated with a word line in a set of sequentially numbered word lines. The first memory page is associated with the kth word line of the first memory block of each of the M memory faces of the N dies, where k is a positive integer.

[0023] In some implementations, a first ratio of the amount of the first parity data to the amount of the first data is greater than a second ratio of the amount of the second parity data to the amount of the second data.

[0024] Another aspect of this disclosure is a non-transitory computer-readable medium. The non-transitory computer-readable medium stores one or more instructions executable by a memory system to perform operations including: generating first parity data by performing a first encoding operation on first data to be written to a first memory page of a memory device; generating second parity data by performing a second encoding operation on second data to be written to a second memory page associated with at least the (k-1)th word line and the (k+1)th word line of a first memory block associated with each of the M memory faces of N dies; and writing the first data, the first parity data, the second data, and the second parity data to the memory device. The memory device includes N dies, each of the N dies including M memory faces, each of the M memory faces including a first memory block, where N and M are positive integers. The first memory block includes memory pages, each memory page being associated with a word line in a set of sequentially numbered word lines. The first storage page is associated with the k-th word line of the first storage block of each of the M storage surfaces of each of the N dies, where k is a positive integer.

[0025] While generally described as computer-implemented software embodied on a tangible medium for processing and transforming corresponding data, some or all of these aspects may be computer-implemented methods or further included in a corresponding system or other apparatus for performing the functions described. These and other aspects of this disclosure, as well as details of their implementation, are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0026] Figure 1 A block diagram of an example system with a memory device is shown.

[0027] Figures 2A to 2B An example storage product is shown.

[0028] Figure 3A An example of a schematic diagram of a memory device including peripheral circuitry is shown.

[0029] Figure 3B An example of a schematic diagram of a storage block including strings is shown.

[0030] Figure 4 Some example peripheral circuits are shown.

[0031] Figure 5 A block diagram of an example memory controller that interacts with a host and memory devices is shown.

[0032] Figure 6 An example data structure for a memory device under a storage plane RAID scheme is shown.

[0033] Figure 7 An example data structure for a memory device under a 2WL RAID scheme is shown.

[0034] Figure 8 An example data structure for a memory device is shown in a RAID scheme combining storage plane RAID and 2WL RAID.

[0035] Figure 9 Another example data structure for a memory device is shown in a RAID scheme combining storage plane RAID and 2WL RAID.

[0036] Figure 10 A flowchart illustrating an example process for operating a memory system is shown.

[0037] In the various figures, the same reference numerals and designations indicate the same elements. Detailed Implementation

[0038] This specification relates to memory controllers, memory systems, and methods for managing parity data in memory systems. Redundant Array of Independent Disks (RAID) parity data can be used to recover data in the event of a read failure (e.g., a read failure due to a word line failure). For example, a memory system can generate RAID parity data by performing an XOR operation between data portions on one or more word lines.

[0039] In some cases, memory systems generate RAID parity data under storage-plane RAID or 2WL RAID schemes to enable data recovery in the event of simultaneous failures of two adjacent word lines (e.g., due to current leakage). Under storage-plane RAID, the memory system generates RAID parity data by performing an XOR operation between data portions that include user data within a single page line. Storage-plane RAID can result in a large ratio between the amount of RAID parity data and the amount of user data, potentially limiting the storage capacity of the memory device. Under 2WL RAID, the memory system generates RAID parity data by performing an XOR operation between data portions in multiple page lines associated with word lines separated from each other by a single word line. 2WL RAID can result in a large number of intermediate results from the XOR operation. If the amount of intermediate results exceeds the storage space of the memory controller's random access memory (RAM), the memory controller may need to perform swapping operations by sending the intermediate results to the memory device for temporary storage and retrieving them from the memory device when needed. Swapping operations can impact the efficiency of write operations.

[0040] This disclosure provides techniques for generating parity data under a combined storage-plane RAID and 2WL RAID scheme. In some embodiments, the memory system can use a storage-plane RAID scheme to generate RAID parity data corresponding to page lines associated with a first set of word lines, and use a 2WL RAID scheme to generate RAID parity data corresponding to page lines associated with a second set of word lines. For example, the first set of word lines includes even-numbered word lines, and the second set of word lines includes odd-numbered word lines. As another example, the first set of word lines includes odd-numbered word lines, and the second set of word lines includes even-numbered word lines.

[0041] The described techniques can achieve one or more technical effects. For example, compared to storage-plane RAID schemes, the described techniques can reduce the ratio of the amount of RAID parity data to the amount of user data in the memory device. As another example, compared to 2WL RAID schemes, the described techniques can reduce the amount of intermediate results used in the XOR operation to generate RAID parity data. Therefore, the memory controller can store the intermediate results in RAM without performing swapping operations. Furthermore, RAID parity data generated using the described techniques can be used to recover damaged data in the event of simultaneous failure of two adjacent word lines. In some implementations, additional or different technical effects can be achieved.

[0042] The technology can be applied to various types of semiconductor devices, such as non-volatile memory (NVM) devices (e.g., NAND flash or NOR flash), volatile memory devices (e.g., DRAM), resistive random access memory (RRAM), phase-change memory (PCM) (e.g., PCRAM), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), etc. The technology can also be applied to charge-trapping based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate based memory devices. The technology can be applied to three-dimensional (3D) memory devices. The technology can be applied to various memory types, such as memory devices configured to operate in single-cell (SLC), multi-cell (MLC), three-cell (TLC), four-cell (QLC), or five-cell (PLC) modes. Alternatively or concurrently, the technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC), universal flash storage devices (UFS) or solid-state drives (SSD), embedded systems, etc.

[0043] Figure 1 A block diagram of an example system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1As shown, system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 may include one or more processors of an electronic device. The processor may be a central processing unit (CPU) or a system-on-a-chip (SoC), such as an application processor (AP). Host 108 may be configured to send data and commands to or receive data and commands from memory system 102.

[0044] Memory device 104 can be any memory device disclosed in this disclosure, such as a NAND flash memory device. Note that, for illustrative purposes, NAND flash memory is merely one example of a memory device. It can include any suitable solid-state non-volatile memory, such as NOR flash memory, ferroelectric RAM (Fe RAM), phase-change memory (PCM), magnetoresistive random access memory (MRAM), spin-torque magnetic random access memory (STT-RAM), or resistive random access memory (RRAM), etc. In some embodiments, memory device 104 includes a three-dimensional (3D) NAND flash memory device.

[0045] The memory controller 106 may be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gated logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform the various functions described in detail below.

[0046] According to some embodiments, a memory controller 106 is coupled to a memory device 104 and a host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and can communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a solid-state drive (SSD) or an embedded multimedia card (eMMC), used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, logical-to-physical mapping management, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104.

[0047] The memory controller 106 can communicate with an external device (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the external device via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc. The memory controller 106 is configured to receive and send commands to the host 108, and to execute or perform various functions and operations provided in this disclosure, which will be described later.

[0048] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices. For example, the memory controller 106 and one or more memory devices 104 can be packaged in a Universal Flash Storage (UFS) package or an eMMC package. Figure 2AIn one example shown, the memory controller 106 and a single memory device 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108. In such a way... Figure 2B In another example shown, the memory controller 106 and multiple memory devices 104 can be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0049] Figure 3A An example of a schematic circuit diagram of a memory device 300 according to some aspects of this disclosure is shown. The memory device 300 may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. The memory array 301 may be a NAND flash memory array including NAND memory cells 306 arranged in rows and columns. In some embodiments, the memory cells 306 in the columns (e.g., along the z-direction) of the memory array 301 are coupled in series and stacked vertically. The memory cells 306 in the rows (e.g., along the x-direction) of the memory array 301 are coupled to and controlled by word lines 318. Each memory cell 306 may maintain a continuous analog value, such as a voltage or charge depending on the number of electrons trapped within the storage layer of the memory cell 306. The logic state (i.e., data) of each memory cell 306 may be determined based on a threshold voltage Vth of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0050] In some implementations, each storage cell 306 may be a single-level cell (SLC) having two possible storage states capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each storage cell 306 may be a multi-level cell (MLC) capable of storing more than one bit of data in more than two storage states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), four bits per cell (also known as a four-level cell (QLC)), or five bits per cell (also known as a five-level cell (PLC)). Each MLC may be programmed to support a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erase state to one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value may be used for the erase state.

[0051] like Figure 3A As shown, memory cells 306 in a column of memory array 301 can be coupled at their source terminals to source-select-gate (SSG) transistors 310 and at their drain terminals to drain-select-gate (DSG) transistors 312. SSG transistors 310 and DSG transistors 312 can be configured to activate selected columns of memory array 301 during read and program operations. In some embodiments, the sources of SSG transistors in the same memory block are coupled via the same source line 314 (also called the common source line, CSL). The drain of each DSG transistor is coupled to a corresponding bit line 316. From the bit line 316, data can be read from or written to memory cells in a column of memory array 301. In some implementations, each column of the memory array 301 is configured to be selected or deselected by applying a DSG select voltage or a DSG unselect voltage to the gate of the corresponding DSG transistor 312 via one or more DSG lines 313 and / or by applying a select voltage or an unselect voltage to the gate of the corresponding SSG transistor 310 via one or more SSG lines 315.

[0052] In some implementations, memory cells 306 in adjacent columns can be coupled via word lines 318 to form memory pages 320. Word lines 318 can select which rows of memory cells 306 are affected by read and program operations. In some implementations where memory cells 306 are SLCs, memory pages 320 of memory cells 306 can store one logical page of data and therefore correspond to one logical page. In some implementations where memory cells 306 are MLCs, memory pages 320 of memory cells 306 can store two logical pages of data and therefore correspond to two logical pages. In some implementations where memory cells 306 are TLCs, memory pages 320 of memory cells 306 can store three logical pages of data and therefore correspond to three logical pages. In some implementations where memory cells 306 are QLCs, memory pages 320 of memory cells 306 can store four logical pages of data and therefore correspond to four logical pages. In some implementations where memory cells 306 are PLCs, memory pages 320 of memory cells 306 can store five logical pages of data and therefore correspond to five logical pages.

[0053] The size of a memory page 320 (in bits) is associated with the number of columns of memory cells coupled through word lines 318 in the block. Each word line 318 may include a gate line that couples multiple control gates (gate electrodes) to multiple memory cells 306 in the corresponding memory page 320. Figure 3A The example word lines shown include WL0, WL1, ..., WLn-3, WLn-2, ​​WLn-1 and WLn between one or more DSG lines 313 and one or more SSG lines 315.

[0054] In some implementations, the storage array 301 may include multiple storage blocks (e.g., such as...). Figure 3B The storage block 304 shown can be used, and each storage block can include multiple strings 334. Figure 3A As shown, each string 334 may include memory cells 306 arranged in rows (e.g., coupled to word lines along the x-direction) and columns (e.g., connected in series along the z-direction). Different strings 334 in the same memory block are coupled together to the same source line 314. The DSG lines 313 of different strings 334 are separated from each other, such that each string 334 in the memory block can be selected or deselected by applying a selection voltage or a non-selection voltage to the respective DSG line 313.

[0055] Peripheral circuitry 302 can be coupled to memory array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of memory array 301.

[0056] Figure 3B An example schematic diagram of a memory block 304 comprising a string 334 is shown according to some aspects of this disclosure. In some embodiments, each memory block 304 may serve as a basic data unit for an erase operation, such that memory cells 306 within the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage may be used to bias the source line 314 coupled to the selected memory block 304. For example, the erase voltage may be a high positive voltage (e.g., 20V or higher). In some embodiments, erase operations may be performed at half-block levels, quarter-block levels, or levels having any suitable number of memory blocks or fractions of memory blocks.

[0057] Storage block 304 may include multiple strings 334. In some embodiments, storage block 304 may be divided into fingers 344. Each finger 344 may include one or more strings 334. The SSG transistors 310 of the strings 334 in the same finger 344 are coupled to the same SSG line 315. For example, the SSG transistors 310 of the strings 334 of the first finger 344a are coupled to a first SSG line represented by SSG0; the SSG transistors 310 of the strings 334 of the second finger 344b are coupled to a second SSG line represented by SSG1.

[0058] In some embodiments, the DSG transistors 312 in different strings 334 are coupled to different DSG lines 313. For example, the DSG transistors 312 in the first string in the memory block 304 are coupled to the first DSG line represented by DSG0; the DSG transistors 312 in the second string in the memory block 304 are coupled to the second DSG line represented by DSG1; the DSG transistors 312 in the third string in the memory block 304 are coupled to the third DSG line represented by DSG2; and the DSG transistors 312 in the fourth string in the memory block 304 are coupled to the fourth DSG line represented by DSG3.

[0059] In some implementations, memory pages 320 at the same vertical position (e.g., along the z-direction) in all strings 334 of memory block 304 are coupled to the same word line. That is, a word line may be coupled to one memory page 320 of each string 334 of memory block 304.

[0060] In some embodiments, the memory block 304 may include a different number of fingers 344, and each finger 344 may include a different number of strings 334. In some embodiments, the strings 334 are not arranged as fingers 344, such that the SSG transistors of all strings 334 of the memory block 304 are coupled to the same SSG line.

[0061] Figure 4Examples of peripheral circuitry 302 according to some aspects of this disclosure are shown. Peripheral circuitry 302 can be coupled to memory array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. Example peripheral circuitry 302 includes a page buffer / sensor amplifier 404, a column decoder / bit line driver 406, a row decoder / word line driver 408, a voltage generator 410, control logic 412, a register 414, an interface 416, and a data bus. In some examples, it may also include Figure 4 Additional peripheral circuitry not shown.

[0062] Page buffer / sensor amplifier 404 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic 412. In one example, page buffer / sensor amplifier 404 can store one page of programming data (write data) in a memory page 320 to be programmed into memory array 301. In another example, page buffer / sensor amplifier 404 can perform a programming verification operation to ensure that data has been properly programmed into memory cell 306 coupled to selected word line 418. In yet another example, page buffer / sensor amplifier 404 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify small voltage swings to a recognizable logic level during read operations. Column decoder / bit line driver 406 can be configured to be controlled by control logic 412 and select one or more columns of memory cells by applying a bit line voltage generated from voltage generator 410.

[0063] The row decoder / word line driver 408 can be configured to be controlled by control logic 412 and to select / deselect memory blocks of memory array 301 and select / deselect word lines 418 of memory blocks. The row decoder / word line driver 408 can also be configured to drive word lines 418 using word line voltages generated from voltage generator 410. In some embodiments, the row decoder / word line driver 408 can also select / deselect and drive SSG lines 315 and DSG lines 313. As described in detail below, the row decoder / word line driver 408 is configured to apply a programming voltage to the selected word line 418 during a programming operation on a memory cell 306 coupled to the selected word line 418.

[0064] Voltage generator 410 can be configured to be controlled by control logic 412 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0065] Control logic 412 can be coupled to each of the aforementioned peripheral circuits and configured to control the operation of each peripheral circuit. Register 414 can be coupled to control logic 412 and includes a status register, a command register, and an address register for storing status information, command opcode (OP code), and command address for controlling the operation of each peripheral circuit.

[0066] Interface 416 can be coupled to control logic 412 and act as a control buffer to buffer and relay control commands received from the host (not shown) to control logic 412, and status information received from control logic 312 to the host. Interface 416 can also be coupled to column decoder / bit line driver 406 via a data bus and act as a data input / output (I / O) interface and data buffer to buffer and relay data to and from memory array 301.

[0067] Figure 5 An example block diagram of a memory controller 106 interacting with a host 108 and a memory device 104, according to some aspects of this disclosure, is shown.

[0068] The memory controller 106 may include a front interface 502, one or more processors 503, random access memory (RAM) 506, and a rear interface 510. RAM 506 may include one or more parity buffers 508. The memory controller 106 may also include error correction code (ECC) circuitry 512, garbage collection (GC) circuitry 514, and redundant array of independent disks (RAID) circuitry 516. In some examples, the memory controller 106 may also include... Figure 5 Additional components not shown.

[0069] The front interface 502 can be configured to handle communication between the host 108 and the memory controller 106. In some embodiments, the front interface 502 can communicate with the host 108 according to a specific communication protocol. For example, the front interface 502 can communicate with the host 108 through at least one of various interface protocols, such as USB, MMC, PCI, PCI-E, ATA, Serial ATA, Parallel ATA, SCSI, ESDI, IDE, FireWire, etc. In some embodiments, the front interface 502 can receive requests from the host 108 and forward them to the rear interface 510, allowing the rear interface 510 to fulfill the requests. Examples of requests may include, but are not limited to, read requests to read data stored in a memory block of the memory device 104, erase requests to erase data in a memory block, write requests to write new data to a memory block, reformat requests to reformat the memory device 104, or any other suitable requests. In some embodiments, the front interface 502 can receive data from the rear interface 510 and send data to the host 108.

[0070] The back interface 510 can be configured to fulfill requests from the host 108. In some implementations, the back interface 510 can receive requests from the host 108 via the front interface 502 and perform one or more operations to fulfill the requests. For example, the back interface 510 can be configured to control the operation of the memory device 104 (e.g., read, erase, or program operations) in response to receiving a request (e.g., a read request, erase request, or program request) from the host 108. The back interface 510 can also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, error correction, wear leveling, garbage collection, RAID parity, etc.

[0071] ECC circuit 512 is configured to process error correction codes regarding data read from or written to memory device 104. Example error correction codes may include, but are not limited to, Hamming codes, Reed-Solomon codes, low-density parity-check (LDPC) codes, etc. In some embodiments, ECC circuit 512 includes an LPDC encoder configured to generate parity data based on the LDPC code of user data received from host 108, such that both user data and parity data can be sent to memory device 104 for storage. ECC circuit 512 may also include an LDPC decoder configured to decode the data including user data and parity data. The ECC circuit can determine whether the data stored in the block has been successfully read (e.g., without errors). If the data stored in the block has been successfully read, the back interface 510 can forward the data to the front interface 502, so that the front interface 502 can return the data to host 108. However, if the data stored in the memory block has not been successfully read, the back interface 510 can generate data describing read errors on the memory block.

[0072] GC circuit 514 can be configured to migrate data from a source storage block to a target storage block, such that the source storage block can be erased to make it available for writing new data. For example, GC circuit 514 can be configured to select a source and a target storage block in memory device 104, read valid data from the source storage block by sending a read command to memory device 104, write valid data to the target storage block by sending a write command to memory device 104, and then erase the source storage block. In some embodiments, GC circuit 514 can be configured to perform foreground garbage collection on memory device 104, wherein garbage collection is performed when there are not enough storage blocks available for writing new data. In some embodiments, GC circuit 514 can be configured to perform background garbage collection on memory device 104, wherein garbage collection is performed when the memory device is idle (e.g., when there are no pending commands to be executed by the memory device).

[0073] RAID circuitry 516 can be configured to generate RAID parity data by performing an encoding operation on data to be written to memory device 104, and to write the data and the corresponding RAID parity data to storage blocks 304 of the memory device. Memory device 104 can be managed under a RAID scheme that employs striping, mirroring, and / or parity techniques to create large, reliable data storage across multiple storage components. In some embodiments, memory device 104 may include multiple dies, each die including multiple storage surfaces. Each storage surface includes multiple storage blocks. Each storage block may include storage pages (e.g., ...). Figure 3AStorage pages 320). Storage pages located at the same position across different storage faces in at least one die (e.g., associated with word lines of the same number and included in strings of the same number) can form page lines (e.g., Figure 6 Page line 602 Figure 7 Page line 702 Figure 8 Page line 802 or Figure 9 Page line 902). The RAID circuit 516 can perform an XOR operation between data in one or more page lines to generate corresponding RAID parity data.

[0074] As Figures 6 to 9 The example shown includes two dies, DIE0 and DIE1. Each die includes six memory surfaces PL0-PL5. Each memory surface includes multiple memory blocks. Each memory block includes memory pages coupled to multiple word lines (e.g., WL0-WLn). The number of memory pages coupled to one word line in each memory block corresponds to the number of strings (e.g., ...) included in the memory block. Figure 3B The number of strings (334). For example, each memory block consists of 8 strings (Str0-Str7), such that in each memory block, word lines are coupled to 8 memory pages. A page line (e.g., represented by a row of cells) (e.g., Figure 6 Page line 602 Figure 7 Page line 702 Figure 8 Page line 802 or Figure 9 Page line 902 may include 12 memory pages (e.g., each memory page represented by a cell). The 12 memory pages in the page line are coupled to word lines of the same number and are located in strings of the same number spanning six memory surfaces in each of the two dies. For example, the 12 memory pages in the first page line 602 are each coupled to WL0 and are located in Str0 of a first memory block spanning 12 memory surfaces; the 12 memory blocks in the second page line are coupled to WL0 and are located in Str1 of a first memory block spanning 12 memory surfaces. It should be noted that the memory device may include any other suitable number of dies and any other suitable number of memory surfaces, and each page line may include any other suitable number of memory pages.

[0075] Return to reference Figure 5 One or more processors 503 are configured to control the operation of the memory controller 106. One or more processors 503 are configured to control read operations, program operations, erase operations, or other operations of the memory device 104.

[0076] RAM 506 is configured to serve as operating memory for one or more processors 503, cache memory between memory device 104 and host 108, and / or buffer memory between memory device 104 and host 108. In some embodiments, RAM 506 may be static random access memory (SRAM). RAM 506 may include one or more parity buffers 508 configured to store RAID parity data and / or intermediate results of XOR operations used to generate RAID parity data. In some embodiments, RAM 506 may also include a read buffer configured to temporarily store data read from memory device 104, a copy buffer configured to temporarily store data to be written to memory device 104, etc.

[0077] In some implementations, each parity buffer 508 may have a limited storage space (e.g., 320KB). If the RAID parity data and / or intermediate results exceed the storage space of the parity buffer 508, the memory controller 106 may use other buffers in RAM 506 (e.g., read buffers and copy buffers) to store the RAID parity data and / or intermediate results. If the RAID parity data and / or intermediate results exceed the available buffer space in RAM 506, the memory controller 106 may perform a swapping operation, for example, sending the RAID parity data and / or intermediate results from the parity buffer 508 to the memory device 104 for temporary storage, and retrieving the RAID parity data and / or intermediate results from the memory device 104 when needed.

[0078] Figure 6 Memory devices under a storage plane RAID scheme are shown in accordance with some aspects of this disclosure (e.g., Figures 1 to 2B and Figure 5 Memory device 104, Figure 3A Example data structure of the memory device 300. In a storage plane RAID scheme, the memory controller (e.g., Figures 1 to 2B and Figure 5The memory controller 106 can generate RAID parity data 614 corresponding to a page line 602 by performing an XOR operation between data portions of user data 612 included in page line 602, and store the RAID parity data 614 as a data portion of page line 602 (e.g., the last data portion in page line 602). The data portion can be data stored in a storage page included in page line 602. In a scenario where one page line 602 includes T data portions (where T is a positive integer), under a storage plane RAID scheme, the ratio of the amount of RAID parity data 614 to the amount of user data 612 in the memory device is 1:(T-1).

[0079] In the event of a data portion failure in page line 602 (e.g., programming or reading failure), the memory controller can recover the damaged data portion, for example, by performing an XOR operation using the RAID parity data 614 of the target page line 602 and the remaining data portion in the target page line 602. In a storage-plane RAID scheme, it is still possible to recover the damaged data portion even if one portion of the data portion fails in each of two page lines 602 associated with adjacent word lines (e.g., the page lines associated with Str0 and WL0 and the page lines associated with Str0 and WL1).

[0080] As Figure 6 In one example shown, the first page line comprises 12 data portions, each associated with a storage page in Str0 of the first storage block coupled to WL0 and located in the 12 storage planes. In a storage plane RAID scheme, the first 11 data portions (D0-D10) comprise user data 612, and the last data portion (P) comprises RAID parity data 614, which is obtained by performing an XOR operation between the first 11 data portions to achieve parity. This is generated. RAID parity data for other page lines can be generated in a similar manner. In this example, the ratio of the amount of RAID parity data 614 to the amount of user data 612 in the memory device is 1:11.

[0081] Before writing the first RAID parity data (e.g., RAID parity data corresponding to one page line) to the memory device, the memory controller stores the intermediate results used to generate the first RAID parity data in the memory controller's parity buffer (e.g., Figure 5The parity buffer (508) is used to store the intermediate results used to generate the second RAID parity data (e.g., RAID parity data corresponding to the next page line) after the first RAID parity data has been written to the memory device. Therefore, in a storage-plane RAID scheme, the parity buffer may only need to store the intermediate results of the RAID parity data corresponding to one page line, which is typically within the storage capacity of the memory controller's RAM. Thus, the memory controller may not need to use other buffers as parity buffers or perform swapping operations to store the intermediate results.

[0082] Figure 7 Memory devices under a 2WL RAID scheme (e.g., according to some aspects of this disclosure) are shown. Figures 1 to 2B Memory device 104, Figure 3A Example data structure of the memory device 300. In the 2WL RAID scheme, the memory controller (e.g., Figures 1 to 2B and Figure 5 The memory controller 106 can generate RAID parity data 714 (including 714A and 714B) corresponding to page lines 702 (including 702A1, 702B1, ..., 702An, 702Bn) separated from each other by a set of word lines separated by a word line. In some embodiments, the first set of word lines includes a set of even-numbered word lines, and the second set of word lines includes a set of odd-numbered word lines. With respect to the first set of word lines, the memory controller can perform an XOR operation on the data portions of the page lines 702A1, ..., 702An associated with the first set of word lines to generate the corresponding RAID parity data 714A, and store the RAID parity data 714A as a data portion (e.g., the last data portion) of the last page line 702An associated with the first set of word lines. Regarding the second set of word lines, the memory controller can perform an XOR operation on the data portion of the page lines 702B1, ..., 702Bn associated with the second set of word lines to generate the corresponding RAID parity data 714B, and store the RAID parity data 714B as a data portion (e.g., the last data portion) of the last page line 702Bn associated with the second set of word lines.

[0083] In a scenario where a page line 702 includes T data sections and the first and second word lines each include W word lines (where T and W are positive integers), under the 2WL RAID scheme, the ratio of the amount of RAID parity data to the amount of user data in the memory device is 1:(W*T-1).

[0084] In the event of a programming or reading failure in a data portion of page line 702, the memory controller can recover the damaged data portion, for example, by performing an XOR operation using RAID parity data 714 generated from multiple page lines 702 including the target page line and the remaining data portions in the multiple page lines 702. In a 2WL RAID scheme, the damaged data portion can still be recovered even if a data portion fails in one of the two page lines 702A and 702B associated with adjacent word lines (e.g., the page lines associated with Str0 and WL0, and the page lines associated with Str0 and WL1).

[0085] As Figure 7 In one example shown, the first set of word lines includes WL0, WL2, ..., and WL14, and the second set of word lines includes WL1, WL3, ..., WL15. In a 2WL RAID scheme, for each set of word lines, the memory controller generates RAID parity data 714 by performing an XOR operation between the data portions in page lines 702 associated with strings of the same number. For example, regarding the first set of word lines, page lines 702A1 associated with Str0 and WL0 include 12 data portions (D0-D11) containing user data, and page lines associated with Str0 and WL2 include 12 data portions (D12-D23, ...). Figure 7 (Not shown in the image), which includes user data, and the page line 702An associated with Str0 and WL14 includes 11 data sections (D84-D94), which include user data and a data section P including RAID parity data 714A, wherein the RAID parity data 714A is used as... Similarly, the last data portion in the page lines associated with StrX (X = 0, 1, 2, ..., 7) and WL14 includes RAID parity data 714A, which is generated by performing an XOR operation between the data portions in page lines 702 associated with each of StrX and WL0, WL2, ..., and WL14. Regarding the second set of word lines, the last data portion in page lines 702Bn associated with StrX (X = 0, 1, 2, ..., 7) and WL15 includes RAID parity data 714B, which is generated by performing an XOR operation between the data portions in page lines 702 associated with each of StrX and WL1, WL3, ..., and WL15. In this example, the ratio of the amount of RAID parity data to the amount of user data in the memory device is 1:95.

[0086] It should be noted that the first and second word lines may include other suitable numbers of word lines. After writing RAID parity data 714 corresponding to the page lines 702 associated with the first and second word lines, the memory controller may write user data to the page lines 702 associated with the third (e.g., WL16, WL18, ..., WL30) and fourth (e.g., WL17, WL9, ..., WL31) word lines, and generate RAID parity data 714 corresponding to the page lines 702 associated with the third and fourth word lines.

[0087] In some implementations, the memory device writes user data in page line numbering order, for example, from the page lines associated with WL0 and Str0, to the page lines associated with WL0 and Str1, ..., to the page lines associated with WL0 and Str7, to the page lines associated with WL1 and Str0, and so on. In a 2WL RAID scheme, the result of an XOR operation between the data portions of a page line (e.g., each page line associated with WL0 and WL1) is not written to the final RAID parity data of the memory device; therefore, the result is retained in a parity buffer for further XOR operations. Thus, the parity buffer may need to store the number of page lines corresponding to each word line (e.g., ...). Figure 7 The example shown contains 16 page lines (twice the amount of RAID parity data in the example). Therefore, the amount of intermediate results can be very large. Consequently, when the amount of intermediate results exceeds the storage capacity of the parity buffer, the memory controller may need to perform swapping operations to store the intermediate results, in addition to using other buffer space as a parity buffer, which can impact the efficiency of write operations.

[0088] Figure 8 Memory devices (e.g., RAID schemes of combined storage plane RAID and 2WL RAID) are shown according to some aspects of this disclosure. Figures 1 to 2B and Figure 5 Memory device 104, Figure 3A Example data structure of the memory device 300. In a RAID scheme combining storage surface RAID and 2WL RAID, the memory controller (e.g., Figures 1 to 2B and Figure 5The memory controller 106 can use a storage plane RAID scheme to generate RAID parity data 814A corresponding to page lines 802A associated with the first group of word lines, and use a 2WL RAID scheme to generate RAID parity data 814B corresponding to page lines 802B1, ..., 802Bn (collectively referred to as 802B) associated with the second group of word lines. In a scenario where one page line 802 (including 802A and 802B) comprises T data portions and each of the first group of word lines comprises W word lines (where T and W are positive integers), the overall ratio of the amount of RAID parity data to the amount of user data in the memory device is:

[0089] In some implementations, the first set of word lines includes even-numbered word lines (e.g., WL0, WL2, ..., WL14), wherein the memory controller generates RAID parity data 814A by performing an XOR operation between data portions in each page line 802A, and stores the RAID parity data 814A as the last data portion in page line 802A. The second set of word lines includes odd-numbered word lines (e.g., WL1, WL3, ..., WL15), wherein the memory controller generates RAID parity data 814B by performing an XOR operation between data portions in page lines 802B1, ..., 802Bn associated with each word line in the second set of word lines, and stores the RAID parity data 814B as the last data portion in the last page line 802Bn associated with the second set of word lines.

[0090] As Figure 8In the example shown, the first set of word lines includes WL0, WL2, ..., and WL14, and the second set of word lines includes WL1, WL3, ..., WL15. The last data portion of each page line 802A associated with WL0, WL2, ..., and WL14 includes RAID parity data 814A generated under the storage plane RAID scheme. The last data portion of each page line 802Bn associated with WL15 includes RAID parity data 814B generated under the 2WL RAID scheme. For example, the last data portion in the page lines associated with Str0 and WL0 includes RAID parity data 814A generated by performing an XOR operation between 11 data portions in page line 802A, which includes user data; the last data portion in the page lines associated with Str0 and WL14 includes RAID parity data 814A generated by performing an XOR operation between 11 data portions in page lines, which includes user data; and the last data portion in the page lines associated with Str0 and WL15 includes RAID parity data 814B generated by performing an XOR operation between 95 data portions (including user data) across 8 page lines associated with each of Str0 and WL1, WL3, ... and WL15. In this example, the total ratio of the amount of RAID parity data to the amount of user data in the memory device is...

[0091] In some implementations, such as Figure 9 As shown, the first set of word lines includes odd-numbered word lines (e.g., WL1, WL3, ..., WL15), wherein the memory controller generates RAID parity data 914A by performing an XOR operation between the data portions in each page line 902A, and stores the RAID parity data 914A as the last data portion in page line 902A. The second set of word lines includes even-numbered word lines (e.g., WL0, WL2, ..., WL14), wherein the memory controller generates RAID parity data 914B by performing an XOR operation between the data portions in page lines 902B1, ..., 902Bn (collectively referred to as 902B) associated with each word line in the second set of word lines, and stores the RAID parity data 914B as the last data portion in the last page line 902Bn associated with the second set of word lines.

[0092] As Figure 9In the example shown, the first set of word lines includes WL1, WL3, ..., and WL15, and the second set of word lines includes WL0, WL2, ..., and WL14. The last data portion in each page line 902A associated with WL1, WL3, ..., and WL15 includes RAID parity data 914A generated under the storage plane RAID scheme. The last data portion in each page line 902Bn associated with WL14 includes RAID parity data 914B generated under the 2WL RAID scheme. For example, the last data portion in the page line associated with Str0 and WL1 includes RAID parity data 914A generated by performing an XOR operation between 11 data portions in that page line, which includes user data; the last data portion in the page line associated with Str0 and WL15 includes RAID parity data 914A generated by performing an XOR operation between 11 data portions in the page line, which includes user data; and the last data portion in the page line associated with Str0 and WL14 includes RAID parity data 914B generated by performing an XOR operation between 95 data portions (including user data) across 8 page lines associated with each of Str0 and WL0, WL2, ... and WL14.

[0093] In the event of a programming or read failure in a data portion of page lines 802A or 902A associated with the first set of word lines, the memory controller can recover the damaged data portion, for example, by performing an XOR operation using RAID parity data 814A or 914A of the target page line and the remaining data portion of the target page line. In the event of a programming or read failure in a data portion of page lines 802B or 902B associated with the second set of word lines, the damaged data portion can be recovered, for example, by performing an XOR operation using RAID parity data 814B or 914B generated based on multiple page lines including the target page line and the remaining data portions of the multiple page lines. In RAID schemes combining storage plane RAID and 2WL RAID, the damaged data portion can still be recovered even if a data portion fails in each of the two page lines 802A and 802B or 902A and 902B associated with adjacent word lines (e.g., page lines associated with Str0 and WL0 and page lines associated with Str0 and WL1).

[0094] In a combined storage-plane RAID and 2WL RAID scheme, regarding the first set of word lines, RAID parity data 814A or 914A is generated under the storage-plane RAID scheme. RAID parity data 814A or 914A can be written to the same page line as the user data applied to the application, so the parity buffer only needs to store the intermediate result of RAID parity data 814A or 914A corresponding to one page line. Regarding the second set of word lines, RAID parity data 814B or 914B is generated under the 2WL RAID scheme. During the process of writing user data to the previous page lines (e.g., all page lines associated with WL1 to WL14), the intermediate result of RAID parity data 814B or 914B needs to be retained in the parity buffer, so the parity buffer needs to store several page lines corresponding to one word line (e.g., ...). Figure 8 or Figure 9 The example shown has 8 page lines, representing an intermediate result of 814B or 914B of RAID parity data. This is compared to a 2WL RAID scheme (e.g., as shown). Figure 7 Compared to (as shown), the amount of intermediate results to be stored in the parity buffer can be smaller. Therefore, when the amount of intermediate results exceeds the storage capacity of the parity buffer, the memory controller can simply use other buffer space as a parity buffer without performing a swapping operation.

[0095] Figure 10 A flowchart of an example process 1000 for operating a memory system according to some aspects of this disclosure is shown. Process 1000 can be performed by any suitable means or system as described herein, for example, according to... Figures 1 to 9 The described example technology. For example, process 1000 may be comprised of a memory device (e.g., Figures 1 to 2B and Figure 5 Memory device 104, Figure 3A The memory device 300) and the memory controller (e.g., Figures 1 to 2B and Figure 5 The memory system (e.g., memory controller 106) of the memory controller 106 Figure 1 The memory system 102) executes. The memory device may include N dies, and each die includes M memory surfaces, where N and M are positive integers. Each memory surface includes one or more memory blocks (e.g., Figure 3B Storage block 304). Each storage block includes storage pages (e.g., Figure 3A Each storage page (320) is associated with one of a set of sequentially numbered word lines (e.g., WL0-WLn).

[0096] The operations shown in process 1000 are not exhaustive, and other operations can be performed before, after, or between any of the shown operations. Furthermore, some operations can be performed simultaneously, or in conjunction with... Figure 10 The different sequences of execution are shown. In some implementations, some operations in the operation may be performed by one or more components of the device or system, such as the peripheral circuitry of the memory device or the memory controller of the memory system.

[0097] At 1002, the memory controller uses the data to be written to the first memory page (e.g., ...). Figure 3A The first data in the storage page 320) is used to perform a first encoding operation to generate first parity data (e.g., Figure 8 RAID parity data 814A or Figure 9 The RAID parity data 914A), wherein the first storage page is associated with the k-th word line of the first storage block of each of the M storage surfaces of each of the N dies. The first data may be the page line to be stored as a data portion associated with the k-th word line (e.g., Figure 8 Page line 802A or Figure 9 The user data is stored in page line 902A. The first encoding operation includes an XOR operation between data portions in the page line associated with the k-th word line. Each data portion may represent data stored in one of the first storage pages.

[0098] At 1004, the memory controller determines the page to be written to (e.g., ...). Figure 3A The second data in storage page 320) undergoes a second encoding operation to generate second parity data (e.g., Figure 8 RAID parity data 814B or Figure 9 The RAID parity data 914B), wherein the second storage page is associated with at least the (k-1)th word line and the (k+1)th word line of the first storage block of each of the M storage surfaces of each of the N dies. The second data may be to be stored as a data portion on a page line associated with a set of word lines including at least the (k-1)th word line and the (k+1)th word line (e.g., Figure 8 Page line 802B or Figure 9 User data in page line 902B). This group of word lines is separated from each other by a word line (e.g., including such as Figure 8 The set of odd-numbered word lines shown, or including, for example Figure 9 (The set of word lines with even numbers shown). The second encoding operation includes an XOR operation between the data portion of a page line associated with the set of word lines, which includes at least the (k-1)th word line and the (k+1)th word line.

[0099] In some implementations, the first parity data is generated based on a storage-plane RAID scheme, and the second parity data is generated based on a 2WL RAID scheme. A first ratio of the amount of the first parity data to the amount of the first data is greater than a second ratio of the amount of the second parity data to the amount of the second data.

[0100] In some implementations, the memory controller responds to the host (e.g., Figure 1 and Figure 5 The host 108) receives one or more write commands for writing first data and second data to a memory device to generate first parity data and second parity data (e.g., via...). Figure 5 (RAID circuit 516). In response to a read failure detected when reading first data from the memory device, the memory controller can use first parity data to recover the faulty data portion of the first data. In response to a read failure detected when reading second data from the memory device, the memory controller can use second parity data to recover the faulty data portion of the second data.

[0101] At position 1006, the memory controller writes the first data, the first parity data, the second data, and the second parity data into the memory device.

[0102] In some implementations, first parity data is written to a storage page associated with the k-th word line of a first storage block on the M-th storage face of the N-th die (e.g., as the last data portion of a page line associated with the k-th word line). Second parity data is written to a storage page associated with the (k+1)-th word line of a first storage block on the M-th storage face of the N-th die (e.g., as the last data portion of a last page line associated with the set of word lines including at least the (k-1)-th word line and the (k+1)-th word line).

[0103] In some implementations, before writing the first parity data and the second parity data to the memory device, the memory controller may store the intermediate result of the XOR operation used to generate the first parity data and the second parity data in a buffer of the memory controller (e.g., ...). Figure 5 In the parity buffer 508), the memory controller can temporarily store intermediate results in the memory device without performing a swap operation.

[0104] This disclosure also provides a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores one or more instructions (e.g., firmware of a memory controller) that can be executed by a computer system. When executed by a computer system, the instructions in the storage medium can be implemented for managing, etc. Figures 1 to 9The method for parity checking data is shown.

[0105] The non-transitory computer-readable storage medium can be an internal storage unit of the device described in any of the above embodiments. For example, the non-transitory computer-readable storage medium can be a hard disk or internal memory of the device. The non-transitory computer-readable storage medium can also be an external storage device of the device, such as an insertable hard disk, a smart memory card (SMC), a secure digital card (SD) card, a flash memory card, etc. In addition, the non-transitory computer-readable storage medium can also include internal storage components and external storage devices.

[0106] While this specification contains numerous details of specific embodiments, these should not be construed as limiting the scope of the claims, but rather as descriptions of features that may be specific to particular embodiments. Certain features described herein in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any sub-combination in multiple embodiments. Furthermore, although previously described features may be described as operating in certain combinations and even initially claimed in this way, in some cases, one or more features from the claimed combination may be removed from the combination, and the claimed combination may be for sub-combinations or variations thereof.

[0107] As used in this disclosure, unless the context clearly indicates otherwise, the terms “a,” “an,” or “the” are used to include one or more. Unless otherwise indicated, the term “or” is used to mean a non-exclusive “or.” The phrase “at least one of A and B” has the same meaning as “A, B, or A and B.” Furthermore, all wording and terms used in this disclosure unless otherwise defined are for descriptive purposes only and not for limitation. Any use of section headings is intended to aid in reading the document and is not to be construed as restrictive; information relating to a section heading may appear within or outside that particular section.

[0108] As used in this disclosure, the terms “about” or “approximately” may allow for a degree of variability in a value or range, for example, within 10%, 5%, or 1% of a specified value, or within a specified range limit.

[0109] As used in this disclosure, the term “substantially” means the majority or most, at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or higher.

[0110] Values ​​expressed in range format should be interpreted flexibly to include not only the numerical value explicitly stated as a range limit, but also all individual numerical values ​​or subranges contained within that range, as if each numerical value and subrange were explicitly stated. For example, the range “0.1% to about 5%” or “0.1% to 5%” should be interpreted to include about 0.1% to about 5%, as well as the individual values ​​(e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the indicated range. Unless otherwise stated, the statement “X to Y” has the same meaning as “about X to about Y”. Similarly, unless otherwise stated, the statement “X, Y, or Z” has the same meaning as “about X, about Y, or about Z”.

[0111] Specific embodiments of the subject matter have been described. Other embodiments, variations, and arrangements of the described embodiments are within the scope of the appended claims and will be apparent to those skilled in the art. Although operations are depicted in a specific order in the drawings or claims, such operations need not be performed in the specific order shown or in a sequential order, or all shown operations need to be performed (some operations may be considered optional) to achieve the desired result. In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and considered appropriate.

[0112] Furthermore, not all implementations require the separation or integration of the various system modules and components described in the previously described implementations, and the described components and systems can generally be integrated together or packaged into multiple products.

[0113] Therefore, the exemplary embodiments described above do not limit or restrict the scope of this disclosure. Other changes, substitutions, and modifications are possible without departing from the spirit and scope of this disclosure.

[0114] The foregoing description of the specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance given herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0115] The scope and extent of this disclosure should not be limited by any of the embodiments described in the foregoing example embodiments, but should be defined solely by the appended claims and their equivalents. Therefore, other embodiments are also within the scope of the claims.

Claims

1. A memory system, comprising: A memory device comprising N dies, each of the N dies comprising M memory surfaces, each of the M memory surfaces comprising a first memory block, wherein N and M are positive integers, and wherein the first memory block comprises memory pages, each memory page being associated with a word line in a set of sequentially numbered word lines; and A memory controller coupled to the memory device, wherein the memory controller is configured to perform operations including the following: First parity data is generated by performing a first encoding operation on the first data, wherein the first data is to be written to a storage page associated with the k-th word line of the first storage block of each of the M storage surfaces of each of the N dies, wherein k is an integer greater than 1; Second parity data is generated by performing a second encoding operation on the second data, wherein the second data is to be written to a memory page associated with at least the (k-1)th word line and the (k+1)th word line of the first memory block of each of the M memory faces of each of the N dies; and The first data, the first parity data, the second data, and the second parity data are written to the memory device.

2. The memory system according to claim 1, wherein, The first parity data and the second parity data include Redundant Array of Independent Disks (RAID) parity data.

3. The memory system according to claim 1 or 2, wherein, The second parity data is generated by performing the second encoding operation on the second data, wherein the second data is to be written to a memory page associated with a set of odd-numbered word lines of the first memory block of each of the M memory faces of each of the N dies.

4. The memory system according to any one of claims 1 to 3, wherein, The second parity data is generated by performing the second encoding operation on the second data, wherein the second data is to be written to a memory page associated with a set of even-numbered word lines of the first memory block of each of the M memory faces of each of the N dies.

5. The memory system according to any one of claims 1 to 4, wherein, The first ratio of the amount of the first parity check data to the amount of the first data is greater than the second ratio of the amount of the second parity check data to the amount of the second data.

6. The memory system according to any one of claims 1 to 5, wherein, The first parity data is written to the memory page associated with the k-th word line of the first memory block on the M-th memory face of the N-th die, and The second parity data is written to the storage page associated with the (k+1)th word line of the first storage block of the Mth storage surface of the Nth die.

7. The memory system according to any one of claims 1 to 6, wherein, The memory controller is configured to perform the operation in response to receiving one or more write commands from the host for writing the first data and the second data.

8. The memory system according to any one of claims 1 to 7, wherein, The first encoding operation and the second encoding operation each include multiple XOR operations, wherein the results of the multiple XOR operations are stored in the buffer of the memory controller.

9. The memory system according to any one of claims 1 to 8, wherein, The operation includes: In response to a read failure detected while reading the first data, the first data is recovered using the first parity data; or In response to a read failure detected while reading the second data, the first parity data is used to recover the first data.

10. A memory controller, comprising: One or more processors and an interface, wherein the one or more processors are configured to perform operations including the following: One or more first write commands for writing first data and first parity data to a memory device are sent through the interface, wherein the memory device includes N dies, each of the N dies includes M memory faces, each of the M memory faces includes a first memory block, wherein N and M are positive integers, wherein the first memory block includes memory pages, each memory page is associated with a word line in a set of sequentially numbered word lines, wherein the first parity data is generated by performing a first encoding operation on the first data, wherein the first data is to be written to a memory page associated with the k-th word line of the first memory block of each of the M memory faces of the N dies, wherein k is a positive integer; and One or more second write commands are sent through the interface to write second data and second parity data to the memory device, wherein the second parity data is generated by performing a second encoding operation on the second data, wherein the second data is to be written to a memory page associated with at least the (k-1)th word line and the (k+1)th word line of the first memory block of each of the M memory surfaces of each of the N dies.

11. The memory controller according to claim 10, wherein, The first parity data and the second parity data include Redundant Array of Independent Disks (RAID) parity data.

12. The memory controller according to claim 10 or 11, wherein, The second parity data is generated by performing the second encoding operation on the second data, wherein the second data is to be written to a memory page associated with a set of odd-numbered word lines of the first memory block of each of the M memory faces of each of the N dies.

13. The memory controller according to any one of claims 10 to 12, wherein, The second parity data is generated by performing the second encoding operation on the second data, wherein the second data is to be written to a memory page associated with a set of even-numbered word lines of the first memory block of each of the M memory faces of each of the N dies.

14. The memory controller according to any one of claims 10 to 13, wherein, The first ratio of the amount of the first parity check data to the amount of the first data is greater than the second ratio of the amount of the second parity check data to the amount of the second data.

15. The memory controller according to any one of claims 10 to 14, wherein, The first parity data is written to the memory page associated with the k-th word line of the first memory block on the M-th memory face of the N-th die, and The second parity data is written to the storage page associated with the (k+1)th word line of the first storage block of the Mth storage surface of the Nth die.

16. The memory controller according to any one of claims 10 to 15, wherein, The memory controller is configured to perform the operation in response to receiving one or more write commands from the host for writing the first data and the second data.

17. The memory controller according to any one of claims 10 to 16, wherein, The first encoding operation and the second encoding operation each include multiple XOR operations, and the results of the multiple XOR operations are stored in the buffer of the memory controller.

18. The memory controller according to any one of claims 10 to 17, wherein, The operation includes: In response to a read failure detected while reading the first data, the first data is recovered using the first parity data; or In response to a read failure detected while reading the second data, the first parity data is used to recover the first data.

19. A method of operating a memory system, comprising: First parity data is generated by performing a first encoding operation on first data to be written to a first storage page of a memory device, wherein the memory device includes N dies, each of the N dies includes M storage surfaces, each of the M storage surfaces includes a first storage block, wherein N and M are positive integers, wherein the first storage block includes storage pages, each storage page is associated with a word line in a set of sequentially numbered word lines, and wherein the first storage page is associated with the k-th word line of the first storage block of each of the M storage surfaces of the N dies, wherein k is a positive integer; Second parity data is generated by performing a second encoding operation on the second data, wherein the second data is to be written to a second memory page associated with at least the (k-1)th word line and the (k+1)th word line of the first memory block of each of the M memory faces of each of the N dies; and The first data, the first parity data, the second data, and the second parity data are written to the memory device.

20. The method according to claim 19, wherein, The first ratio of the amount of the first parity check data to the amount of the first data is greater than the second ratio of the amount of the second parity check data to the amount of the second data.

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