Chip testing method, device, storage medium and equipment

Abstract

One or more embodiments of the present application disclose a chip testing method, device, storage medium and equipment, the method comprising: obtaining a first test file according to a chip to be tested, wherein the first test file is an executable file; selecting a target test definition file from a plurality of preset test definition files according to the chip to be tested, wherein the test definition file comprises test parameters; obtaining the target test definition file; combining the first test file and the target test definition file to obtain a second test file; and testing the chip to be tested according to the second test file to obtain a test result of the chip to be tested, which can effectively shorten the chip testing period.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a chip testing method, apparatus, storage medium, and device. Background Technology

[0002] With the continuous development of semiconductor chip manufacturing processes, the number of transistors on silicon-based semiconductor chips per unit area is constantly increasing. Improving processes and increasing yield is imperative, and chip testing based on ATE platforms has become a valuable tool for guiding yield improvement and identifying weaknesses in the process. As the integration and complexity of SoCs (System-on-a-Chip) increase, the development cycle of test programs is constantly increasing, and the testing difficulty is also constantly rising. This results in significant time losses for new product development and mass production. In the field of semiconductor chip testing, ATE (Automatic Test Equipment) is a test system used to provide test modes for chips and analyze the chip's response to these modes to detect whether the chip meets expectations. In the field of semiconductor chip testing, the testing of various mainstream chips is basically based on ATE. ATE itself is a programmable automated test machine that can flexibly implement various test logic signals and judgments by setting different timing, level, rate, wave type, and drive type. Therefore, ATE test program development is particularly important in the entire semiconductor chip testing field.

[0003] Currently, even within the same chip series, updates to different models and specifications require continuous updates to the corresponding ATE (Automatic Test Equipment) programs to meet new testing demands. This necessitates the constant development of new ATE programs, extending the chip testing cycle. Summary of the Invention

[0004] In view of this, one or more embodiments of the present invention provide a chip testing method, apparatus, storage medium and device, which can effectively shorten the chip testing cycle.

[0005] One or more embodiments of the present invention provide a chip testing method, comprising: obtaining a first test file based on a chip to be tested, wherein the first test file is an executable file; selecting a target test definition file from a plurality of preset test definition files based on the chip to be tested, wherein the test definition file includes test parameters; obtaining the target test definition file; combining the first test file and the target test definition file to obtain a second test file; and testing the chip to be tested based on the second test file to obtain a test result for the chip to be tested.

[0006] Optionally, the method further includes: acquiring multiple different product definition parameters for the chip under test before acquiring the first test file based on the chip under test; generating the multiple test definition files based on the product definition parameters; storing the multiple test definition files in a target device; and sharing the memory of the target device with a testing machine, wherein the testing machine is used to test the chip under test.

[0007] Optionally, the test equipment stores the first test file, and obtaining the target test definition file includes: reading the target test definition file from the memory through the test equipment.

[0008] Optionally, the test definition file interface defines the correspondence between the chip under test and the target test definition file. Selecting a target test definition file from a set of preset test definition files based on the chip under test includes: selecting the target test definition file corresponding to the chip under test from the set of test definition files according to the correspondence. Optionally, the test definition file may also include: attribute parameters of the chip under test and the numerical range of the test parameters.

[0009] One or more embodiments of the present invention provide a chip testing apparatus, comprising: a first acquisition module configured to acquire a first test file based on a chip to be tested, wherein the first test file is an executable file; a selection module configured to select a target test definition file from a plurality of preset test definition files based on the chip to be tested, wherein the test definition file includes test parameters; a second acquisition module configured to acquire the target test definition file; a combination module configured to combine the first test file and the target test definition file to obtain a second test file; and a testing module configured to test the chip to be tested based on the second test file to obtain a test result for the chip to be tested.

[0010] Optionally, the apparatus further includes: a third acquisition module configured to acquire multiple different product definition parameters of the chip under test before acquiring the first test file based on the chip under test; a generation module configured to generate the multiple test definition files based on the product definition parameters; a storage module configured to store the multiple test definition files in a target device; and a sharing module configured to share the memory of the target device with a testing machine, wherein the testing machine is used to test the chip under test.

[0011] Optionally, the test equipment stores the first test file, and the second acquisition module is specifically configured to read the target test definition file from the memory through the test equipment.

[0012] Optionally, the test definition file interface defines the correspondence between the chip under test and the target test definition file; the selection module is specifically configured to: select the target test definition file corresponding to the chip under test from the plurality of test definition files according to the correspondence.

[0013] Optionally, the test definition file may also include: attribute parameters of the chip under test and the numerical range of the test parameters.

[0014] One or more embodiments of the present invention provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement any of the chip testing methods described above.

[0015] One or more embodiments of the present invention provide a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute any of the above-described chip testing methods.

[0016] The chip testing method provided by one or more embodiments of the present invention obtains a first test file and a target test definition file corresponding to the chip under test before testing the chip under test. The test definition file includes test parameters, and the first test file is an executable file. The first test file and the target test definition file are combined to obtain a second test file. The second test file is used to test the chip under test. In this method, the executable file and the test definition file in the chip test program exist independently. In this way, when testing different chips, only the target test definition file needs to be obtained. The complete test program can be obtained by combining the target test definition file with the first test file without the need to redevelop a new test program, thus shortening the chip testing cycle. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating a chip testing method according to one or more embodiments of the present invention;

[0019] Figure 2This is a schematic diagram illustrating the combination of a target test definition file and a first test file according to one or more embodiments of the present invention;

[0020] Figure 3 This is a schematic diagram of a chip testing system according to one or more embodiments of the present invention;

[0021] Figure 4 This is a schematic diagram of the structure of a chip testing apparatus according to one or more embodiments of the present invention;

[0022] Figure 5 This is a schematic diagram of the structure of an electronic device according to one or more embodiments of the present invention. Detailed Implementation

[0023] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0024] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0025] In the development of test programs based on the ATE platform, in addition to developing the main framework of the test program, including common parts such as configuration files, vector files, and test procedures, it is also necessary to determine the test definition files. These include upper and lower limits for some parameters, test parameters (such as timing, level, frequency, waveform, and drive type), and even some parameters related to product definition, such as frequency and power. These parameters are developed as part of the test program and are closely linked to the main framework.

[0026] Taking SoC (System-on-a-Chip) chips as an example, due to their large scale, numerous internal IPs (Intellectual Property, referring to a design module with intellectual property rights), and many parameters, the corresponding test programs are also quite complex and extensive. Typically, SoC chips within the same series have relatively similar internal modules, with the main differences being in the performance and specifications of some modules. For ATE (Automatic Test Equipment) programs, this manifests as differences in parameter configurations, while the overall testing methods and processes remain consistent—that is, the main framework of the test program is the same, only the test definition files differ. Currently, even within the same series of SoC chips, the corresponding ATE test programs need continuous updates to meet new testing requirements for different models and specifications.

[0027] If the test definition file needs to be updated, then both the main program framework and the test definition file need to be redeveloped / updated, greatly extending the development cycle. It also results in a significant amount of redundant and repetitive work.

[0028] If different specifications of SoC chips in the same series each have their own complete ATE test programs, it will result in a large number of test programs, occupy a large amount of storage space, and make program management difficult. For example, if a certain IP module of a certain series of SoC chips needs to upgrade the test program flow or algorithm, then all test programs of different models in that series need to be upgraded, which is a large workload and extends the chip testing cycle.

[0029] Figure 1 This is a flowchart illustrating a chip testing method according to one or more embodiments of the present invention, such as... Figure 1 As shown, the method includes:

[0030] Step 101: Obtain the first test file based on the chip to be tested, wherein the first test file is an executable file;

[0031] The first test file may include, for example, the main framework of the test program described above, and may include configuration files, vector files, and test procedures, etc.

[0032] Step 102: Select a target test definition file from a plurality of preset test definition files according to the chip to be tested, wherein the test definition file includes test parameters;

[0033] In one or more embodiments of the present invention, test definition files corresponding to multiple different chips can be pre-set. These test definition files may contain at least the test parameters required to perform the current test. These test definition files may correspond to the identifiers of their respective chips. Based on this, before testing the chip to be tested, the target test definition file corresponding to the chip to be tested can be determined according to the identifier of the chip to be tested. The test definition file may be, for example, a CSV (comma-separated values) file or an XML (Extensible Markup Language) file.

[0034] Step 103: Obtain the target test definition file;

[0035] In one or more embodiments of the present invention, the testing equipment used to test the chip under test may store only the first test file. In this way, when testing different chips under test, the testing equipment can only obtain the target test definition file corresponding to the current chip under test. Obviously, this can reduce the storage space occupied by the test file on the testing equipment. In addition, the test definition files corresponding to different chips can be stored in other storage devices besides the testing equipment. After the target test definition file required for the current test is determined, the target test definition file is obtained from the storage device. It can be seen that only the target test definition file needs to be transmitted to the testing equipment, and there is no need to transmit the entire test program file to the testing equipment, resulting in a smaller data transmission volume.

[0036] Step 104: Combine the first test file with the target test definition file to obtain the second test file;

[0037] by Figure 2 For example, the first test file may include binning (rules or criteria for classifying test results), communication, configuration files, script files, tests for each IP module, vectors, test algorithms, and test parameters. The first test file may also include a call interface, which can be used to call the target test definition file. For example, by re-executing the initial operation on the test machine, the test parameters in the target test definition file can be integrated into the first test file to form a complete test program.

[0038] Step 105: Test the chip under test according to the second test file to obtain the test results of the chip under test.

[0039] The chip testing method provided by one or more embodiments of the present invention obtains a first test file and a target test definition file corresponding to the chip under test before testing the chip under test. The test definition file includes test parameters, and the first test file is an executable file. The first test file and the target test definition file are combined to obtain a second test file. The second test file is used to test the chip under test. In this method, the executable file and the test definition file in the chip test program exist independently. In this way, when testing different chips, only the target test definition file needs to be obtained. The complete test program can be obtained by combining the target test definition file with the first test file without the need to redevelop a new test program, thus shortening the chip testing cycle.

[0040] In one or more embodiments of the present invention, the above-described chip testing method may further include:

[0041] Before obtaining the first test file based on the chip under test, obtain product definition parameters for multiple different chips under test;

[0042] Generate the multiple test definition files based on the product definition parameters;

[0043] For example, when testing multiple SoCs from the same series, the customized parameters can be extracted from the test program of the same series of SoCs. These parameters can then be defined to create one or more independent program-callable files (an example of the test definition file mentioned above). For instance, a single program-callable file can be created, or, if multiple different parameters are included, multiple independent program-callable files can be created based on the type of parameter.

[0044] Store the multiple test definition files to the target device;

[0045] The target device may be, for example, an electronic device independent of the ATE (Automatic Test Equipment) platform. The memory of the target device is shared with the test platform, which is used to test the chip under test. The test platform may be, for example, an ATE, and therefore, the test performed on the chip under test may be an ATE test. The memory of the target device may be, for example, the target device's hard drive. After sharing the target device's hard drive with the test platform, the test platform can access the hard drive to obtain the target test definition file from it.

[0046] In one or more embodiments of the present invention, the testing equipment stores the first test file, and based on this, obtaining the target test definition file may include:

[0047] The target test definition file is read from the memory using the test equipment. Figure 3 Taking the chip testing system shown as an example, in this example, the system involves an electronic device that stores test definition files. This electronic device can be connected to an ATE test machine via a local area network and share its hard drive with the ATE test machine, so that the ATE test machine can directly obtain the target test definition file from the hard drive via the local area network before testing the chip to be tested.

[0048] In one or more embodiments of the present invention, taking a SoC chip as an example, the script of the test definition file can support customized definitions for multiple series of SoC chips of different products. After the script is started, it can automatically identify the target test definition file required by the current chip test program, and then download the required target test definition file from the electronic device storing the test definition file. The downloaded target test definition file is integrated with the chip test program to form a complete test program, and the chip can be tested through the complete test program.

[0049] In one or more embodiments of the present invention, the first test file may include a test definition file interface, wherein the test definition file interface defines the correspondence between the chip under test and the target test definition file. Selecting a target test definition file from a plurality of preset test definition files according to the chip under test may include: selecting the target test definition file corresponding to the chip under test from the plurality of test definition files according to the correspondence. Figure 3 The example shown, Figure 3 The process also involves a remote system that can be used to manage and maintain test definition files and upload them to electronic devices via the internet as needed. An interface is set up during test program development; here, the test program with the interface set up is equivalent to the first test file mentioned above. The script through this interface can load the target test definition files required for the test from the electronic device to the ATE test machine at the start of each test, integrating the target test definition files with the test program to form a complete test program. This allows for updating the test program without updating the main framework, achieving the goal of updating the test program by only updating the test definition files, saving test program development time, improving work efficiency, and achieving rapid mass production.

[0050] In one or more embodiments of the present invention, the test definition file may further include: attribute parameters of the chip under test and the numerical range of the test parameters. The attribute parameters may be, for example, parameters related to the chip definition, such as power and frequency. The numerical range of the test parameters may include, for example, an upper limit and a lower limit for the test parameters. When testing the chip under test, the attribute parameters and the numerical range of the test parameters are called through the test definition file in the first test file. These data are then combined with the first test file to obtain the entire chip test program.

[0051] Since chip design companies are typically fabless companies, the ATE (Automatic Test Equipment) program actually needs to be transmitted to a professional packaging and testing facility for testing. However, the chip testing method provided by one or more embodiments of this invention only requires the transmission of the test definition file, saving program transmission time and network bandwidth.

[0052] Figure 4 This is a schematic diagram of the structure of a chip testing device according to one or more embodiments of the present invention, such as... Figure 4 As shown, the device 40 includes:

[0053] The first acquisition module 41 is configured to acquire a first test file based on the chip to be tested, wherein the first test file is an executable file;

[0054] Selection module 42 is configured to select a target test definition file from a plurality of preset test definition files based on the chip to be tested, wherein the test definition file includes test parameters;

[0055] The second acquisition module 43 is configured to acquire the target test definition file;

[0056] Module 44 is configured to combine the first test file with the target test definition file to obtain a second test file;

[0057] The test module 45 is configured to test the chip under test according to the second test file and obtain the test results of the chip under test.

[0058] In one or more embodiments of the present invention, the chip testing apparatus may further include:

[0059] The third acquisition module is configured to acquire multiple different product definition parameters of the chip under test before acquiring the first test file based on the chip under test;

[0060] The generation module is configured to generate the plurality of test definition files based on the product definition parameters;

[0061] The storage module is configured to store the plurality of test definition files to the target device;

[0062] A sharing module is configured to share the memory of the target device with a test bench, wherein the test bench is used to test the chip under test.

[0063] In one or more embodiments of the present invention, the testing equipment stores the first test file, and the second acquisition module may be specifically configured as follows:

[0064] The target test definition file is read from the memory using the test equipment.

[0065] In one or more embodiments of the present invention, the first test file includes a test definition file interface, wherein the test definition file interface defines the correspondence between the chip under test and the target test definition file;

[0066] The selection module is specifically configured to: select the target test definition file corresponding to the chip under test from the plurality of test definition files according to the correspondence.

[0067] In one or more embodiments of the present invention, the test definition file may further include:

[0068] The attribute parameters of the chip under test and the numerical range of the test parameters.

[0069] One or more embodiments of the present invention also provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement any of the chip testing methods described above.

[0070] One or more embodiments of the present invention also provide a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute any of the above-described chip testing methods.

[0071] Figure 5 The diagram illustrates a more specific hardware structure of an electronic device according to one or more embodiments of the present invention. The device may include: a processor 510, a memory 520, an input / output interface 530, a communication interface 540, and a bus 550. The processor 510, memory 520, input / output interface 530, and communication interface 540 are interconnected internally via the bus 550.

[0072] The processor 510 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0073] The memory 520 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 520 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 520 and is called and executed by the processor 510.

[0074] Input / output interface 530 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touch screens, microphones, various sensors, etc., and output devices may include displays, speakers, vibrators, indicator lights, etc.

[0075] The communication interface 540 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (e.g., USB, Ethernet cable) or wireless means (e.g., mobile network, Wi-Fi, Bluetooth).

[0076] Bus 550 includes a pathway for transmitting information between various components of the device, such as processor 510, memory 420, input / output interface 530, and communication interface 540.

[0077] It should be noted that although the above-described device only shows the processor 510, memory 520, input / output interface 530, communication interface 540, and bus 550, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0078] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0079] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0080] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0081] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0082] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0083] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0084] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip testing method, characterized in that, include: A first test file is obtained based on the chip to be tested, wherein the first test file is an executable file; the chip to be tested is any one of the SoC chips in the same series, and the main framework of each test program of the SoC chips in the same series is consistent with each other; the first test file includes the main framework. According to the chip under test, select the target test definition file corresponding to the chip under test from a plurality of preset test definition files, wherein the test definition file includes test parameters; Obtain the target test definition file; The first test file is combined with the target test definition file to obtain the second test file; the second test file is a complete test program. The chip under test is tested according to the second test file to obtain the test results of the chip under test.

2. The method according to claim 1, characterized in that, The method further includes: Before obtaining the first test file based on the chip under test, obtain product definition parameters for multiple different chips under test; Generate the multiple test definition files based on the product definition parameters; Store the multiple test definition files to the target device; The memory of the target device is shared with a test equipment, which is used to test the chip under test.

3. The method according to claim 2, characterized in that, The testing equipment stores the first test file, and obtaining the target test definition file includes: The target test definition file is read from the memory using the test equipment.

4. The method according to claim 1, characterized in that, The first test file includes a test definition file interface, which defines the correspondence between the chip under test and the target test definition file. The target test definition file is selected from a plurality of preset test definition files based on the chip under test, including: Based on the correspondence, select the target test definition file corresponding to the chip under test from the plurality of test definition files.

5. The method according to any one of claims 1 to 4, characterized in that, The test definition file also includes: The attribute parameters of the chip under test and the numerical range of the test parameters.

6. A chip testing device, characterized in that, include: The first acquisition module is configured to acquire a first test file based on the chip to be tested, wherein the first test file is an executable file; the chip to be tested is any one of the SoC chips in the same series, and the main framework of each test program of the SoC chips in the same series is consistent with each other; the first test file includes the main framework. The selection module is configured to select a target test definition file corresponding to the chip under test from a plurality of preset test definition files based on the chip under test, wherein the test definition file includes test parameters; The second acquisition module is configured to acquire the target test definition file; The module is configured to combine the first test file with the target test definition file to obtain a second test file; the second test file is a complete test program. The testing module is configured to test the chip under test according to the second test file and obtain the test results of the chip under test.

7. The apparatus according to claim 6, characterized in that, The device further includes: The third acquisition module is configured to acquire multiple different product definition parameters of the chip under test before acquiring the first test file based on the chip under test; The generation module is configured to generate the plurality of test definition files based on the product definition parameters; The storage module is configured to store the plurality of test definition files to the target device; A sharing module is configured to share the memory of the target device with a test bench, wherein the test bench is used to test the chip under test.

8. The apparatus according to claim 7, characterized in that, The testing machine stores the first test file, and the second acquisition module is specifically configured as follows: The target test definition file is read from the memory using the test equipment.

9. The apparatus according to claim 6, characterized in that, The first test file includes a test definition file interface. The test definition file interface defines the correspondence between the chip under test and the target test definition file; The selection module is specifically configured as follows: Based on the correspondence, select the target test definition file corresponding to the chip under test from the plurality of test definition files.

10. The apparatus according to any one of claims 6 to 9, characterized in that, The test definition file also includes: The attribute parameters of the chip under test and the numerical range of the test parameters.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the chip testing method as described in any one of claims 1 to 5.

12. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer instructions for causing the computer to perform the chip testing method according to any one of claims 1 to 5.

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