Memory devices and memory systems including memory devices

Abstract

Memory devices and memory systems including memory devices are provided. A memory device provides a first memory region and a second memory region. An intelligent buffer includes a priority setting unit that receives sensing data and a corresponding weight, determines a priority of the sensing data based on the corresponding weight, and classifies the sensing data as first priority sensing data or second priority sensing data based on the priority, and a lane controller that assigns a lane to a first lane group, assigns another lane to a second lane group, assigns the first lane group to handle the first priority sensing data related to the first memory region, and assigns the second lane group to handle the second priority sensing data related to the second memory region.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0138720, filed on November 1, 2019, with the Korean Intellectual Property Office, the subject of which is incorporated herein by reference. Technical Field

[0002] The inventive concept relates to memory devices and memory systems including memory devices. Background Technology

[0003] With the development of the automotive electronics market, various sensors such as image sensors, radar, and lidar have been installed in automobiles. Due to the large amount of sensor data generated, more efficient memory devices are needed. Such memory devices must be able to send, receive, store, and / or retrieve data to provide faster data processing and data transfer speeds. Unfortunately, conventional memory devices cannot provide the required data processing and data transfer speeds without becoming too expensive and / or physically too large. Furthermore, conventional memory devices cannot easily provide sufficient data transfer channels. Summary of the Invention

[0004] In one aspect, embodiments of the inventive concept provide a memory device including a smart buffer capable of classifying sensed data according to their relative importance. In another aspect, embodiments of the inventive concept provide a memory device capable of allocating transmission channels to sensed data according to their relative importance.

[0005] According to an aspect of the inventive concept, a memory device includes a smart buffer and a total memory region divided into a first memory region and a second memory region. The smart buffer includes: a priority setting unit configured to receive sensed data and corresponding weights from a controller, determine a priority for the sensed data based on the weights, and classify the sensed data into one of first priority sensed data and second priority sensed data; and a channel controller configured to assign at least one channel selected from a plurality of channels to a first channel group, assign at least another channel selected from a plurality of channels to a second channel group, assign the first channel group to process first priority sensed data associated with the first memory region, and assign the second channel group to process second priority sensed data associated with the second memory region, wherein the number of data input / output (I / O) pins connected to the second channel group is greater than the number of data input / output (I / O) pins connected to the first channel group.

[0006] According to another aspect of the inventive concept, a memory device includes: a memory package including a smart buffer mounted on a semiconductor substrate and a plurality of semiconductor chips, wherein the smart buffer is implemented on a semiconductor chip different from the plurality of semiconductor chips, and the plurality of semiconductor chips provide a plurality of memory regions including a first memory region and a second memory region, wherein the smart buffer includes: a priority setting unit configured to receive sensed data and corresponding weights obtained by performing a neural network operation on the sensed data, determine a priority of the sensed data based on the corresponding weights, and classify the sensed data into one of first priority sensed data and second priority sensed data based on the priority; and a channel controller configured to assign at least one channel selected from the plurality of channels to a first channel group, assign at least another channel selected from the plurality of channels to a second channel group, assign the first channel group to process first priority sensed data associated with a first memory region, and assign the second channel group to process second priority sensed data associated with a second memory region.

[0007] According to another aspect of the inventive concept, a memory system includes: a controller and a memory device, the controller including a weight calculator configured to use neural network operations to calculate corresponding weights for sensed data. The memory device includes: a total memory region and a smart buffer, the total memory region being divided into a plurality of memory regions including a first memory region and a second memory region. The smart buffer includes: a priority setting unit configured to receive sensed data and corresponding weights, determine a priority of the sensed data based on the corresponding weights, and classify the sensed data into one of first priority sensed data and second priority sensed data based on the priority; and a channel controller configured to assign at least one channel selected from a plurality of channels to a first channel group, assign at least another channel selected from a plurality of channels to a second channel group, assign the first channel group to process first priority sensed data associated with the first memory region, and assign the second channel group to process second priority sensed data associated with the second memory region.

[0008] According to another aspect of the inventive concept, a vehicle-based system includes a sensor disposed in the vehicle and providing sensing data to a memory system including a controller and a memory device. The controller includes a weight calculator configured to calculate corresponding weights for the sensing data using a mapping table. The memory device includes a total memory region and a smart buffer, the total memory region being divided into multiple memory regions including a first memory region and a second memory region. The smart buffer includes a priority setting unit configured to receive the sensing data and corresponding weights, determine the priority of the sensing data based on the corresponding weights, and classify the sensing data into one of first priority sensing data and second priority sensing data based on the priority; and a channel controller configured to assign at least one channel selected from a plurality of channels to a first channel group, assign at least another channel selected from a plurality of channels to a second channel group, assign the first channel group to process first priority sensing data associated with the first memory region, and assign the second channel group to process second priority sensing data associated with the second memory region. Attached Figure Description

[0009] The above and other aspects, features and advantages of the inventive concept will be clearly understood from the following detailed description taken in conjunction with the accompanying drawings:

[0010] Figure 1 This is a simplified view illustrating a computing system according to an embodiment of the inventive concept.

[0011] Figures 2 to 4 This is a view illustrating a memory system according to an embodiment of the inventive concept.

[0012] Figure 5 This is a view illustrating a memory device according to an embodiment of the inventive concept.

[0013] Figure 6A and Figure 6B This is a view illustrating a method for generating a channel group via a memory device according to an embodiment of the inventive concept.

[0014] Figure 7 This is a view illustrating the configuration of a memory according to an embodiment of the inventive concept.

[0015] Figure 8 , Figure 9A and Figure 9B This is a view illustrating the structure of a memory cell that may be included in a memory according to an embodiment of the inventive concept.

[0016] Figure 10A and Figure 10B This is a schematic diagram illustrating the structure of a memory device according to an embodiment of the inventive concept.

[0017] Figure 11A and Figure 11B This is a schematic diagram illustrating the structure of a memory device according to an embodiment of the inventive concept.

[0018] Figure 12 This is a flowchart illustrating a method of operating a memory device according to an embodiment of the inventive concept.

[0019] Figure 13A and Figure 13B This is a view illustrating a method of sending data to a memory region via a smart buffer according to an embodiment of the inventive concept.

[0020] Figure 14 This is a view illustrating a memory device according to an embodiment of the inventive concept.

[0021] Figure 15A and Figure 15B This is a schematic diagram illustrating the structure of a memory device according to an embodiment of the inventive concept.

[0022] Figure 16 This is a view illustrating a memory system according to an embodiment of the inventive concept.

[0023] Figure 17 and Figure 18 This is a view illustrating a memory device according to an embodiment of the inventive concept.

[0024] Figure 19 This is a block diagram schematically illustrating an electronic device including a memory device according to an embodiment of the inventive concept.

[0025] Figure 20 This is a view illustrating an application example of a memory device according to an embodiment of the inventive concept. Detailed Implementation

[0026] In the following description, embodiments of the inventive concept will be illustrated with some additional detail by reference to the accompanying drawings. Throughout the drawings, the same reference numerals and labels are used to denote the same components.

[0027] Figure 1 This is a general block diagram illustrating a computing system 1 according to an embodiment of the inventive concept.

[0028] Reference Figure 1 The computing system 1 may include a sensor unit 10, a controller 20, and a memory device 30.

[0029] Sensor unit 10 may include a plurality of sensors 11, 12, and 13 (hereinafter, “sensors”). The sensors (e.g., the first through nth sensors, including sensors 11, 12, and 13) may be one or more of various known sensor types, including image sensors, speed sensors, light sensors, temperature sensors, distance sensors, etc. Sensor unit 10 may process and / or aggregate various “sensing data” provided by the sensors. For example, sensor unit 10 may receive, process, and / or aggregate visual information, motion information, incident light information, temperature information, spatial relationship information, etc., provided by the sensors. In this respect, sensor unit 10 may be implemented in hardware, software, or a combination of both. Sensor unit 10 may be implemented as a single component or a group of components within computing system 1, and one or more of the components may be distributed components. The individual sensors among the sensors may provide sensing data in various formats and / or using various data transmission protocols. Nevertheless, once processed and / or aggregated by sensor unit 10, the sensing data may be provided to controller 20.

[0030] In the case where computing system 1 is a vehicle-based computing system for processing various data related to the vehicle's state and ongoing operations, sensors (e.g., 11, 12, and 13) can be differently mounted on or installed within the vehicle. In this respect, some of the sensors may be factory-installed in the vehicle, while one or more sensors may be aftermarket (or temporarily installed) in the vehicle by the vehicle's user or owner. For example, the sensors can be configured and connected via a wireless network connected to the Internet. Therefore, computing system 1 can be entirely or partially an Internet of Things (IoT) component or node.

[0031] The controller 20 can assign weights (or weighting factors) to the sensed data received from the sensor unit 10. In embodiments, the controller 20 may include neural network circuitry that can be used to calculate or determine appropriate weights for various sensed data. The neural network circuitry may be circuitry engineered based on the operational structure of the human brain and may include, for example, convolutional neural network (CNN) models, recurrent neural network (RNN) models, generative adversarial network (GAN) models, etc.

[0032] Once the sensed data is weighted by the controller 20, the weighted sensed data can be transmitted to the memory device 30 along with associated commands, requests, and / or addresses. The weighted sensed data can be accessed by the memory device 30 using recognized data access operations (such as write (or program) operations, read operations, erase operations, etc.). The controller 20 can use one or more interfaces to exchange data with the sensor unit 10 and / or the memory device 30.

[0033] The memory device 30 may include multiple memory regions configured differently to store weighted sense data, and multiple channels configured differently to transmit and / or receive (hereinafter, "transmit / receive") the weighted sense data. Each channel may be associated with (or used in combination with) one or more memory regions, wherein each memory region has a defined data storage capacity. In this regard, the memory device 30 may group the channels differently to logically divide the multiple memory regions. For example, the memory device 30 may group the channels into a first channel group, a second channel group, etc.

[0034] The data processing speed and / or data transfer speed of a corresponding memory region among multiple memory regions can vary with the assignment (or allocation) of a specific channel group. For example, a first memory region (e.g., a memory region comprising NAND flash memory cells operating as single-level memory cells (SLC)) can be assigned to a first channel group, thus exhibiting a first data processing speed and a first data transfer speed. A second memory region (e.g., a memory region comprising NAND flash memory cells operating as multi-level memory cells (MLC)) can be assigned to a second channel group, thus exhibiting a second data processing speed slower than the first data processing speed and a second data transfer speed slower than the first data transfer speed.

[0035] In this regard, the memory device 30 can dynamically allocate channel groups (e.g., reallocate channels within channel groups) and / or reassign channel groups within memory regions based on the amount and / or characteristics of the received sensed data. One feature that can be considered in this regard is the weight (e.g., importance weighting factor) assigned to the sensed data by the controller 20. The dynamic channel allocation capability of the memory device 30 provides more efficient use of memory device resources and faster overall data processing and data transfer.

[0036] In the following text, reference will be made to Figure 2 , Figure 3 and Figure 4 Description can be used Figure 1 The memory system (e.g., controller and memory device) in the computing system 1, wherein, Figure 2 It's a block diagram. Figure 3 It is a conceptual user manual. Figure 4 It is a conceptual list of data.

[0037] Reference Figure 2 The memory system 2 according to an embodiment of the inventive concept may include a controller 100 and a memory device 200. The controller 100 may include a weight calculator 110.

[0038] The weight calculator 110 can be used to assign weights to data (e.g., sensing data) received from an external source (e.g., sensor unit 10). Here, each "weight" can be a value representing the importance of the sensing data to the corresponding memory system 2 and / or computing system 1. The weight assigned to a particular sensing data can vary depending on the amount of data, the operating environment of the memory system 2, etc. For example, when the memory system 2 is part of a vehicle-based computing system, the nature and amount of sensing data provided by the sensors can vary depending on the vehicle's operating conditions (such as driving speed, driving time (e.g., day and night), driving direction (e.g., forward or backward) etc.). Therefore, the corresponding weights assigned to various sensing data can also vary depending on the vehicle's operating conditions.

[0039] Optionally or additionally, when the storage system 2 is an IoT system, the specific weights of various sensed data can vary with many factors, such as the user's lifestyle (e.g., bedtime), the layout or structure of the dwelling (e.g., south-facing windows), etc. (See reference...) Figure 3 and Figure 4 The memory system 2 is described in some additional detail as a specific example of a vehicle-based system.

[0040] Reference Figure 3 The memory system 2 and the corresponding sensors can be installed in the first vehicle V1. The sensors may include two image sensors (e.g., an RGB sensor and an infrared (IR) sensor), a speed sensor (e.g., an acceleration sensor), a distance sensor (e.g., a lidar or ultrasonic sensor), etc.

[0041] The sensors can collect various sensing data while the first vehicle V1 is being operated. For example, assuming the first vehicle V1 is traveling in a forward direction, two image sensors disposed in the first vehicle V1 can be used to detect obstacles appearing in a predetermined sensing area SR. Therefore, one or more of the image sensors disposed in the first vehicle V1 can detect a second vehicle V2 and a third vehicle V3 within the sensing area SR, where the second vehicle V2 is traveling in the same traffic lane as the first vehicle and the third vehicle V3 is traveling in the opposite traffic lane.

[0042] When the first vehicle V1 is traveling during the day, the RGB sensor is most effective at detecting the second vehicle V2 and the third vehicle V3. Conversely, when the first vehicle V1 is traveling at night, the IR sensor is most effective at detecting the second vehicle V2 and the third vehicle V3. Therefore, in order to most accurately and effectively detect the presence of the second vehicle V2 and the third vehicle V3 in the sensing area SR under different operating conditions, the first weight of the first sensing data provided by the RGB sensor data and the second weight of the second sensing data provided by the IR sensor can vary with different operating conditions. Thus, during the day, the first sensing data can be weighted more heavily than the second sensing data to represent its higher daytime driving utility, while at night, the second sensing data can be weighted more heavily than the first sensing data to represent its higher nighttime driving utility.

[0043] When the first vehicle V1 is traveling in a forward direction, sensing data collected by the speed sensor is more important than sensing data collected by the distance sensor (e.g., to maintain a constant speed during cruise control). However, when the first vehicle V1 is traveling in a backward direction (e.g., while stationary), sensing data collected by rearward-facing image sensors (e.g., distance sensors) is more important than sensing data collected by the speed sensor in order to prevent collisions with obstacles behind.

[0044] Therefore, the weight calculator 110 can assign different weights to various sensed data according to the vehicle's state and / or operating conditions. In an embodiment, the weight calculator 110 may include neural network circuits implemented using convolutional neural network (CNN) models, recurrent neural network (RNN) models, generative adversarial network (GAN) models, etc.

[0045] In some embodiments, the weight calculator 110 can be used to “map” sensed data using assigned weights to efficiently store and manage the weighted sensed data using one or more mapping tables included in a memory device. Figure 4 An example of a mapping table that can be used in some embodiments is shown.

[0046] Reference Figure 4 The mapping table assigns various weights to different sensing data related to vehicle operating conditions (e.g., daytime / nighttime driving and forward / backward driving) provided by different sensors (e.g., RGB sensors, IR sensors, accelerometers, lidar, and ultrasonic sensors) and different sensor types (e.g., image sensors, speed sensors, and distance sensors).

[0047] Now refer to Figure 2The memory device 200 may include a smart buffer 210 and a memory region (or “total memory region”) 230.

[0048] The smart buffer 210 can be used as an interface between the controller 100 and the memory region 230. For example, the smart buffer 210 can use its input channel to store (write or program) data received from the controller 100 in the memory region 230. In addition, the smart buffer 210 can retrieve (or read) data from the memory region 230 and use its output channel to transmit the read data to the controller 100.

[0049] In this regard, the smart buffer 210 can receive sensed data DATA and corresponding (or mapped) weights WEIGHT from the controller 100, and assign one or more channels to various data access operations based on the received sensed data and the mapped weights.

[0050] In some embodiments, the smart buffer 210 can group channels (e.g., one or more channels selected from a plurality of available channels) to logically divide the total memory region 230 into multiple memory regions (or "multiple memories") (e.g., a first memory region (or first memory) 231, a second memory region (or second memory) 232, and an nth memory region (or nth memory) 233). Here, a first channel group can be designated and assigned to the first memory region 231, a second channel group can be designated and assigned to the second memory region 232, and so on, until the nth channel group is designated and assigned to the nth memory region 233. Figure 2 In the example shown, individual channel groups are assigned to corresponding memory regions, but other embodiments of the inventive concept may assign one channel group to access more than one memory region, or may assign more than one channel group to access a single memory region.

[0051] In some embodiments, the corresponding data processing speed and / or data transfer speed associated with memory regions 231 to 233 partitioned from memory region 230 of memory device 200 can vary depending on the number and / or nature of the assigned channel groups. For example, when the number of channels grouped into a first channel group is different from the number of channels grouped into a second channel group, the data processing speed and / or data transfer speed of the first channel group may differ from that of the second channel group.

[0052] For example, the data processing speed and / or data transfer speed of a particular memory region (e.g., 231 to 233) can vary depending on the nature of the constituent memory cells of the memory region. Therefore, the first memory region 231 may include NAND flash memory cells operating as SLC and assigned to a first channel group, and the second memory region 232 may include NAND flash memory cells operating as MLC (e.g., three-level memory cell (TLC) or four-level memory cell (QLC)) and assigned to a second channel group. Therefore, the first data processing speed and the first data transfer speed for data accessed by the first channel group in the first memory region 231 can be faster than the second data processing speed and the second data transfer speed for data accessed by the second channel group in the second memory region 232. Therefore, the first memory region 231 can be designated as a high-speed memory region, and the second memory region 232 can be designated as a low-speed memory region.

[0053] It should be noted here that phase-change random access memory (PRAM), resistive random access memory (RRAM) and / or dynamic random access memory (DRAM) may be disposed alternately or additionally in the first memory region 231 (and / or the second memory region 232) together with (or in place of) SLC NAND flash memory (or MLC NAND flash cell).

[0054] Considering these exemplary configurations, the smart buffer 210 can transmit sensing data received from the controller 100 to memory region 230, and selectively store the sensing data (once weighted) in at least one high-speed memory region (e.g., 231) and / or at least one low-speed memory region (e.g., 232) according to the importance weights assigned to the sensing data. Optionally or additionally, the smart buffer 210 can dynamically group and assign channels based on data characteristics such as data size, data importance, etc. In this way, sensing data can be processed and transmitted efficiently, and memory device resources can be managed effectively.

[0055] The respective sizes of memory regions (e.g., 231 to 233) can be changed (or remain the same) and can be dynamically changed using controller 100 and / or smart buffer 210. For example, first memory region 231 may include memory cells storing N bits of data, and second memory region 232 may include memory cells storing M bits of data, where “N” and “M” are positive integers (i.e., natural numbers greater than 0) and N is less than M. In some embodiments, consecutively specified memory regions (e.g., the nth memory region 233) may include memory cells storing M+1 bits of data, M+2 bits of data, etc.

[0056] Figure 5 , Figure 6A and Figure 6B This is a corresponding block diagram illustrating a comparative example of a memory device according to an embodiment of the inventive concept.

[0057] Reference Figure 5 The memory device 300 includes a smart buffer 310 and a memory region 330, wherein the smart buffer 310 includes a priority setting unit 311, a channel controller 313, and multiple interfaces 315 and 317.

[0058] The priority setting unit 311 can be used to assign (or set) a priority for the sensed data based on previously assigned weights determined by the controller. For example, the priority setting unit 311 can compare the weights of the sensed data with one or more priority thresholds and classify the sensed data into first-priority sensed data, second-priority sensed data, etc., based on the comparison. Here, taking into account the memory system capacity (e.g., the size of memory region 330) and capabilities, one or more priority thresholds can be determined with respect to the amount of sensed data, the size of the sensed data, the number of activated sensors, etc.

[0059] exist Figure 5In the illustrated example, channel controller 313 can be used to group and assign channels among multiple channels CH1 to CH4 to multiple memory regions (or "multiple memories") 331 to 336 based on the size of the sensed data. When the size of the sensed data classified as first priority sensed data is less than 1 gigabyte (GB), channel controller 313 can assign the first channel CH1 to the first memory 331. Additionally, when the size of the sensed data classified as second priority sensed data is at least 3 gigabytes (GB) but less than 4 gigabytes (GB), channel controller 313 can assign the second channel CH2, the third channel CH3, and the fourth channel CH4 to the fourth memory 334, the fifth memory 335, and the sixth memory 336, respectively. In this example configuration, the first channel CH1 can be understood as the first channel group, and the second channel CH2, the third channel CH3, and the fourth channel CH4 can be understood as the second channel group.

[0060] The first memory region 331, the fourth memory region 334, the fifth memory region 335, and the sixth memory region 336, which are assigned to the aforementioned channels CH1 to CH4, can be implemented using different memory chips, a portion of a single memory chip, or a portion of multiple memory chips. The corresponding memory regions 331 to 336 can be divided according to different address ranges, different physical locations, different memory chips, etc.

[0061] and Figure 5 Consistent with the example shown, channel controller 313 can allocate (or group) and assign channels CH1 to CH4 based on one or more priorities set by priority setting unit 311. For example, channel controller 313 can allocate and assign the first channel CH1 to the first memory region 331 via the first interface 315 to process first priority sensing data using the first channel group G1. Channel controller 313 can also allocate and assign the second channel CH2, the third channel CH3, and the fourth channel CH4 to the fourth memory region 334, the fifth memory region 335, and the sixth memory region 336 respectively via the second interface 317 to process second priority sensing data using the second channel group G2.

[0062] The foregoing embodiments are examples of how many channels can be dynamically allocated, and many groups of channels can be dynamically assigned by the channel controller 313 based on one or more sensing data characteristics (e.g., quantity, size, and / or weight).

[0063] Reference Figure 6A The memory device 300a shown, for example, when the amount of second priority sensing data in the sensing data received from the controller is relative to the amount of sensing data involved... Figure 5As the described example increases, channel controller 313 can also allocate the fifth channel CH5 to the second channel group G2 and assign the fifth channel CH5 to the third memory 333. In other words, the second channel group G2 can be dynamically expanded to access additional memory regions (e.g., the third memory 333) to accommodate the increased amount of second-priority sensed data.

[0064] Reference Figure 6B The memory device 300b shown, for example, when the amount of first priority sensing data in the sensing data received from the controller is relative to the amount of sensing data involved... Figure 5 As the described example increases, channel controller 313 can also allocate a fifth channel CH5 to the first channel group G1 and assign the fifth channel CH5 to the second memory 332. In other words, the first channel group G1 can be dynamically expanded to access additional memory areas (e.g., the second memory 332) to accommodate the increased amount of first priority sense data.

[0065] Of course, about Figure 5 , Figure 6A and Figure 6B The comparative examples presented are merely illustrative. The number of sensed data categories, sensed data priorities, sensed data thresholds, smart buffer interfaces, memory regions, channels, and channel groups can vary with the design. Furthermore, channel allocation, channel group assignment, and interface (e.g., interfaces 315 and 317) interconnects can be dynamically changed based on requirements and memory system resources.

[0066] However, one or more channel controllers (such as channel controller 313) can be used to control the overall exchange of data across multiple memories (e.g., 331 to 336) using one of multiple interfaces (e.g., 315 and 317). Here, each of interfaces 315 and 317 may include at least one switching element. In addition, each of interfaces 315 and 317 may satisfy at least one of a variety of interface protocols, such as Universal Serial Bus (USB), Small Computer System Interface (SCSI), High Speed ​​Peripheral Component Interconnect (PCIe), Mobile PCIe (M-PCIe), Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), Serial Attached SCSI (SAS), Integrated Drive Electronics (IDE), Universal Flash Memory (UFS), etc.

[0067] Figure 5 , Figure 6A and Figure 6BThe memory region 330 includes a plurality of memories 331 to 336, and channels CH1 to CH4 allocated and assigned among the plurality of memories 331 to 336. In some embodiments, the plurality of memories 331 to 336 may include one or more memory regions designated for storing one or more types of sense data (e.g., sense data with a specific priority and / or classification). For example, the plurality of memories 331 to 336 may include a first memory region designated for storing only first-priority sense data, and a second memory region designated for storing nth sense data with a lower nth priority. Here, the first memory region may include high-speed memory cells such as SLC NAND flash memory cells, PRAM cells, RRAM cells, and / or DRAM cells, while the nth memory region may include low-speed memory cells such as MLC NAND flash memory cells.

[0068] Figure 7 This is a block diagram illustrating one possible configuration of a memory 400 according to an embodiment of the inventive concept.

[0069] Reference Figure 7 The memory 400 includes peripheral circuitry 410 and memory cell region 430.

[0070] Depending on the type of memory cell included in memory cell region 430, peripheral circuitry 410 may include various circuit elements. For example, when memory cell region 430 includes dynamic random access memory (DRAM), peripheral circuitry 410 may include command / address buffers, command decoders, data buffers, data input / output pins, row decoders, column decoders, etc.

[0071] The command / address buffer can store various commands and address signals received from the controller. Commands can include write commands, read commands, precharge commands, refresh commands, etc. Address signals can include bank addresses, row addresses, column addresses, etc.

[0072] The command decoder can receive commands from the command / address buffer and decode the received commands. The command decoder can then control the row and column decoders based on the decoded commands. For example, the command decoder can control the row decoder based on a precharge command or a flush command. Similarly, the command decoder can control the column decoder based on a write command or a read command.

[0073] The data buffer can receive written data via data input / output pins and output data stored in memory cell area 430 via data input / output pins. In other words, memory 400 can receive or output data via data input / output pins connected to channel CH.

[0074] The number of data input / output pins connected to each channel group can vary depending on the size of the memory included in each channel group. For example, the number of data input / output pins connected to a first channel group that includes high-speed, low-capacity memory can be greater than the number of data input / output pins connected to a second channel group that includes low-speed, high-capacity memory.

[0075] The line decoder can select word lines based on the line control signals received from the command decoder and the line address received from the command / address buffer.

[0076] The column decoder can select column lines based on the column control signals received from the command decoder and the column addresses received from the command / address buffer.

[0077] The memory 400 can store data in the memory cell region 430 corresponding to the selected word line and the selected column line, or read data from the memory cell region 430.

[0078] Memory cell region 430 may include multiple memory cells. According to embodiments, different channel groups can be allocated to memory 400 based on the type of memory cells included in memory cell region 430. For example, when memory cell region 430 includes multiple MTJ elements, PRAM elements, and / or RRAM elements, a first channel group for storing first priority sensing data can be allocated to memory 400. Additionally, when memory cell region 430 includes MLC NAND flash memory, a second channel group for storing second priority sensing data can be allocated to memory 400.

[0079] Figure 8 , Figure 9A and Figure 9B This is a diagram illustrating certain example structures of memory cells that may be included in a memory device according to an embodiment of the inventive concept.

[0080] Reference Figure 8 The memory cell region 500 may include multiple memory cells MC disposed in the region where multiple word lines WL0 to WLN and multiple bit lines BL0 to BLM intersect. Each memory cell MC may include a variable resistor VAR and a cell transistor CT.

[0081] When multiple memory cells MC are MTJ elements, the variable resistor VAR may include a pinning layer 510, a blocking layer 520, and a free layer 530.

[0082] The magnetization direction of the pinned layer 510 can be fixed, and the magnetization direction of the free layer 530 can be parallel to or antiparallel to the magnetization direction of the pinned layer 510, depending on the data stored in each memory cell MC. For example, when the data stored in each memory cell MC is "0", the magnetization direction of the free layer 530 can be the same as that of the pinned layer 510. When the data stored in each memory cell MC is "1", the magnetization direction of the free layer 530 can be opposite to that of the pinned layer 510. The resistance value of each memory cell MC can vary depending on the magnetization direction of the free layer 530.

[0083] Each memory cell MC may also include an antiferromagnetic layer that fixes the magnetization direction of the pinned layer 510.

[0084] The gate of a cell transistor CT can be connected to word lines WL0 to WLN. Additionally, one electrode (e.g., the drain of the cell transistor CT) can be connected to bit lines BL0 to BLM through each memory cell MC, and another electrode (e.g., the source of the cell transistor CT) can be connected to source line SL. The source line SL connected to the cell transistor CT can be different for each memory cell MC. Alternatively, the source line SL connected to the cell transistor CT can be shared in one or more memory cells MC.

[0085] exist Figure 8 In this context, when the variable resistors (VARs) of multiple memory cells (MCs) are replaced with phase change materials such as Ge-Sb-Te (GST), the multiple memory cells (MCs) can be phase change random access memory (PRAM) elements. Alternatively, when the variable resistors (VARs) of multiple memory cells (MCs) are replaced with resistive materials such as transition metal oxides, the multiple memory cells (MCs) can be resistive random access memory (RRAM) elements.

[0086] exist Figure 9A and Figure 9B The diagram illustrates alternative structures for memory cells that may be included in a memory device according to an embodiment of the inventive concept.

[0087] Reference Figure 9A The memory cell MC included in the memory cell region can be disposed between a word line WL extending along a first direction (DIR1) and a bit line BL extending along a second direction (DIR2) perpendicular to the first direction (DIR1).

[0088] The memory cell MC may include a first electrode 610 connected to the word line WL, a second electrode 620 connected to the bit line BL, and a third electrode 630 disposed between the first electrode 610 and the second electrode 620. Additionally, the memory cell MC may include a storage element layer 640 disposed between the first electrode 610 and the third electrode 630, and a selective element layer 650 disposed between the third electrode 630 and the second electrode 620.

[0089] The storage element layer 640 may include a GST material in which germanium (Ge), antimony (Sb), and tellurium (Te) are combined. The storage element layer 640 can store data based on a difference in threshold voltage or resistance. For example, the storage element layer 640 may have low resistance and low threshold voltage in a crystalline state, and high resistance and high threshold voltage in an amorphous state, and such characteristics can be used to store data.

[0090] The selective element layer 650 may be an element for selecting memory cells MC and may include a chalcogenide material in which germanium (Ge), selenium (Se) and tellurium (Te) are combined.

[0091] Reference Figure 9B The memory cell region may include a first memory cell MC1 disposed between a first word line WL1 extending along a first direction (DIR1) and a bit line BL extending along a second direction (DIR2) perpendicular to the first direction (DIR1). Additionally, the memory cell region may include a second memory cell MC2 disposed between the bit line BL and the second word line WL2, the second memory cell MC2 extending along a third direction (DIR3) perpendicular to both the first direction (DIR1) and the second direction (DIR2) and spaced apart from the first word line WL1.

[0092] Each of the first memory unit MC1 and the second memory unit MC2 may have the same characteristics as described above. Figure 9AThe described memory cell MC has the same structure. For example, the first memory cell MC1 may include a first electrode 710 to a third electrode 730, a storage element layer 740 disposed between the first electrode 710 and the third electrode 730, and a selective element layer 750 disposed between the third electrode 730 and the second electrode 720. The second memory cell MC2 may include a first electrode 760 to a third electrode 780, a storage element layer 790 disposed between the first electrode 760 and the third electrode 780, and a selective element layer 795 disposed between the third electrode 780 and the second electrode 770. The storage element layer 740 of the first memory cell MC1 and the storage element layer 790 of the second memory cell MC2 may include GST material. Furthermore, the selective element layer 750 of the first memory cell MC1 and the selective element layer 795 of the second memory cell MC2 may include chalcogenide materials.

[0093] Figure 10A and Figure 10B These are perspective views showing possible layouts of a memory device according to embodiments of the inventive concept.

[0094] Reference Figure 10A The memory device 800a can be implemented as a memory package. The memory device 800a may include a package substrate SUB and a smart buffer 810 mounted on the package substrate SUB and multiple memories (or "multiple memory regions") 831 to 836.

[0095] The package substrate SUB can provide an input / output path between the controller and the memory device 800a. The package substrate SUB can include a printed circuit board, flexible circuit board, ceramic plate, or interposer. When the package substrate SUB can be an interposer, it can be implemented using a silicon wafer.

[0096] Multiple traces can be formed within the package substrate (SUB). Multiple traces can provide data paths for multiple channels.

[0097] Multiple memory modules 831 to 836 can be formed on different memory dies (or semiconductor chips) and can be stacked vertically on a package substrate (SUB). For example... Figure 10AAs shown, each of the memories 831 to 836 may be included in a different memory chip, but this is merely illustrative. Embodiments of the inventive concept are not limited thereto. For example, the first memory 831 and the second memory 832 may be included in a single memory chip. In other words, after dividing a plurality of memory cells included in a single memory chip into a first region and a second region with different address ranges, the first region and the second region may be configured as the first memory 831 and the second memory 832. In this case, the first memory 831 and the second memory 832 may be included in the same memory die so that they are arranged at the same level on the package substrate (SUB).

[0098] Each of the memories 831 to 836 may include peripheral circuitry 856 and a memory cell region 876. The memory cell region 876 may include a plurality of memory cells, and the peripheral circuitry 856 may store sensed data input from the smart buffer 810 in the plurality of memory cells, or may output sensed data read from the plurality of memory cells to the smart buffer 810.

[0099] Channels can be grouped according to the priority of the sensed data to be stored in memory device 800a, and can be assigned to one or more of the multiple memories 831 to 836. That is, the channel group assigned to the multiple memories 831 to 836 can include at least one channel based on the priority of the data. For example, according to weights calculated by the controller, the sensed data to be stored in memory device 800a can be classified into first priority sensed data and second priority sensed data. The smart buffer 810 can allocate a first channel group G1 to a first memory 831 to store first priority data, and can allocate a second channel group G2 to a fourth memory 834 to a sixth memory 836 to store second priority data.

[0100] Memory 831 and 834 to 836 included in each of channel groups G1 and G2 can be connected to smart buffer 810 via leads. For example, the first memory 831 included in the first channel group G1 can be connected to smart buffer 810 via a first lead. Additionally, the fourth memory 834 to the sixth memory 846 included in the second channel group G2 can be connected to smart buffer 810 via a second lead. As the number of memories connected to the leads increases, the resulting data processing load increases. Therefore, the data processing speed and data transfer speed decrease. For example, the time required to store and retrieve data in the fourth memory 834 to the sixth memory 836 connected to the second lead will be longer than the time required to store and retrieve data in the first memory 831 connected to the first lead. This result can increase as the number of memories included in each channel group increases. Therefore, the smart buffer 810 according to the embodiment of the inventive concept can compactly set the size of the channel group assigned to the memory region storing the sensing data with relatively high importance (or weight), and can sparsely set the size of the channel group assigned to the memory region storing the sensing data with relatively low importance, so as to provide a balanced difference in data transmission speed and thus process the overall data more efficiently.

[0101] Multiple memories 831 to 836 can be distributed on the package substrate SUB. For example, see reference... Figure 10B The memory device 800b shown in the figure has a first memory 831 that can be separately disposed on the package substrate SUB from the second memory 832 to the sixth memory 836, and the first memory 831 may include peripheral circuitry 851 and memory cell region 871. Similarly, the second memory 832 to the sixth memory 836 can also be separately disposed on the package substrate SUB.

[0102] Figure 11A and Figure 11B This is a perspective view showing a possible structure of a memory device according to an embodiment of the inventive concept.

[0103] Reference Figure 11A The memory device 900a can be implemented as a memory package. The memory device 900a may include a package substrate SUB and a smart buffer 910 and multiple memories (or "multiple memory regions") 931 to 936 mounted on the package substrate SUB.

[0104] The package substrate SUB can provide an input / output path between the controller and the memory device 900a. Additionally, wiring for multiple channels can be formed within the package substrate SUB.

[0105] The smart buffer 910 can allocate at least one channel to multiple memories 931 to 936 and can provide interface functions for controlling data input / output.

[0106] The smart buffer 910 can set priorities based on the weights of sensing data collected from multiple sensors, and can allocate at least one channel to multiple memories 931 to 936 according to the priorities to control data input / output operations. In an embodiment, the smart buffer 910 can designate sensing data with a weight higher than a first threshold as first priority data, and can allocate a high-speed memory region for the first priority sensing data to provide higher-speed data processing. Additionally, the smart buffer 910 can set sensing data with a weight lower than the first threshold as second priority sensing data, and can provide a low-speed, high-capacity memory region for the second priority sensing data to control data processing at a slower speed.

[0107] In this embodiment, the high-speed memory region and the low-speed high-capacity memory region can be divided according to the number of channels allocated to each region. For example, the number of channels allocated to the high-speed memory region can be smaller than the number of channels allocated to the low-speed high-capacity memory region.

[0108] In this embodiment, the high-speed memory region and the low-speed high-capacity memory region can be divided according to the type of memory cells included in each region. For example, the high-speed memory region may include at least one of phase-change random access memory (PRAM), resistive random access memory (RRAM), dynamic random access memory (DRAM), and SLC NAND flash memory. Additionally, the low-speed high-capacity memory region may include at least one of MLC NAND flash memory, TLC NAND flash memory, and QLC NAND flash memory.

[0109] In this embodiment, the high-speed memory region and the low-speed high-capacity memory region can be divided according to the number of data input / output pins included in each region. For example, the number of data input / output pins included in the high-speed memory region can be greater than the number of data input / output pins included in the low-speed high-capacity memory region.

[0110] The smart buffer 910 can prioritize the sensed data to be stored in the multiple memories 931 to 936 based on its importance. For example, the smart buffer 910 can classify the sensed data to be stored in the multiple memories 931 to 936 into first priority sensed data or second priority sensed data. The smart buffer 910 can allocate a first channel group G1 to a first memory 931 to store first priority sensed data, and allocate a second channel group G2 to a fourth memory 934 to a sixth memory 936 to store second priority sensed data.

[0111] The buffer die (BD) can be positioned between multiple memories (931 to 936) and the package substrate (SUB). Peripheral circuitry for driving the multiple memories (931 to 936) can be located within the buffer die (BD).

[0112] Multiple memories 931 to 936 may include memory cell regions (CELLs) for storing data. Additionally, the multiple memories 931 to 936 may include multiple through-silicon vias (TSVs) passing through multiple dies, and the multiple memories 931 to 936 may be interconnected via the multiple TSVs. The multiple TSVs may be configured to correspond to channels allocated to the multiple memories 931 to 936. For example, when a total of four channels, each with 64 bits, are allocated to the multiple memories 931 to 936, the multiple TSVs may include a total of 256 bits of configuration for data input / output.

[0113] Multiple memories 931 to 936 can be distributed on the package substrate SUB. For example, see reference... Figure 11B The memory device 900b shown in the figure has a first memory 931 that can be disposed separately from the second memory 932 to the sixth memory 936 on the package substrate SUB, and the first memory 931 may include peripheral circuitry 951 and memory cell regions 971. Similarly, the second memory 932 to the sixth memory 936 can also be divided and distributed in a predetermined number on the package substrate SUB.

[0114] In the following text, reference will be made to Figure 12 , Figure 13A and Figure 13B A method of operating a memory device according to an embodiment of the inventive concept is described with some additional details.

[0115] Figure 12 This is a flowchart illustrating a method of operating a memory device according to an embodiment of the inventive concept.

[0116] Reference Figure 12The controller 1000 can receive sensing data collected by one or more sensors and calculate weights for the received sensing data (S10). The weights can be values ​​representing the relative importance of the sensing data and can vary depending on the operating environment of the system or host (e.g., a vehicle) including the memory system. Here, the controller 1000 can execute neural network circuitry on data collected from multiple sensors to calculate the weights of the data. The neural network circuitry can include CNN models, RNN models, GAN models, etc. In an embodiment, the controller 1000 can use a mapping table to store and manage the sensing data and corresponding weights.

[0117] Then, the controller 1000 can transmit the sensing data and the corresponding weights to the smart buffer 1110 of the memory device 1100 (S20).

[0118] The smart buffer 1110 can use the sensing data and weights received from the controller 1000 to determine (or set) the priority for the sensing data (S30). For example, when the sensing data is greater than a first threshold, the smart buffer 1110 can determine that the sensing data is relatively high priority sensing data and can designate it as first priority sensing data. However, when the sensing data is less than or equal to the first threshold, the smart buffer 1110 can determine that the sensing data is relatively low priority sensing data and can designate it as second priority sensing data.

[0119] The smart buffer 1110 can also assign one or more channels from a plurality of channels into one or more channel groups, and specify the channel groups in memories 1131 to 1134 to store first priority sensing data and second priority sensing data (S30). For example, the smart buffer 1110 can assign the first channel of the first channel group to the first memory 1131 to process the first priority sensing data. The smart buffer 1110 can also assign the second, third, and fourth channels to the second channel group, and assign these channels to the second memory 1132, the third memory 1133, and the fourth memory 1134 respectively to process the second priority sensing data.

[0120] The smart buffer 1110 can use a first channel of the first channel group to send first priority sensing data to the first memory 1131 (S40). In this case, the smart buffer 1110 can use a direct transmission method (e.g., instead of existing time-division transmission methods, channel interleaving methods, etc.) to transmit the first priority sensing data to improve data transmission speed. The first priority sensing data transmitted from the smart buffer 1110 can be stored in the memory cells of the first memory 1131 (S50). In some embodiments, the memory cells of the first memory 1131 may include next-generation memory elements such as MTJ elements, PRAM elements, RRAM elements, etc. Optionally or additionally, the memory cells included in the first memory region 1131 may include DRAM elements, SLC NAND flash memory elements, etc.

[0121] The smart buffer 1110 can transmit second-priority sensing data to the second memory 1132, the third memory 1133, and the fourth memory 1134 respectively via the second, third, and fourth channels of the second channel group (S60). In this case, the smart buffer 1110 can transmit the second-priority sensing data in parallel using a time-division transmission method, a channel interleaving method, or the like. The second-priority sensing data transmitted from the smart buffer 1110 can be stored in memory cells included in the second memory 1132, the third memory 1133, and the fourth memory 1134 (S70). In some embodiments, the memory cells included in the second memory 1132, the third memory 1133, and the fourth memory 1134 may include MLCNAND flash memory elements.

[0122] Similar to Figure 5 , Figure 6A and Figure 6B , Figure 13A and Figure 13B This is a corresponding block diagram illustrating a comparative example of a memory device according to an embodiment of the inventive concept.

[0123] Reference Figure 13A The memory device 1200a may include a smart buffer 1210 and a memory region 1230, wherein the smart buffer 1210 includes a priority setting unit 1211, a channel controller 1213, and multiple interfaces 1215 and 1217.

[0124] The priority setting unit 1211 can use the sensing data received from the controller and the corresponding weights mapped to the sensing data to set a priority for the sensing data. The priority set by the priority setting unit 1211 for the sensing data can indicate the importance of the sensing data, and can also indicate the memory area in which the sensing data will be stored using the assigned channel allocated to the channel group.

[0125] In other words, considering the given priority of the sensed data, the channel controller 1213 can allocate at least one channel to a channel group and assign the resulting channel group to the memory region 1230. Figure 13A In this context, memory region 1230 includes first memory 1231 to sixth memory 1236. For example, channel controller 1213 can allocate first channel CH1 to first channel group G1 and assign the first channel group to first memory 1231 to store first priority sensing data. Additionally, channel controller 1213 can allocate second channel CH2, third channel CH3, and fourth channel CH4 to second channel group G2 and assign second channel CH2, third channel CH3, and fourth channel CH4 to fourth memory 1234, fifth memory 1235, and sixth memory 1236 respectively to store second priority sensing data.

[0126] The first channel CH1 can be connected to the first memory 1231, and the second channel CH2, the third channel CH3, and the fourth channel CH4 can be connected to the fourth memory 1234, the fifth memory 1235, and the sixth memory 1236, respectively. Here, the channel controller 1213 can control whether the first interface 1215 and / or the second interface 1217 are activated to send first priority sensing data and / or second priority sensing data at any given time.

[0127] For example, the smart buffer 1210 can activate the first interface 1215 and disable the second interface 1217 to send first priority sensing data to the first memory 1231 via the first channel CH1. In an embodiment, the smart buffer 1210 can serially send the first priority sensing data to the first memory 1231 to improve data transmission speed.

[0128] In comparison and reference Figure 13B The memory device 1200b shown herein includes a smart buffer 1210 that can disable a first interface 1215 and activate a second interface 1217 to transmit second-priority sensing data to a fourth memory 1234, a fifth memory 1235, and a sixth memory 1236 via a second channel CH2, a third channel CH3, and a fourth channel CH4. In embodiments, the smart buffer 1210 may use a time-division multiplexing method or a channel interleaving method to transmit the second-priority sensing data to the fourth memory 1234, the fifth memory 1235, and the sixth memory 1236.

[0129] Figure 13A and Figure 13BThe embodiment shown depicts the priority setting unit 1211 and the channel controller 1213 as separate system components; however, this is not necessary, and in other embodiments of the inventive concept, these components may be integrated into a single system component. Alternatively or additionally, the priority setting unit 1211 may be used to allocate channels within a channel group, rather than the channel controller 1213 performing this function. In this case, the priority setting unit 1211 may use sensed data and corresponding weights to set the priority of sensed data, and may allocate and / or assign at least one channel to process the weighted sensed data in memory region 1230 based on the priority of the sensed data.

[0130] Similar to Figure 5 , Figure 6A , Figure 6B , Figure 13A and Figure 13B , Figure 14 This is a block diagram illustrating a memory device 1300 according to an embodiment of the inventive concept.

[0131] Reference Figure 14 The memory device 1300 may include a smart buffer 1310 and a memory region (or “total memory region”) 1330.

[0132] The smart buffer 1310 may include a priority setting unit 1311, a channel controller 1313, and multiple interfaces 1315, 1317, and 1319. In addition, the total memory area 1330 may be divided into multiple memory areas (or "multiple memories") 1331 to 1336, each including peripheral circuitry and memory cell areas.

[0133] Here, the channel controller 1313 can assign one or more channels to one or more channel groups, and assign channel groups to process weighted sensing data based on the priority of the sensing data set (or determined) by the priority setting unit 1311.

[0134] For example, when the weight of the sensing data sent from the controller is greater than or equal to a priority threshold (e.g., 1.2), the priority setting unit 1311 can determine that the sensing data is first-priority sensing data. Furthermore, when the weight of the sensing data is greater than or equal to 0.8 but less than 1.2, the priority setting unit 1311 can determine that the sensing data is second-priority sensing data, and when the weight of the sensing data is less than 0.8, the priority setting unit 1311 can determine that the sensing data is third-priority sensing data. Here, it is assumed that the first-priority sensing data has high importance, the second-priority sensing data has intermediate importance, and the third-priority sensing data has low importance.

[0135] Channel controller 1313 can assign a first channel CH1 to a first channel group G1 via a first interface 1315, and assign the first channel group G1 to process first priority sensing data associated with the first memory 1331. Channel controller 1313 can assign a second channel CH2 and a third channel CH3 to a second channel group G2 via a second interface 1317, and assign the second channel group G2 to process second priority sensing data associated with the second memory 1332 and the third memory 1333. In an embodiment, the second channel CH2 can be assigned to the second memory 1332, and the third channel CH3 can be assigned to the third memory 1333. Channel controller 1313 can assign a fourth channel CH4, a fifth channel CH5, and a sixth channel CH6 to a third channel group G3, and assign the third channel group G3 to process third priority sensing data associated with the fourth memory 1334, the fifth memory 1135, and the sixth memory 1336 via a third interface 1319.

[0136] Channel controller 1313 can be used to control the activation / deactivation of first interface 1315, second interface 1315, and third interface 1319. For example, channel controller 1313 can activate first interface 1315 to send first priority sense data to first memory region 1331, and disable second interface 1317 and third interface 1319 to maximize the data transfer rate for the first priority sense data. When the transmission of the first priority sense data is complete, channel controller 1313 can sequentially activate second interface 1317 and third interface 1319 to send second priority sense data and subsequently third priority sense data to memory region 1330.

[0137] Here, the transmission of the first priority sensing data can be accomplished using a direct transmission method (e.g., a serial data transmission method), while the transmission of the second and third priority sensing data can be accomplished using a parallel transmission method such as a time-division method or a channel interleaving method. Therefore, in some embodiments, the channel controller 1313 can simultaneously activate the second interface 1317 and the third interface 1319 to simultaneously send the second priority sensing data and the third priority sensing data to the assigned memory region.

[0138] Similar to Figure 10A , Figure 10B , Figure 11A and Figure 11B , Figure 15A and Figure 15B These are perspective views showing possible layouts of memory devices according to embodiments of the inventive concept.

[0139] Reference Figure 15AThe memory device 1400a according to an embodiment of the inventive concept can be implemented as at least one memory package. The memory device 1400a may include a package substrate SUB, a smart buffer 1410 mounted on the package substrate SUB, and a plurality of memories 1431 to 1436.

[0140] Each of the memories 1431 to 1436 may include peripheral circuitry 1456 and a memory cell region 1476. The memory cell region 1476 may include multiple memory cells, and the peripheral circuitry 1456 may store data input from the smart buffer 1410 in the multiple memory cells, or may output data read from the multiple memory cells.

[0141] Figure 14 As an extended working example, the smart buffer 1410 can be used to classify data into first-priority sensed data, second-priority sensed data, and third-priority sensed data based on data priority. Additionally, the smart buffer 1410 can assign different first-channel groups, second-channel groups, and third-channel groups corresponding to the first-priority sensed data, second-priority sensed data, and third-priority sensed data to memories 1431 to 1436. Therefore, in this illustrated example, a particular memory (e.g., 1431) can be considered as a particular memory region (e.g., ...). Figure 14 The first memory region 1331).

[0142] Therefore, memories 1431 to 1436 can be assigned to at least one channel in at least one channel group by the smart buffer 1410 using connection leads. For example, the first memory 1431 assigned to the first channel group G1 can be connected to the smart buffer 1410 via a first lead; the second memory 1432 and the third memory 1433 assigned to the second channel group G2 can be connected to the smart buffer 1410 via a second lead; and the fourth memory 1434, the fifth memory 1435, and the sixth memory 1436 assigned to the third channel group G3 can be connected to the smart buffer 1410 via a third lead.

[0143] However, here, as the number of memories connected to a particular lead increases, the corresponding data processing load increases. Therefore, the data processing speed and data transfer speed decrease. For example, the data transfer time for the fourth memory 1434, the fifth memory 1435, and the sixth memory 1436 connected to the third lead can be longer than the data transfer time for the second memory 1432 and the third memory 1433 connected to the second lead. The data transfer time for the second memory 1432 and the third memory 1433 connected to the second lead can be longer than the data transfer time for the first memory 1431 connected to the first lead.

[0144] Under these assumptions, the smart buffer 1410 can generously allocate channels to channel groups assigned to process sensing data with relatively high importance (or greater weight) (thereby increasing sensing data throughput), and can less generously allocate channels to channel groups assigned to process data with relatively low importance, taking into account different data transmission rates, desired data transmission speeds, etc.

[0145] Through with Figure 15A A comparison of the embodiments is provided. Figure 15B The memory device 1400b shown herein, the memories 1431 to 1436 can be configured to be stacked vertically and connected to the smart buffer 1410 using various through-silicon vias (TSVs) and interconnect wiring disposed in the package substrate SUB instead of interconnect leads.

[0146] Figure 16 This is a block diagram illustrating a memory system 3 according to an embodiment of the inventive concept, and it can be used with... Figure 2 The embodiments are compared.

[0147] Reference Figure 16 The memory system 3 may include a controller 1500 and a memory device 1600.

[0148] The controller 1500 may include a priority setting unit 1510 and a high bandwidth memory (HBM) mode controller 1530.

[0149] As described above, the priority setting unit 1510 can assign weights to the sensing data received from the external source and use the assigned weights to determine the priority of the sensing data. That is, when the weight of the data is greater than or equal to the first threshold, the priority setting unit 1510 can determine that the sensing data is the first priority sensing data, and when the weight of the data is less than the first threshold, the priority setting unit 1510 can determine that the sensing data is the second priority sensing data.

[0150] The priority of the data set by the priority setting unit 1510 can be categorized in various ways, taking into account the requirements of the merging host device, memory system, memory device, etc. As mentioned above, the priority of certain weighted sensing data can be determined by using different thresholds through the priority setting unit 1510.

[0151] Additionally, the priority setting unit 1510 and / or the HBM mode controller 1530 can determine that certain sensed data having a weight greater than or equal to a highest threshold (e.g., a fourth threshold (e.g., 1.4) – an extension of the previously described use of the first, second, and third thresholds) is either highest priority sensed data or HBM sensed data. After determining that the sensed data is highest priority sensed data, the High Bandwidth Memory (HBM) mode controller can cause the memory device 1600 to operate according to the HBM mode.

[0152] When the HBM mode controller 1530 decides to operate in HBM mode, an HBM mode enable signal (HBMon) and its corresponding sensing data can be transmitted to the memory device 1600. In this case, the memory device 1600 can store the HBM sensing data in the HBM region in response to the HBMon signal. In an embodiment, the HBM region can be preset in the memory region 1630 of the memory device 1600, and one or more HBM channels can be pre-assigned to HBM channel groups to process HBM sensing data associated with the HBM region. When operating in HBM mode, the memory device 1600 can use the pre-assigned HBM channel groups (including at least one HBM channel) to transmit HBM sensing data to the HBM region.

[0153] Memory device 1600 may include a smart buffer 1610 and a memory region 1630, the memory region 1630 including first memory 1631 to nth memory 1633, wherein the smart buffer 1610 and the memory region 1630 are referenced to Figure 17 and Figure 18 describe.

[0154] Figure 17 and Figure 18 This is a block diagram illustrating a comparative example of a memory device according to an embodiment of the inventive concept.

[0155] Reference Figure 17 The memory device 1700a according to an embodiment of the inventive concept may include a smart buffer 1710 and a total memory region 1730.

[0156] The smart buffer 1710 may include a channel controller 1711 and multiple interfaces 1713 and 1715.

[0157] Channel controller 1711 can allocate and / or assign at least one channel to the total memory region 1730 according to the priority of the sensing data received from the controller. For example, channel controller 1711 can allocate the first channel CH1 (as a first channel group G1) to the first memory 1731 for processing first priority sensing data. In addition, channel controller 1711 can allocate and assign the second channel CH2, the third channel CH3, and the fourth channel CH4 (as a second channel group G2) to the fourth memory 1734, the fifth memory 1735, and the sixth memory 1736 for processing second priority sensing data, respectively.

[0158] In an embodiment, the first channel group G1 can be configured to operate with respect to the first memory 1731, which is configured to operate as a high-bandwidth memory, while the second channel group G2 can be configured to operate with respect to the fourth memory 1734, the fifth memory 1735, and the sixth memory 1736, which are configured to operate as MLC memories (e.g., low-speed, high-capacity memories).

[0159] Before HBM mode is activated, only the second channel group G2 can be activated, allowing data of relatively low importance to be transmitted to the total memory region 1730 in real time. However, after HBM mode is activated (e.g., upon receiving the HBMon signal), the first channel group G1 can be activated, allowing data of much higher importance to be transmitted to the high-bandwidth memory HBM in the total memory region 1730. In this embodiment, the size of the high-bandwidth memory HBM included in the first channel group G1 can be dynamically changed based on the capacity of the sensed data to be stored using the first channel group G1. Thus, the memory device 1700a can reduce overall power consumption by performing data processing operations using only a portion of the channels before activating HBM mode. Furthermore, after activating HBM mode, the memory device 1700a can also allocate high-speed channels to the high-bandwidth memory HBM, and can change the number of allocated high-speed channels based on changes in the capacity of highly important data, etc., to improve data processing efficiency and performance. Figure 17 The smart buffer 1710 may include one or more interfaces (e.g., a first interface 1713 and a second interface 1715).

[0160] Reference Figure 18The memory device 1700b shown may include a smart buffer 1710, comprising a first interface 1713, a second interface 1715, and a third interface 1717. In this configuration, the first interface 1713 may be connected to a first channel group G1 allocated to a first memory 1731, the second interface 1715 may be connected to a second channel group G2 allocated to a second memory 1732 and a third memory 1733, and the third interface 1717 may be connected to a third channel group G3 allocated to a fourth memory 1734 through a sixth memory 1736.

[0161] To store first-priority sensing data, channel controller 1711 can activate first interface 1713; to store second-priority sensing data, channel controller 1711 can activate second interface 1715.

[0162] Figure 19 This is a general block diagram illustrating an electronic device including a memory device according to an embodiment of the inventive concept.

[0163] according to Figure 19 The electronic device 1900 of the embodiment shown may include a sensor unit 1910, a memory device 1920, a port 1930, a processor 1940, etc. Additionally, the electronic device 1900 may also include wired / wireless communication devices, a power supply, etc. Figure 19 Among the components shown, port 1930 can be a device provided by electronic device 1900 that communicates with video cards, sound cards, memory cards, USB devices, etc. Besides a typical desktop or laptop computer, electronic device 1900 can also include concepts such as smartphones, tablet PCs, and smart wearable devices.

[0164] The sensor unit 1910 may include multiple sensors, which may include image sensors, event sensors, illuminance sensors, GPS devices, accelerometers, etc. These multiple sensors may be located within or adjacent to the electronic device 1900 to exchange data via wired or wireless communication.

[0165] Processor 1940 can execute specific operations, commands, tasks, etc. Processor 1940 can be a central processing unit (CPU), microprocessor unit (MCU), system-on-a-chip (SoC), etc., and can communicate with memory device 1920 and other units with connection port 1930 via bus 1950. Processor 1940 may include neural network circuitry to calculate predetermined weights by performing neural network operations on data collected by sensor unit 1910. In one embodiment, the neural network circuitry can be implemented as a CNN model, RNN model, or GAN model.

[0166] Memory device 1920 may be a storage medium for storing data or multimedia data required for the operation of electronic device 1900. Memory device 1920 may include memory cells based on semiconductor devices. For example, memory device 1920 may include dynamic random access memory devices (such as DRAM, synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), low power double data rate SDRAM (LPDDR SDRAM), graphics double data rate SDRAM (GDDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, etc.) or resistive random access memory devices (such as phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.).

[0167] Additionally, the memory device 1920 may include at least one of a solid-state drive (SSD), a hard disk drive (HDD), and an optical drive (ODD) as a storage unit.

[0168] In an embodiment, the memory device 1920 may include, according to the above references Figures 1 to 18 Memory devices of various embodiments described.

[0169] Figure 20 This is a conceptual diagram illustrating an application example of a memory device according to an embodiment of the inventive concept.

[0170] Reference Figure 20 The memory device 2130 according to an embodiment of the inventive concept can be included in a vehicle system.

[0171] The vehicle 2000 may include multiple sensors (e.g., sensor 2010 and sensor 2020) configured to collect various sensing data related to the state or operating conditions of the vehicle 2000 as described above.

[0172] The controller 2030 can store (e.g., in storage) various sets of sensing data collected by sensors 2010 and 2020 in a memory device 2130. In addition, the controller 2030 can use the data collected by multiple sensors 2010 and 2020 to drive multiple actuators 2050 to control the vehicle 2000.

[0173] Although the memory device 2130 is implemented in the vehicle 2000, however... Figure 20As shown, the memory device 2130 can be implemented outside the vehicle 2000 and can perform wireless communication with the controller 2030 using communication units 2040 and 2110. For example, the memory system 2100 may include the memory device 2130 and the communication unit 2110.

[0174] The memory device 2130 may include a smart buffer 2131 and a memory region 2133, and may be provided as a single memory package.

[0175] The intelligent buffer 2131 can set data priorities based on data weight (or importance), and can dynamically allocate channels to memory regions 2133 according to the set priorities. The intelligent buffer 2131 can allocate high-speed memory regions as channels for data with relatively high priority, and can allocate low-speed, high-capacity memory regions as channels for data with relatively low priority. In this way, the intelligent buffer 2131 can increase the transmission speed for data with relatively high priority and decrease the transmission speed for data with relatively low priority, thereby effectively improving data processing.

[0176] The memory device according to an embodiment of the inventive concept can access various sensing data sent from a controller and can be partitioned to store sensing data in at least one higher-speed memory region and at least one lower-speed memory region according to the relative importance of the sensing data.

[0177] Furthermore, the memory device according to embodiments of the inventive concept can dynamically allocate / assign channels based on many factors as described above.

[0178] The various advantages and effects of the inventive concept are not limited to those described above, and can be readily understood when considering the foregoing description and claims.

[0179] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A memory device, the memory device comprising: a smart buffer; and a total memory area divided into a first memory area and a second memory area, wherein the smart buffer comprises a priority setting unit configured to receive sensing data and a corresponding weight from a controller, determine a priority of the sensing data based on the weight, and classify the sensing data into one of first priority sensing data and second priority sensing data, and a lane controller configured to assign at least one lane selected from among a plurality of lanes to a first lane group, assign another at least one lane selected from among the plurality of lanes to a second lane group, assign the first lane group to process the first priority sensing data related to the first memory area, and assign the second lane group to process the second priority sensing data related to the second memory area, wherein a number of data input / output pins connected to the first lane group is greater than a number of data input / output pins connected to the second lane group.

2. The memory device of claim 1, further comprising: a first interface configured to connect the at least one lane of the first lane group to the first memory area to transmit the first priority sensing data under control of the lane controller; and a second interface configured to connect the another at least one lane of the second lane group to the second memory area to transmit the second priority sensing data under control of the lane controller.

3. The memory device of claim 2, wherein, The first interface transmits the first priority sensing data serially to the first memory area, and the second interface transmits the second priority sensing data in parallel to the second memory area.

4. The memory device of claim 1, further comprising a mapping table, wherein The mapping table maps the corresponding weight to the sensing data, and the priority setting unit classifies the sensing data as the first priority sensing data if the corresponding weight is greater than a first threshold.

5. The memory device of claim 1, wherein, The first memory area comprises at least one of phase change random access memory cells, resistive random access memory cells, and dynamic random access memory cells, and The second memory area comprises NAND flash memory cells.

6. The memory device of claim 1, wherein, The first memory area comprises memory cells storing N-bit data, and the second memory area comprises memory cells storing M-bit data, where "N" and "M" are natural numbers greater than 0, and M is greater than N.

7. The memory device of claim 1, wherein, The first memory area is implemented on a first semiconductor chip, and the second memory area is implemented on at least one second semiconductor chip different from the first semiconductor chip.

8. The memory device of claim 7, wherein, The first semiconductor chip and the at least one second semiconductor chip are vertically stacked, and The first memory area is connected to the second memory area using a plurality of through silicon vias.

9. The memory device of claim 7, wherein, The at least one second semiconductor chip comprises a fourth semiconductor chip and a third semiconductor chip, and The fourth semiconductor chip is connected to the third semiconductor chip using a plurality of through silicon vias. The first semiconductor chip is connected to a first interface of the smart buffer through a first lead, the fourth semiconductor chip is connected to a second interface of the smart buffer through a second lead, and the third semiconductor chip is connected to the second interface through the second lead.

10. The memory device of any one of claims 1-9, wherein, The channel controller assigns the at least one channel to the first channel group and assigns the further at least one channel to the second channel group based on a size of the sense data.

11. A memory device, the memory device comprising: a memory package including a smart buffer and a plurality of semiconductor chips mounted on a semiconductor substrate, wherein the smart buffer is implemented on a different semiconductor chip from the plurality of semiconductor chips, and the plurality of semiconductor chips provide a plurality of memory regions including a first memory region and a second memory region, wherein the smart buffer includes a priority setting unit configured to receive sense data and corresponding weights obtained by performing a neural network operation on the sense data, determine a priority of the sense data based on the corresponding weights, and classify the sense data into one of first priority sense data and second priority sense data based on the priority, and a channel controller configured to assign at least one channel selected from among a plurality of channels to a first channel group, assign a further at least one channel selected from among the plurality of channels to a second channel group, assign the first channel group to process the first priority sense data related to the first memory region, and assign the second channel group to process the second priority sense data related to the second memory region.

12. The memory device of claim 11, wherein, Each of the plurality of semiconductor chips provides one of the plurality of memory regions.

13. The memory device of any one of claims 11 and 12, wherein, The smart buffer further includes: a first interface configured to connect the first channel group to the first memory region and transmit the first priority sense data at a first data transfer speed; and a second interface configured to connect the second channel group to the second memory region and transmit the second priority sense data at a second data transfer speed slower than the first data transfer speed.

14. The memory device of claim 13, wherein, At least one of the plurality of semiconductor chips provides a high bandwidth memory region.

15. A memory system, the memory system comprising: a controller including a weight calculator configured to calculate corresponding weights for sense data using a neural network operation, and a high bandwidth memory mode controller configured to generate a high bandwidth memory mode on signal when the corresponding weights are greater than a predetermined threshold; and A memory device including a total memory region and an intelligent buffer, the total memory region being divided into a plurality of memory regions including a first memory region and a second memory region, the intelligent buffer including: a priority setting unit configured to receive the sense data and the corresponding weight, determine a priority of the sense data based on the corresponding weight, and classify the sense data into one of first priority sense data and second priority sense data based on the priority; and a channel controller configured to assign at least one channel selected from among a plurality of channels to a first channel group, assign another at least one channel selected from among the plurality of channels to a second channel group, assign the first channel group to process the first priority sense data related to the first memory region, and assign the second channel group to process the second priority sense data related to the second memory region, wherein the channel controller, in response to the high bandwidth memory mode enable signal, assigns at least one high bandwidth memory channel selected from among the plurality of channels to a high bandwidth memory channel group, and assigns the high bandwidth memory channel group to process high bandwidth memory sense data having a priority determined based on the corresponding weight being greater than the predetermined threshold.

16. The memory system of claim 15, wherein, The intelligent buffer, when receiving the high bandwidth memory mode enable signal from the controller, controls an amount of a high bandwidth memory memory region for processing the high bandwidth memory sense data based on a change in a size of the high bandwidth memory sense data.

17. The memory system of claim 15, wherein, The memory device includes a plurality of semiconductor chips that collectively provide the total memory region, a first semiconductor chip among the plurality of semiconductor chips provides the first memory region, and at least two semiconductor chips among the plurality of semiconductor chips other than the first semiconductor chip provide the second memory region.

18. The memory system of claim 17, wherein, The first semiconductor chip includes at least one of a phase change random access memory device, a resistive random access memory device, and a dynamic random access memory device, and The at least two semiconductor chips include at least one NAND flash memory device.

19. The memory system of claim 18, wherein, The first semiconductor chip and the at least two semiconductor chips are vertically stacked, and the first memory region is connected to the second memory region using a through silicon via.

20. The memory system according to any one of claim 17 to claim 19, wherein, Each of the first semiconductor chip and the at least two semiconductor chips is connected to the intelligent buffer using a connection lead, respectively.

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