Light emission control driving unit and display device including the same

Abstract

The present disclosure provides a light emission control driving unit and a display device including the same. The light emission control driving unit may include a plurality of stages for supplying a light emission control signal to a light emission control line. Each of the stages includes: an input circuit that controls voltages of a first node and a second node based on one of a light emission start signal and a carry signal from a previous stage and a first clock signal; a first main circuit that controls a voltage of a third node based on the voltage of the first node and a second clock signal; a second main circuit that controls the voltage of the third node based on the voltage of the second node so that the third node has a voltage with a level opposite to that of the second node; and an output circuit that controls a light emission control signal output to an output terminal based on the voltages of the second node and the third node. Therefore, the low-level output characteristic of the light emission control signal can be improved.

Description

Technical Field

[0001] The present disclosure relates to a light emission control driving unit and a display device including the same. Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has emerged. In response to this, the use of display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices is increasing.

[0003] Each pixel of the display device can emit light with a brightness corresponding to a data voltage supplied through a data line. The display device can display an image frame with a combination of pixel emissions.

[0004] In addition, the light emission period of each pixel of the display device is controlled according to a light emission control signal supplied through a light emission control line. Therefore, in the display device, a light emission control driving unit capable of supplying such a light emission control signal to each pixel is required. Summary of the Invention

[0005] An object of the present disclosure is to provide a light emission control driving unit and a display device including the same that improve output characteristics when the light emission control signal is at a low level.

[0006] One aspect of the present disclosure for achieving the above object provides a light emission control driving unit.

[0007] It may be that the light emission control driving unit includes a plurality of stages for supplying a light emission control signal to a light emission control line.

[0008] It may be that each of the multiple stages includes: an input circuit that controls the voltages of a first node and a second node based on one of a light emission start signal and a carry signal from a previous stage and a first clock signal; a first main circuit that controls the voltage of a third node based on the voltage of the first node and a second clock signal; a second main circuit that controls the voltage of the third node based on the voltage of the second node so that the third node has a voltage with a level opposite to that of the second node; an output circuit that controls a light emission control signal output to an output terminal based on the voltages of the second node and the third node; a first auxiliary circuit that controls the low-level output of the light emission control signal based on the second clock signal so that the light emission control signal is further reduced from a first low level to a second low level; and a second auxiliary circuit that controls the low-level output of the light emission control signal in a single step down form based on the voltage of the second node.

[0009] It may be that the second auxiliary circuit includes: a fourth capacitor connected between an eighth node and the output terminal; a thirteenth transistor connected between the second node and the eighth node with its gate electrode connected to a second power supply; and a fourteenth transistor connected between the output terminal and the second power supply with its gate electrode connected to the eighth node.

[0010] It may be that when a low-level voltage is applied to the second node, the fourth capacitor increases the absolute value of the voltage difference between the eighth node and the output terminal so that the light emission control signal is converted to the second low level.

[0011] It may be that between the input circuit and the output circuit, there is also included: a twelfth transistor that limits the rate of voltage drop of the second node.

[0012] It may be that the twelfth transistor is connected between the second node and a fourth node and includes a gate electrode connected to a second power supply.

[0013] It may be that the first auxiliary circuit reduces the voltage of the fourth node based on the voltage of the fourth node and the second clock signal.

[0014] It may be that the first auxiliary circuit includes: a third capacitor connected between the fourth node and a seventh node; a third transistor connected between the seventh node and a third input terminal to which the second clock signal is input, with its gate electrode connected to the fourth node; and a second transistor connected between a first power supply and the seventh node, with its gate electrode connected to the first node.

[0015] It may be that the third capacitor additionally reduces the voltage of the fourth node that transitions to a low level as the light emission start signal or the carry signal of the previous stage transitions to a low level.

[0016] It may be that the input circuit includes: a first transistor connected between a first input terminal to which one of the light emission start signal and the carry signal is input and the second node, with a gate electrode connected to a second input terminal to which the first clock signal is input; a fourth transistor connected between the first node and the second input terminal, with a gate electrode connected to the second node; and a fifth transistor connected between the first node and the second power supply.

[0017] It may be that the first main circuit includes: a sixth transistor connected between the third node and the sixth node, with a gate electrode connected to a third input terminal to which the second clock signal is input; a seventh transistor connected between the sixth node and the third input terminal, with a gate electrode connected to the first node; and a second capacitor connected between the sixth node and the first node.

[0018] It may be that the second main circuit includes: an eighth transistor connected between the first power supply and the third node, with a gate electrode connected to the second node; and a first capacitor connected between the first power supply and the third node.

[0019] It may be that the output circuit includes: a ninth transistor connected between the first power supply and the output terminal, with a gate electrode connected to the third node; and a tenth transistor connected between the output terminal and the second power supply, with a gate electrode connected to the second node.

[0020] It may be that the light emission control driving unit further includes, between the input circuit and the first main circuit: an eleventh transistor that limits the voltage drop amplitude of the first node.

[0021] It may be that the eleventh transistor has a gate electrode connected to the second power supply and is always kept in an on state.

[0022] Other aspects of the present disclosure for achieving the above object provide a display device.

[0023] It may be that the display device includes: a pixel unit including a plurality of pixels; a scan driving unit that supplies a scan signal to the pixels; a data driving unit that supplies a data signal to the pixels; a light emission control driving unit including a plurality of stages that supply a light emission control signal to the pixels; and a timing control unit that controls the driving of the scan driving unit, the data driving unit, and the light emission control driving unit.

[0024] It may be that each stage includes: an input circuit that controls the voltages of a first node and a second node based on one of a light emission start signal and a carry signal from a previous stage and a first clock signal; a first main circuit that controls the voltage of a third node based on the voltage of the first node and a second clock signal; a second main circuit that controls the voltage of the third node based on the voltage of the second node so that the third node has a voltage with a level opposite to that of the second node; an output circuit that controls a light emission control signal output to an output terminal based on the voltages of the second node and the third node; a first auxiliary circuit that controls the low-level output of the light emission control signal based on the second clock signal so that the light emission control signal is further reduced from a first low level to a second low level; and a second auxiliary circuit that controls the low-level output of the light emission control signal in a single step down form based on the voltage of the second node.

[0025] It may be that the second auxiliary circuit includes: a fourth capacitor connected between an eighth node and the output terminal; a thirteenth transistor connected between the second node and the eighth node with its gate electrode connected to a second power supply; and a fourteenth transistor connected between the output terminal and the second power supply with its gate electrode connected to the eighth node.

[0026] It may be that when a low-level voltage is applied to the second node, the fourth capacitor increases the absolute value of the voltage difference between the eighth node and the output terminal so that the light emission control signal is converted to the second low level.

[0027] It may be that the output circuit includes: a ninth transistor connected between a first power supply and the output terminal with its gate electrode connected to the third node; and a tenth transistor connected between the output terminal and a second power supply with its gate electrode connected to the second node.

[0028] It may be that the first clock signal and the second clock signal have the same period and a phase difference of more than a half period from each other.

[0029] It may be that the carry signal includes the light emission control signal from the previous stage.

[0030] (Disclosed effect)

[0031] The light emission control driving unit according to the present disclosure and a display device including the same can improve the output characteristics when the light emission control signal is reduced to a low level to a single step form, thereby preventing the generation of transient current.

[0032] In addition, by keeping the light emission control signal at a sufficiently low level, power consumption can be reduced. Description of the Drawings

[0033] Figure 1 is a diagram for explaining a display device according to an embodiment of the present disclosure.

[0034] Figure 2 Illustratively shows according to Figure 1 a circuit diagram of a pixel of the display device.

[0035] Figure 3 is a diagram for explaining a light emission control driving unit according to an embodiment of the present disclosure.

[0036] Figure 4 is according to Figure 3 a circuit diagram of a stage according to the first embodiment.

[0037] Figure 5 Shows according to Figure 4 the operation of a stage.

[0038] Figure 6 is according to Figure 3 a circuit diagram of a stage according to the second embodiment.

[0039] Figure 7 Shows according to Figure 6 the operation of a stage.

[0040] Figure 8 is according to Figure 3 a circuit diagram of a stage according to the third embodiment.

[0041] Figure 9 is according to Figure 3 a circuit diagram of a stage according to the fourth embodiment.

[0042] (Description of Reference Numerals)

[0043] VGH: First power supply VGL: Second power supply

[0044] CLK1: First clock signal CLK2: Second clock signal

[0045] 101: First input terminal 102: Second input terminal

[0046] 103: Third input terminal 104: Output terminal

[0047] 410: Input circuit 420: First main circuit

[0048] 430: Second main circuit 440: Output circuit

[0049] 450: First auxiliary circuit 460: Second auxiliary circuit Detailed Description of the Invention

[0050] Hereinafter, with reference to the accompanying drawings, a plurality of embodiments of the present disclosure will be described in detail so that those skilled in the art to which the present disclosure pertains can easily implement it. The present disclosure can be implemented in various different forms and is not limited to the embodiments described herein.

[0051] To clearly illustrate the present disclosure, parts irrelevant to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification. Therefore, the reference numerals described above can also be used in other drawings.

[0052] In addition, since the sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown for ease of explanation, the present disclosure is not necessarily limited to the illustration. In the drawings, the thickness may be exaggerated to clearly show a plurality of layers and regions.

[0053] Figure 1 is a diagram for explaining a display device according to an embodiment of the present disclosure.

[0054] Referring to Figure 1 , a display device according to an embodiment of the present disclosure may include a pixel unit 10, a scan driving unit 20, a data driving unit 30, a light emission control driving unit 40, and a timing control unit 50.

[0055] The pixel unit 10 includes: a plurality of pixels PXij, which are arranged in a matrix form by being connected to scan lines SC1 to SCn, data lines D1 to Dm, and light emission control lines E1 to En. The pixel PXij receives an input scan signal through the scan lines SC1 to SCn, receives an input data signal through the data lines D1 to Dm, and receives an input light emission control signal through the light emission control lines E1 to En. When a scan signal is supplied from the scan lines SC1 to SCn, the pixel PXij emits light with a brightness corresponding to the data signal supplied from the data lines D1 to Dm.

[0056] The scan driving unit 20 is connected to a plurality of scan lines SC1 to SCn, generates a scan signal in response to a scan driving control signal SCS of the timing control unit 50, and outputs the generated scan signal to the scan lines SC1 to SCn. The scan driving unit 20 may be composed of a plurality of stage circuits. The scan driving unit 20 may provide a scan signal having conductive level pulses in sequence in the scan lines SC1 to SCn to the pixel PXij. The scan driving unit 20 may be configured in the form of a shift register.

[0057] The data driving unit 30 is connected to a plurality of data lines D1 to Dm, generates a data signal based on the data driving control signal DCS and the image data DATA' of the timing control unit 50, and outputs the generated data signal to the data lines D1 to Dm. Whenever a scan signal is supplied, the data signal supplied to the data lines D1 to Dm is supplied to the pixel PXij selected by the scan signal. In this way, the pixel PXij can charge a voltage corresponding to the data signal.

[0058] The light emission control driving unit 40 is connected to a plurality of light emission control lines E1 to En, generates a light emission control signal in response to the light emission driving control signal ECS of the timing control unit 50, and outputs the generated light emission control signal to the light emission control lines E1 to En. The light emission control driving unit 40 may be composed of a plurality of stage circuits, and supplies the light emission control signal to the light emission control lines E1 to En to control the light emission period of the pixel PXij.

[0059] The timing control unit 50 receives the input image data DATA and synchronization signals Hsync, Vsync, and clock signal CLK for controlling the display thereof. The timing control unit 50 performs image processing on the input image data DATA, thereby generating image data DATA' corrected to be suitable for image display of the pixel unit 10 and outputting it to the data driving unit 30. In addition, the timing control unit 50 may generate driving control signals SCS, DCS, and ECS for controlling the driving of the scan driving unit 20, the data driving unit 30, and the light emission control driving unit 40 based on the synchronization signals Hsync, Vsync, and clock signal CLK. Specifically, the timing control unit 50 may generate a scan driving control signal SCS and supply it to the scan driving unit 20, generate a data driving control signal DCS and supply it to the data driving unit 30, and generate a light emission driving control signal ECS and supply it to the light emission control driving unit 40.

[0060] Figure 2 is illustratively shown according to Figure 1 of the pixel of the display device.

[0061] In Figure 2 for ease of explanation, a pixel PXij located on the i-th horizontal line and connected to the j-th data line is shown.

[0062] Referring to Figure 2 the pixel PXij may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a storage capacitor Cst, and a light emitting element EL.

[0063] In one embodiment, the first scan signal GWi may be a scan signal supplied to a first scan line connected to the ith horizontal line, the second scan signal GCi may be a scan signal supplied to a second scan line connected to the ith horizontal line, and the third scan signal GIi may be a scan signal supplied to a third scan line connected to the ith horizontal line.

[0064] The second transistor M2 may be connected between a data line supplied with a data voltage Data and the first pixel node PN1, and may be turned on by the first scan signal GWi based on the scan line.

[0065] The first transistor M1 may be connected between the first pixel node PN1 and the third pixel node PN3. The first transistor M1 may also be referred to as a driving transistor. The gate electrode of the first transistor M1 may be connected to the second pixel node PN2.

[0066] The third transistor M3 may be connected between the second pixel node PN2 and the third pixel node PN3, and may be turned on by the second scan signal GCi.

[0067] The storage capacitor Cst may be connected between a wiring supplied with the voltage of the first driving power supply VDD and the second pixel node PN2. Therefore, if the second transistor M2 is turned on by the first scan signal GWi and the third transistor M3 is turned on by the second scan signal GCi, the data voltage Data based on the data line may be charged to the storage capacitor Cst.

[0068] The fourth transistor M4 may be connected between the second pixel node PN2 and a wiring supplied with an initialization voltage Vint, and may be turned on by the third scan signal GIi based on the scan line. If the fourth transistor M4 is turned on by the third scan signal GIi, the voltage charged to the storage capacitor Cst may be initialized to the initialization voltage Vint. That is, if the fourth transistor M4 is turned on by the third scan signal GIi, the storage capacitor Cst may output a discharge voltage based on the initialization voltage Vint. Generally, the initialization voltage Vint may be defined as a voltage for initializing the pixel PXij.

[0069] The fifth transistor M5 may be connected between the first driving power supply VDD and the first pixel node PN1, and may be turned on by a low-level light emission control signal EMi. Hereinafter, the light emission control signal EMi may mean a light emission control signal supplied to each pixel PXij through an arbitrary ith light emission control line among light emission control lines E1, E2,..., En according to Figure 1 the light emission control line E1, E2,..., En.

[0070] The sixth transistor M6 can be connected between the third pixel node PN3 and the fourth pixel node PN4, and can be turned on by a low-level emission control signal EMi.

[0071] The anode of the light-emitting element EL is connected to the fourth pixel node PN4, and the cathode of the light-emitting element EL is connected to a wiring supplied with the voltage of the second driving power source VSS, so that the light-emitting element EL can emit light with a brightness corresponding to the driving current.

[0072] Therefore, if the fifth transistor M5 and the sixth transistor M6 are turned on by the emission control signal EMi, a driving current corresponding to the voltage charged in the storage capacitor Cst can be supplied to the light-emitting element EL.

[0073] The seventh transistor M7 can be connected between a wiring supplied with the initialization voltage Vint and the fourth pixel node PN4, and is turned off by a low-level emission control signal EMi. If the seventh transistor M7 is turned on, a parasitic capacitor (not shown) built in the light-emitting element EL can be initialized by the initialization voltage Vint. Specifically, if a voltage difference Vint - VSS between the initialization voltage Vint and the voltage of the second driving power source VSS is applied to the parasitic capacitor of the light-emitting element EL, the light-emitting element EL can discharge according to the applied voltage difference Vint - VSS.

[0074] In Figure 2 the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 among the transistors are shown as P-type transistors, and the third transistor M3, the fourth transistor M4, and the seventh transistor M7 are shown as N-type transistors. Therefore, it can be that a case where the voltage applied to the gate electrode of the P-type transistor is at a low level is called a turn-on level, and a case where the voltage applied to the gate electrode of the P-type transistor is at a high level is called a turn-off level. Similarly, it can be that a case where the voltage applied to the gate electrode of the N-type transistor is at a high level is called a turn-on level, and a case where the voltage applied to the gate electrode of the N-type transistor is at a low level is called a turn-off level. Those skilled in the art can also change at least a part of the transistors M1, M2, M3, M4, M5, M6, and M7 to N-type transistors (or P-type transistors).

[0075] Figure 3 is a diagram for explaining a light emission control driving unit according to an embodiment of the present disclosure.

[0076] Refer together to Figure 1 andFigure 3 , the light emission control driving unit 40 may include: a plurality of stages 401, 402, 403,... for supplying light emission control signals EM1, EM2, EM3,... to the light emission control lines E1 to En. However, in the drawings, for ease of explanation, only three stages 401, 402, 403 are shown.

[0077] The stages 401, 402, 403,... are driven by the light emission start signal FLM, the first clock signal CLK1, and the second clock signal CLK2, and output the light emission control signals EM1, EM2, EM3,.... The light emission start signal FLM, the first clock signal CLK1, and the second clock signal CLK2 can be received through the light emission driving control signal ECS from the timing control unit 50. The stages 401, 402, 403,... can be constituted by circuits that are the same as or different from each other.

[0078] Each of the stages 401, 402, 403,... may include a first input terminal 101, a second input terminal 102, a third input terminal 103, and an output terminal 104.

[0079] The first input terminal 101 may receive the carry signals CR1, CR2,... of the previous stage or the light emission start signal FLM. For example, it may be that the first stage 401 receives the light emission start signal FLM through the first input terminal 101, and the remaining stages receive the carry signals CR1, CR2,... of the previous stage through the first input terminal 101. The carry signals CR1, CR2,... may also include the light emission control signals EM1, EM2, EM3,... of the previous stage.

[0080] The second input terminal 102 and the third input terminal 103 may each receive the first clock signal CLK1 and the second clock signal CLK2.

[0081] The output terminal 104 may be connected to one of the light emission control lines E1, E2,..., En and output the light emission control signals EM1, EM2, EM3,....

[0082] The first clock signal CLK1 or the second clock signal CLK2 may be a square wave signal with repeated logic high and logic low levels. The periods of the first clock signal CLK1 and the second clock signal CLK2 may be the same, for example, it may be 1 horizontal period 1H or two horizontal periods 2H. The first clock signal CLK1 and the second clock signal CLK2 may be signals with the same waveform as each other. It may be that the first clock signal CLK1 and the second clock signal CLK2 have a phase difference of more than half a period, and the gate conduction voltage periods of the first clock signal CLK1 and the second clock signal CLK2 are set not to overlap with each other. For example, during the period when the first clock signal CLK1 is at logic high level, the second clock signal CLK2 may be at logic low level, and during the period when the first clock signal CLK1 is at logic low level, the second clock signal CLK2 may be at logic high level. However, this is illustrative, and the waveform relationship between the first clock signal CLK1 and the second clock signal CLK2 does not have to be limited to this.

[0083] Referring to Figure 3 , the first stage 401 can respond to the light emission start signal FLM, the first clock signal CLK1, and the second clock signal CLK2, output the first light emission control signal EM1 to the pixel connected to one of the light emission control lines (E1 to En), and output the first carry signal CR1 to the second stage 402.

[0084] The second stage 402 can respond to the first clock signal CLK1, the second clock signal CLK2, and the first carry signal CR1, output the second light emission control signal EM2 to the pixel connected to one of the light emission control lines (E1 to En), and output the second carry signal CR2 to the third stage 403.

[0085] The third stage 403 can respond to the first clock signal CLK1, the second clock signal CLK2, and the second carry signal CR2, output the third light emission control signal EM3 to the pixel connected to one of the light emission control lines (E1 to En), and output the third carry signal CR3 to the fourth stage 404 (not shown).

[0086] On the other hand, although in Figure 3It is shown that each stage directly receives the input first clock signal CLK1 and the second clock signal CLK2 through the second input terminal 102 and the third input terminal 103, but it is not necessarily limited thereto. As other embodiments, it may be that although the first stage 401 directly receives the input first clock signal CLK1 and the second clock signal CLK2, the remaining stages 402, 403,... receive and transmit either the first clock signal CLK1 or the second clock signal CLK2 from the previous stage. As a more detailed illustration, the odd-numbered stages 403,... except the first stage 401 may receive and transmit the first clock signal CLK1 from the previous stage and directly receive the input second clock signal CLK2. The even-numbered stages 402,... may directly receive the input first clock signal CLK1 and receive and transmit the second clock signal CLK2 from the previous stage. Thus, according to other embodiments, the carry signal may include at least one of the first clock signal CLK1 and the second clock signal CLK2.

[0087] In addition, the first clock signal CLK1 and the second clock signal CLK2 may be alternately input to each stage.

[0088] For example, as Figure 3 shown, the odd-numbered stages 401, 403,... may receive the input first clock signal CLK1 through the second input terminal 102 and receive the input second clock signal CLK2 through the third input terminal 103, and the even-numbered stages 402,... may receive the input second clock signal CLK2 through the second input terminal 102 and receive the input first clock signal CLK1 through the third input terminal 103.

[0089] Figure 4 is a circuit diagram of the first embodiment of the stage according to Figure 3 the stage.

[0090] Referring to Figure 4 , the stage 400 may include an input circuit 410, a first main circuit 420, a second main circuit 430, an output circuit 440, and a first auxiliary circuit 450. Figure 4 The stage 400 shown may represent Figure 3 the circuit diagram of any i-th stage among the multiple stages 401, 402, 403,... shown. Hereinafter, although the description is made on the premise that the first clock signal CLK1 and the second clock signal CLK2 are respectively received through the second input terminal 102 and the third input terminal 103, it may also include the case contrary to the Figure 3 description.

[0091] In addition, it may be that in accordance with Figure 4In stage 400, a first power supply VGH supplies a high-level voltage (or gate cut-off voltage) for turning off the P-type transistor, and a second power supply VGL supplies a low-level voltage (or gate conduction voltage) for turning on the P-type transistor.

[0092] The input circuit 410 can control the voltages of the first node N1 and the second node N2 based on one of the light emission start signal FLM and the carry signal CR[i - 1] from the previous stage, and the first clock signal CLK1. For example, it can be that Figure 4 If the shown stage 400 is the first stage 401 according to Figure 3 , the light emission start signal FLM is input to the input circuit 410 through the first input terminal 101, and if it is any of the remaining other stages, the carry signal CR[i - 1] from the previous stage is input to the input circuit 410 through the first input terminal 101.

[0093] Specifically, the input circuit 410 can include a first transistor T1, a fourth transistor T4, and a fifth transistor T5. The first transistor T1 can be connected between the first input terminal 101, which is input with one of the light emission start signal FLM and the carry signal CR[i - 1] from the previous stage, and the second node N2. The second input terminal 102 can be connected to the gate electrode of the first transistor T1. Therefore, the first transistor T1 can be turned on or off according to the first clock signal CLK1.

[0094] The fourth transistor T4 can be connected between the first node N1 and the second input terminal 102. The gate electrode of the fourth transistor T4 can be connected to the second node N2. Therefore, the fourth transistor T4 can be turned on or off according to the voltage applied to the second node N2. At this time, the fourth transistor T4 can include a first sub-transistor and a second sub-transistor having gate electrodes connected in common as shown and connected in series with each other. At this time, the gate electrode where the first sub-transistor and the second sub-transistor are connected in common can be connected to the second node N2. In this way, since the fourth transistor T4 is composed of multiple sub-transistors, even when the voltage difference between the first node N1 and the second node N2 is high, a current path can be stably formed between the first node N1 and the second input terminal 102.

[0095] The fifth transistor T5 can be connected between the first node N1 and the second power supply VGL. The gate electrode of the fifth transistor T5 can be connected to the second input terminal 102 to which the first clock signal CLK1 is input. Therefore, the fifth transistor T5 can be turned on or off according to the first clock signal CLK1.

[0096] The first main circuit 420 can control the voltage of the third node N3 based on the voltage applied to the fifth node N5 and the second clock signal CLK2. The first main circuit 420 can include a second capacitor C2, a sixth transistor T6, and a seventh transistor T7. The sixth transistor T6 can be connected between the third node N3 and the sixth node N6. The seventh transistor T7 can be connected between the sixth node N6 and the third input terminal 103. The gate electrode of the sixth transistor T6 can be connected to the third input terminal 103 to which the second clock signal CLK2 is input. Therefore, the sixth transistor T6 can be turned on or off according to the second clock signal CLK2. The gate electrode of the seventh transistor T7 can be connected to the fifth node N5. Therefore, the seventh transistor T7 can be turned on or off according to the voltage applied to the fifth node N5. The second capacitor C2 can be connected between the sixth node N6 and the fifth node N5.

[0097] On the other hand, the first node N1 and the fifth node N5 can be the same node as each other, but are not limited thereto. For example, the stage 400 can further include: an eleventh transistor T11 connected between the first node N1 of the input circuit 410 and the fifth node N5 of the first main circuit 420. The eleventh transistor T11 can limit the voltage of the first node N1 from dropping excessively lower than the voltage of the fifth node N5. That is, the eleventh transistor T11 can limit the voltage drop amplitude of the first node N1.

[0098] The gate electrode of the eleventh transistor T11 can be connected to the second power supply VGL. The second power supply VGL has a low-level voltage (or a voltage that triggers a p-type transistor into a conducting state), so the eleventh transistor T11 can always be kept in a conducting state. Therefore, since the voltage of the first node N1 and the voltage of the fifth node N5 can be kept the same as each other, the voltage applied to the first node N1 of the input circuit 410 can also be applied to the fifth node N5 of the first main circuit 420.

[0099] The second main circuit 430 can output the voltage of the third node N3 based on the voltage applied to the second node N2, so that the third node N3 has a voltage with a level opposite to that of the second node N2 (for example, if the voltage of the third node N3 is high level, the voltage of the second node N2 is low level). The second main circuit 430 can include a first capacitor C1 and an eighth transistor T8. The eighth transistor T8 can be connected between the first power supply VGH and the third node N3. The gate electrode of the eighth transistor T8 can be connected to the second node N2. Therefore, the eighth transistor T8 can be turned on or off according to the voltage applied to the second node N2. The first capacitor C1 can be connected between the first power supply VGH and the third node N3. Therefore, the first capacitor C1 can be charged when a low-level voltage is applied to the third node N3 and then assist in keeping the ninth transistor T9 in a conducting state.

[0100] The output circuit 440 can control the light emission control signal EMi output to the output terminal 104 based on the voltage applied to the third node N3 and the voltage applied to the fourth node N4. The output circuit 440 can include a ninth transistor T9 and a tenth transistor T10.

[0101] The ninth transistor T9 can be connected between the first power supply VGH and the output terminal 104 that outputs the light emission control signal EMi. The gate electrode of the ninth transistor T9 can be connected to the third node N3. Therefore, the ninth transistor T9 can be turned on or off according to the voltage applied to the third node N3. If the ninth transistor T9 is turned on, a high-level light emission control signal EMi can be output while a current based on the first power supply VGH flows to the output terminal 104.

[0102] The tenth transistor T10 can be connected between the output terminal 104 and the second power supply VGL. The gate electrode of the tenth transistor T10 can be connected to the fourth node N4. Therefore, the tenth transistor T10 can be turned on or off according to the voltage input to the fourth node N4. If the tenth transistor T10 is turned on, a low-level light emission control signal EMi based on the second power supply VGL can be output.

[0103] On the other hand, the second node N2 and the fourth node N4 can be the same as each other, but are not limited thereto. For example, the stage 400 can further include: a twelfth transistor T12, connected between the second node N2 of the input circuit 410 and the fourth node N4 of the output circuit 440. The twelfth transistor T12 can limit the voltage of the second node N2 from dropping excessively lower than the voltage of the fourth node N4. That is, the twelfth transistor T12 can limit the voltage drop amplitude of the second node N2.

[0104] The second power supply VGL can be input to the gate electrode of the twelfth transistor T12. Since the second power supply VGL has a low-level voltage (or a voltage that triggers a p-type transistor into a conducting state), the twelfth transistor T12 can always be kept in a conducting state. Therefore, since the voltage of the second node N2 and the voltage of the fourth node N4 can be kept the same as each other, the voltage applied to the second node N2 of the input circuit 410 can also be applied to the fourth node N4 of the output circuit 440.

[0105] On the other hand, in an embodiment of the present disclosure, it can further include: a first auxiliary circuit 450, which assists in stably maintaining the fourth node N4 at a low level (or stably turning on the tenth transistor T10 of the output circuit 440) based on the voltage applied to the fourth node N4 and the second clock signal CLK2.

[0106] Specifically, the first auxiliary circuit 450 may include a third capacitor C3, a second transistor T2, and a third transistor T3. The second transistor T2 may be connected between a first power supply VGH and a seventh node N7. The gate electrode of the second transistor T2 may be connected to the first node N1. Therefore, the second transistor T2 may be turned on or off by the voltage applied to the first node N1. The third capacitor C3 may be connected between a fourth node N4 and the seventh node N7.

[0107] When the light emission start signal FLM or the carry signal CR[i-1] of the previous stage is converted to a low level, the third capacitor C3 may additionally reduce the voltage of the fourth node N4 converted to the low level by an amount equal to the charged voltage magnitude.

[0108] If the voltage of the fourth node N4 is further reduced, the voltage difference Vgs between the gate electrode and the source electrode of the tenth transistor T10 is maintained even lower below the threshold voltage of the tenth transistor T10. Therefore, the light emission control signal EMi can be maintained at a sufficiently low level. Thus, the first auxiliary circuit 450 including the third capacitor C3 assists in generating a sufficiently low low-level signal for the light emission control signal EMi, which can save power consumption.

[0109] The third transistor T3 may be connected between the seventh node N7 and a third input terminal 103. The gate electrode of the third transistor T3 may be connected to the fourth node N4. Therefore, the third transistor T3 may be turned on or off according to the voltage applied to the fourth node N4.

[0110] Figure 4 The illustrated first transistor T1 to twelfth transistor T12 may be P-type transistors. Therefore, Figure 4 the gate turn-on voltage of the illustrated first transistor T1 to twelfth transistor T12 may be a low level, and the gate turn-off voltage may be a high level. However, it is not necessarily limited thereto and should be interpreted as including Figure 4 deforming all or a part of the illustrated first transistor T1 to twelfth transistor T12 into n-type transistors in an embodiment of the present disclosure.

[0111] Figure 5 is a waveform diagram showing the operation of the stage according to Figure 4 the stage.

[0112] Referring to Figure 5 it is possible to explain Figure 4 the operation flow of the stage 400 shown.

[0113] Hereinafter, since the configuration according to Figure 4The transistor of stage 400 is premised on a P-type transistor, and the meaning that the first clock signal CLK1 and / or the second clock signal CLK2 are at a low level can also be interpreted as the meaning that "the first clock signal CLK1 and / or the second clock signal CLK2 are supplied to the stage".

[0114] Refer to Figure 5 , the first clock signal CLK1 and the second clock signal CLK2 may have a period of two horizontal periods 2H, and have gate conduction levels in different horizontal periods. That is, the second clock signal CLK2 may be a signal shifted by a half period (or one horizontal period 1H) from the first clock signal CLK1.

[0115] In addition, the light emission start signal FLM input to the input circuit 410 or the carry signal CR[i - 1] of the previous stage may be supplied to the input circuit 410 together with the first clock signal CLK1 for more than the period (or half period) of the first clock signal CLK1. For example, the period when the light emission start signal FLM or the carry signal CR[i - 1] of the previous stage is input to the input circuit 410 may be more than twice as large as the period of the first clock signal CLK1 (shown as input during about 4 horizontal periods in Figure 5 .

[0116] Refer to Figure 4 and Figure 5 , the operation of stage 400 based on the first time period t1 is described as follows.

[0117] In the first time period t1, if the first clock signal CLK1 transitions to a low level (or if the first clock signal CLK1 is supplied), the first transistor T1 and the fifth transistor T5 of the input circuit 410 are turned on. At this time, since the second clock signal CLK2 remains at a high level, the sixth transistor T6 is turned off.

[0118] If the first transistor T1 is turned on, the low-level light emission start signal FLM or the carry signal CR[i - 1] of the previous stage input to the input circuit 410 can be transmitted to the second node N2. As a result, a low-level voltage is applied to the second node N2. If a low-level voltage is applied to the second node N2, the fourth transistor T4 and the eighth transistor T8 are turned on.

[0119] In addition, since the twelfth transistor T12 always remains turned on, the voltage of the second node N2 is transmitted to the fourth node N4 as it is and a low-level voltage is applied to the fourth node N4. Therefore, if a low-level voltage is applied to the fourth node N4, the tenth transistor T10 and the third transistor T3 are turned on.

[0120] If the third transistor T3 is turned on, the high-level voltage based on the second clock signal CLK2 is applied to the seventh node N7. Therefore, the third capacitor C3 connected between the fourth node N4 at a low-level voltage and the seventh node N7 at a high-level voltage is charged with the voltage applied between the fourth node N4 and the seventh node N7.

[0121] If the fourth transistor T4 is turned on, the fifth transistor T5 connected between the first node N1 and the second power supply VGL can operate as a diode. Therefore, even if the fifth transistor T5 is turned on, the low-level voltage of the second power supply VGL will not be transmitted to the first node N1, and the first node N1 can maintain the voltage in the previous state (for example, a high-level voltage as Figure 5 such).

[0122] If the first node N1 maintains a high-level voltage, the second transistor T2 is turned off. In addition, since the voltage of the first node N1 is transmitted to the fifth node N5 through the eleventh transistor T11 that is always turned on, a high-level voltage is applied to the fifth node N5. If a high-level voltage is applied to the fifth node N5, the seventh transistor T7 is turned off.

[0123] If the eighth transistor T8 is turned on, the voltage based on the first power supply VGH is applied to the third node N3, and the ninth transistor T9 is turned off.

[0124] If the tenth transistor T10 is turned on, the low-level voltage based on the second power supply VGL is output as the light emission control signal EMi to the output terminal 104. At this time, if the light emission control signal EMi is a low-level voltage, it can be defined that the light emission control signal EMi is supplied to the pixel (because the fifth transistor M5 and the sixth transistor M6 in the pixel based on Figure 2 are turned on).

[0125] In Figure 5 the operation of the stage based on the second period t2 is described as follows.

[0126] In the second period t2, the first clock signal CLK1 maintains a high-level voltage. Therefore, the first transistor T1 and the fifth transistor T5 are turned off. However, even if the first transistor T1 and the fifth transistor T5 are turned off, the third node N3 maintains the voltage in the previous state (high level) through the first capacitor C1, and the fourth node N4 maintains the voltage in the previous state (low level) through the third capacitor C3. Therefore, if the third node N3 is at a high-level voltage, the ninth transistor T9 remains in the off state. Since the fourth node N4 maintains a low-level voltage, the third transistor T3, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 remain turned on.

[0127] In the second time period t2, if the second clock signal CLK2 transitions to a low level, the sixth transistor T6 turns on. If the sixth transistor T6 turns on, the high-level voltage of the third node N3 is applied to the sixth node N6.

[0128] In addition, if the third transistor T3 turns on, the low-level voltage based on the second clock signal CLK2 is applied to the seventh node N7. At this time, a voltage lower than the voltage amount of the third capacitor C3 with respect to the voltage applied to the seventh node N7 is applied to the fourth node N4.

[0129] In Figure 5 the operation of the stage based on the third time period t3 is described as follows.

[0130] In the third time period t3, since the second clock signal CLK2 maintains a high-level voltage, the sixth transistor T6 is turned off. In addition, in the third time period t3, the light emission start signal FLM or the carry signal CR[i - 1] of the previous stage is input to the input circuit 410 at a high level, and the first clock signal CLK1 transitions to a low level.

[0131] If the first clock signal CLK1 transitions to a low level, the first transistor T1 and the fifth transistor T5 turn on.

[0132] If the first transistor T1 turns on, the low-level light emission start signal FLM or the carry signal CR[i - 1] input to the input circuit 410 can be transmitted to the second node N2. As a result, a high-level voltage is applied to the second node N2. If a high-level voltage is applied to the second node N2, the fourth transistor T4 and the eighth transistor T8 are turned off.

[0133] In addition, since the twelfth transistor T12 always remains turned on, the voltage of the second node N2 is transmitted to the fourth node N4 as it is, and a high-level voltage is applied to the fourth node N4. Therefore, if a high-level voltage is applied to the fourth node N4, the tenth transistor T10 and the third transistor T3 are turned off.

[0134] If the fifth transistor T5 turns on, the low-level voltage based on the second power supply VGL is applied to the first node N1. In addition, since the eleventh transistor T11 is always turned on, the low-level voltage based on the second power supply VGL is also applied to the fifth node N5. Therefore, the second transistor T2 turns on through the low-level voltage of the first node N1, and the seventh transistor T7 turns on through the low-level voltage of the fifth node N5.

[0135] If the second transistor T2 is turned on, the voltage of the first power supply VGH is applied to the seventh node N7. At this time, since the third transistor T3 remains in the off state, the second clock signal CLK2 is not transmitted to the seventh node N7. In addition, since the voltages applied to the seventh node N7 connected to the third capacitor C3 and the second node N2 (or the fourth node N4) are all high-level voltages, no voltage difference is generated in the third capacitor C3, and charging and discharging are not performed.

[0136] If the seventh transistor T7 is turned on, the high-level voltage based on the second clock signal CLK2 is applied to the sixth node N6. At this time, since the second clock signal CLK2 is a high-level voltage, the sixth transistor T6 is turned off. Since a low-level voltage is applied to the fifth node N5, the differential voltage between the high-level voltage applied to the sixth node N6 and the low-level voltage based on the fifth node N5 (or the on-voltage for the seventh transistor T7) is stored in the second capacitor C2.

[0137] In Figure 5 the following describes the operation of the stage according to the fourth time period t4.

[0138] In the fourth time period t4, the first clock signal CLK1 remains high, and the second clock signal CLK2 transitions to low. Therefore, the first transistor T1 and the fifth transistor T5 remain in the off state, and the sixth transistor T6 is turned on.

[0139] At this time, the seventh transistor T7 was turned on through the second capacitor C2 in the previous third time period t3. Therefore, if the sixth transistor T6 is also turned on, the low-level voltage based on the second clock signal CLK2 can be applied to the sixth node N6 and the third node N3. If a low-level voltage is applied to the third node N3, the ninth transistor T9 is turned on.

[0140] If the ninth transistor T9 is turned on, while current flows from the first power supply VGH to the output terminal 104, the high-level light emission control signal EMi is output through the output terminal 104.

[0141] On the other hand, the fifth node N5 (or the first node N1) is applied with a voltage (second-order low-level voltage) (second capacitor coupling effect) that is smaller than the low-level voltage based on the sixth node N6 by the voltage difference amount based on the second capacitor C2.

[0142] In Figure 5 the following describes the operation of the stage 400 based on the fifth time period t5.

[0143] In the fifth time period t5, since the second clock signal CLK2 remains high, the sixth transistor T6 remains in the off state. Since the first clock signal CLK1 transitions to low, the first transistor T1 and the fifth transistor T5 can be turned on.

[0144] If the first transistor T1 is turned on, the low-level light emission start signal FLM input to the input circuit 410 or the carry signal CR[i-1] from the previous stage can be transmitted to the second node N2. As a result, the second node N2 is converted to a low level. If the second node N2 is converted to a low level, the fourth transistor T4 and the eighth transistor T8 are turned on.

[0145] In addition, since the twelfth transistor T12 is always kept on, the voltage of the second node N2 is transmitted to the fourth node N4 as it is, and a low-level voltage is applied to the fourth node N4. Therefore, if a low-level voltage is applied to the fourth node N4, the tenth transistor T10 and the third transistor T3 are turned on.

[0146] If the third transistor T3 is turned on, a high-level voltage based on the second clock signal CLK2 is applied to the seventh node N7. Therefore, the third capacitor C3 connected between the fourth node N4 as a low-level voltage and the seventh node N7 as a high-level voltage is charged with the voltage applied between the fourth node N4 and the seventh node N7.

[0147] If the fourth transistor T4 is turned on, the fifth transistor T5 connected between the first node N1 and the second power supply VGL can operate as a diode. Therefore, even if the fifth transistor T5 is turned on, the low-level voltage based on the second power supply VGL is not transmitted to the first node N1, and the first node N1 can maintain the voltage in the previous state (for example, as Figure 5 such as a low-level voltage).

[0148] If the first node N1 maintains a low-level voltage, the second transistor T2 is turned on. In addition, since the voltage of the first node N1 is transmitted to the fifth node N5 through the eleventh transistor T11 that is always kept on, a low-level voltage is applied to the fifth node N5. If a low-level voltage is applied to the fifth node N5, the seventh transistor T7 is turned on.

[0149] If the second transistor T2 is turned on, a high voltage based on the first power supply VGH can be applied to the seventh node N7.

[0150] In addition, if the seventh transistor T7 is turned on, a high-level voltage based on the second clock signal CLK2 is applied to the sixth node N6.

[0151] If the eighth transistor T8 is turned on, the voltage of the first power supply VGH is applied to the third node N3, and the ninth transistor T9 is turned off.

[0152] If the tenth transistor T10 is turned on, the light emission control signal EMi output to the output terminal 104 of the stage 400 is converted to a low level. However, at this time, as in Figure 4As observed, the low-level output of the light emission control signal EMi is slightly high. To solve such a problem, according to Figure 4 The first auxiliary circuit 450 can additionally reduce the low-level output of the light emission control signal EMi.

[0153] Specifically, the operation of stage 400 based on the sixth time period t6 is described as follows. Figure 5 The operation of stage 400 based on the sixth time period t6.

[0154] In the sixth time period t6, as the second clock signal CLK2 transitions to a low level, through the third transistor T3, the low-level voltage based on the second clock signal CLK2 is applied to the seventh node N7. The third capacitor C3 further reduces the charged voltage amount by one order of magnitude for the voltage of the fourth node N4. If the voltage of the fourth node N4 is further reduced through the coupling of the third capacitor C3, since the absolute value of the voltage difference Vgs between the gate electrode and the source electrode of the tenth transistor T10 further increases, the light emission control signal EMi can be reduced to a level that is one order lower.

[0155] Therefore, as Figure 5 shown, as the light emission start signal FLM transitions to a low level in the fifth time period t5, the light emission control signal EMi output to the output terminal 104 of stage 400 transitions to a first low level, and then as the second clock signal CLK2 transitions to a low level in the sixth time period t6, the first auxiliary circuit 450 operates, so that the light emission control signal EMi can transition to a second low level that is one order lower than the first low level.

[0156] In this way, based on stage 400 according to Figure 4 the light emission control signal EMi is gradually reduced and transitions to a low-level voltage (defined as the voltage in the state of supplying the light emission control signal) (two-step falling). In this way, when the light emission control signal EMi is gradually reduced, problems such as overcurrent and increased power consumption may occur in special pixels. Therefore, in an embodiment of the present disclosure, a stage in which the light emission control signal EMi can be reduced in a single-step form without gradual reduction is additionally proposed.

[0157] Figure 6 is the circuit diagram of the second embodiment of the stage according to Figure 3 the stage.

[0158] Referring to Figure 6 , it can be confirmed that the output of the stage 400 circuit according to Figure 4 the light emission control signal EMi can be improved to a circuit that does not decrease in a stepped manner.

[0159] Referring to Figure 6 , according to Figure 4On the premise of stage 400, stage 500 according to the second embodiment can be based on Figure 4 Stage 400 further includes: a second auxiliary circuit 460 that receives the voltage applied to the second node N2 and controls the low-level output of the light emission control signal EMi in a single-step manner.

[0160] The second auxiliary circuit 460 may include a thirteenth transistor T13, a fourteenth transistor T14, and a fourth capacitor C4.

[0161] The fourteenth transistor T14 may be connected between the output terminal 104 and the second power supply VGL. The gate electrode of the fourteenth transistor T14 may be connected to the eighth node N8.

[0162] The thirteenth transistor T13 may be connected between the second node N2 and the eighth node N8. The gate electrode of the thirteenth transistor T13 may be connected to the second power supply VGL.

[0163] The fourth capacitor C4 may be connected between the eighth node N8 and the output terminal 104.

[0164] When the light emission start signal FLM or the carry signal CR[i - 1] of the previous stage changes from high level to low level, a low-level voltage is applied to the second node N2. At this time, based on the voltage applied to the second node N2 changing from high level to low level, the second auxiliary circuit 460 further reduces the voltage of the eighth node N8 connected to the gate electrode of the fourteenth transistor T14 by the amount of voltage charged in the fourth capacitor C4. Therefore, since the voltage difference between the gate electrode and the source electrode of the fourteenth transistor T14 remains at an amplitude lower than the threshold voltage of the fourteenth transistor T14 and further increases, instead of the Figure 5 stepwise decrease (two-step falling) according to

[0165] For reference, different from stage 400 according to Figure 4 stage 500 according to Figure 6 shows the positions of the input terminal to which the first clock signal CLK1 is applied and the input terminal to which the second clock signal CLK2 is applied in the reverse. This is to show that the first clock signal CLK1 and the second clock signal CLK2 input to each stage are alternately input in terms of the relationship between the stages according to Figure 3 Therefore, Figure 6 the positions of the first clock signal CLK1 and the second clock signal CLK2 applied to the shown stage 500 can be swapped with each other.

[0166] Figure 7 shows according to Figure 6Waveform diagram of the operation of the stage. The first clock signal CLK1 and the second clock signal CLK2 may have a period of 1 horizontal period 1H and have a gate conduction level in different horizontal periods.

[0167] Referring to Figure 7 , it is possible to confirm the operating waveform of the stage 500 according to Figure 6 the stage 500.

[0168] In Figure 7 , observing the period t5-1 when the light emission start signal FLM transitions to a low level, as the light emission start signal FLM transitions to a low level, the second clock signal CLK2 transitions to a low level, and according to Figure 6 the first transistor T1 of the stage 500 can conduct. Therefore, since the low-level light emission start signal FLM is transmitted to the second node N2, the second node N2 can transition to a low level.

[0169] In addition, if the second node N2 transitions to a low level, the eighth node N8 transitions to a low level through the thirteenth transistor T13 that is always in a conducting state. If the eighth node N8 transitions to a low level, while the fourteenth transistor T14 conducts, the light emission control signal EMi starts to decrease. When the light emission control signal EMi decreases, through the fourth capacitor C4, the absolute value of the voltage difference Vgs between the gate electrode (or the eighth node N8) and the source electrode (or the output terminal 104) of the fourteenth transistor T14 further increases. Therefore, since the absolute value of the voltage difference Vgs between the gate electrode and the source electrode of the fourteenth transistor T14 increases, the light emission control signal EMi can immediately drop to the second low level (first-order drop (1step falling)) through the fourth capacitor C4.

[0170] That is, when transitioning to a low level, according to Figure 4 the light emission control signal EM_before of the stage 400 according to Figure 6 is in a form where it first drops to the first low level and then, as the first clock signal CLK1 transitions to a low level, drops to the second low level through the first auxiliary circuit 450. In contrast, the light emission control signal EM_after of the stage 500 according to

[0171] Figure 8 can immediately drop to the second low level through the second auxiliary circuit 460. Figure 3 is a circuit diagram of the third embodiment of the stage according to

[0172] According to Figure 6The stage 500 includes: an eleventh transistor T11, whose gate electrode is connected to the second power supply VGL and always remains in the on state. At this time, the eleventh transistor T11 is used to stably control the voltage drop amplitude of the first node N1 without substantially affecting the operation of the circuit.

[0173] Therefore, if there are no problems such as leakage current according to the characteristics of the light-emitting element, then in accordance with Figure 6 it is possible to omit the eleventh transistor T11 in the stage 500. Referring to Figure 8 in accordance with Figure 6 it is possible to confirm the stage 600 (third embodiment) in which the eleventh transistor T11 is omitted in the stage 500.

[0174] Thus, in the stage 600 where the eleventh transistor T11 is omitted, the first node N1 is regarded as the same as the fifth node N5. In other words, the first node N1 and the fifth node N5 are short-circuited to each other.

[0175] Figure 9 is the circuit diagram of the fourth embodiment of the stage according to Figure 3

[0176] In the stage 400 according to Figure 4 the eleventh transistor T11 and the twelfth transistor T12 always have a low-level voltage based on the second power supply VGL applied to their gate electrodes and remain in the on state.

[0177] Therefore, since the eleventh transistor T11 and the twelfth transistor T12 are used to stably control the voltage drop amplitude, they can be omitted if there are no problems such as leakage current according to the characteristics of the light-emitting element.

[0178] In addition, if there is no problem of increased power consumption when the light-emitting control signal EMi is at a low level, then in the stage 400 according to Figure 4 it is also possible to omit the first auxiliary circuit 450.

[0179] In addition, in the stage 400 according to Figure 4 it is possible to omit the tenth transistor T10. Therefore, the output circuit 440' can be simplified.

[0180] In addition, in the stage 400 according to Figure 4 when a fourth capacitor C4 is additionally connected between the fourth node N4 and the output terminal 104, it is possible to form the same form as the second auxiliary circuit 460 according to Figure 6

[0181] If maintaining the same structure as the second auxiliary circuit 460, then due to the fourth capacitor C4, it is possible to shorten the time for the light-emitting control signal EMi to drop to a low level. ​​

[0182] In summary, if in stage 400 according to Figure 4 , the eleventh transistor T11 and the twelfth transistor T12, and the first auxiliary circuit 450 are omitted, and a fourth capacitor C4 is added, then a simplified stage 700 (fourth embodiment) can be configured as Figure 9 .

[0183] The drawings and the detailed descriptions of the disclosures referred to so far are examples of the present disclosure, which are only used for the purpose of explaining the present disclosure and not for limiting the meaning or the scope of the present disclosure described in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present disclosure should be determined by the technical concept of the appended claims.

Claims

1. A light emission control driving unit, wherein, including a plurality of stages for supplying a light emission control signal to a light emission control line, each of the plurality of stages including: an input circuit that controls the voltage of a first node and the voltage of a second node based on one of a light emission start signal and a carry signal from a previous stage and a first clock signal; a first main circuit that controls the voltage of a third node based on the voltage of the first node and a second clock signal; a second main circuit that controls the voltage of the third node based on the voltage of the second node so that the third node has a voltage of a level opposite to that of the second node; an output circuit that controls a light emission control signal output to an output terminal based on the voltage of the second node and the voltage of the third node; a first auxiliary circuit that controls a low-level output of the light emission control signal based on the second clock signal so that the light emission control signal is further reduced from a first low level to a second low level; and a second auxiliary circuit that controls a low-level output of the light emission control signal in a single-step decreasing form based on the voltage of the second node, the second auxiliary circuit including: a fourth capacitor connected between an eighth node and the output terminal; a thirteenth transistor connected between the second node and the eighth node, with a gate electrode connected to a second power supply; and a fourteenth transistor connected between the output terminal and the second power supply, with a gate electrode connected to the eighth node.

2. The light emission control driving unit according to claim 1, wherein when a low-level voltage is applied to the second node, the fourth capacitor increases the absolute value of the voltage difference between the eighth node and the output terminal so that the light emission control signal is converted to the second low level.

3. The light emission control driving unit according to claim 1, wherein an additional component is included between the input circuit and the output circuit: a twelfth transistor that limits the voltage drop amplitude of the second node.

4. The light emission control driving unit according to claim 3, wherein the twelfth transistor is connected between the second node and a fourth node and includes a gate electrode connected to a second power supply.

5. The light emission control driving unit according to claim 4, wherein the first auxiliary circuit reduces the voltage of the fourth node based on the voltage of the fourth node and the second clock signal.

6. The light emission control driving unit according to claim 5, wherein the first auxiliary circuit includes: a third capacitor connected between the fourth node and a seventh node; a third transistor connected between the seventh node and a third input terminal to which the second clock signal is input, with a gate electrode connected to the fourth node; and a second transistor connected between a first power supply and the seventh node, with a gate electrode connected to the first node.

7. The light emission control driving unit according to claim 6, wherein the third capacitor additionally reduces the voltage of the fourth node that is converted to a low level as the light emission start signal or the carry signal from the previous stage is converted to a low level.

8. The light emission control driving unit according to claim 1, wherein the input circuit includes: A first transistor is connected between a first input terminal to which one of the light emission start signal and the carry signal is input and the second node, and a gate electrode is connected to a second input terminal to which the first clock signal is input; A fourth transistor is connected between the first node and the second input terminal, and a gate electrode is connected to the second node; and A fifth transistor is connected between the first node and a second power supply.

9. The light emission control driving unit according to claim 1, wherein The first main circuit includes: A sixth transistor is connected between the third node and the sixth node, and a gate electrode is connected to a third input terminal to which the second clock signal is input; A seventh transistor is connected between the sixth node and the third input terminal, and a gate electrode is connected to the first node; and A second capacitor is connected between the sixth node and the first node.

10. The light emission control driving unit according to claim 1, wherein The second main circuit includes: An eighth transistor is connected between a first power supply and the third node, and a gate electrode is connected to the second node; and A first capacitor is connected between the first power supply and the third node.

11. The light emission control driving unit according to claim 1, wherein The output circuit includes: A ninth transistor is connected between a first power supply and the output terminal, and a gate electrode is connected to the third node; and A tenth transistor is connected between the output terminal and a second power supply, and a gate electrode is connected to the second node.

12. The light emission control driving unit according to claim 1, wherein Between the input circuit and the first main circuit, there is further included: An eleventh transistor that limits the voltage drop amplitude of the first node.

13. The light emission control driving unit according to claim 12, wherein The eleventh transistor is a transistor whose gate electrode is connected to a second power supply and that is always in a conducting state.

14. A display device, wherein, Includes: A pixel unit including a plurality of pixels; A scan driving unit that supplies a scan signal to the pixels; A data driving unit that supplies a data signal to the pixels; A light emission control driving unit including a plurality of stages that supply a light emission control signal to the pixels; And A timing control unit that controls the driving of the scan driving unit, the data driving unit, and the light emission control driving unit, Each of the stages includes: An input circuit that controls the voltage of a first node and the voltage of a second node based on one of a light emission start signal and a carry signal from a previous stage and a first clock signal; A first main circuit that controls the voltage of a third node based on the voltage of the first node and a second clock signal; A second main circuit that controls the voltage of the third node based on the voltage of the second node so that the third node has a voltage with a level opposite to that of the second node; An output circuit that controls a light emission control signal output to an output terminal based on the voltage of the second node and the voltage of the third node; A first auxiliary circuit that controls the low-level output of the light emission control signal based on the second clock signal so that the light emission control signal is further reduced from a first low level to a second low level; and A second auxiliary circuit controls the low-level output of the light-emitting control signal in a single-step decreasing form based on the voltage of the second node. The second auxiliary circuit includes: A fourth capacitor connected between the eighth node and the output terminal; A thirteenth transistor connected between the second node and the eighth node, with its gate electrode connected to the second power supply; and A fourteenth transistor connected between the output terminal and the second power supply, with its gate electrode connected to the eighth node.

15. The display device according to claim 14, wherein When a low-level voltage is applied to the second node, the fourth capacitor increases the absolute value of the voltage difference between the eighth node and the output terminal, causing the light-emitting control signal to convert to the second low level.

16. The display device according to claim 14, wherein The output circuit includes: A ninth transistor connected between the first power supply and the output terminal, with its gate electrode connected to the third node; and A tenth transistor connected between the output terminal and the second power supply, with its gate electrode connected to the second node.

17. The display device according to claim 14, wherein The first clock signal and the second clock signal have the same period and a phase difference of more than half a period from each other.

18. The display device according to claim 14, wherein The carry signal includes the light-emitting control signal of the previous stage.

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