Display device

Abstract

A display device is disclosed, and the display device includes: a plurality of pixels connected to a plurality of first scan lines, a plurality of second scan lines, a plurality of third scan lines, a plurality of emission control lines, and a plurality of data lines; a first scan driver for supplying a first scan signal to each of the plurality of first scan lines in a first time period; a second scan driver for supplying a second scan signal to each of the plurality of second scan lines in the first time period; a third scan driver for supplying a third scan signal to each of the plurality of third scan lines in the first time period and the second time period; an emission driver for supplying an emission control signal to each of the plurality of emission control lines in the first time period and the second time period; and a data driver for supplying a data signal to each of the plurality of data lines in the first time period, wherein the width of the second scan signal is greater than the width of the first scan signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0139750, filed on November 4, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present invention relate generally to electronic devices, and more particularly to display devices. Background Art

[0004] The display device displays an image on a display panel by using a control signal applied from the outside.

[0005] A display device includes a plurality of pixels. Each of the plurality of pixels includes a plurality of transistors, a light-emitting device electrically connected to the plurality of transistors, and a capacitor. In response to a plurality of signals provided via a plurality of lines, the plurality of transistors are respectively turned on to generate a drive current, and the light-emitting device emits light in accordance with the drive current.

[0006] Recently, there has been a demand for display devices that correspond to various driving frequencies (or image refresh rates) for high-resolution driving, low-power driving, stereoscopic image driving, etc. Accordingly, in order to utilize the advantages of polycrystalline silicon semiconductor transistors and oxide semiconductor transistors, research has been conducted on a pixel structure in which a polycrystalline silicon semiconductor transistor and an oxide semiconductor transistor are combined and included in one pixel.

[0007] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0008] The display device constructed according to the exemplary embodiment of the present invention can ensure the threshold voltage compensation time of the first transistor of the pixel and can periodically apply the bias voltage to the first transistor.

[0009] Additional features of the present inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the present inventive concepts.

[0010] According to an exemplary embodiment, a display device includes: a plurality of pixels connected to a plurality of first scan lines, a plurality of second scan lines, a plurality of third scan lines, a plurality of emission control lines, and a plurality of data lines; a first scan driver configured to supply a first scan signal to each of the plurality of first scan lines in a first period; a second scan driver configured to supply a second scan signal to each of the plurality of second scan lines in the first period; a third scan driver configured to supply a third scan signal to each of the plurality of third scan lines in the first period and the second period; an emission driver configured to supply an emission control signal to each of the plurality of emission control lines in the first period and the second period; and a data driver configured to supply a data signal to each of the plurality of data lines in the first period, wherein a width of the second scan signal is greater than a width of the first scan signal.

[0011] The first scan driver may sequentially supply a first scan signal to the plurality of first scan lines, and the second scan driver may synchronously supply a second scan signal to at least two of the plurality of second scan lines.

[0012] The third scan driver may synchronously supply a third scan signal to at least two of the plurality of third scan lines.

[0013] When the image refresh rate is a first frequency, the first period may be repeated, and when the image refresh rate is less than the first frequency, the second period may be activated at least once immediately after the first period.

[0014] Among a plurality of pixels, a pixel located on an i-th (i is a natural number) horizontal line may include: a light-emitting device; a first transistor including a first electrode connected to a first node, the first node being electrically connected to a first power supply, the first transistor controlling a driving current based on a voltage at a second node; a second transistor connected between one of a plurality of data lines and the first node, the second transistor being turned on by a first scan signal supplied to the i-th first scan line; a third transistor connected between a third node and a second node, the third transistor being turned on by a second scan signal supplied to the i-th second scan line, the third node being connected to the second electrode of the first transistor; and a fourth transistor, being turned on by a third scan signal supplied to the i-th third scan line to supply a bias voltage to the first node.

[0015] The pixel located on the i-th horizontal line may further include: a fifth transistor connected between the first power supply and the first node, the fifth transistor being turned off by the emission control signal supplied to the i-th emission control line; a sixth transistor connected between the third node and the first electrode of the light-emitting device, the sixth transistor being turned off by the emission control signal; and a storage capacitor connected between the first power supply and the second node.

[0016] The pixel located on the i-th horizontal line may further include: a seventh transistor connected between the third node and the first initialization power supply, the seventh transistor being turned on by the first scan signal supplied to the i-1-th first scan line; and an eighth transistor connected between the first electrode of the light-emitting device and the second initialization power supply, the eighth transistor being turned on by the third scan signal supplied to the i-th third scan line.

[0017] When the third transistor is turned on, the seventh transistor and the second transistor may be sequentially turned on.

[0018] When the second transistors of the pixels located on the i-th horizontal line are turned on, the seventh transistors of the pixels located on the (i+1)-th horizontal line and the third transistors of the pixels located on the (i+1)-th horizontal line may be sequentially turned on.

[0019] A turn-on period of the third transistor and a turn-on period of the fourth transistor may not overlap with each other.

[0020] The second scan driver may supply the second scan signal to the i-th second scan line a plurality of times in the first period.

[0021] The display device may further include: a power supplier configured to supply a bias power corresponding to the bias voltage and the first and second initialization power to the plurality of pixels.

[0022] The power supplier may supply the bias power having a first voltage level in a first period, and supply the bias power having a second voltage level different from the first voltage level in a second period.

[0023] The power supplier may supply the first initialization power having a first voltage level in a first period, and supply the first initialization power having a second voltage level different from the first voltage level in a second period.

[0024] When the second period is repeated a plurality of times, the power supplier may change a voltage level of at least one of the first initialization power source, the second initialization power source, and the bias power source in a plurality of stages.

[0025] The fourth transistor may be connected between the first node and the i-th emission control line.

[0026] The emission driver may supply a high level of the emission control signal supplied in the first period and a high level of the emission control signal supplied in the second period as different voltage levels.

[0027] Each of the second transistor and the fourth transistor may be a polysilicon semiconductor transistor.

[0028] The third transistor may be an oxide semiconductor transistor.

[0029] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain the inventive concept. The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification.

[0031] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment.

[0032] Figure 2 is a diagram showing a method according to an exemplary embodiment Figure 1 A circuit diagram of a pixel included in a display device is shown in FIG.

[0033] Figure 3 is a diagram showing a method according to an exemplary embodiment Figure 2 The timing diagram of the pixel operation is shown in FIG.

[0034] Figure 4 is a diagram showing a method according to another exemplary embodiment Figure 2 The timing diagram of the pixel operation is shown in FIG.

[0035] Figure 5A is a diagram showing a method according to an exemplary embodiment Figure 1 A diagram including connections between pixels and signal lines in a display device is shown in .

[0036] Figure 5B is a diagram showing a method according to another exemplary embodiment Figure 1 A diagram including connections between pixels and signal lines in a display device is shown in .

[0037] Figure 6A and 6B is a diagram showing a method according to an exemplary embodiment Figure 2 The timing diagram of the pixel operation is shown in FIG.

[0038] Figure 7 is a diagram showing a method according to another exemplary embodiment Figure 2 The timing diagram of the pixel operation is shown in FIG.

[0039] Figure 8 is a diagram showing a method according to another exemplary embodiment Figure 2 The timing diagram of the pixel operation is shown in FIG.

[0040] Figure 9 is a diagram showing a method according to another exemplary embodiment Figure 1 A circuit diagram of a pixel included in a display device is shown in FIG.

[0041] Figure 10 is a diagram showing a method according to another exemplary embodiment Figure 1 A circuit diagram of a pixel included in a display device is shown in FIG.

[0042] Figure 11 is a diagram showing a method according to another exemplary embodiment Figure 1 A circuit diagram of a pixel included in a display device is shown in FIG.

[0043] Figure 12 is a diagram showing a method according to an exemplary embodiment Figure 11 The timing diagram of the pixel operation is shown in FIG. DETAILED DESCRIPTION

[0044] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words, and the interchangeable words are non-limiting examples of one or more devices or methods using multiple inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be put into practice without these specific details or in the case of one or more equivalent arrangements. In other examples, well-known structures and devices are shown in block diagram form in order to avoid unnecessary confusion of various exemplary embodiments. In addition, various exemplary embodiments may be different, but are not necessarily exclusive. For example, without departing from the present invention, the specific shape, configuration and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0045] Unless otherwise indicated, the exemplary embodiments shown are to be understood as providing exemplary features that provide some of the varying details of how the inventive concept may be implemented in practice. Therefore, unless otherwise indicated, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0046] The use of cross hatching and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. As such, unless otherwise stated, the presence or absence of cross hatching or shading does not convey or indicate a preference or requirement for a specific material, material performance, size, ratio, commonality and / or any other characteristics, attributes, performance, etc. of the element between the elements shown. In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiment can be implemented differently, the specific processing order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order. In addition, similar reference numerals represent similar elements.

[0047] When an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it may be directly on or connected to or coupled to the other element or layer, or there may be intermediate elements or layers. However, when an element or layer is referred to as being "directly on" or "directly connected to" or "directly coupled to" another element or layer, there are no intermediate elements or layers. For this purpose, the term "connected" may refer to a physical, electrical, and / or fluid connection with or without intermediate elements. In addition, the D1 axis, the D2 axis, and the D3 axis are not limited to the three axes of a rectangular coordinate system (such as the x, y, and z axes) and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] Although the terms "first," "second," etc. are used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0049] Spatially relative terms, such as "below," "beneath," "below," "above," "upper," "higher," "side" (e.g., as in "sidewall"), and the like, may be used herein for descriptive purposes and thereby describe the relationship of one element to another element as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the drawings were turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein are to be interpreted accordingly.

[0050] The professional terms used in this article are for the purpose of describing specific embodiments, and are not intended to limit. As used herein, the "one" and "the" in the singular are also intended to include plural forms, unless the context clearly indicates otherwise. Moreover, when used in this specification, the term "comprising" illustrates the existence of stated features, integers, steps, operations, elements, components and / or its cluster. But the existence or increase of one or more other features, integers, steps, operations, elements, components and / or its cluster is not excluded. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than degree terms, and, for their own sake, are utilized to explain the inherent deviation of the value measured, calculated and / or provided, and those of ordinary skill in the art will recognize this inherent deviation.

[0051] Various exemplary embodiments are described herein with reference to cross-sections and / or exploded views, which are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. As such, variations from the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the specific illustrated shapes of regions, but are to include deviations in shapes that result, for example, from manufacturing. In this manner, the regions illustrated in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of regions of a device and, as such, are not necessarily intended to be limiting.

[0052] As is customary in the art, some exemplary embodiments are described and shown in the accompanying drawings in terms of functional blocks, units and / or modules. Those skilled in the art will appreciate that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, storage elements, wiring connections and the like that can be formed using semiconductor-based preparation techniques or other manufacturing techniques). In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be selectively driven by firmware and / or software. It is also conceivable that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware for performing some functions and a processor for performing other functions (e.g., one or more programmed microprocessors and related circuits). In addition, without departing from the scope of the present invention, each block, unit and / or module of some exemplary embodiments can be physically divided into two or more interacting and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0054] Hereinafter, exemplary embodiments will be described in more detail with reference to the accompanying drawings. Throughout the drawings, the same reference numerals are assigned to the same elements, and therefore, repeated description will be omitted.

[0055] Figure 1 is a block diagram illustrating a display apparatus 1000 according to an exemplary embodiment.

[0056] Reference Figure 1 The display device 1000 may include a pixel unit 100, a plurality of scan drivers 200, 300, and 400, an emission driver 500, a data driver 600, and a timing controller 700. The display device 1000 may further include a power supplier 800.

[0057] In an exemplary embodiment, the plurality of scan drivers 200, 300, and 400 may be classified into a first scan driver 200, a second scan driver 300, and a third scan driver 400 based on their configuration and operation. However, the classification of the plurality of scan drivers 200, 300, and 400 is for convenience of description, and in some exemplary embodiments, at least some of the plurality of scan drivers may be integrated into a single driving circuit, a single module, etc., depending on design.

[0058] The display device 1000 can display images at various driving frequencies (e.g., image refresh rate or screen refresh rate) depending on driving conditions. As used herein, the driving frequency may refer to the frequency at which a data signal is substantially written to the driving transistor of the pixel PX. For example, the driving frequency may be referred to as the screen scan rate or screen refresh rate, and represents the number of times the display screen is refreshed per second.

[0059] In an exemplary embodiment, the image refresh rate is an output frequency of the data driver 600 and / or the first scan driver 200. For example, the refresh rate for driving a moving image may be about 60 Hz or higher (eg, 120 Hz).

[0060] In an exemplary embodiment, the display device 1000 may control the output frequency of the first scan driver 200 and the second scan driver 300 and the output frequency of the data driver 600, and the output frequency of the data driver 600 corresponds to the output frequency of the first scan driver 200 and the second scan driver 300 according to the driving conditions. For example, the display device 1000 may display images according to various image refresh rates within a range of 1 Hz to 120 Hz. However, the present inventive concept is not limited thereto, and in some exemplary embodiments, the display device 1000 may display images at an image refresh rate of 120 Hz or higher (e.g., 240 Hz or 480 Hz).

[0061] The pixel unit 100 includes a plurality of pixels PX connected to a plurality of data lines D, a plurality of first scan lines S1, a plurality of second scan lines S2, a plurality of third scan lines S3, and a plurality of emission control lines E. The pixels PX may be externally supplied with voltages of a first power supply VDD, a second power supply VSS, and an initialization power supply Vint. In an exemplary embodiment, the pixels PX may further be externally supplied with a voltage of a bias power supply Vbs.

[0062] The timing controller 700 can generate a first scan drive control signal SCS1, a second scan drive control signal SCS2, a third scan drive control signal SCS3, an emission drive control signal ECS, and a data drive control signal DCS based on externally supplied synchronization signals. The first scan drive control signal SCS1 can be supplied to the first scan driver 200, the second scan drive control signal SCS2 can be supplied to the second scan driver 300, and the third scan drive control signal SCS3 can be supplied to the third scan driver 400. Furthermore, the emission drive control signal ECS can be supplied to the emission driver 500, and the data drive control signal DCS can be supplied to the data driver 600. Furthermore, the timing controller 700 can adjust externally supplied image data and supply the adjusted image data to the data driver 600.

[0063] The first scan start pulse and the clock signal may be included in the first scan driving control signal SCS1. The first scan start pulse may control the first timing of the first scan signal. The clock signal may be used to shift the first scan start pulse.

[0064] The second scan start pulse and the clock signal may be included in the second scan drive control signal SCS2. The second scan start pulse may control the first timing of the second scan signal. The clock signal may be used to shift the second scan start pulse.

[0065] The third scan start pulse and the clock signal may be included in the third scan drive control signal SCS3. The third scan start pulse may control the first timing of the third scan signal. The clock signal may be used to shift the third scan start pulse.

[0066] In an exemplary embodiment, at least one of the first to third scan start pulses may have a pulse width different from a pulse width of another of the first to third scan start pulses. For its part, a plurality of scan signals corresponding to the first to third scan start pulses may have different widths.

[0067] The emission control start pulse and the clock signal may be included in the emission drive control signal ECS. The emission control start pulse may control the first timing of the emission control signal. The clock signal may be used to shift the emission control start pulse.

[0068] A source start pulse and a clock signal may be included in the data drive control signal DCS. The source start pulse may control the start time of data sampling. The clock signal may be used to control the sampling operation.

[0069] In some exemplary embodiments, the timing controller 700 may generate a power control signal PCS for controlling driving of the power supplier 800. The power control signal PCS may control supply timing and / or voltage level of at least one of the first power supply VDD, the second power supply VSS, the initialization power supply Vint, and the bias power supply Vbs.

[0070] The data driver 600 may convert the adjusted image data RGB into a data signal in an analog form and supply the data signal to a plurality of data lines D according to a data driving control signal DCS.

[0071] The data driver 600 supplies data signals to the plurality of data lines D during one frame period according to an image refresh rate. For example, the data driver 600 supplies data signals to the plurality of data lines D at a frequency equal to the image refresh rate. The data signals supplied to the plurality of data lines D may be supplied in synchronization with the scan signal supplied to the first scan line S1.

[0072] The first scan driver 200 supplies a scan signal to the plurality of first scan lines S1 based on a first scan drive control signal SCS1. For example, the first scan driver 200 may sequentially supply the first scan signal to the plurality of first scan lines S1. The first scan signal is set to a gate-on voltage, thereby turning on the plurality of transistors included in the plurality of pixels PX.

[0073] In an exemplary embodiment, the first scan driver 200 may supply a first scan signal to the plurality of first scan lines S1 during a first period. The first period may be repeated at a frequency (e.g., a first frequency) equal to the image refresh rate of the display device 1000. The first scan driver 200 may supply the first scan signal at a frequency equal to the image refresh rate. For example, when the first frequency is 120 Hz, the first period may be repeated at 120 Hz.

[0074] The first period may include an emission period and a non-emission period. The first period may be a period in which a data signal corresponding to an image is written into the pixel PX. Accordingly, the first period may be defined as a data programming subframe.

[0075] The second scan driver 300 supplies a scan signal to the plurality of second scan lines S2 based on the second scan drive control signal SCS2. For example, the second scan driver 300 may sequentially supply the second scan signal to the plurality of second scan lines S2. The second scan signal is set to a gate-on voltage, thereby turning on the plurality of transistors included in the plurality of pixels PX.

[0076] In an exemplary embodiment, the second scan driver 300 may supply the second scan signal to the plurality of second scan lines S2 in the first period. As such, the second scan driver 300 may supply the second scan signal to the plurality of second scan lines S2 at a frequency equal to an image refresh rate.

[0077] The third scan driver 400 supplies a scan signal to the plurality of third scan lines S3 based on a third scan drive control signal SCS3. For example, the third scan driver 400 may sequentially supply the third scan signal to the plurality of third scan lines S3. The third scan signal is set to a gate-on voltage, thereby turning on the plurality of transistors included in the plurality of pixels PX.

[0078] Among the first scan signal to the third scan signal, the gate-on voltage of the scan signal supplied to the P-type transistor may have a low level (or a logic low level), and among the first scan signal to the third scan signal, the gate-on voltage of the scan signal supplied to the N-type transistor may have a high level (or a logic high level).

[0079] In an exemplary embodiment, the third scan driver 400 may supply the third scan signal to the plurality of third scan lines S3 in the first period and the second period. As such, the third scan driver 400 may supply the third scan signal to the plurality of third scan lines S3 regardless of the image refresh rate.

[0080] When the display device 1000 is driven at a low frequency, the second period may be activated. For example, when the image refresh rate is lower than the first frequency, the second period immediately after the first period may be activated at least once.

[0081] For example, the second period may include an emission period and a non-emission period. The second period may be a bias period in which a bias is applied to the pixel PX by the third scan signal. For example, in response to the third scan signal, a predetermined bias voltage may be applied to the source electrode and / or drain electrode of the drive transistor of the pixel PX, and the drive transistor may be biased on. Since the second period is a drive period applied to low-frequency drive and is a period in which the image programmed in the first period is maintained, the second period may be defined as a hold subframe.

[0082] The number of consecutive repetitions of the second period (eg, the total length of consecutive second periods) may be changed according to the image refresh rate.

[0083] The emission driver 500 may receive an emission driving control signal ECS from the timing controller 700 and supply an emission control signal to the plurality of emission control lines E based on the emission driving control signal ECS. For example, the emission driver 500 may supply the emission control signal to the plurality of emission control lines E sequentially.

[0084] When the emission control signal is sequentially supplied to the plurality of emission control lines E, the plurality of pixels PX do not emit light in units of horizontal lines. To this end, the emission control signal is set to a gate-off voltage (e.g., a high level) so that some transistors (e.g., P-type transistors) included in the plurality of pixels PX can be turned off.

[0085] The emission control signal is used to control the emission time of the pixel PX. To this end, the emission control signal may be set to have a width wider than that of the first to third scan signals.

[0086] The emission driver 500 may supply the emission control signal to the emission control line E in the first period and the second period. In particular, the emission driver 500 may output the emission control signal at the second frequency regardless of the image refresh rate (eg, the first frequency).

[0087] For example, when the second frequency (i.e., the output frequency of the emission control signal) is 120 Hz and the first frequency (i.e., the image refresh rate) is 60 Hz, the first period and one second period may be repeated alternately. When the second frequency is 120 Hz and the first frequency is 30 Hz, the first period and two second periods may be repeated alternately.

[0088] In an exemplary embodiment, when the first frequency and the second frequency are the same, only the first period may be repeated.

[0089] The plurality of scan drivers 200 , 300 , and 400 may include a plurality of stages configured to shift scan signals, and the emission driver 500 may include a plurality of stages configured to shift emission control signals.

[0090] The power supplier 800 may supply at least one of a first power source VDD, a second power source VSS, an initialization power source Vint, and a bias power source Vbs to the pixel unit 100 based on a power control signal PCS.

[0091] In addition, depending on the circuit structure of the plurality of pixels PX, the pixel PX located on the current horizontal line (or current pixel row) may be additionally connected to the scan line located on the previous horizontal line (or previous pixel row) and / or the scan line located on the next horizontal line (or next pixel row). To this end, a dummy scan line and / or a dummy emission control line may be additionally formed.

[0092] High-speed driving of the display device 1000 may be required to achieve high resolution or stereoscopic images, etc. In addition, to ensure at least a certain level of image quality, it may be necessary to sufficiently ensure the time required to compensate for the threshold voltage of the driving transistor.

[0093] Figure 2 is a diagram showing a method according to an exemplary embodiment Figure 1, a circuit diagram of a pixel 10 included in a display device 1000 is shown in FIG.

[0094] exist Figure 2 , a circuit diagram of a pixel 10 located on an i-th horizontal line and connected to a j-th data line Dj is exemplarily shown.

[0095] Reference Figure 2 , the pixel 10 may include a light emitting device LD, first to eighth transistors M1 to M8, and a storage capacitor Cst.

[0096] A first electrode (anode electrode or cathode electrode) of the light emitting device LD may be connected to the fourth node N4, and a second electrode (cathode electrode or anode electrode) of the light emitting device LD may be connected to the second power supply VSS. The light emitting device LD generates light having a predetermined brightness corresponding to the amount of current supplied from the first transistor M1.

[0097] In an exemplary embodiment, the light-emitting device LD may be an organic light-emitting diode including an organic light-emitting layer. In another exemplary embodiment, the light-emitting device LD may be an inorganic light-emitting device formed of an inorganic material. Alternatively, the light-emitting device LD may include a plurality of inorganic light-emitting devices connected in parallel and / or in series between the second power source VSS and the fourth node N4.

[0098] A first electrode of the first transistor M1 (or driving transistor) may be connected to a first node N1, and a second electrode of the first transistor M1 may be connected to a third node N3. A gate electrode of the first transistor M1 may be connected to a second node N2. The first transistor M1 may control the amount of current flowing from the first power supply VDD to the second power supply VSS via the light-emitting device LD according to the voltage of the second node N2. To this end, the first power supply VDD may be set to a voltage higher than the voltage of the second power supply VSS.

[0099] The second transistor M2 may be connected between the data line Dj and the first node N1. A gate electrode of the second transistor M2 may be connected to the i-th first scan line S1i. When the first scan signal is supplied to the i-th first scan line S1i, the second transistor M2 is turned on to electrically connect the data line Dj and the first node N1 to each other.

[0100] The third transistor M3 may be connected between the second electrode (i.e., the third node N3) and the second node N2 of the first transistor M1. The gate electrode of the third transistor M3 may be connected to the i-th second scan line S2i. When the second scan signal is supplied to the i-th second scan line S2i, the third transistor M3 is turned on to electrically connect the second electrode of the first transistor M1 and the second node N2 to each other. For its part, when the third transistor M3 is turned on, the first transistor M1 is diode-connected.

[0101] In an exemplary embodiment, the third transistor M3 may be formed as an oxide semiconductor transistor. For example, the third transistor M3 may be an N-type oxide semiconductor transistor and include an oxide semiconductor layer as an active layer. Accordingly, the gate-on voltage at which the third transistor M3 is turned on may have a high level.

[0102] Oxide semiconductor transistors can be formed through a low-temperature process and have charge mobility lower than that of polysilicon semiconductor transistors. In itself, when the third transistor M3 is formed as an oxide semiconductor transistor, leakage current from the second node N2 can be minimized, and accordingly, display quality can be improved.

[0103] The fourth transistor M4 may be turned on by the third scan signal supplied to the i-th third scan line S3i to supply a bias voltage to the first node N1. In an exemplary embodiment, the fourth transistor M4 may be connected between the first node N1 and the bias power supply Vbs. A gate electrode of the fourth transistor M4 may be connected to the i-th third scan line S3i.

[0104] The fifth transistor M5 may be connected between the first power supply VDD and the first node N1. A gate electrode of the fifth transistor M5 may be connected to the i-th emission control line Ei. The fifth transistor M5 is turned off when an emission control signal is supplied to the i-th emission control line Ei, and is turned on otherwise.

[0105] The sixth transistor M6 may be connected between the second electrode (i.e., the third node N3) of the first transistor M1 and the first electrode (i.e., the fourth node N4) of the light emitting device LD. The gate electrode of the sixth transistor M6 may be connected to the i-th emission control line Ei. When the emission control signal is supplied to the i-th emission control line Ei, the sixth transistor M6 is turned off, and otherwise turned on.

[0106] In an exemplary embodiment, each of the fifth transistor M5 and the sixth transistor M6 may be a P-type polysilicon semiconductor transistor.

[0107] The seventh transistor M7 may be connected between the third node N3 and the initialization power supply Vint. A gate electrode of the seventh transistor M7 may be connected to the (i-1)th first scan line S1i-1. When a scan signal is supplied to the (i-1)th first scan line S1i-1, the seventh transistor M7 is turned on to supply the voltage of the initialization power supply Vint to the third node N3.

[0108] The seventh transistor M7 may be turned on when the third transistor M3 is turned on. For its part, the voltage of the initialization power source Vint may be supplied to the second node N2 through the third node N3.

[0109] In an exemplary embodiment, the voltage of the initialization power supply Vint is set to a voltage lower than the voltage of the data signal supplied to the data line Dj. Accordingly, when the seventh transistor M7 is turned on, the gate voltage of the first transistor M1 may be initialized to the voltage of the initialization power supply Vint.

[0110] The eighth transistor M8 may be connected between the initialization power source Vint and the fourth node N4. In an exemplary embodiment, a gate electrode of the eighth transistor M8 may be connected to the i-th third scan line S3i.

[0111] When the third scan signal is supplied, the eighth transistor M8 is turned on to supply the voltage of the initialization power supply Vint to the first electrode of the light-emitting device LD. When the voltage of the initialization power supply Vint is supplied to the first electrode of the light-emitting device LD, the parasitic capacitor of the light-emitting device LD can be discharged. The residual voltage stored in the parasitic capacitor is discharged (or removed), thereby preventing unintended fine light emission. Accordingly, the ability to represent black in the pixel 10 can be improved.

[0112] In an exemplary embodiment, the plurality of transistors M1, M2, M4, M5, M6, M7, and M8, excluding the third transistor M3, may be implemented using polysilicon transistors and include a polysilicon semiconductor layer as an active layer (or channel). For example, the active layer may be formed using a low-temperature polysilicon (LTPS) process. For example, each of the plurality of transistors M1, M2, M4, M5, M6, M7, and M8 may be a P-type polysilicon transistor.

[0113] Since polycrystalline silicon semiconductor transistors have a high response speed, polycrystalline silicon semiconductor transistors can be applied to switching elements that require fast switching.

[0114] However, the inventive concept is not limited thereto, and in some exemplary embodiments, at least some of the first to eighth transistors M1 to M8 may be implemented with oxide semiconductor transistors, while the rest of the first to eighth transistors M1 to M8 may be implemented with polysilicon transistors.

[0115] Figure 3 is a diagram showing a method according to an exemplary embodiment Figure 2 A timing diagram of the operation of the pixel 10 is shown in FIG.

[0116] Reference Figures 1 to 3 , a signal for image display may be supplied to the pixel 10 during the first period P1. The first period P1 may include a period in which a data signal DS substantially corresponding to an output image is written.

[0117] Hereinafter, the i-th emission control line Ei may also be referred to as the emission control line Ei, and the plurality of i-th scan lines S1i, S2i, and S3i may also be referred to as the first scan line S1i, the second scan line S2i, and the third scan line S3i, respectively.

[0118] The pixel 10 and the display device 1000 may operate in a period divided into an emission period EP and a non-emission period NEP.

[0119] Figure 3 The operation of the pixel 10 during the first period P1 is shown. For example, the display device 1000 may be driven in a first mode, and in the first mode, an image is displayed at a first frequency.

[0120] When the display device 1000 is driven in the first mode, the first scan signal and the second scan signal may be supplied at the first frequency to the pixel 10. The third scan signal and the emission control signal may also be supplied at the first frequency.

[0121] A period during which the emission control signal is supplied to the i-th light emitting control line Ei (i.e., a period during which the emission control signal having a high level is supplied) is a non-emission period NEP of the pixel 10. A period during which the emission control signal is not supplied to the i-th emission control line Ei (i.e., a period during which the emission control signal having a low level is supplied) is an emission period EP of the pixel 10.

[0122] In the non-emission period NEP, the fifth transistor M5 and the sixth transistor M6 are turned off by the emission control signal, and thus, the pixel 10 does not emit light.

[0123] The non-emission period NEP may include a first bias period BP1, an initialization period IP, a writing period WP, ​​a compensation period CP, and a second bias period BP2. The second scan signal may be maintained during the initialization period IP, the writing period WP, ​​and the compensation period CP. The third scan signal may be supplied during the first bias period BP1 and the second bias period BP2.

[0124] In an exemplary embodiment, each of the initialization period IP and the writing period WP is a period in which the first scan signal is supplied, and may correspond to approximately one horizontal period.

[0125] After the emission control signal is supplied to the emission control line Ei, a third scan signal may be supplied to the third scan line S3i during the first bias period BP1. The third scan signal is a signal for controlling a P-type transistor and has a low level.

[0126] Although Figure 3The pulse width of the third scan signal is exemplarily shown to be three horizontal periods or more, however, the present inventive concept is not limited thereto. For example, in some exemplary embodiments, the pulse width of the third scan signal may be one horizontal period or more.

[0127] In the first bias period BP1, the fourth transistor M4 and the eighth transistor M8 may be turned on in response to the third scan signal. When the fourth transistor M4 is turned on, the voltage of the bias power supply Vbs may be supplied to the first node N1, and the first transistor M1 may be in an on-bias state (i.e., on-biased). Accordingly, a voltage of the bias power supply Vbs having a constant value is supplied, and thus, the hysteresis characteristic of the first transistor M1 can be improved. The voltage of the bias power supply Vbs may be approximately 5V or higher. For example, the voltage of the bias power supply Vbs may be in a range of approximately 5V to approximately 8V. The voltage level of the bias power supply Vbs can be easily controlled according to the driving conditions of the display device 1000. In addition, the bias power supply Vbs is implemented as a DC voltage source, so that the bias difference between the first transistors M1 of each pixel can be reduced.

[0128] In addition, when the eighth transistor M8 is turned on, the voltage of the initialization power source Vint may be supplied to the first electrode of the light emitting device LD. When the voltage of the initialization power source Vint is supplied to the first electrode of the light emitting device LD, the parasitic capacitor of the light emitting device LD may be discharged.

[0129] After the first bias period BP1 ends, a second scan signal may be supplied to the second scan line S2i. When the second scan signal is supplied to the second scan line S2i, the third transistor M3 may be turned on. The second scan signal may have a pulse width of four horizontal periods or more. The third transistor M3 remains turned on for a long time.

[0130] In addition, the first scan signal supplied to the (i+1)th first scan line S1i+1 and the (i+2)th first scan line S1i+2 may overlap with the second scan signal supplied to the second scan line S2i. In an exemplary embodiment, the second scan signal supplied to the second scan line S2i may be supplied to pixels on the (i+1)th horizontal line and pixels on the (i+2)th horizontal line.

[0131] The second scan signal is a signal for controlling the N-type transistor and has a high level.

[0132] The initialization period IP and the write period WP may be performed in a state in which the third transistor M3 is turned on.

[0133] During the initialization period IP, the first scan signal is supplied to the previous first scan line S1i-1. When the first scan signal is supplied to the previous first scan line S1i-1, the seventh transistor M7 may be turned on. Since the third transistor M3 is in the on state, the voltage of the initialization power supply Vint may be supplied to the second node N2 through the seventh transistor M7 and the third transistor M3. Therefore, the gate voltage of the first transistor M1 may be initialized.

[0134] In some exemplary embodiments, the voltage level of the initialization power source Vint is controlled so that the degree of on-bias of the first transistor M1 can be controlled.

[0135] In the writing period WP, ​​the first scan signal is supplied to the first scan line S1i. When the first scan signal is supplied to the first scan line S1i, the second transistor M2 may be turned on. When the second transistor M2 is turned on, the data signal DS may be supplied to the first node N1.

[0136] Since the third transistor M3 is in the on state, the first transistor M1 is diode-connected and can compensate for the threshold voltage of the first transistor M1. For example, the compensation period CP may include a writing period WP.

[0137] Subsequently, driving for threshold voltage compensation may be maintained until supply of the second scan signal stops.

[0138] When the display device is driven at high speed, the time of one horizontal period can be shortened, and therefore, sufficient threshold voltage compensation may not occur. However, in the display device 1000 according to the exemplary embodiment, the third transistor M3 maintains the on state for five horizontal periods or longer, and therefore, the threshold voltage compensation time can be sufficiently ensured. Accordingly, the image deviation caused by the threshold voltage deviation of the first transistor M1 can be minimized.

[0139] After the compensation period CP ends, the third scan signal may be supplied to the third scan line S3i again during the second bias period BP2. In the second bias period BP2, the fourth transistor M4 and the eighth transistor M8 may be turned on in response to the third scan signal. The operation of the second bias period BP2 is substantially the same as that of the first bias period BP1, and therefore, a repeated description thereof will be omitted.

[0140] In an exemplary embodiment, the plurality of bias periods BP1 and BP2 and the period for supplying the second scan signal to the second scan line S2i do not overlap with each other. More specifically, the on-period of the third transistor M3 and the on-period of the fourth transistor M4 do not overlap with each other.

[0141] Subsequently, the emission control signal is stopped from being supplied to the emission control line Ei. When the emission control signal is stopped, the fifth transistor M5 and the sixth transistor M6 are turned on. The first transistor M1 controls the amount of drive current flowing through the light-emitting device LD according to the voltage of the second node N2. The light-emitting device LD then generates light having a brightness corresponding to the amount of drive current during the emission period EP.

[0142] As described above, in the pixel 10 and the display device 1000 according to the exemplary embodiment, a relatively stable on-bias can be applied to the first transistor M1 before / after initialization and data writing (i.e., the first transistor can be stably on-biased), thereby minimizing image flickering, afterimages, and the like due to the hysteresis characteristics of the first transistor M1. In addition, since the third transistor M3 is turned on for a relatively long time (e.g., five horizontal periods or more, or 5 μs or more) according to the high-speed driving of 120 Hz, sufficient time for threshold voltage compensation can be ensured, thereby improving image quality.

[0143] Figure 4 is a diagram showing a method according to another exemplary embodiment Figure 2 A timing diagram of the operation of the pixel 10 is shown in FIG.

[0144] Reference Figures 1 to 4 , the pixel 10 may be supplied with a signal for image display to display an image during the first period P1 , and maintain the image displayed in the first period P1 during the second period P2 .

[0145] Figure 4 The display device 1000 is shown as being driven at a low frequency. For example, the display device 1000 may be driven in a second mode, and in the second mode, an image is displayed by driving the display device 1000 at a low frequency.

[0146] The first scanning signal and the second scanning signal may be supplied to the pixel 10 at a frequency corresponding to the image refresh rate of the display device 1000. Figure 3 The third scanning signal and the emission control signal are supplied to the pixel 10 at the supply timing of the scanning signal and the emission control signal shown in , regardless of the image refresh rate.

[0147] The operation of the first period P1 is Figure 3 The operation of the pixel 10 shown in FIG. 1 is substantially the same.

[0148] In the second period P2, the same emission control signal as that in the first period P1 may be provided. More specifically, the second period P2 may include an emission period EP and a non-emission period NEP. In the second period P2, the first scan signal and the second scan signal are not provided as a holding subframe.

[0149] In an exemplary embodiment, the data signal DS corresponding to the image to be displayed during the second period P2 may not be supplied. For example, any data signal DS may be supplied during the second period P2, or the data signal DS may have a state for minimizing power consumption.

[0150] The non-emission period NEP of the second period P2 may include a third bias period BP3. The third scan signal may be supplied to the third scan line S3i during the third bias period BP3. Figure 4 , although the length of the third scan signal supplied in the second period P2 is shown to be longer than the length of the third scan signal supplied in the first period P1, the present inventive concept is not limited thereto. For example, in some exemplary embodiments, the pulse width of the third scan signal supplied in the third bias period BP3 may be one horizontal period or more.

[0151] When the third scan signal is supplied to the third scan line S3i, the fourth transistor M4 and the eighth transistor M8 may be turned on. When the fourth transistor M4 is turned on, the voltage of the bias power supply Vbs may be supplied to the first node N1, and the first transistor M1 may be in an on-bias state (i.e., on-biased). When the eighth transistor M8 is turned on, the voltage of the initialization power supply Vint may be supplied to the first electrode of the light-emitting device LD.

[0152] Accordingly, since the on bias is applied to the first transistor M1 in the second period P2 for maintaining an image, image flickering, afterimage, etc. due to hysteresis characteristics of the first transistor M1 in low-frequency driving can be minimized.

[0153] Meanwhile, the number of times the second period P2 is continuously repeated may vary according to the image refresh rate.

[0154] Figure 5A is a diagram showing a method according to an exemplary embodiment Figure 1 A diagram showing connections between pixels and signal lines included in a display device 1000 is shown in FIG.

[0155] Reference Figure 1 、 Figure 2 and Figure 5A , the first to third scan lines and the emission control lines can be connected to respective pixels PXi, PXi+1, and PXi+2.

[0156] The first scan driver 200 may sequentially supply first scan signals to a plurality of first scan lines S1i-1 to S1i+2. The second scan driver 300 may sequentially supply second scan signals to a plurality of second scan lines S2i to S2i+2. The third scan driver 400 may sequentially supply third scan signals to a plurality of third scan lines S3i to S3i+2.

[0157] As mentioned above Figure 2 As described, the i-th pixel PXi may be connected to the i-1-th first scan line S1i-1, the i-th first scan line S1i, the i-th second scan line S2i, the i-th third scan line S3i, and the i-th emission control line Ei.

[0158] The i+1th pixel PXi+1 can be connected to the i-th first scan line S1i, the i+1th first scan line S1i+1, the i+1th second scan line S2i+1, the i+1th third scan line S3i+1 and the i+1th emission control line Ei+1.

[0159] The i+2th pixel PXi+2 can be connected to the i+1th first scan line S1i+1, the i+2th first scan line S1i+2, the i+2th second scan line S2i+2, the i+2th third scan line S3i+2 and the i+2th emission control line Ei+2.

[0160] As described above, in order to drive the plurality of pixels PXi, PXi+1, and PXi+2 corresponding to respective horizontal lines (or pixel rows), the first scan driver 200, the second scan driver 300, and the third scan driver 400, as well as the emission driver 500, may include stages corresponding to the respective horizontal lines. For their part, different timing signals may be supplied to different signal lines.

[0161] Figure 5B is a diagram showing a method according to another exemplary embodiment Figure 1 A diagram showing connections between pixels and signal lines included in a display device 1000 is shown in FIG.

[0162] exist Figure 5B In, with reference Figure 5A Components identical to those described above are designated by similar reference numerals, and therefore, repeated descriptions of substantially identical components will be omitted. In addition, except for the second scan line and the third scan line, Figure 5B The connections between the pixels and signal lines shown in Figure 5A The connections shown in are substantially the same or similar.

[0163] Reference Figure 1 、 Figure 2 and Figure 5B, the first to third scan lines and the emission control lines can be connected to respective pixels PXi, PXi+1, and PXi+2.

[0164] In an exemplary embodiment, the i-th second scan line S2i, the i+1-th second scan line S2i+1, and the i+2-th second scan line S2i+2 may commonly receive the k-th (k is a natural number i or less) second scan signal SS2k. More specifically, the i-th second scan line S2i, the i+1-th second scan line S2i+1, and the i+2-th second scan line S2i+2 share the k-th second scan signal SS2k.

[0165] As such, the same second scan signal (ie, SS2k) may be synchronously supplied to the i-th pixel PXi, the (i+1)-th pixel PXi+1, and the (i+2)-th pixel PXi+2.

[0166] like Figure 3 and Figure 4 As shown in , the pulse width of the second scan signal may overlap with a plurality of first scan signals (e.g., six or more first scan signals). Therefore, although a common second scan signal (i.e., SS2k) is supplied to the i-th pixel PXi, the (i+1)-th pixel PXi+1, and the (i+2)-th pixel PXi+2, initialization, writing, and compensation operations for each of the i-th pixel PXi, the (i+1)-th pixel PXi+1, and the (i+2)-th pixel PXi+2 can be performed without error.

[0167] Accordingly, the number of stages included in the second scan driver 300 for outputting the second scan signal can be reduced to Figure 5A In this way, manufacturing costs, dead space and power consumption can be reduced.

[0168] Similarly, the i-th third scan line S3i, the i+1-th third scan line S3i+1, and the i+2-th third scan line S3i+2 can commonly receive the k-th third scan signal (i.e., SS3k). More specifically, the i-th third scan line S3i, the i+1-th third scan line S3i+1, and the i+2-th third scan line S3i+2 share the k-th third scan signal (i.e., SS3k).

[0169] As such, the same third scan signal (ie, SS3k) may be synchronously supplied to the i-th third scan line S3i, the i+1-th third scan line S3i+1, and the i+2-th third scan line S3i+2.

[0170] Accordingly, the i-th third scan line S3i, the i+1-th third scan line S3i+1, and the i+2-th third scan line S3i+2 can simultaneously have the first bias period BP1 to the third bias period BP3.

[0171] In addition, the number of stages included in the third scan driver 400 can be reduced to Figure 5A 1 / 3 or less of the amount shown in . This, in itself, can reduce manufacturing costs, dead space, and power consumption.

[0172] However, the present invention is not limited to a specific number of second scan lines that share the second scan signal and a specific number of third scan lines that share the third scan signal. For example, in some exemplary embodiments, the second scan signal may be shared in units of two second scan lines, and the third scan signal may be shared in units of six third scan lines.

[0173] Figure 6A and 6B is a diagram showing a method according to an exemplary embodiment Figure 2 A timing diagram of the operation of the pixel 10 is shown in FIG.

[0174] Reference Figure 6A and Figure 6B , the times and lengths of the plurality of bias periods BP1 and BP2 during the first period P1 may be variously controlled.

[0175] In an exemplary embodiment, Figure 6A As shown in , the bias period BP1 in the first period P1 may be activated before the initialization period IP. Specifically, after the third scan signal is supplied to the third scan line S3i in the first period P1, the first scan signal may be supplied to the i-1th first scan line S1i-1. As such, the length of the bias period BP1 may be one horizontal period or longer.

[0176] In another exemplary embodiment, Figure 6B As shown in , the bias period BP2 may be activated after the compensation period CP. In particular, after the second scan signal is supplied to the second scan line S2i, the third scan signal may be supplied to the third scan line S3i. The length of the bias period BP2 may be one horizontal period or longer.

[0177] As described above, the voltage of the bias power source Vbs is supplied to the first transistor M1 in the optimal period during the non-emission period NEP, thereby making it possible to minimize image flickering, afterimage, etc. due to hysteresis characteristics of the first transistor M1.

[0178] Figure 7 is a diagram showing a method according to another exemplary embodiment Figure 2 A timing diagram of the operation of the pixel 10 is shown in FIG.

[0179] exist Figure 7 In the above reference Figure 3 and Figure 4The same components as those described above are designated with the same reference numerals, and therefore, repeated description of substantially the same components will be omitted. In addition, except for the initialization power supply Vint and the bias power supply Vbs, Figure 7 The operation of the pixel 10 and the display device 1000 shown in FIG. 1 may be similar to that of FIG. Figure 3 and Figure 4 are substantially the same or similar as shown in .

[0180] Reference Figure 1 、 Figure 2 and Figure 7 , the pixel 10 may be supplied with a signal for image display to display an image during the first period P1 , and maintain the image displayed in the first period P1 during the second period P2 .

[0181] In an exemplary embodiment, the power supplier 800 may supply the bias power Vbs having different voltage levels in the first period P1 and the second period P2. Figure 7 As shown in FIG, the second voltage level of the bias power source Vbs supplied in the second period P2 may be lower than the first voltage level of the bias power source Vbs supplied in the first period P1.

[0182] More specifically, in the first period P1, a stronger on-bias than the on-bias in the second period P2 may be applied to the first transistor M1. However, the present inventive concept is not limited thereto, and in some exemplary embodiments, the second voltage level may be higher than the first voltage level. That is, in the second period P2, a stronger on-bias than the on-bias in the first period P1 may be applied to the first transistor M1.

[0183] In an exemplary embodiment, the initialization power supply Vint may also have different voltage levels in the first period P1 and the second period P2. For example, in the second period P2, an initialization voltage lower than the initialization voltage in the first period P1 may be applied to the gate electrode of the light emitting device LD and the first transistor M1.

[0184] For example, the voltage level of the initialization power source Vint may vary within a range of approximately -1 to -5V.

[0185] As described above, the voltage level of the bias power supply Vbs and / or the voltage level of the initialization power supply Vint can be adaptively controlled corresponding to the first period P1 and the second period P2, which in turn can further improve image quality in low-frequency driving.

[0186] Figure 8 is a diagram showing a method according to another exemplary embodiment Figure 2 A timing diagram of the operation of the pixel 10 is shown in FIG.

[0187] exist Figure 8In the above reference Figure 3 、 Figure 4 and Figure 7 The same components as those described above are designated with the same reference numerals, and therefore, repeated description of substantially the same components will be omitted. In addition, except for the initialization power supply Vint and the bias power supply Vbs, Figure 8 The operation of the pixel 10 and the display device 1000 shown in FIG. 1 may be similar to that of FIG. Figure 3 and Figure 4 are substantially the same or similar as shown in .

[0188] Reference Figure 1 、 Figure 2 、 Figure 7 and Figure 8 , the pixel 10 may be supplied with a signal for image display to display an image during the first period P1 , and maintain the image displayed in the first period P1 during the second period P2 .

[0189] As the image refresh rate decreases (ie, as the driving frequency decreases), the number of repetitions of the second period P2 may increase.

[0190] In an exemplary embodiment, the power supplier 800 may change the voltage level of the bias power source Vbs in a plurality of stages during the plurality of second periods P2.

[0191] In an exemplary embodiment, the voltage level of the bias power source Vbs may be increased corresponding to the repetition of the second period P2. As such, as time passes in one frame period, a stronger on-bias may be applied to the first transistor M1.

[0192] Meanwhile, the voltage level of the bias power supply Vbs returns to the lowest set value in the first period P1.

[0193] In an exemplary embodiment, the power supplier 800 may change the voltage level of the initialization power supply Vint in multiple stages during the plurality of second periods P2. For example, the voltage level of the initialization power supply Vint may be reduced. Therefore, as time passes in one frame period, a lower initialization voltage may be applied to the light emitting device LD.

[0194] Meanwhile, the voltage level of the initialization power source Vint returns to the highest set value in the first period P1.

[0195] like Figure 8 As shown in , in an exemplary embodiment, a change period of the bias power source Vbs and a change period of the initialization power source Vint may be different from each other.

[0196] As described above, the voltage level of the bias power supply Vbs and / or the voltage level of the initialization power supply Vint can be adaptively controlled corresponding to the first period P1 and the second period P2, which in turn can further improve image quality in low-frequency driving.

[0197] Figure 9 is a diagram showing a method according to another exemplary embodiment Figure 1 , a circuit diagram of a pixel 11 included in a display device 1000 is shown in FIG.

[0198] exist Figure 9 In the above reference Figure 2 Components identical to those described above are designated with similar reference numerals, and therefore, repeated descriptions of substantially identical components will be omitted. In addition, in addition to the first initialization power supply Vint1 and the second initialization power supply Vint2, Figure 9 The pixel 11 shown in FIG. Figure 2 The pixels 10 shown in FIG. 1 are substantially the same or similar.

[0199] Reference Figure 1 and Figure 9 , the pixel 11 may include a light emitting device LD, first to eighth transistors M1 to M8, and a storage capacitor Cst.

[0200] In exemplary embodiments, the seventh transistor M7 may be connected between the third node N3 and the first initialization power source Vint1 , and the eighth transistor M8 may be connected between the fourth node N4 and the second initialization power source Vint2 .

[0201] In particular, the power supplier 800 may generate a first initialization power Vint1 corresponding to a voltage supplied to the third node N3 and a second initialization power Vint2 corresponding to a voltage supplied to the fourth node N4 .

[0202] In low-frequency driving that extends the length of a frame period, when the voltage of the first initialization power supply Vint1 supplied to the third node N3 is too low, the hysteresis variation of the first transistor M1 in the corresponding frame period may be large. The hysteresis may cause a flicker phenomenon in low-frequency driving. As such, in a display device driven at a low frequency, a voltage of the first initialization power supply Vint1 higher than the voltage of the second power supply VSS may be required.

[0203] At the same time, the second initialization power source Vint2 may have a voltage lower than a predetermined reference, thereby preventing the voltage from being charged into the parasitic capacitor of the light-emitting device LD by the voltage of the second initialization power source Vint2, and the voltage of the second initialization power source Vint2 is supplied to the fourth node N4. For example, the second initialization power source Vint2 may have a voltage similar to the voltage of the second power source VSS. However, the present inventive concept is not limited thereto, and in some exemplary embodiments, the voltage of the second initialization power source Vint2 may be higher than the voltage of the second power source VSS according to the driving conditions of the display device.

[0204] Therefore, the image quality of the display device 1000 can be improved.

[0205] Figure 10 is a diagram showing a method according to another exemplary embodiment Figure 1 , a circuit diagram of a pixel 12 included in a display device 1000 is shown in FIG.

[0206] exist Figure 10 In the above reference Figure 9 Components identical to those described above are designated with similar reference numerals, and therefore, repeated descriptions of substantially identical components will be omitted. In addition, except for the third transistor M3, Figure 10 The pixel 12 shown in FIG. Figure 9 The pixels 11 shown in FIG. 1 are substantially the same or similar.

[0207] Reference Figure 10 , the pixel 12 may include a light emitting device LD, first to eighth transistors M1 to M8, and a storage capacitor Cst.

[0208] In an exemplary embodiment, the third transistor M3 may be a P-type polysilicon semiconductor transistor. A gate-on voltage of the second scan signal supplied to the second scan line S2i may be a low voltage.

[0209] Figure 10 The plurality of transistors M1 to M8 included in the pixel 12 shown in FIG are all formed by the LTPS process. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0210] Figure 11 is a diagram showing a method according to another exemplary embodiment Figure 1 , a circuit diagram of a pixel 13 included in a display device 1000 is shown in FIG.

[0211] exist Figure 11 In the above reference Figure 9 Components identical to those described above are designated with similar reference numerals, and thus, repeated descriptions of substantially identical components will be omitted. In addition, except for the fourth transistor M4, Figure 11The pixel 13 shown in FIG can be used with Figure 9 The pixels 11 shown in FIG. 1 are substantially the same or similar.

[0212] Reference Figure 11 , the pixel 13 may include a light emitting device LD, first to eighth transistors M1 to M8, and a storage capacitor Cst.

[0213] In an exemplary embodiment, the fourth transistor M4 may be connected between the first node N1 and the i-th emission control line Ei. When the third scan signal is supplied to the i-th third scan line S3i, the fourth transistor M4 may be turned on. When the fourth transistor M4 is turned on, a high-level emission control signal may be supplied to the first node N1. The first transistor M1 may be biased to be turned on by the high-level emission control signal.

[0214] Accordingly, the configuration for generating the bias power supply Vbs can be omitted, thereby reducing manufacturing costs and power consumption.

[0215] Figure 12 is a diagram showing a method according to an exemplary embodiment Figure 11 A timing diagram of the operation of the pixel 13 is shown in FIG.

[0216] exist Figure 12 In the above reference Figure 3 and Figure 4 Components identical to those described above are designated with similar reference numerals, and therefore, repeated descriptions of substantially identical components will be omitted. Figure 12 The operation of the display device 1000 shown in FIG. Figure 3 and Figure 4 The operations shown in are basically the same or similar.

[0217] Reference Figure 1 、 Figure 11 and Figure 12 , the pixel 13 may be supplied with a signal for image display to display an image during the first period P1 , and maintain the image displayed in the first period P1 during the second period P2 .

[0218] In an exemplary embodiment, the emission driver 500 may supply the high level of the emission control signal supplied in the first period P1 and the high level of the emission control signal supplied in the second period P2 as different voltage levels. For example, the high level of the emission control signal supplied in the second period P2 may be lower than the high level of the emission control signal supplied in the first period P1. Accordingly, a relatively low (weak) conduction bias may be applied in the second period P2.

[0219] However, the present inventive concept is not limited thereto, and in some exemplary embodiments, depending on the applied conditions, the high level of the emission control signal supplied in the second period P2 may be higher than the high level of the emission control signal supplied in the first period P1. Accordingly, a relatively strong on-bias may be applied in the second period P2.

[0220] As described above, in a display device including a pixel according to an exemplary embodiment, a stable DC conduction bias is applied to the first transistor before and after initialization and data writing, thereby minimizing image flickering, afterimages, and the like caused by the hysteresis characteristics of the first transistor. Furthermore, with high-speed driving of 120 Hz or higher, the third transistor is turned on for a relatively long time (e.g., five horizontal periods or longer, or 5 μs or longer). Therefore, sufficient time for threshold voltage compensation can be ensured, thereby improving image quality.

[0221] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that are apparent to those of ordinary skill in the art.

Claims

1. A display device, comprising: a plurality of pixels connected to a plurality of first scan lines, a plurality of second scan lines, a plurality of third scan lines, a plurality of emission control lines, and a plurality of data lines; a first scan driver configured to supply a first scan signal to each of the plurality of first scan lines in a first period; a second scan driver configured to supply a second scan signal to each of the plurality of second scan lines in the first period; a third scan driver configured to supply a third scan signal to each of the plurality of third scan lines in the first period and the second period; an emission driver configured to supply an emission control signal to each of the plurality of emission control lines in the first period and the second period; as well as a data driver configured to supply a data signal to each of the plurality of data lines in the first period, wherein the width of the second scanning signal is greater than the width of the first scanning signal, so that one of the plurality of second scanning signals overlaps with the plurality of first scanning signals during the first period; Among the plurality of pixels, the pixels located on the i-th horizontal line include: Light-emitting devices; a first transistor including a first electrode connected to a first node electrically connected to a first power source and configured to control a driving current based on a voltage of a second node; a third transistor connected between a third node and the second node and configured to be turned on in response to the second scan signal supplied to the i-th second scan line, the third node being connected to the second electrode of the first transistor; and a fourth transistor configured to be turned on in response to the third scan signal supplied to the i-th third scan line to supply a bias voltage to the first node; Wherein, i is a natural number, and The on-time period of the third transistor and the on-time period of the fourth transistor do not overlap with each other.

2. The display device according to claim 1, wherein The first scan driver is configured to sequentially supply the first scan signal to the plurality of first scan lines; and The second scan driver is configured to synchronously supply the second scan signal to at least two of the plurality of second scan lines.

3. The display device according to claim 2, wherein: The third scan driver is configured to synchronously supply the third scan signal to at least two of the plurality of third scan lines.

4. The display device according to claim 1, wherein The first period is configured to be repeated when the image refresh rate is a first frequency; and The second period is configured to be activated at least once immediately after the first period when the image refresh rate is less than the first frequency.

5. The display device according to claim 1, wherein Among the plurality of pixels, the pixels located on the i-th horizontal line also include: A second transistor is connected between one of the plurality of data lines and the first node and is configured to be turned on in response to the first scan signal supplied to the i-th first scan line. The display device according to claim 5 , wherein: The pixels located on the i-th horizontal line further include: a fifth transistor connected between the first power source and the first node and configured to be turned off in response to the emission control signal supplied to the i-th emission control line; a sixth transistor connected between the third node and the first electrode of the light emitting device and configured to be turned off in response to the emission control signal; a storage capacitor connected between the first power source and the second node; a seventh transistor connected between the third node and a first initialization power source and configured to be turned on in response to the first scan signal supplied to the (i-1)th first scan line; and An eighth transistor is connected between the first electrode of the light emitting device and a second initialization power source and is configured to be turned on in response to the third scan signal supplied to the i-th third scan line.

7. The display device according to claim 6, wherein: The seventh transistor and the second transistor are configured to be sequentially turned on when the third transistor is turned on.

8. The display device according to claim 7, wherein: The seventh transistor of the pixel located on the (i+1)th horizontal line and the second transistor of the pixel located on the (i+1)th horizontal line are configured to be sequentially turned on when the third transistor of the pixel located on the i-th horizontal line is turned on.

9. The display device according to claim 6, wherein: The second scan driver is configured to supply the second scan signal to the i-th second scan line a plurality of times in the first period.

10. The display device according to claim 6, further comprising: The power supplier is configured to supply a bias power corresponding to the bias voltage and the first initialization power and the second initialization power to the plurality of pixels. The display device according to claim 10 , wherein: The power supplier is configured to supply the bias power having a first voltage level in the first period, and to supply the bias power having a second voltage level different from the first voltage level in the second period.

12. The display device according to claim 10, wherein: The power supplier is configured to supply the first initialization power having a first voltage level in the first period, and to supply the first initialization power having a second voltage level different from the first voltage level in a second period.

13. The display device according to claim 11, wherein When the second period is repeated a plurality of times, the power supplier is configured to change a voltage level of at least one of the first initialization power source, the second initialization power source, and the bias power source in a plurality of stages.

14. The display device according to claim 6, wherein The fourth transistor is connected between the first node and the i-th emission control line.

15. The display device according to claim 14, wherein The emission driver is configured to supply a high level of the emission control signal supplied in the first period and a high level of the emission control signal supplied in the second period as different voltage levels.

16. A display device comprising: a pixel connected to a first scan line, a second scan line, a third scan line, an emission control line, and a data line; a first scan driver configured to supply a first scan signal to the first scan line in a first period; a second scan driver configured to supply a second scan signal to the second scan line during the first period; a third scan driver configured to supply a third scan signal to the third scan line in the first period and the second period; an emission driver configured to supply an emission control signal to the emission control line in the first period and the second period; as well as a data driver configured to supply a data signal to the data line in the first period, The width of the second scanning signal is greater than the width of the first scanning signal, so that the second scanning signal overlaps with a plurality of first scanning signals respectively supplied to a plurality of first scanning lines during the first period. The pixels include: Light-emitting devices; a first transistor including a first electrode connected to a first node electrically connected to a first power source and configured to control a driving current based on a voltage of a second node; a third transistor connected between a third node connected to the second electrode of the first transistor and the second node and configured to be turned on in response to the second scan signal supplied to the second scan line; and a fourth transistor configured to be turned on in response to the third scan signal supplied to the third scan line to supply a bias voltage to the first node, and The gate-on voltage of the third scan signal supplied to the third scan line does not overlap with the gate-on voltage of the second scan signal supplied to the second scan line.

17. The display device according to claim 16, wherein: The first period is configured to be repeated when the image refresh rate is a first frequency; and The second period is configured to be activated at least once immediately after the first period when the image refresh rate is less than the first frequency.

18. The display device according to claim 16, wherein: The plurality of first scan signals overlapping the second scan signal are sequentially supplied to consecutive first scan lines.

19. The display device according to claim 18, wherein A width of the third scan signal is greater than the width of the first scan signal.

20. The display device according to claim 19, wherein The third scan driver is configured to supply the third scan signal to the third scan line a plurality of times in the first period.

21. The display device according to claim 19, wherein A gate-on voltage of the first scan signal and the gate-on voltage of the third scan signal are different from the gate-on voltage of the second scan signal.

22. The display device according to claim 21, wherein The gate-on voltage of the first scan signal and the gate-on voltage of the third scan signal are logic low levels; and The gate-on voltage of the second scan signal is a logic high level.

23. The display device according to claim 16, wherein The pixel further comprises: The second transistor is connected between the data line and the first node and is configured to be turned on in response to the first scan signal supplied to the first scan line.

24. The display device according to claim 23, wherein The pixel further comprises: a fifth transistor connected between the first power source and the first node and configured to be turned off in response to the emission control signal supplied to the emission control line; a sixth transistor connected between the third node and the first electrode of the light emitting device and configured to be turned off in response to the emission control signal; and A storage capacitor is connected between the first power source and the second node.

25. The display device according to claim 24, wherein The pixel further comprises: a seventh transistor connected between the third node and a first initialization power source and configured to be turned on in response to a first scan signal supplied to a previous first scan line; and An eighth transistor is connected between the first electrode of the light emitting device and a second initialization power source and is configured to be turned on by the third scan signal supplied to the third scan line.

26. The display device according to claim 25, wherein The seventh transistor and the second transistor are configured to be sequentially turned on when the third transistor is turned on. 27 . The display device according to claim 23 , further comprising an electric supplier configured to supply a bias power corresponding to the bias voltage to the pixels.

28. The display device according to claim 27, wherein: The power supplier is configured to supply the bias power having a first voltage level in the first period, and to supply the bias power having a second voltage level different from the first voltage level in the second period.

29. The display device according to claim 27, wherein When the second period is repeated a plurality of times, the power supplier is configured to change a voltage level of the bias power supply in a plurality of stages.

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