Display device

Abstract

A display device is provided. The display device includes: a display panel including a plurality of gate lines, a data line and a pixel; a gate driver that provides a gate signal to the pixel through the plurality of gate lines; a data driver that provides a data voltage to the pixel through the data line; and a timing controller that obtains a precharge gray value based on the gray value of the pixel. The gate driver supplies a gate signal to the plurality of gate lines simultaneously in a first period, and sequentially supplies the gate signal to the plurality of gate lines in a second period. The data driver supplies a data voltage corresponding to the precharge gray value to the data line in the first period, and supplies a data voltage corresponding to the gray value of the pixel to the data line in the second period.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0132431 filed on October 23, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosure relates to a display device and a method of driving the display device. Background Art

[0003] The display device may include a display panel, a gate driver, a data driver, and a timing controller. The display panel may include a gate line, a data line, and a pixel. The gate driver may provide a gate signal to the pixel through the gate line. The data driver may provide a data voltage to the pixel through the data line. The timing controller may control the driving timing of each of the gate driver and the data driver.

[0004] If the resolution of the display device is increased and the driving frequency of the display device is increased, the time during which the switching element of the pixel can be turned on by the gate signal (e.g., the gate turn-on time) will be reduced, thereby reducing the charging time of the data voltage. As a result, the charging rate of the pixel will be reduced (or the charging time of the pixel will be reduced).

[0005] It will be understood that the background of the present technology section is intended, in part, to provide a useful background for understanding the technology. However, the background of the present technology section may also include ideas, concepts or cognitions that were not known or recognized as part of the subject matter disclosed herein before the corresponding effective filing date by a person skilled in the relevant art. Summary of the invention

[0006] The disclosed embodiments relate to a display device capable of improving a charging rate of a pixel and a method of driving the display device.

[0007] The disclosed embodiments relate to a display device capable of charging a desired data voltage to a pixel regardless of a data voltage charged in a previous frame (eg, N-1 Frame) and a method of driving the display device.

[0008] The disclosed embodiments may provide a display device, comprising: a display panel including a plurality of gate lines, a data line, and a pixel; a gate driver, which may provide a gate signal to the pixel through the plurality of gate lines; a data driver, which may provide a data voltage to the pixel through the data line; and a timing controller, which may obtain a precharged gray value based on the gray value of the pixel. The gate driver may simultaneously supply the gate signal to the plurality of gate lines in a first period, and sequentially supply the gate signal to the plurality of gate lines in a second period. The data driver may supply a data voltage corresponding to the precharged gray value to the data line in the first period, and supply a data voltage corresponding to the gray value of the pixel to the data line in the second period.

[0009] In an embodiment, the gate driver may simultaneously supply the gate signals to a predetermined number of gate lines in the first period.

[0010] In an embodiment, the plurality of gate lines may be divided into a first group to a kth group. The gate driver may simultaneously supply gate signals to the gate lines in the pth group included in the first group to the kth group in a first period, and sequentially supply gate signals to the gate lines included in the pth group in a second period. Here, k may be a natural number of 2 or more, and p may be a natural number of 1 or more.

[0011] In an embodiment, the first frame period may include a first subframe period to a k-th subframe period. The p-th subframe period among the first subframe period to the k-th subframe period may include a first period and a second period.

[0012] In an embodiment, a first precharge grayscale value corresponding to a data voltage supplied to a first data line among the data lines may be obtained based on grayscale values ​​of pixels electrically connected to the first data line and gate lines included in the p-th group.

[0013] In an embodiment, the first precharge gray value may be an average value of gray values ​​of pixels electrically connected to the first data line and gate lines included in the p-th group.

[0014] In an embodiment, the first precharge grayscale value may be half of a value obtained by subtracting a minimum value of the grayscale values ​​of pixels electrically connected to the first data line and the gate lines included in the pth group from a maximum value of the grayscale values ​​of pixels electrically connected to the first data line and the gate lines included in the pth group.

[0015] In an embodiment, the first precharge gray value may be an average value of a maximum value and a minimum value of gray values ​​of pixels electrically connected to the first data line and gate lines included in the p-th group.

[0016] In an embodiment, the timing controller may generate the first to qth gate clock signals. The gate driver may generate the gate signal based on the first to qth gate clock signals. Here, q may be a natural number of 2 or more.

[0017] In an embodiment, each of the first to qth gate clock signals may include pulses that may be simultaneously formed in the same segment during the first period and may be sequentially formed in different segments during the second period.

[0018] In an embodiment, the gate lines included in the p-th group may be adjacent to each other, and the number of the gate lines included in the p-th group may be a multiple of q.

[0019] In an embodiment, the number of gate clock signals may be q.

[0020] In an embodiment, pulse widths of gate signals simultaneously supplied to gate lines included in the p-th group in the first period may be equal to pulse widths of gate signals sequentially supplied to gate lines included in the p-th group in the second period.

[0021] In an embodiment, a pulse width of gate signals simultaneously supplied to gate lines included in the p-th group in the first period may be smaller than a pulse width of gate signals sequentially supplied to gate lines included in the p-th group in the second period.

[0022] The disclosed embodiments may provide a method for driving a display device, the method comprising: obtaining a precharged grayscale value based on a grayscale value of a pixel; supplying a gate signal to gate lines in a p-th group included in a first group to a k-th group at the same time in a first period; supplying a data voltage corresponding to the precharged grayscale value to the data line in the first period; sequentially supplying a gate signal to gate lines included in the p-th group in a second period; and supplying a data voltage corresponding to the grayscale value of the pixel to the data line in a second period. Here, p may be a natural number of 1 or more, and k may be a natural number of 2 or more.

[0023] In an embodiment, a first precharged gray value corresponding to a data voltage supplied to a first data line among the data lines may be an average value of gray values ​​of pixels electrically connected to the first data line and gate lines included in the p-th group.

[0024] In an embodiment, a first precharged grayscale value corresponding to a data voltage supplied to a first data line among the data lines may be half of a value obtained by subtracting a minimum value of the grayscale values ​​of pixels electrically connected to the first data line and gate lines included in the pth group from a maximum value of the grayscale values ​​of pixels electrically connected to the first data line and gate lines included in the pth group.

[0025] In an embodiment, a first precharged gray value corresponding to a data voltage supplied to a first data line among the data lines may be an average of maximum and minimum gray values ​​of pixels electrically connected to the first data line and gate lines included in the pth group.

[0026] In an embodiment, the method may further include: generating a first gate clock signal to a qth gate clock signal, and generating a gate signal based on the first gate clock signal to the qth gate clock signal. Each of the first gate clock signal to the qth gate clock signal may include pulses that may be simultaneously formed in the same segment during the first period and sequentially formed in different segments during the second period. Here, q may be a natural number of 2 or greater.

[0027] In an embodiment, the gate lines included in the p-th group may be adjacent to each other, and the number of the gate lines included in the p-th group may be a multiple of q.

[0028] In an embodiment, a pulse width of gate signals simultaneously supplied to gate lines included in the p-th group in the first period may be less than or equal to a pulse width of gate signals sequentially supplied to gate lines included in the p-th group in the second period. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other features of the disclosure will become more apparent by describing the disclosed embodiments in more detail with reference to the accompanying drawings.

[0030] Figure 1 is a diagram showing a display device according to an embodiment.

[0031] Figure 2 is a diagram showing the embodiment including Figure 1 An equivalent circuit diagram of a pixel in a display device.

[0032] Figure 3A is a diagram showing the Figure 1 Waveforms of a load signal, a gate clock signal, and a gate signal measured in a display device.

[0033] Figure 3B is a diagram showing the comparison example. Figure 1 Waveforms of a load signal, a gate clock signal, and a gate signal measured in a display device.

[0034] Figure 3C is a diagram showing the Figure 1 Waveforms of a load signal, a gate clock signal, and a gate signal measured in a display device.

[0035] FIG. 4A to FIG. 4D is shown by including Figure 1A diagram of a precharge grayscale value calculated or obtained by a timing controller in a display device.

[0036] Figure 5A is a diagram showing the Figure 1 Waveform diagram of a gate pulse start signal, a load signal, a data voltage, a gate signal, and a voltage for charging a pixel measured in a display device.

[0037] Figure 5B is a diagram showing the comparison example. Figure 1 Waveform diagram of a gate pulse start signal, a load signal, a data voltage, a gate signal, and a voltage for charging a pixel measured in a display device.

[0038] Figure 6 is a flowchart illustrating a method of driving a display device according to an embodiment. DETAILED DESCRIPTION

[0039] Although the disclosure can be modified in various ways and have additional embodiments, the embodiments are shown in the drawings and will be mainly described in the specification. However, the scope of the disclosure is not limited to the embodiments in the drawings and the specification, and should be interpreted as including all changes, equivalents and substitutes included in the spirit and scope of the disclosure.

[0040] In order to clearly describe the disclosure, parts not related to the description are omitted, and the same or similar components are represented by the same reference numerals throughout the specification. Therefore, the above reference numerals may be used in other drawings.

[0041] In addition, for the convenience of description, the size and thickness of the elements shown in the drawings are arbitrarily shown, and therefore the disclosure is not necessarily limited to the size and thickness of the elements shown in the drawings. In the drawings, the thickness may be exaggerated to clearly express each layer and region.

[0042] Furthermore, in the specification, the phrase "in a plan view" means a case where the target portion is viewed from above, and the phrase "in a schematic cross-sectional view" means a case where a schematic cross-section taken by vertically cutting the target portion is viewed from the side. Furthermore, in the present specification, the phrase "on a plane" means a case where the target portion is viewed from the top.

[0043] In addition, the term "overlap" or "coincidence" means that the first object can be above or below or on one side of the second object, and vice versa. In addition, as will be appreciated and understood by those of ordinary skill in the art, the term "overlap" can include stacking, stacking, facing or facing, extending above, covering or partially covering or any other suitable term. The terms "facing" and "facing" mean that the first element can be directly or indirectly opposite to the second element. In the case where the third element is between the first element and the second element, the first element and the second element can be understood to be indirectly opposite to each other. When an element is described as "not "overlapping" or "coinciding" with another element, it can include that the element and the other element are spaced apart from each other, offset from each other or separated from each other, or any other suitable term as will be appreciated or understood by those of ordinary skill in the art.

[0044] It will be understood that when an element such as a layer, film, region, substrate or area is referred to as being "on" another element, the element may be directly on the other element, or intervening elements may also be present. Conversely, when an element is referred to as being "directly on" another element, there may not be intervening elements between them.

[0045] In addition, when a layer, film, zone, substrate or region is referred to as "below" another layer, film, zone, substrate or region, the layer, film, zone, substrate or region may be directly below the other layer, film, zone, substrate or region, or there may be an intermediate layer, intermediate film, intermediate zone, intermediate substrate or intermediate region between them. Conversely, when a layer, film, zone, substrate or region is referred to as "directly below" another layer, film, zone, substrate or region, there may not be an intermediate layer, intermediate film, intermediate zone, intermediate substrate or intermediate region between them. In addition, "above" or "on" may include being located on or below an object, and does not necessarily imply a direction based on gravity.

[0046] For ease of description, spatially relative terms such as "below", "beneath", "below", "above", "above", etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the drawings. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, where the device shown in the drawings is reversed, a device "below" or "below" another device may be placed "above" another device. Thus, the illustrative term "below" may include both a position below and a position above. The device may also be oriented in other directions, so spatially relative terms may be interpreted differently depending on the orientation.

[0047] Throughout the specification, when an element is referred to as being "connected" to another element, the element may be "directly connected" to the other element, or "electrically connected" to the other element using one or more intermediate elements placed between the element and the other element. It will also be understood that when the terms "include" and / or "comprise" are used in this specification, they may specify the presence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of other features, wholes, steps, operations, elements, components and / or any combination thereof.

[0048] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, within the spirit and scope of the disclosure, a first component can be a second component, and vice versa.

[0049] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0050] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunctive or non-conjunctive sense and may be understood to be equivalent to "and / or". In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined in the specification, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted as an ideal or overly formal meaning.

[0052] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0053] Figure 1 is a diagram showing a display device 100 according to an embodiment.

[0054] Reference Figure 1 , the display device 100 may include a timing controller 110 , a gate driver 120 , a data driver 130 , a sensor 140 , and a display panel 150 .

[0055] The display panel 150 may include gate lines G1, G2...Gn (n is a positive integer), sensing lines S1, S2...Sn, data lines D1, D2...Dm (m is a positive integer), receiving lines R1, R2...Rm and pixels. Each pixel PXij (i and j are both positive integers) may be coupled to a corresponding or corresponding gate line, a corresponding or corresponding data line, a corresponding or corresponding sensing line and a corresponding or corresponding receiving line. Pixel PXij may refer to a pixel that may be electrically connected or electrically coupled to the i-th gate line and the j-th data line. Each pixel PXij may emit light in response to a data voltage supplied thereto by a corresponding or corresponding data line and a gate signal supplied thereto by a corresponding or corresponding gate line.

[0056] The timing controller 110 may provide a first control signal CONT1, for example, to the gate driver 120. Within the spirit and scope of the disclosure, the first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0057] In an embodiment, the timing controller 110 may generate the first to qth gate clock signals (q may be a natural number of 2 or greater). For example, the timing controller 110 may generate the first to sixth gate clock signals.

[0058] The timing controller 110 may provide the data signal DATA and the second control signal CONT2, for example, to the data driver 130. Within the spirit and scope of the disclosure, the second control signal CONT2 may include a horizontal start signal, a data clock signal, and a load signal.

[0059] In an embodiment, the timing controller 110 may calculate or obtain a precharge grayscale value based on the grayscale value of the pixel. For example, the precharge grayscale value may be an average value of the grayscale value of the pixel, half of a value obtained by subtracting a minimum value of the grayscale value of the pixel from a maximum value of the grayscale value of the pixel, or an average value of a maximum value and a minimum value of the grayscale value of the pixel. The precharge grayscale value may be included in the data signal DATA. FIG. 4A to FIG. 4D Describes a configuration for calculating or obtaining a precharge grayscale value.

[0060] The gate driver 120 may generate a gate signal and a sensing signal based on a first control signal CONT1 (e.g., provided from the timing controller 110), and provide the gate signal and the sensing signal to the gate lines G1, G2 ... Gn and the sensing lines S1, S2 ... Sn, respectively. For example, the gate driver 120 may provide the gate signal and the sensing signal, both of which have a conduction level (or conduction voltage level) pulse, to the gate lines G1, G2 ... Gn and the sensing lines S1, S2 ... Sn, respectively and sequentially. For example, the gate driver 120 may generate a scanning signal and a sensing signal in a scheme in which the conduction level pulse is sequentially transmitted to subsequent stages in response to a gate clock signal. For example, the gate driver 120 may be in the form of a shift register.

[0061] In an embodiment, the gate driver 120 may simultaneously supply gate signals to at least some of the gate lines G1, G2, ... Gn in a first period, and sequentially supply gate signals to the at least some of the gate lines in a second period. The at least some of the gate lines G1, G2, ... Gn may be a predetermined number of gate lines or a selected number of gate lines.

[0062] In an embodiment, the gate lines G1, G2, ..., Gn may be divided into the first gate line group to the kth gate line group (k may be a natural number of 2 or more) (or referred to as the first group to the kth group). The gate driver 120 may simultaneously supply gate signals to the gate lines in the pth gate line group (p may be a natural number greater than or equal to 1 and less than or equal to k) (or referred to as the pth group) included in the first gate line group to the kth gate line group in the first period, and sequentially supply gate signals to the gate lines included in the pth gate line group in the second period. The following will refer to FIG. 3A to FIG. 3C A detailed operation of the gate driver 120 is described.

[0063] The gate driver 120 may be implemented as an integrated circuit or may be implemented as a gate-in-panel (GIP) type and may be directly formed on the display panel 150. In some examples, the gate driver 120 may be integrated with the display panel 150.

[0064] Depending on the driving type, the gate driver 120 may be located or disposed only on one side of the display panel 150 (eg, Figure 1 ), or may be alternatively disposed on each of both sides of the display panel 150.

[0065] The data driver 130 may generate a data voltage using a data signal DATA and a second control signal CONT2 (e.g., provided from the timing controller 110). The data driver 130 may generate an analog data voltage based on the digital data signal DATA. For example, the data driver 130 may sample a grayscale value included in the data signal DATA and apply a data voltage corresponding to the grayscale value to the data lines D1, D2, ..., Dm per pixel row.

[0066] In an embodiment, the data driver 130 may supply a data voltage corresponding to the precharged gray value calculated or obtained by the timing controller 110 to the data lines D1, D2, ..., Dm in a first period, and supply a data voltage corresponding to the gray value of the pixel to the data lines D1, D2, ..., Dm in a second period. FIG. 4A to FIG. 5B A detailed operation of the data driver 130 is described.

[0067] The sensor 140 may measure information related to the characteristics of the pixel based on the current or voltage received through the receiving lines R1, R2, ... Rm. For example, the information related to the characteristics of the pixel may include mobility information and threshold voltage information of each of the driving transistors included in each pixel and degradation information of each of the light emitting elements included in each pixel.

[0068] Figure 2 is a diagram showing the embodiment including Figure 1 1 is an equivalent circuit diagram of a pixel PXij in the display device 100 .

[0069] Reference Figure 2 , the pixel PXij may include transistors M1, M2, and M3, a storage capacitor Cst, and a light emitting element LD. Each of the transistors M1, M2, and M3 may be formed of an N-type transistor.

[0070] At least one of the transistors M1, M2, and M3 may be formed by an oxide semiconductor thin film transistor including an active layer made of an oxide semiconductor. However, the disclosure is not limited thereto. For example, at least one of the transistors M1, M2, and M3 may be formed by an LTPS thin film transistor including an active layer made of polysilicon.

[0071] The first transistor M1 may include a gate electrode electrically connected to or electrically coupled to the first node Na, one electrode (or first electrode) electrically connected to or electrically coupled to the first power line VDD, and another electrode (or second electrode) coupled to the second node Nb. The first transistor M1 may be referred to as a driving transistor. The first transistor M1 may control the amount of current flowing from the first power line VDD to the second power line VSS via the light emitting element LD in response to the voltage of the first node Na.

[0072] The second transistor M2 may include a gate electrode electrically connected to or electrically coupled to the gate line Gi, a first electrode electrically connected to or electrically coupled to the data line Dj, and a second electrode electrically connected to or electrically coupled to the first node Na. In the spirit and scope of the disclosure, the second transistor M2 may be referred to as a switching transistor, a scanning transistor, etc. When a gate signal having a turn-on level is supplied to the gate line Gi, the second transistor M2 may be turned on so that the data line Dj may be electrically connected to or electrically coupled to the first node Na. Therefore, the second transistor M2 may transmit the data voltage supplied through the data line Dj to the gate electrode (or the first node Na) of the first transistor M1.

[0073] The third transistor M3 may include a gate electrode electrically connected to or electrically coupled to the sensing line Si, a first electrode coupled to the receiving line Rj, and a second electrode electrically connected to or electrically coupled to the second node Nb. In the spirit and scope of the disclosure, the third transistor M3 may be referred to as an initialization transistor, a sensing transistor, etc. When a sensing signal having a turn-on level is supplied to the sensing line Si, the third transistor M3 may be turned on so that the receiving line Rj may be electrically connected to the second electrode (or the second node Nb) of the first transistor M1 or electrically coupled to the second electrode (or the second node Nb) of the first transistor M1.

[0074] The storage capacitor Cst may include a first electrode electrically connected to or electrically coupled to the first node Na and a second electrode electrically connected to or electrically coupled to the second node Nb. The storage capacitor Cst may store the voltage of the first node Na. In other words, during a period (or gate-on time) in which the second transistor M2 is turned on in response to the gate signal, the data voltage supplied to the data line Dj may be transmitted to the first node Na, so that the data voltage may be charged to the storage capacitor Cst.

[0075] The light emitting element LD may include an anode coupled to the second node Nb and a cathode coupled to the second power line VSS. The light emitting element LD may emit light at a brightness corresponding to the amount of current supplied thereto through the second node Nb. The light emitting element LD may be formed of an organic light emitting diode or an inorganic light emitting diode, but the disclosure is not limited thereto.

[0076] Figure 3A is a diagram showing that according to an embodiment, Figure 1 The waveform diagram of the load signal TP, the gate clock signals GCLK1 to GCLK6 and the gate signals GATE1 to GATE12 measured in the display device 100 is shown in FIG. Figure 3B is a diagram showing that according to the comparative example, Figure 11 is a waveform diagram of a load signal TP, gate clock signals GCLK1 to GCLK6, and gate signals GATE1 to GATE12 measured in a display device 100.

[0077] Reference Figure 1 and Figure 3A , each frame (1 frame) period may include a first subframe period to a kth (k may be a natural number of 2 or more) subframe period SF1, SF2, .... Each of the first subframe period to the kth subframe period SF1, SF2, ... may include a first period P11, P21, ... and a second period P12, P22, ....

[0078] The load signal TP may be a square wave that may be repeated at a regular cycle (or at a cycle corresponding to the gate on time). In other words, the width of the first gate on time GOT1 may be the same as the width of the second gate on time GOT2. However, this is for illustrative purposes only, and the disclosure is not limited thereto. For example, the width of the first gate on time GOT1 may be smaller than the width of the second gate on time GOT2.

[0079] The data driver 130 may generate a data voltage based on a load signal TP and a data signal DATA provided from the timing controller 110. In an embodiment, the data voltage may be synchronized with the load signal TP. For example, the data voltage may be output synchronously with the rising edge of a logic high level pulse included in the load signal TP. The data driver 130 may sequentially supply the data voltage through the data lines D1, D2, ... Dm. In detail, in response to the rising edge of a first logic high level pulse included in the load signal TP, the data driver 130 may provide a data voltage to a pixel electrically connected to the first gate line G1 or electrically combined with the first gate line G1. Similarly, in response to the rising edge of a second logic high level pulse included in the load signal TP, the data driver 130 may provide a data voltage to a pixel electrically connected to the second gate line G2 or electrically combined with the second gate line G2.

[0080] The on-level pulse included in each of the gate clock signals GCLK1 to GCLK6 may be formed in synchronization with the load signal TP. For example, the on-level pulse included in each of the gate clock signals GCLK1 to GCLK6 may be formed in synchronization with a rising edge of a logic high level pulse included in the load signal TP.

[0081] In an embodiment, the on-level pulses included in the gate clock signals GCLK1 to GCLK6 may be simultaneously formed in the same section during the first period P11, and sequentially formed in different sections in the second period P12. For example, the on-level pulses included in each of the gate clock signals GCLK1 to GCLK6 may be simultaneously formed in response to the rising edge of the first logic high level pulse of the load signal TP that may be generated in the first period P11. The on-level pulses included in each of the gate clock signals GCLK1 to GCLK6 may be sequentially formed in response to the rising edges of the second logic high level pulse to the seventh logic high level pulse of the load signal TP that may be generated in the second period P12.

[0082] The gate driver 120 may generate gate signals GATE1 , GATE2 , . . . based on the gate clock signals GCLK1 to GCLK6 .

[0083] In an embodiment, the gate driver 120 may simultaneously supply gate signals GATE1 to GATE6 to at least some of the gate lines G1, G2, ... Gn in a first period P11, and sequentially supply gate signals GATE1 to GATE6 to the at least some of the gate lines in a second period P12. The at least some of the gate lines G1, G2, ... Gn may be a predetermined number of gate lines or a selected number of gate lines.

[0084] For example, in the first period P11, the gate driver 120 may simultaneously supply the first to sixth gate signals GATE1, GATE2, . . . GATE6, all of which have a turn-on level, to the gate lines included in the first gate line group GLG1 (refer to Figure 4A and Figure 4B ) in the first gate line G1 to the sixth gate line G6 (refer to Figure 4A and Figure 4B In the second period P12, the gate driver 120 may sequentially supply the first to sixth gate signals GATE1, GATE2, . . . GATE6, all of which have a turn-on level, to the first to sixth gate lines G1 to G6 (refer to Figure 4A and Figure 4B ).

[0085] The data driver 130 may supply a data voltage corresponding to a precharge gray value in the first period P11 , and supply a data voltage corresponding to a gray value of a pixel in the second period P12 .

[0086] In this case, the gate line group GLG1 (refer to Figure 4A and Figure 4B) and the pixels of the data lines D1, D2, ... Dm can be precharged in the first period P11, and can be charged with the corresponding or corresponding data voltage in the second period P12. Therefore, the charging rate of the pixels can be improved. Figure 4A and Figure 4B A detailed operation of the data driver 130 is described.

[0087] In an embodiment, the pulse width of the gate signals GATE1, GATE2 ... GATE6 that can be supplied simultaneously in the first period P11 can be the same as the pulse width of the gate signals GATE1, GATE2 ... GATE6 that can be supplied sequentially in the second period P12. In other words, the width of the first gate on time GOT1 can be the same as the width of the second gate on time GOT2. However, this is for illustrative purposes only, and the disclosure is not limited thereto. For example, the pulse width of the gate signals GATE1, GATE2 ... GATE6 that can be supplied simultaneously in the first period P11 can be smaller than the pulse width of the gate signals GATE1, GATE2 ... GATE6 that can be supplied sequentially in the second period P12. In other words, the width of the first gate on time GOT1 can be smaller than the width of the second gate on time GOT2. Therefore, the time (for example, the second gate on time GOT2) that each pixel can be individually charged with the corresponding or corresponding data voltage can be increased, thereby further improving the charging rate of the pixel.

[0088] The load signal TP, the gate clock signals GCLK1 to GCLK6 and the gate signals GATE7 to GATE12 in the second subframe period SF2 may be substantially identical or similar to the load signal TP, the gate clock signals GCLK1 to GCLK6 and the gate signals GATE1 to GATE6 in the first subframe period SF1 , respectively; therefore, repeated explanations thereof will be omitted.

[0089] although Figure 3A The number of gate clock signals GCLK1 to GCLK6 is shown to be six, but this is for illustrative purposes only, and the disclosure is not limited thereto. For example, the number of gate clock signals may be four or eight. For example, if the number of gate clock signals is eight, the on-level pulses included in the first to eighth gate signals may be formed in the first subframe period, and the on-level pulses included in the ninth to sixteenth gate signals may be formed in the second subframe period.

[0090] As reference Figures 1 to 3A As described above, in the display device 100 according to the embodiment, the gate lines G1, G2, ..., Gn may be divided into gate line groups GLG1, GLG2, ... (refer to FIG. 4A to FIG. 4D). The gate driver 120 may simultaneously supply the first to sixth gate signals GATE1 to GATE6 to the gate line groups GLG1, GLG2, ... (refer to FIG. 4A to FIG. 4D ) (e.g., the first gate line G1 to the sixth gate line G6) in one of the gate line groups (e.g., the first gate line G1 to the sixth gate line G6), and the first gate signal GATE1 to the sixth gate signal GATE6 can be sequentially supplied to the gate lines included in the gate line groups GLG1, GLG2 ... (refer to FIG. 4A to FIG. 4D ) (eg, the gate line of one gate line group (eg, the first gate line G1 to the sixth gate line G6) in the first gate line group GLG1). Therefore, during the first gate on time GOT1 and the second gate on time GOT2, refer to Figure 2 The switching transistor (or second transistor M2) of each pixel described can remain turned on. During the first gate on time GOT1, the data driver 130 can supply a data voltage corresponding to the precharged grayscale value to the pixel, so that the pixel can be precharged at the same time. During the second gate on time GOT2, the data driver 130 can supply a data voltage corresponding to the grayscale value of the pixel to the pixel, so that the pixel can be individually charged with the corresponding data voltage. Therefore, the charging rate of the pixel can be improved.

[0091] Reference Figure 3B , Figure 3B Each frame may not include a reference Figure 3A The first time period P11, P21, ... described in the figure. In other words, the conduction level pulses included in the gate clock signals GCLK1 to GCLK6 will not be formed simultaneously in the same section. Therefore, the conduction level pulses included in the gate signals GATE1 to GATE12 will not be formed simultaneously in the same section. Each of the gate signals GATE1 to GATE12 will have a conduction level pulse only during the corresponding or corresponding third gate on time GOT3. Therefore, only during the corresponding or corresponding third gate on time GOT3, the switching transistor of each pixel can remain turned on, so that the pixel can be charged only during the corresponding or corresponding third gate on time GOT3.

[0092] For example, if the number of gate lines G1, G2, ... Gn is 4320 and the driving frequency is about 120 Hz, the third gate on time GOT3 according to the comparative example may be about 1.35 μs. Therefore, the time each of the pixels is charged may be about 1.35 μs. On the other hand, according to the embodiment, the first gate on time GOT1 and the second gate on time GOT2 may both be about 1.21 μs. Therefore, the time a pixel may be charged may be about 2.42 μs.

[0093] As reference Figures 1 to 3B As described, the switch transistor (or second transistor M2) of each pixel can be turned on during the first gate-on time GOT1 (e.g., the time when the pixels can be charged or precharged at the same time) of the first period P11, P21, ... and the second gate-on time GOT2 (e.g., the time when the pixels can be charged individually) of the second period P12, P22, .... Therefore, the pixel can be precharged with a data voltage corresponding to the precharged grayscale value, so that the charging rate of each pixel can be improved.

[0094] Figure 3C is a diagram showing that according to an embodiment, Figure 1 1 is a waveform diagram of a load signal TP, gate clock signals GCLK1 to GCLK6, and gate signals GATE1 to GATE12 measured in a display device 100.

[0095] Reference Figure 3A and Figure 3C , in sections other than the sections in which the gate clock signals GCLK1 to GCLK6 and the gate signals GATE1 to GATE12 can be simultaneously formed, Figure 3C The load signal TP, the gate clock signals GCLK1 to GCLK6 and the gate signals GATE1 to GATE12 can be respectively Figure 3A The load signal TP, the gate clock signals GCLK1 to GCLK6, and the gate signals GATE1 to GATE12 are substantially identical or similar; therefore, a repeated description thereof will be omitted.

[0096] Reference Figure 1 and Figure 3C , the on-level pulses included in the gate clock signals GCLK1 to GCLK6 may be simultaneously formed in the first period P31. The on-level pulses included in the gate clock signals GCLK1 to GCLK6 may be sequentially formed twice in the second period P32.

[0097] Based on the gate clock signals GCLK1 to GCLK6, the gate driver 120 may simultaneously supply the first to twelfth gate signals GATE1 to GATE12 to the first to twelfth gate lines in the first period P31, and sequentially supply the first to twelfth gate signals GATE1 to GATE12 to the first to twelfth gate lines in the second period P32.

[0098] The width of each of the fourth gate on time GOT4 and the fifth gate on time GOT5 can be compared with the reference Figure 3A It is described that the width of each of the first gate on time GOT1 and the second gate on time GOT2 is large.

[0099] Thus, when the timing controller 110 generates the first gate clock signal to the qth (q can be a natural number of 2 or more) gate clock signal, the gate line groups GLG1, GLG2, ... (refer to FIG. 4A to FIG. 4D ) may be a multiple of q. Based on the first gate clock signal to the qth gate clock signal, the gate driver 120 may simultaneously supply the first gate signal to the rth gate signal to the first gate line to the rth gate line (r may be a multiple of q) in the first period, and sequentially supply the first gate signal to the rth gate signal to the first gate line to the rth gate line in the second period. For example, in the case where the timing controller 110 generates the first gate clock signal GCLK1 to the sixth gate clock signal GCLK6, the gate line groups GLG1, GLG2, ... (refer to FIG. 4A to FIG. 4D ) in the gate lines G1 to G12 (refer to FIG. 4A to FIG. 4D ) may be 12. However, this is for illustrative purposes only, and the disclosure is not limited thereto. For example, in a case where the timing controller 110 can generate the first gate clock signal GCLK1 to the sixth gate clock signal GCLK6, the number of gate lines included in the gate line groups GLG1, GLG2, ... may be 18 or 24. In this case, the number of gate signals that can be simultaneously supplied to the gate lines in the first period may be increased, so that the gate-on time (e.g., the fourth gate-on time GOT4 and the fifth gate-on time GOT5) may be increased.

[0100] As reference Figure 3C As described above, the number of gate signals GATE1 to GATE12 that can be simultaneously supplied to the gate lines in the first period P31 can be increased, so that the gate on times GOT4 and GOT5 can be increased. Therefore, the charging rate (or charging time) of each pixel can be further increased.

[0101] FIG. 4A to FIG. 4D is shown by including Figure 11 is a diagram of a pre-charged grayscale value calculated or obtained by the timing controller 110 in the display device 100.

[0102] Figure 4A and Figure 4B The first to sixth data lines D1 to D6, the first to sixth gate lines G1 to G6 included in the first gate line group GLG1, and the pixels PX11 to PX66 electrically connected to or coupled to the first to sixth gate lines G1 to G6 and the first to sixth data lines D1 to D6 are all shown. Figure 4A 1 and 2 show the precharged gray values ​​RV1, RV2 and RV3 and the gray values ​​corresponding to the data voltages supplied to the corresponding pixels PX11 to PX66 in the previous frame N-1Frame. Similarly, Figure 4B Precharged gray values ​​RV1 , RV2 , and RV3 and gray values ​​corresponding to data voltages supplied to corresponding pixels PX11 to PX66 in the current frame N Frame are shown.

[0103] Reference Figure 1 , Figure 3A and Figure 4A , in the previous frame N-1Frame, during the first period P11, P21... during which the gate driver 120 can simultaneously supply gate signals to some of the gate lines G1, G2... Gn, the data driver 130 can supply data voltages corresponding to the precharged gray values ​​RV1, RV2, and RV3 to the data lines. For example, during the first subframe period SF1, during the first period P11 during which the gate driver 120 can simultaneously supply the first gate signal GATE1 to the sixth gate signal GATE6 to the first gate line G1 to the sixth gate line G6 included in the first gate line group GLG1, the data driver 130 can supply the data voltages corresponding to the precharged gray values ​​RV1, RV2, and RV3 to the first data line D1. Similarly, in the first period P11, the data driver 130 can supply the data voltages corresponding to the precharged gray values ​​RV1, RV2, and RV3 to the second data line D2 to the sixth data line D6.

[0104] In the second period P12, P22, ... in which the gate driver 120 may sequentially supply gate signals to some gate lines, the data driver 130 may supply data voltages corresponding to the grayscale values ​​of the pixels PX11 to PX66 to the data lines. For example, during the first subframe period SF1, in the second period P12 in which the gate driver 120 may sequentially supply the first gate signal GATE1 to the sixth gate signal GATE6 to the first gate line G1 to the sixth gate line G6, the data driver 130 may sequentially (or successively) supply data voltages corresponding to 0 grayscale (0G), 0 grayscale (0G), 128 grayscale (128G), 64 grayscale (64G), 32 grayscale (32G), and 128 grayscale (128G) to the first data line D1. Similarly, in the second period P12 , the data driver 130 may supply data voltages corresponding to grayscale values ​​of the pixels PX12 , PX22 , PX32 . . . PX46 , PX56 , and PX66 to the second to sixth data lines D2 to D6 .

[0105] Similarly, refer to Figure 1 , Figure 3A and Figure 4B , in the current frame N Frame, the data driver 130 can supply data voltages corresponding to the pre-charged grayscale values ​​RV1, RV2 and RV3 and data voltages corresponding to the grayscale values ​​of pixels PX11 to PX66 to the data lines D1 to D6 during the first period P11, P21... and the second period P12, P22... respectively.

[0106] Reference Figure 1 and Figure 4A , as referenced Figure 1As described above, the timing controller 110 may calculate or obtain the precharge grayscale values ​​RV1, RV2, and RV3 based on the grayscale values ​​of the pixels. Here, the precharge grayscale values ​​RV1, RV2, and RV3 may be calculated or obtained based on the grayscale values ​​of the pixels that may be electrically connected to or electrically coupled to both the corresponding data line and the gate line included in the corresponding gate line group. For example, the precharge grayscale values ​​RV1, RV2, and RV3 corresponding to the data voltage supplied to the first data line D1 may be calculated or obtained based on the grayscale values ​​(0G, 0G, 128G, 64G, 32G, and 128G) of the pixels PX11 to PX61 that are electrically connected to or electrically coupled to the first data line D1 and the first gate line G1 to the sixth gate line G6 included in the first gate line group GLG1. Similarly, precharge gray values ​​RV1, RV2, and RV3 corresponding to the data voltage supplied to the second data line D2 may be calculated or obtained based on the gray values ​​(0G, 0G, 128G, 0G, 0G, and 0G) of the pixels PX12 to PX62 electrically connected to or coupled to the second data line D2 and the first to sixth gate lines G1 to G6 included in the first gate line group GLG1. Precharge gray values ​​RV1, RV2, and RV3 corresponding to the data voltage supplied to each of the third to sixth data lines D3 to D6 may also be calculated or obtained in a manner similar to the manner in which the precharge gray values ​​RV1, RV2, and RV3 corresponding to the data voltage supplied to each of the first and second data lines D1 and D2 are calculated or obtained.

[0107] In an embodiment, the precharge gray values ​​RV1 , RV2 , and RV3 may include at least one of a first precharge gray value RV1 , a second precharge gray value RV2 , and a third precharge gray value RV3 .

[0108] The first precharge gray value RV1 can be calculated or obtained as the average value of the gray values ​​of the pixels that can be electrically connected to or electrically coupled to the corresponding data line and the gate line included in the corresponding gate line group. For example, the first precharge gray value RV1 corresponding to the data voltage supplied to the first data line D1 can be calculated or obtained as 58 gray (58G), which is 0 gray (0G), 0 gray (0G), 128 gray (128G), 64 gray (64G), 32 gray (32G) and 128 gray (128G) (which can be the gray values ​​of the pixels PX11 to PX61 that are electrically connected to or electrically coupled to the first data line D1 and the first gate line G1 to the sixth gate line G6 included in the first gate line group GLG1). For example, the first pre-charged gray value RV1 corresponding to the data voltage supplied to the second data line D2 can be calculated or obtained as 21 gray (21G), which is the average of 0 gray (0G), 0 gray (0G), 128 gray (128G), 0 gray (0G), 0 gray (0G) and 0 gray (0G) (which can be the gray values ​​of pixels PX12 to PX62 electrically connected to or electrically coupled to the second data line D2 and the first gate line G1 to the sixth gate line G6 included in the first gate line group GLG1). The first pre-charged grayscale value RV1 corresponding to the data voltage supplied to the third data line D3 to the sixth data line D6 can be calculated or obtained in a manner similar to the manner in which the first pre-charged grayscale value RV1 corresponding to the data voltage supplied to the first data line D1 and the second data line D2 is calculated or obtained, and can be calculated or obtained as 149 grayscale (149G), 138 grayscale (138G), 74 grayscale (74G) and 74 grayscale (74G), respectively.

[0109] The second precharge grayscale value RV2 can be calculated or obtained as half of the value obtained by subtracting the minimum value from the maximum value of the grayscale values ​​of the pixels that can be electrically connected to or electrically coupled to both the corresponding data line and the gate line included in the corresponding gate line group. For example, the second pre-charged grayscale value RV2 corresponding to the data voltage supplied to the first data line D1 can be calculated or obtained as 64 grayscales (64G), which is half of the value obtained by subtracting 0 grayscale (0G) from 128 grayscales (128G), and among the grayscale values ​​of 0 grayscale (0G), 0 grayscale (0G), 128 grayscales (128G), 64 grayscales (64G), 32 grayscales (32G) and 128 grayscales (128G) of the pixels PX11 to PX61 which can be electrically connected to or electrically coupled to the first data line D1 and the first gate line G1 to the sixth gate line G6 included in the first gate line group GLG1, 0 grayscale (0G) is the minimum value and 128 grayscale (128G) is the maximum value. Similarly, the second pre-charged grayscale value RV2 corresponding to the data voltage supplied to the second data line D2 can be calculated or obtained as 64 grayscales (64G), which is half of the value obtained by subtracting 0 grayscale (0G) from 128 grayscales (128G), and among the grayscale values ​​of 0 grayscale (0G), 0 grayscale (0G), 128 grayscales (128G), 0 grayscale (0G), 0 grayscale (0G) and 0 grayscale (0G) of the pixels PX12 to PX62 which can be electrically connected to or electrically coupled to the second data line D2 and the first gate line G1 to the sixth gate line G6 included in the first gate line group GLG1, 0 grayscale (0G) is the minimum value and 128 grayscale (128G) is the maximum value. The second pre-charged grayscale value RV2 corresponding to the data voltage supplied to the third data line D3 to the sixth data line D6 can be calculated or obtained in a manner similar to the manner in which the second pre-charged grayscale value RV2 corresponding to the data voltage supplied to the first data line D1 and the second data line D2 is calculated or obtained, and can be calculated or obtained as 127 gray (127G), 127 gray (127G), 127 gray (127G) and 127 gray (127G), respectively.

[0110] The third precharge gray value RV3 can be calculated or obtained as the average value of the maximum and minimum gray values ​​of the pixels that can be electrically connected to or electrically coupled to the corresponding data line and the gate line included in the corresponding gate line group. For example, the third precharge gray value RV3 corresponding to the data voltage supplied to the first data line D1 can be calculated or obtained as 64 gray (64G), which is the average value of 128 gray (128G) and 0 gray (0G), among 0 gray (0G), 0 gray (0G), 128 gray (128G), 64 gray (64G), 32 gray (32G) and 128 gray (128G) of the gray values ​​of the pixels PX11 to PX61 that can be electrically connected to or electrically coupled to the first data line D1 and the first gate line G1 to the sixth gate line G6 included in the first gate line group GLG1, 128 gray (128G) is the maximum value and 0 gray (0G) is the minimum value. Similarly, the third pre-charged grayscale value RV3 corresponding to the data voltage supplied to the second data line D2 can be calculated or obtained as 64 grayscales (64G), which is the average of 128 grayscales (128G) and 0 grayscale (0G), among the grayscale values ​​of 0 grayscale (0G), 0 grayscale (0G), 128 grayscales (128G), 0 grayscale (0G), 0 grayscale (0G) and 0 grayscale (0G) of the pixels PX12 to PX62 which can be electrically connected to or electrically coupled to the second data line D2 and the first gate line G1 to the sixth gate line G6 included in the first gate line group GLG1, 128 grayscale (128G) is the maximum value and 0 grayscale (0G) is the minimum value. The third pre-charged gray value RV3 corresponding to the data voltage supplied to the third data line D3 to the sixth data line D6 can be calculated or obtained in a manner similar to the manner in which the third pre-charged gray value RV3 corresponding to the data voltage supplied to the first data line D1 and the second data line D2 is calculated or obtained, and can be calculated or obtained as 127 gray (127G), 127 gray (127G), 127 gray (127G) and 127 gray (127G), respectively.

[0111] Reference Figure 1 , Figure 3A , Figure 4A and Figure 4B ,exist Figure 4B The method of calculating or obtaining the precharge grayscale values ​​RV1, RV2 and RV3 in the current frame N Frame can be the same as that in Figure 4A The method of calculating or obtaining the pre-charge grayscale values ​​RV1, RV2 and RV3 in the previous frame N-1Frame is basically the same or similar; therefore, its repeated description will be omitted.

[0112] Reference Figure 4B, the first precharge grayscale value RV1 calculated or obtained in the current frame N Frame can be 101 grayscale (101G), 74 grayscale (74G), 170 grayscale (170G), 180 grayscale (180G), 32 grayscale (32G) and 32 grayscale (32G) respectively. The second precharge grayscale value RV2 calculated or obtained in the current frame N Frame can be 127 grayscale (127G), 127 grayscale (127G), 63 grayscale (63G), 95 grayscale (95G), 64 grayscale (64G) and 64 grayscale (64G) respectively. The third precharge grayscale value RV3 calculated or obtained in the current frame N Frame can be 127 grayscale (127G), 127 grayscale (127G), 191 grayscale (191G), 159 grayscale (159G), 64 grayscale (64G) and 64 grayscale (64G) respectively.

[0113] Reference FIG. 4A to FIG. 4D , except for being electrically connected to or electrically bonded to Figure 4C and Figure 4D In addition to the configuration of the pixels PX71 to PX126 of the seventh gate line G7 to the twelfth gate line G12 of the second gate line group GLG2, based on Figure 4C and Figure 4D The method of calculating the grayscale values ​​of the pixels PX71 to PX126 or obtaining the precharge grayscale values ​​RV1, RV2 and RV3 can be based on Figure 4A and Figure 4B The method of calculating the grayscale values ​​of the pixels PX11 to PX66 or obtaining the pre-charged grayscale values ​​RV1, RV2 and RV3 is substantially the same or similar; therefore, a repeated description thereof will be omitted.

[0114] Figure 4C and Figure 4D Each shows the seventh to twelfth gate lines G7 to G12, the first to sixth data lines D1 to D6 included in the second gate line group GLG2, and the pixels PX71 to PX126 electrically connected to or coupled to the seventh to G7 to G12 and the first to D6. Figure 4C Gray values ​​corresponding to the data voltages supplied to the corresponding pixels PX71 to PX126 in the previous frame N-1Frame and precharge gray values ​​RV1, RV2, and RV3 are shown. Similarly, Figure 4D Gray values ​​corresponding to data voltages supplied to corresponding pixels PX71 to PX126 in the current frame N Frame and precharged gray values ​​RV1 , RV2 , and RV3 are shown.

[0115] With reference to Figure 1 , Figure 3A , Figure 4A and Figure 4BIn a manner similar to the description, the data driver 130 can supply data voltages corresponding to pre-charged grayscale values ​​RV1, RV2, RV3 to the first data line D1 to the sixth data line D6 in the first time period P11, P21..., and can supply data voltages corresponding to the corresponding grayscale values ​​of the pixels PX71 to PX126 to the first data line D1 to the sixth data line D6 in the second time period P12, P22...

[0116] With reference to Figure 1 , Figure 3A , Figure 4A and Figure 4B In a manner similar to that described, the timing controller 110 may calculate or obtain precharged gray values ​​RV1 , RV2 , and RV3 corresponding to data voltages supplied to the first to sixth data lines D1 to D6 based on gray values ​​of the pixels PX71 to PX126 .

[0117] like Figure 4C As shown in, the first pre-charge grayscale value RV1 calculated or obtained in the previous frame N-1Frame can be 90 grayscale (90G), 21 grayscale (21G), 85 grayscale (85G), 191 grayscale (191G), 5 grayscale (5G) and 170 grayscale (170G) respectively. The second pre-charge grayscale value RV2 calculated or obtained in the previous frame N-1Frame can be 48 grayscale (48G), 32 grayscale (32G), 32 grayscale (32G), 63 grayscale (63G), 16 grayscale (16G) and 63 grayscale (63G) respectively. The third pre-charge grayscale value RV3 calculated or obtained in the previous frame N-1Frame can be 80 grayscale (80G), 32 grayscale (32G), 96 grayscale (96G), 191 grayscale (191G), 16 grayscale (16G) and 191 grayscale (191G) respectively. Similarly, as Figure 4D As shown in, the first precharge grayscale value RV1 calculated or obtained in the current frame N Frame can be 101 grayscale (101G), 13 grayscale (13G), 96 grayscale (96G), 212 grayscale (212G), 10 grayscale (10G) and 191 grayscale (191G). The second precharge grayscale value RV2 calculated or obtained in the current frame N Frame can be 127 grayscale (127G), 32 grayscale (32G), 32 grayscale (32G), 63 grayscale (63G), 32 grayscale (32G) and 63 grayscale (63G). The third precharge grayscale value RV3 calculated or obtained in the current frame N Frame can be 127 grayscale (127G), 32 grayscale (32G), 96 grayscale (96G), 191 grayscale (191G), 32 grayscale (32G) and 191 grayscale (191G).

[0118] Reference Figure 1 , Figure 3A and FIG. 4A to FIG. 4D , the timing controller 110 may calculate or obtain at least one of the first precharge gray value RV1, the second precharge gray value RV2, and the third precharge gray value RV3 as the precharge gray value. Here, the calculated or obtained precharge gray value may be included in the data signal DATA. The data driver 130 may generate a data voltage based on the data signal DATA that may include the precharge gray value, and provide the data voltage corresponding to the precharge gray value to the corresponding data line D1, D2...Dm in the first period P11, P21...

[0119] As reference Figure 1 , Figure 3A and FIG. 4A to FIG. 4D As described above, the timing controller 110 may calculate or obtain the precharge gray values ​​RV1, RV2, and RV3 based on the gray values ​​of the pixels, and generate the data signal DATA based on the precharge gray values ​​RV1, RV2, and RV3. Therefore, the data driver 130 may supply the data voltage corresponding to the precharge gray values ​​RV1, RV2, and RV3 to the pixels, and charge the pixels during the first period.

[0120] Figure 5A is a diagram showing that according to an embodiment, Figure 1 1 is a waveform diagram of a gate pulse start signal STVP, a load signal TP, a data voltage, gate signals GATE1 and GATE12, and a voltage for charging a pixel measured in a display device 100. Figure 5B is a diagram showing that according to the comparative example, Figure 1 1 is a waveform diagram of a gate pulse start signal STVP, a load signal TP, a data voltage, gate signals GATE1 and GATE12, and a voltage for charging a pixel measured in a display device 100.

[0121] Reference Figure 3A and Figure 5A , Figure 5A The load signal TP and gate signals GATE1 and GATE12 can be Figure 3A The load signal TP and the gate signals GATE1 and GATE12 are substantially identical or similar; therefore, repeated explanations thereof will be omitted.

[0122] Reference Figure 5A The gate pulse start signal STVP can be based on the timing controller 110 (refer to Figure 1 ) is provided to the gate driver 120 (refer to Figure 1) is generated by a vertical start signal. Before the time point at which each frame period starts, a logic high level pulse of the gate pulse start signal STVP can be generated. After the time point at which the frame period starts, the gate pulse start signal STVP can be maintained at a logic low level.

[0123] Reference Figure 1 , Figure 3A , Figure 4B and Figure 5A , the first data voltage DATA1 may be a data voltage supplied to the first data line D1. Figure 1 and Figure 3A As described above, the data driver 130 may generate the first data voltage DATA1 based on the load signal TP and the data signal DATA provided from the timing controller 110 .

[0124] In an embodiment, the first data voltage DATA1 may be synchronized with the load signal TP. For example, the first data voltage DATA1 may be output in synchronization with a rising edge of a logic high level pulse included in the load signal TP.

[0125] The data driver 130 may sequentially supply the first data voltage DATA1 through the first data line D1. In detail, in response to the rising edge of the first logic high level pulse included in the load signal TP, the data driver 130 may provide a data voltage corresponding to 101 gray (101G) which may be a precharge gray value to the first data line D1. Therefore, the data voltage corresponding to 101 gray (101G) may be supplied to the pixels PX11 to PX61 electrically connected or electrically combined with the first data line D1 and the first to sixth gate lines G1 to G6 included in the first gate line group GLG1.

[0126] In response to rising edges of the second to seventh logic high pulses included in the load signal TP, the data driver 130 may sequentially (or sequentially) provide data voltages corresponding to grayscale values ​​of the pixels PX11 to PX61 electrically connected to or coupled to the first data line D1 and the first to sixth gate lines G1 to G6 to the first data line D1. Thus, data voltages corresponding to 255 grayscale (255G), 0 grayscale (0G), 128 grayscale (128G), 64 grayscale (64G), 32 grayscale (32G), and 128 grayscale (128G) may be provided to the pixels PX11 to PX61, respectively.

[0127] Reference Figure 4A , Figure 4B and Figure 5A, in the previous frame N-1Frame, the pixel PX11 electrically connected to or electrically coupled to the first data line D1 and the first gate line G1 may be charged with a data voltage corresponding to 0 gray (0G). Thereafter, in the first period P11 of the current frame NFrame, the first gate signal GATE1 may be applied to the first gate line G1, and a data voltage corresponding to 101 gray (101G), which may be a precharged gray value, may be applied to the first data line D1. Therefore, the pixel PX11 may be precharged in response to 101 gray (101G). For example, in the second period P12, the first gate signal GATE1 may be applied to the first gate line G1, and a data voltage corresponding to 255 gray (255G), which may be a gray value of the pixel PX11, may be applied to the first data line D1. Therefore, the pixel PX11 may be charged with a desired data voltage in response to 255 gray (255G).

[0128] Reference Figure 5B , Figure 5B Each frame may not include a reference Figure 5A The first period P11, P21, ... described. In other words, in the previous frame N-1Frame, the pixel PX11 electrically connected to or electrically coupled to the first data line D1 and the first gate line G1 may be charged with a data voltage corresponding to 0 gray (0G). Thereafter, in the current frame N Frame, the first gate signal GATE1 may be applied to the first gate line G1, and a data voltage corresponding to 255 grays (255G) which may be the gray value of the pixel PX11 may be applied to the first data line D1. However, in the case where there is a large difference between the gray value (0 gray (0G)) of the pixel PX11 of the previous frame N-1Frame and the gray value (255 gray (255G)) of the pixel PX11 of the current frame N Frame, the time (e.g., the third gate on time GOT3) for which the pixel PX11 can be charged may be insufficient, so that the pixel PX11 may not be charged with a data voltage corresponding to the desired gray value (255 gray (255G)). On the other hand, as referenced Figure 5A As described above, in a case where the pixel PX11 can be pre-charged with a data voltage corresponding to the pre-charged grayscale value (101 grayscale (101G)) in the first period P11 and can be separately charged with a data voltage corresponding to the grayscale value (255 grayscale (255G)) of the pixel PX11 in the second period P12, even if there is a large difference between the grayscale value (0 grayscale (0G)) of the pixel PX11 of the previous frame N-1Frame and the grayscale value (255 grayscale (255G)) of the pixel PX11 of the current frame NFrame, the pixel PX11 can be charged with a data voltage corresponding to the desired grayscale value (255 grayscale (255G)).

[0129] Similarly, refer to Figure 4C , Figure 4D , Figure 5A and Figure 5B , for the pixel P121 electrically connected to or coupled to the first data line D1 and the twelfth gate line G12, when the grayscale value of the pixel P121 of the previous frame N-1Frame may be 64 grayscales (64G) and the grayscale value of the pixel P121 of the current frame N Frame may be 255 grayscales (255G), the pixel PX121 may be precharged with a data voltage corresponding to the precharged grayscale value (101 grayscale (101G)) in the first period P21, and may be separately charged with a data voltage corresponding to the grayscale value (255 grayscale (255G)) of the pixel PX121 in the second period P22. Therefore, the pixel PX121 may be charged with a data voltage corresponding to the desired grayscale value (255 grayscale (255G)).

[0130] As reference Figure 5A and Figure 5B As described above, the pixel can be pre-charged with a data voltage corresponding to the pre-charged gray value in the first period P11, P21, ..., and individually charged with a data voltage corresponding to the gray value of the pixel in the second period P12, P22, .... Therefore, even if the gray value of the pixel is greatly different between the previous frame and the current frame, the pixel can be charged with a data voltage corresponding to the desired gray value.

[0131] Figure 6 is a flowchart illustrating a method of driving a display device according to an embodiment.

[0132] Reference Figure 1 and Figure 6 , you can Figure 1 The display device 100 is executed Figure 6 A method for driving a display device.

[0133] exist Figure 6 In the method for driving a display device, the precharge grayscale value may be calculated or obtained based on the grayscale value of the pixel (at step S610). Here, the precharge grayscale value may include reference FIG. 4A to FIG. 4D At least one of the first pre-charge gray value RV1, the second pre-charge gray value RV2 and the third pre-charge gray value RV3 described.

[0134] Afterwards, in Figure 6 In the method of driving a display device, in a first period, a gate signal may be simultaneously supplied to the gate line, and a data voltage corresponding to a precharged gray value may be supplied to the data line (at step S620).

[0135] In an embodiment, Figure 6In a method for driving a display device, during a first period, gate signals may be simultaneously supplied to gate lines included in a pth (p may be a natural number greater than or equal to 1 and less than or equal to k) group, and data voltages corresponding to precharged gray values ​​may be supplied to the data lines. Figure 1 , Figure 3A and FIG. 4A to FIG. 4B As described above, in the first period P11, the gate driver 120 may simultaneously supply gate signals GATE1 to GATE6 to the first to sixth gate lines G1 to G6 included in the first gate line group GLG1, and the data driver 130 may supply data voltages corresponding to the precharged gray values ​​RV1, RV2, and RV3 to the data lines D1 to D6.

[0136] exist Figure 6 In the method of driving a display device, in the second period, gate signals may be sequentially supplied to the gate lines, and data voltages corresponding to grayscale values ​​of pixels may be supplied to the data lines (at step S630).

[0137] In an embodiment, Figure 6 In the method of driving a display device, during the second period, the gate signal may be sequentially supplied to the gate lines included in the p-th group, and the data voltage corresponding to the gray value of the pixel may be supplied to the data line. Figure 1 , Figure 3A and FIG. 4A to FIG. 4B As described, in the second period P12, the gate driver 120 may sequentially supply gate signals GATE1 to GATE6 to the first to sixth gate lines G1 to G6 included in the first gate line group GLG1, and the data driver 130 may supply data voltages corresponding to the grayscale values ​​of the pixels PX11 to PX66 to the data lines D1 to D6.

[0138] In a display device and a method of driving the display device according to an embodiment, a gate signal may be simultaneously supplied to at least some of the gate lines (or a predetermined number of gate lines or a selected number of gate lines) during a precharge period, and a data voltage corresponding to a precharge gray value may be supplied to the data line. Thus, the charging rate of the pixel may be improved.

[0139] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and will be interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art, as of the time of filing this application, unless otherwise expressly noted, features, characteristics, and / or elements described in connection with an embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, one of ordinary skill in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the disclosure as set forth in the claims.

Claims

1. A display device, comprising: A display panel, comprising a plurality of gate lines, data lines and pixels; a gate driver, the gate driver providing a gate signal to the pixel through the plurality of gate lines; a data driver that provides a data voltage to the pixel through the data line; as well as A timing controller, wherein the timing controller obtains a precharge grayscale value based on the grayscale value of the pixel, wherein: The gate driver supplies the gate signals to the plurality of gate lines simultaneously in a first period, and sequentially supplies the gate signals to the plurality of gate lines in a second period, and The data driver supplies a data voltage corresponding to the precharge grayscale value to the data line in the first period, and supplies a data voltage corresponding to the grayscale value of the pixel to the data line in the second period.

2. The display device according to claim 1, wherein: The gate driver simultaneously supplies the gate signal to a predetermined number of gate lines in the first period.

3. The display device according to claim 1, wherein: The plurality of gate lines are divided into first to kth groups, and the gate driver simultaneously supplies the gate signals to the gate lines included in the p-th group among the first to k-th groups in the first period, and sequentially supplies the gate signals to the gate lines included in the p-th group in the second period, Here, k is a natural number of 2 or more, and p is a natural number of 1 or more.

4. The display device according to claim 3, wherein: The first frame period includes the first subframe period to the kth subframe period, and The p-th subframe period among the first to k-th subframe periods includes the first period and the second period.

5. The display device according to claim 3, wherein: A first precharge grayscale value corresponding to a data voltage supplied to a first data line among the data lines is obtained based on grayscale values ​​of pixels electrically connected to the first data line and the gate lines included in the p-th group.

6. The display device according to claim 4, wherein: The timing controller generates a first gate clock signal to a qth gate clock signal, and The gate driver generates the gate signal based on the first to qth gate clock signals, Here, q is a natural number of 2 or greater.

7. The display device according to claim 6, wherein: Each of the first to q-th gate clock signals includes pulses that are simultaneously formed in the same segment during the first period and are sequentially formed in different segments during the second period.

8. The display device according to claim 6, wherein: The gate lines included in the p-th group are adjacent to each other, and The number of the gate lines included in the p-th group is a multiple of q.

9. The display device according to claim 4, wherein: A pulse width of the gate signal simultaneously supplied to the gate lines included in the p-th group in the first period is equal to a pulse width of the gate signal sequentially supplied to the gate lines included in the p-th group in the second period.

10. The display device according to claim 4, wherein: A pulse width of the gate signal simultaneously supplied to the gate lines included in the p-th group in the first period is smaller than a pulse width of the gate signal sequentially supplied to the gate lines included in the p-th group in the second period.

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