Pixel and organic light emitting diode display device including the same

Abstract

A pixel and an organic light emitting diode display device including the same are provided. The pixel includes a capacitor coupled between a first node and a second node; first and second transistors each including a gate receiving a corresponding initialization signal, a first terminal receiving a first power supply voltage, and a second terminal coupled to the capacitor; a third transistor including a first terminal coupled to a data line and a second terminal coupled to the first node; a fourth transistor including a gate coupled to the second node, a first terminal receiving the first power supply voltage, and a second terminal coupled to a third node; a fifth transistor including a first terminal coupled to the third node and a second terminal coupled to the second node; sixth and seventh transistors receiving a scan signal; eighth and ninth transistors receiving an emission signal; and an OLED.

Description

TECHNICAL FIELD

[0001] The disclosure relates generally to a display apparatus, and more particularly to a pixel of an organic light emitting diode (OLED) display apparatus and an OLED display apparatus including the same. BACKGROUND

[0002] In particular, when the OLED display apparatus is employed in a portable device such as a smartphone, a tablet computer, etc., it is highly required to reduce power consumption in the OLED display apparatus. Recently, in order to reduce the power consumption of the OLED display apparatus, a low-frequency driving technique has been developed. The low-frequency driving technique drives or refreshes a display panel of the OLED display apparatus at a frequency lower than a normal frequency (e.g., an input frame frequency) at which the display panel is driven.

[0003] When the display panel of the OLED display apparatus is driven at a low frequency, a gate-source voltage having a high absolute value can be applied to a driving transistor of each pixel as a bias voltage in a part of a plurality of frame periods (e.g., in a first frame period among 60 or 120 frame periods), but the bias voltage can not be applied to the driving transistor in the remaining frame periods (e.g., in subsequent 59 frame periods among 60 frame periods or in subsequent 119 frame periods among 120 frame periods). In this case, in the part of the plurality of frame periods (e.g., the first frame period) in which the gate-source voltage having the high absolute value is applied, the threshold voltage of the driving transistor can be shifted in a negative direction (i.e., a negative shift of the threshold voltage can occur), and in the subsequent frame periods, the threshold voltage can be gradually shifted in a positive direction. Accordingly, under the low-frequency driving, the gradual positive shift of the threshold voltage can cause the luminance of the OLED display apparatus to gradually increase. SUMMARY

[0004] Some example embodiments provide a pixel of an organic light emitting diode (OLED) display apparatus capable of preventing luminance from gradually increasing under low-frequency driving.

[0005] Some example embodiments provide an OLED display apparatus capable of preventing luminance from gradually increasing under low-frequency driving.

[0006] According to an example embodiment, a pixel of an OLED display apparatus includes: a capacitor including a first electrode coupled to a first node and a second electrode coupled to a second node; a first transistor including a gate receiving a first initialization signal, a first terminal receiving a first power voltage, and a second terminal coupled to the first node; a second transistor including a gate receiving a second initialization signal, a first terminal receiving the first power voltage, and a second terminal coupled to the second node; a third transistor including a first terminal coupled to a data line and a second terminal coupled to the first node; a fourth transistor including a gate coupled to the second node, a first terminal receiving the first power voltage, and a second terminal coupled to a third node; a fifth transistor including a first terminal coupled to the third node and a second terminal coupled to the second node; a sixth transistor including a gate receiving a scan signal, a first terminal receiving an initialization voltage, and a second terminal coupled to a fourth node; a seventh transistor including a gate receiving the scan signal, a first terminal receiving the initialization voltage, and a second terminal coupled to the first node; an eighth transistor including a gate receiving an emission signal, a first terminal receiving a reference voltage, and a second terminal coupled to the first node; a ninth transistor including a first terminal coupled to the third node and a second terminal coupled to the fourth node; and an OLED including an anode coupled to the fourth node and a cathode receiving a second power voltage.

[0007] The pixel can include at least one P-type metal oxide semiconductor (PMOS) transistor and at least one N-type metal oxide semiconductor (NMOS) transistor.

[0008] The first, third, fourth, sixth, seventh, eighth, and ninth transistors can be PMOS transistors, and the second and fifth transistors can be NMOS transistors.

[0009] The OLED display apparatus can be operable to perform normal frequency driving by driving the pixel at a normal frequency, and each frame period of the OLED display apparatus under the normal frequency driving can include: an initialization period in which the capacitor is initialized; a threshold voltage compensation period in which a data voltage is provided to the first electrode of the capacitor through the data line and a threshold voltage of the fourth transistor is compensated; a bias period in which a bias voltage is applied to the fourth transistor and the OLED is initialized; and an emission period in which the OLED emits light.

[0010] In the initialization period, the first transistor can apply the first power voltage to the first node in response to the first initialization signal having a first level, and the second transistor can apply the first power voltage to the second node in response to the second initialization signal having a second level, the second initialization signal having an opposite polarity of the first initialization signal.

[0011] In the initialization period, the capacitor can be initialized based on a first power voltage at the first node and the second node, and the first power voltage can be applied to the first terminal of the fourth transistor and the gate of the fourth transistor.

[0012] In the threshold voltage compensation period, the third transistor can apply a data voltage provided through a data line to the first node in response to a first write signal having a first level applied to the gate of the third transistor, and the fifth transistor can diode-connect the fourth transistor in response to a second write signal having a second level applied to the gate of the fifth transistor, and wherein the second write signal has an opposite polarity of the first write signal.

[0013] In the threshold voltage compensation period, the data voltage can be stored at the first electrode of the capacitor, and the first power voltage minus the threshold voltage of the fourth transistor can be stored at the second electrode of the capacitor.

[0014] In the bias period, the sixth transistor can apply the initialization voltage to the fourth node in response to a scan signal having a first level, and the seventh transistor can apply the initialization voltage to the first node in response to the scan signal having the first level.

[0015] In the bias period, the OLED can be initialized based on the initialization voltage at the fourth node, the voltage of the first electrode of the capacitor can change from the data voltage to the initialization voltage, and the voltage of the second electrode of the capacitor can change to the first power voltage minus the threshold voltage of the fourth transistor plus the initialization voltage minus the data voltage by coupling with the first electrode of the capacitor.

[0016] In the emission period, the eighth transistor can apply a reference voltage to the first node in response to an emission signal having a first level, the fourth transistor can generate a driving current based on the voltage of the second electrode of the capacitor, the ninth transistor can couple the third node to the fourth node in response to the emission signal having the first level applied to the gate of the ninth transistor, and the OLED can emit light based on the driving current.

[0017] In the emission period, the voltage of the first electrode of the capacitor can change from the initialization voltage to the reference voltage, and the voltage of the second electrode of the capacitor can change to the first power voltage minus the threshold voltage of the fourth transistor minus the data voltage plus the reference voltage by coupling with the first electrode of the capacitor.

[0018] The OLED display apparatus can be operable to perform low-frequency driving by driving the pixel at a low frequency lower than a normal frequency, and at least one of the plurality of frame periods of the OLED display apparatus under the low-frequency driving can include: an initialization period in which the capacitor is initialized; a threshold voltage compensation period in which a data voltage is supplied to the first electrode of the capacitor through the data line and a threshold voltage of the fourth transistor is compensated for; a bias period in which a bias voltage is applied to the fourth transistor and the OLED is initialized; and an emission period in which the OLED emits light, and each of the remaining frame periods of the plurality of frame periods can include only the bias period and the emission period.

[0019] When the OLED display apparatus performs the low-frequency driving, the first and second initialization signals can be supplied to the pixel at a low frequency of the low-frequency driving, and the scan signal and the emission signal can be supplied to the pixel at a normal frequency.

[0020] The second transistor can further include a first bottom electrode under the gate of the second transistor, and the fifth transistor can further include a second bottom electrode under the gate of the fifth transistor.

[0021] The first bottom electrode of the second transistor can receive the second initialization signal, and the second bottom electrode of the fifth transistor can receive a second write signal applied to the gate of the fifth transistor.

[0022] The first bottom electrode of the second transistor can be coupled to the first terminal of the second transistor, and the second bottom electrode of the fifth transistor can be coupled to the second terminal of the fifth transistor.

[0023] According to an example embodiment, a pixel of an OLED display apparatus includes: a capacitor including a first electrode coupled to a first node and a second electrode coupled to a second node; a first transistor including a gate receiving a first initialization signal, a first terminal receiving a first power voltage, and a second terminal coupled to the first node; a second transistor including a gate receiving a second initialization signal, a first terminal receiving the first power voltage, and a second terminal coupled to the second node; a driving transistor including a gate coupled to the second node; an emission transistor including a gate receiving an emission signal; and an OLED coupled to the emission transistor and including a cathode receiving a second power voltage.

[0024] The OLED display apparatus can be operable to perform low-frequency driving by driving the pixels at a low frequency lower than a normal frequency, and at least one of the plurality of frame periods of the OLED display apparatus under the low-frequency driving can include an initialization period in which the capacitor is initialized, a threshold voltage compensation period in which a data voltage is supplied to the first electrode of the capacitor through the data line, a threshold voltage of the driving transistor is compensated for, and the OLED is initialized, and an emission period in which the OLED emits light based on a driving current generated by the driving transistor, and each of the remaining frame periods of the plurality of frame periods can include only the emission period.

[0025] According to an example embodiment, an OLED display apparatus includes a plurality of pixels, each of the plurality of pixels including a capacitor including a first electrode coupled to a first node and a second electrode coupled to a second node, a first transistor including a gate receiving a first initialization signal, a first terminal receiving a first power voltage, and a second terminal coupled to the first node, a second transistor including a gate receiving a second initialization signal, a first terminal receiving the first power voltage, and a second terminal coupled to the second node, a driving transistor including a gate coupled to the second node, an emission transistor including a gate receiving an emission signal, and an OLED coupled to the emission transistor and including a cathode receiving a second power voltage.

[0026] As described above, each pixel of the OLED display apparatus can include at least one PMOS transistor and at least one NMOS transistor. Accordingly, a leakage current in the pixel can be reduced, and thus the pixel can be suitable for low-frequency driving.

[0027] Further, in each pixel of the OLED display apparatus according to an example embodiment, a voltage for initializing the capacitor and a voltage for initializing the OLED can be different from each other, and when the capacitor is initialized, a gate-source voltage having a low absolute value can be applied to the driving transistor. Accordingly, a gradual increase in luminance under low-frequency driving can be prevented. BRIEF DESCRIPTION OF DRAWINGS

[0028] Illustrative, non-limited example embodiments of the inventive concept will be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0029] Figure 1 is a circuit diagram illustrating a pixel of an organic light emitting diode (OLED) display apparatus according to an example embodiment.

[0030] Figure 2 is Figure 1 is a timing diagram of an example operation of the pixel of

[0031] Figure 3 is Figure 1a circuit diagram of example operation of the pixel of FIG. 1 in an initialization period.

[0032] Figure 4 is Figure 1 a circuit diagram of example operation of the pixel of FIG. 1 in a threshold voltage compensation period.

[0033] Figure 5 is Figure 1 a circuit diagram of example operation of the pixel of FIG. 1 in a bias period.

[0034] Figure 6 is Figure 1 a circuit diagram of example operation of the pixel of FIG. 1 in an emission period.

[0035] Figure 7 is Figure 1 a timing diagram of example operation of the pixel of FIG. 1 under low frequency driving.

[0036] Figure 8 is a graph showing an example of luminance of an OLED display device including the pixel of FIG. 1 under low frequency driving. Figure 1

[0037] Figure 9 is a circuit diagram showing a pixel of an OLED display device according to an example embodiment.

[0038] Figure 10 is a circuit diagram showing a pixel of an OLED display device according to an example embodiment.

[0039] Figure 11 is a circuit diagram showing a pixel of an OLED display device according to an example embodiment.

[0040] Figure 12 is Figure 11 a timing diagram of example operation of the pixel of FIG. 1 under normal frequency driving.

[0041] Figure 13 is Figure 11 a circuit diagram of example operation of the pixel of FIG. 1 in an initialization period.

[0042] Figure 14 is Figure 11 a circuit diagram of example operation of the pixel of FIG. 1 in a threshold voltage compensation period.

[0043] Figure 15 is Figure 11 a circuit diagram of example operation of the pixel of FIG. 1 in an emission period.

[0044] Figure 16 is Figure 11 a timing diagram of example operation of the pixel of FIG. 1 under low frequency driving.

[0045] Figure 17 ​is a block diagram illustrating an OLED display apparatus according to an example embodiment.

[0046] Figure 18 is an electronic device including an OLED display apparatus according to an example embodiment. DETAILED DESCRIPTION

[0047] Embodiments of the inventive concept will hereinafter be explained in detail with reference to the accompanying drawings.

[0048] Figure 1 is a circuit diagram illustrating a pixel 100 of an organic light emitting diode (OLED) display apparatus according to an example embodiment.

[0049] Referring to Figure 1 , the pixel 100 of the OLED display apparatus can include a capacitor CST, first to ninth transistors T1, T2, T3, T4, T5, T6, T7, T8, and T9, and an organic light emitting diode (OLED) EL.

[0050] The capacitor CST can store a data voltage VDAT provided through a data line DL. In some example embodiments, the capacitor CST can be referred to as a storage capacitor. For example, as shown in Figure 1 , the capacitor CST can include a first electrode coupled to a first node N1 and a second electrode coupled to a second node N2.

[0051] The first transistor T1 can transfer a first power voltage ELVDD to the first node N1 in response to a first initialization signal GI_P, and the second transistor T2 can transfer the first power voltage ELVDD to the second node N2 in response to a second initialization signal GI_N. In some example embodiments, the first transistor T1 and the second transistor T2 can be referred to as capacitor initialization transistors. For example, as shown in Figure 1 , the first transistor T1 can include a gate that receives the first initialization signal GI_P, a first terminal that receives the first power voltage ELVDD, and a second terminal coupled to the first node N1, and the second transistor T2 can include a gate that receives the second initialization signal GI_N, a first terminal that receives the first power voltage ELVDD, and a second terminal coupled to the second node N2.

[0052] The third transistor T3 can transfer the data voltage VDAT to the first node N1 in response to a first write signal GW_P. In some example embodiments, the third transistor T3 can be referred to as a data write transistor. For example, as shown in Figure 1 , the third transistor T3 can include a gate that receives the first write signal GW_P, a first terminal coupled to a data line DL, and a second terminal coupled to the first node N1.

[0053] The fourth transistor T4 can generate a drive current based on a voltage of the second node N2 or a voltage of the second electrode of the capacitor CST. In some example embodiments, the fourth transistor T4 can be referred to as a drive transistor. For example, as shown in FIG. 4A, the fourth transistor T4 can include a gate coupled to the second node N2, a first terminal receiving the first supply voltage ELVDD, and a second terminal coupled to the third node N3. Figure 1

[0054] The fifth transistor T5 can diode-connect the fourth transistor T4 in response to the second write signal GW_N. In some example embodiments, the fifth transistor T5 can be referred to as a compensation transistor. For example, as shown in FIG. 4A, the fifth transistor T5 can include a gate receiving the second write signal GW_N, a first terminal coupled to the third node N3, and a second terminal coupled to the second node N2. Figure 1

[0055] The sixth transistor T6 can transfer the initialization voltage VINT to the anode of the OLED EL in response to the scan signal SS. In some example embodiments, the sixth transistor T6 can be referred to as an anode initialization transistor. For example, as shown in FIG. 4A, the sixth transistor T6 can include a gate receiving the scan signal SS, a first terminal receiving the initialization voltage VINT, and a second terminal coupled to the fourth node N4. Figure 1

[0056] The seventh transistor T7 can transfer the initialization voltage VINT to the first node N1 in response to the scan signal SS. In some example embodiments, the seventh transistor T7 can be referred to as a bias transistor. For example, as shown in FIG. 4A, the seventh transistor T7 can include a gate receiving the scan signal SS, a first terminal receiving the initialization voltage VINT, and a second terminal coupled to the first node N1. Figure 1

[0057] The eighth transistor T8 can transfer the reference voltage VREF to the first node N1 in response to the emission signal EM, and the ninth transistor T9 can couple the third node N3 to the fourth node N4 in response to the emission signal EM. In some example embodiments, the eighth transistor T8 and the ninth transistor T9 can be referred to as emission transistors. For example, as shown in FIG. 4A, the eighth transistor T8 can include a gate receiving the emission signal EM, a first terminal receiving the reference voltage VREF, and a second terminal coupled to the first node N1, and the ninth transistor T9 can include a gate receiving the emission signal EM, a first terminal coupled to the third node N3, and a second terminal coupled to the fourth node N4. Figure 1

[0058] ​​​​​The OLED EL can emit light based on a driving current generated by the fourth transistor T4. For example, as shown in FIG. 1B, the OLED EL can include an anode coupled to the fourth node N4 and a cathode receiving a second power voltage ELVSS. Figure 1

[0059] In some example embodiments, at least one of the first through ninth transistors T1-T9 can be implemented using a low temperature poly-silicon (LTPS) P-type metal oxide semiconductor (PMOS) transistor, and at least another one of the first through ninth transistors T1-T9 can be implemented using an oxide N-type metal oxide semiconductor (NMOS) transistor. For example, as shown in FIG. 1B, the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be PMOS transistors, and the second transistor T2 and the fifth transistor T5 can be NMOS transistors. Further, the first initialization signal GI_P, the first write signal GW_P, the scan signal SS, and the emission signal EM applied to the first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be active low signals having a low level as an active level, and the second initialization signal GI_N and the second write signal GW_N applied to the second transistor T2 and the fifth transistor T5 can be active high signals having a high level as an active level. In this case, since the second transistor T2 and the fifth transistor T5 directly connected to the second node N2 (or the second electrode of the capacitor CST) are implemented using NMOS transistors, a leakage current from the second electrode of the capacitor CST can be reduced. Accordingly, when the pixel 100 is driven at a low frequency lower than a normal frequency (e.g., about 60 Hz or about 120 Hz), a voltage of the second electrode of the capacitor CST can not be very large, and thus the pixel 100 can be suitable for low frequency driving. Figure 1

[0060] ​​As a comparative example, in a conventional OLED display apparatus performing low-frequency driving, a gate-source voltage having a high absolute value can be applied to a driving transistor of each pixel as a bias voltage in a part of a plurality of frame periods (e.g., in a first frame period among 60 or 120 frame periods), and the bias voltage can not be applied to the driving transistor in the remaining frame periods (e.g., in subsequent 59 or 119 frame periods among 60 or 120 frame periods). In this case, in the first frame period, a threshold voltage of the driving transistor can be shifted in a negative direction (i.e., a negative shift of the threshold voltage can occur), and in the subsequent frame periods, the threshold voltage can be gradually shifted in a positive direction. Accordingly, the luminance of the conventional OLED display apparatus can be gradually increased under low-frequency driving due to the gradual positive shift of the threshold voltage. However, in the pixel 100 according to an example embodiment, the voltage for initializing the capacitor CST (i.e., the first power voltage ELVDD) and the voltage for initializing the OLEDEL (i.e., the initialization voltage VINT) can be different from each other, and when the capacitor CST is initialized, a gate-source voltage having a low absolute value (e.g., approximately 0 V in the case of the pixel 100) can be applied to the driving transistor or the fourth transistor T4. Accordingly, in the pixel 100 according to an example embodiment, a gradual increase in luminance under low-frequency driving can be prevented. Figure 1

[0061] In the following, examples will be described below with reference to Figure 2 to Figure 6 the pixel 100 operating under normal frequency driving. Figure 1

[0062] Figure 2 is a timing diagram of an example operation of the pixel 100 under normal frequency driving, Figure 1 is a circuit diagram of an example operation of the pixel 100 in an initialization period PINIT, Figure 3 is a circuit diagram of an example operation of the pixel 100 in a threshold voltage compensation period PVTH, Figure 1 is a circuit diagram of an example operation of the pixel 100 in a bias period PBIAS, and Figure 4 is a circuit diagram of an example operation of the pixel 100 in an emission period PEM. Figure 1 Figure 5 Reference is made to Figure 1 Figure 6 Figure 1

[0063] Figure 2 ​​​​​​​When the OLED display apparatus performs normal frequency driving in which the display panel is driven at a normal frequency (e.g., about 60 Hz or about 120 Hz), each frame period FP of the OLED display apparatus can include an initialization period PINIT, a threshold voltage compensation period PVTH, a bias period PBIAS, and an emission period PEM. In the initialization period PINIT, the threshold voltage compensation period PVTH, and the bias period PBIAS, an emission signal EM having an off level or a high level can be applied to the pixel 100.

[0064] In the initialization period PINIT, as shown in Figure 2 and Figure 3 , a first initialization signal GI_P having a low level as an active level or an on level can be applied, and a second initialization signal GI_N having a high level as an active level or an on level can be applied. The first transistor T1 can apply the first power voltage ELVDD to the first node N1 in response to the first initialization signal GI_P having the low level, and the second transistor T2 can apply the first power voltage ELVDD to the second node N2 in response to the second initialization signal GI_N having the high level. The capacitor CST can be initialized based on the first power voltage ELVDD at both the first node N1 and the second node N2. The capacitor CST can be discharged based on the first power voltage ELVDD at both the first electrode and the second electrode of the capacitor CST. Since the first power voltage ELVDD is applied to the second node N2 when the capacitor CST is initialized, the first power voltage ELVDD can be applied to a first terminal (e.g., a source) of the fourth transistor T4 and a gate of the fourth transistor T4. Accordingly, when the capacitor CST is initialized, a gate-source voltage of about 0 V can be applied to the fourth transistor T4.

[0065] In the threshold voltage compensation period PVTH, as shown in Figure 2 and Figure 4As shown in the middle, a data voltage VDAT can be provided through the data line DL, a first write signal GW_P having a low level as an active level or an on level can be applied, and a second write signal GW_N having a high level as an active level or an on level can be applied. The third transistor T3 can apply the data voltage VDAT provided through the data line DL to the first node N1 in response to the first write signal GW_P having the low level, and the fifth transistor T5 can diode-connect the fourth transistor T4 in response to the second write signal GW_N having the high level. Accordingly, in the threshold voltage compensation period PVTH, the data voltage VDAT can be stored at the first electrode of the capacitor CST, and a voltage (or “ELVDD-VTH”) corresponding to the first power voltage ELVDD minus the threshold voltage VTH of the fourth transistor T4 can be stored at the second electrode of the capacitor CST. This operation of the fifth transistor T5 diode-connecting the fourth transistor T4 to store the voltage (or “ELVDD-VTH”) corresponding to the first power voltage ELVDD minus the threshold voltage VTH of the fourth transistor T4 at the second electrode of the capacitor CST can be referred to as a threshold voltage compensation operation.

[0066] In the bias period PBIAS, as shown in the middle, Figure 2 and Figure 5 a scan signal SS having a low level as an active level or an on level can be applied. The sixth transistor T6 can apply the initialization voltage VINT to the fourth node N4 in response to the scan signal SS having the low level, and the seventh transistor T7 can apply the initialization voltage VINT to the first node N1 in response to the scan signal SS having the low level. Accordingly, the OLED EL can be initialized based on the initialization voltage VINT at the fourth node N4. In some example embodiments, the initialization voltage VINT can be substantially the same as the second power voltage ELVSS (e.g., about -3.5 V), and a parasitic capacitor of the OLED EL can be discharged based on the initialization voltage VINT at the anode of the OLED EL and the second power voltage ELVSS at the cathode of the OLED EL.

[0067] Furthermore, the initialization voltage VINT applied to the first node Nl by the seventh transistor T7 can change the voltage of the first electrode of the capacitor CST from the data voltage VDAT to the initialization voltage VINT. That is, the voltage of the first electrode of the capacitor CST can change by a voltage corresponding to the initialization voltage VINT minus the data voltage VDAT (or "VINT-VDAT"). In this case, the voltage of the second electrode of the capacitor CST can also change by a voltage corresponding to the initialization voltage VINT minus the data voltage VDAT (or "VINT-VDAT") by being coupled with the first electrode of the capacitor CST. Accordingly, the voltage of the second electrode of the capacitor CST can change from a voltage corresponding to the first supply voltage ELVDD minus the threshold voltage VTH (or "ELVDD-VTH") to a voltage corresponding to the initialization voltage VINT minus the data voltage VDAT (or "VINT-VDAT"), and thus to a voltage corresponding to the first supply voltage ELVDD minus the threshold voltage VTH plus the initialization voltage VINT minus the data voltage VDAT (or "ELVDD-VTH+VINT-VDAT"). In some example embodiments, the initialization voltage VINT can be a negative voltage or can be substantially the same as the second supply voltage ELVSS (e.g., about -3.5V), and thus the voltage of the second electrode of the capacitor CST (or "ELVDD-VTH+VINT-VDAT") can be lower than the first supply voltage ELVDD in the bias period PBIAS. Accordingly, a bias voltage (e.g., a turn-on bias voltage) can be applied to the fourth transistor T4, and the hysteresis of the fourth transistor T4 or the drive transistor can be initialized or compensated in the bias period PBIAS.

[0068] In the emission period PEM, as Figure 2 and Figure 6As shown, a low-level transmit signal EM, which is either an active or on-state level, can be applied. An eighth transistor T8 can apply a reference voltage VREF to the first node N1 in response to the low-level transmit signal EM. A fourth transistor T4 can generate a drive current based on the voltage at the second electrode of capacitor CST. A ninth transistor T9 can couple the third node N3 to the fourth node N4 in response to the low-level transmit signal EM, and the OLED EL can emit light based on the drive current generated by the fourth transistor T4. The eighth transistor T8, which is turned on in response to the transmit signal EM, can change the voltage at the first electrode of capacitor CST from the initialization voltage VINT to the reference voltage VREF at the first node N1. Therefore, by coupling with the first electrode of capacitor CST, the voltage at the second electrode of capacitor CST can be changed to the voltage corresponding to the first power supply voltage ELVDD minus the threshold voltage VTH minus the data voltage VDAT plus the reference voltage VREF (or "ELVDD-VTH-VDAT+VREF"). Therefore, the fourth transistor T4 can generate a drive current based on the data voltage VDAT and the reference voltage VREF, independent of the threshold voltage VTH of the fourth transistor T4. In some example embodiments, the reference voltage VREF can be, but is not limited to, approximately 0V.

[0069] In the following text, reference will be made to Figure 1 , Figure 7 and Figure 8 Description of operation under low-frequency drive Figure 1 An example of 100 pixels.

[0070] Figure 7 yes Figure 1 Timing diagram of example operation of pixel 100 under low-frequency drive, and Figure 8 It shows including Figure 1 An example of the brightness of a 100-pixel OLED display device driven at low frequency.

[0071] refer to Figure 1 and Figure 7OLED display device performs low frequency driving of the display panel of the OLED display device at a low frequency (e.g., about 1 Hz) lower than a normal frequency (e.g., about 60 Hz or about 120 Hz) in at least one frame period (e.g., the first frame period FP1) of a plurality of consecutive frame periods FP1, FP2, …, FPN. The low frequency frame period or the first frame period FP1 of the OLED display device can include an initialization period PINIT, a threshold voltage compensation period PVTH, a bias period PBIAS, and an emission period PEM, and each of the remaining frame periods FP2, …, FPN of the plurality of frame periods FP1, FP2, …, FPN can include only the bias period PBIAS and the emission period PEM. Here, the normal frequency can refer to a driving frequency of the display panel under normal frequency driving. In some example embodiments, the normal frequency can be an input frame frequency of input image data provided to the OLED display device. Further, the low frequency can be a driving frequency under low frequency driving, and can be any frequency lower than the normal frequency. In some example embodiments, the OLED display device can perform the low frequency driving of the display panel at the low frequency when input image data provided to the OLED display device represents a still image. In other example embodiments, the OLED display device can receive a mode signal indicating a low frequency driving mode from a main processor, and can perform the low frequency driving in response to the mode signal indicating the low frequency driving.

[0072] For example, in a case where a normal frequency of the OLED display apparatus is about 60 Hz, the OLED display apparatus can perform low frequency driving at a low frequency of about 1 Hz. In this case, a first frame period FP1 of 60 consecutive frame periods FP1, FP2, …, FPN can include an initialization period PINIT, a threshold voltage compensation period PVTH, a bias period PBIAS, and an emission period PEM, and each of the remaining 59 frame periods FP2, …, FPN of the 60 frame periods FP1, FP2, …, FPN can include only the bias period PBIAS and the emission period PEM. In another example, in a case where a normal frequency of the OLED display apparatus is about 120 Hz and the OLED display apparatus can perform low frequency driving at a low frequency of about 10 Hz, a first frame period FP1 of 12 consecutive frame periods FP1, FP2, …, FPN can include an initialization period PINIT, a threshold voltage compensation period PVTH, a bias period PBIAS, and an emission period PEM, and each of the remaining 11 frame periods FP2, …, FPN of the 12 frame periods FP1, FP2, …, FPN can include only the bias period PBIAS and the emission period PEM. As described above, a ratio of a number of the first frame periods FP1 including the four periods PINIT, PVTH, PBIAS, and PEM to a number of the total frame periods FP1, FP2, …, FPN under the low frequency driving can be a ratio of the low frequency to the normal frequency.

[0073] Since the first frame period FP1 of the plurality of frame periods FP1, FP2, …, FPN can include the four periods PINIT, PVTH, PBIAS, and PEM, and each of the remaining frame periods FP2, …, FPN can include only the bias period PBIAS and the emission period PEM, the scan signal SS applied in the bias period PBIAS and the emission signal EM applied in the emission period PEM can be provided at a normal frequency (e.g., about 60 Hz or about 120 Hz), and the first initialization signal GI_P and the second initialization signal GI_N, the first write signal GW_P and the second write signal GW_N, and the data voltage VDAT can be provided at a low frequency (e.g., about 1 Hz). Accordingly, when driving the display panel at the low frequency, power consumption of the OLED display apparatus can be reduced.

[0074] In Figure 7In the example of low-frequency driving shown in FIG. 6, the first frame period FP1 can include an initialization period PINT, a threshold voltage compensation period PVTH, a bias period PBIAS, and an emission period PEM. In the initialization period PINT, the first initialization signal GI P and the second initialization signal GI N can be applied, and the capacitor CST can be initialized. In the threshold voltage compensation period PVTH, the first write signal GW P and the second write signal GW N can be applied, the data voltage VDAT can be provided to the first electrode of the capacitor CST, and the first power supply voltage ELVDD minus the threshold voltage VTH (i.e., ELVDD-VTH) can be stored at the second electrode of the capacitor CST, so that the threshold voltage VTH of the fourth transistor T4 can be compensated. In the bias period PBIAS, the scan signal SS can be applied, the OLED EL can be initialized, the voltage of the second electrode of the capacitor CST can be changed based on the initialization voltage VINT applied to the first electrode of the capacitor CST, and a bias voltage (e.g., a turn-on bias voltage) can be applied to the fourth transistor T4 based on the changed voltage of the second electrode of the capacitor CST. In the emission period PEM, the emission signal EM can be applied, and the OLED EL can emit light.

[0075] Each of subsequent frame periods, i.e., the second to Nth frame periods FP2,..., FPN, can include only the bias period PBIAS and the emission period PEM, where N is an integer greater than 1. In the bias period PBIAS of the subsequent frame periods, the OLED EL can be initialized, and a bias voltage (e.g., a turn-on bias voltage) can be applied to the fourth transistor T4. Thus, under low-frequency driving, although the first initialization signal GI P and the second initialization signal GI N, the first write signal GW P and the second write signal GW N, and the data voltage VDAT can not be provided in the second to Nth frame periods FP2,..., FPN, the turn-on bias voltage can be applied to the fourth transistor T4, and thus the hysteresis of the fourth transistor T4 can be periodically initialized or compensated. Further, in the emission period PEM, the OLED EL can emit light. Thus, under low-frequency driving, the OLED EL can emit light at substantially the same brightness as under normal frequency driving.

[0076] As a comparative example, in a conventional OLED display apparatus performing low-frequency driving, the storage capacitor or capacitor CST can be initialized by using the initialization voltage VINT in the first frame period FP1, and at this time, the initialization voltage VINT (e.g., approximately -3.5 V) can be applied to the gate of the driving transistor or fourth transistor T4 of each pixel, and the gate-source voltage having a high absolute value can be applied to the driving transistor as a bias voltage. Further, in subsequent frame periods FP2,..., FPN, the bias voltage can not be applied to the driving transistor. In this case, in the first frame period FP1, the threshold voltage of the driving transistor can be shifted in the negative direction (i.e., a negative shift of the threshold voltage can occur), and in the subsequent frame periods FP2,..., FPN, the threshold voltage can be gradually shifted in the positive direction. Referring to Figure 8 Under low-frequency driving using a low frequency of approximately 1 Hz, the luminance 140 of the conventional OLED display apparatus can gradually increase in each period (one second in the present example) corresponding to the low frequency of approximately 1 Hz. However, in the pixel 100, the voltage for initializing the capacitor CST (i.e., the first power voltage ELVDD) and the voltage for initializing the OLED EL (i.e., the initialization voltage VINT) can be different from each other, and when the capacitor CST is initialized, the gate-source voltage having a low absolute value (e.g., approximately 0 V) can be applied to the driving transistor or fourth transistor T4. Accordingly, in the pixel 100, the luminance 120 of the present OLED display apparatus can be maintained at a substantially constant level under low-frequency driving, unlike the luminance 140 of the conventional OLED display apparatus, without gradually increasing. Figure 1

[0077] Figure 9 is a circuit diagram illustrating a pixel 200 of an OLED display apparatus according to an example embodiment.

[0078] Referring to Figure 9 , the pixel 200 of the OLED display apparatus can include the capacitor CST, the first to ninth transistors T1, T2', T3, T4, T5', T6, T7, T8, and T9, and the OLED EL. The pixel 200 can have a similar configuration and similar operation as the pixel 100 of Figure 1 , except that the second transistor T2' and the fifth transistor T5' can further include the first and second bottom electrodes BML1 and BML2.

[0079] ​The second transistor T2’ can include a gate receiving the second initialization signal GI_N, a first terminal receiving the first power supply voltage ELVDD, a second terminal coupled to the second node N2, and a first bottom electrode BML1 receiving the second initialization signal GI_N. In some example embodiments, the first bottom electrode BML1 can be disposed under the gate of the second transistor T2’. Accordingly, the first bottom electrode BML1 can block internal light and / or external light to prevent a change in characteristics of the second transistor T2’ due to the internal light and / or the external light. For example, the first bottom electrode BML1 can block light (e.g., infrared light) emitted by a light sensor (e.g., an infrared sensor) located under the second transistor T2’. In some example embodiments, the first bottom electrode BML1 can include, but is not limited to, molybdenum (Mo). In other example embodiments, the first bottom electrode BML1 can include a low-resistance opaque conductive material such as aluminum (Al), an aluminum alloy, tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), platinum (Pt), tantalum (Ta), etc.

[0080] The fifth transistor T5’ can include a gate receiving the second write signal GW_N, a first terminal coupled to the third node N3, a second terminal coupled to the second node N2, and a second bottom electrode BML2 receiving the second write signal GW_N. In some example embodiments, the second bottom electrode BML2 can be disposed under the gate of the fifth transistor T5’. Accordingly, the second bottom electrode BML2 can block internal light and / or external light to prevent a change in characteristics of the fifth transistor T5’ due to the internal light and / or the external light. In some example embodiments, the second bottom electrode BML2 can include, but is not limited to, Mo. In other example embodiments, the second bottom electrode BML2 can include a low-resistance opaque conductive material such as Al, an Al alloy, W, Cu, Ni, Cr, Ti, Pt, Ta, etc.

[0081] Figure 10 is a circuit diagram illustrating a pixel 300 of an OLED display apparatus according to an example embodiment.

[0082] Referring to Figure 10 , the pixel 300 of the OLED display apparatus can include the capacitor CST, the first to ninth transistors T1, T2”, T3, T4, T5”, T6, T7, T8, and T9, and the OLED EL. The pixel 300 can have a similar configuration and similar operations as the pixel 100 of Figure 1 , except that the second transistor T2” and the fifth transistor T5” can further include the first bottom electrode BML1 and the second bottom electrode BML2.

[0083] The second transistor T2” can include a gate that receives the second initialization signal GI_N, a first terminal that receives the first power supply voltage ELVDD, a second terminal that is coupled to the second node N2, and a first bottom electrode BML1 that is coupled to the first terminal of the second transistor T2”. In some example embodiments, the first bottom electrode BML1 can be disposed under the gate of the second transistor T2”. In some example embodiments, the first bottom electrode BML1 can include, but is not limited to, Mo. In other example embodiments, the first bottom electrode BML1 can include a low-resistance opaque conductive material such as Al, Al alloy, W, Cu, Ni, Cr, Ti, Pt, Ta, etc.

[0084] The fifth transistor T5” can include a gate that receives the second write signal GW_N, a first terminal that is coupled to the third node N3, a second terminal that is coupled to the second node N2, and a second bottom electrode BML2 that is coupled to the second terminal of the fifth transistor T5”. In some example embodiments, the second bottom electrode BML2 can be disposed under the gate of the fifth transistor T5”. In some example embodiments, the second bottom electrode BML2 can include, but is not limited to, Mo. In other example embodiments, the second bottom electrode BML2 can include a low-resistance opaque conductive material such as Al, Al alloy, W, Cu, Ni, Cr, Ti, Pt, Ta, etc.

[0085] Figure 11 is a circuit diagram illustrating a pixel 400 of an OLED display apparatus according to an example embodiment.

[0086] Referring to Figure 11 , the pixel 400 of the OLED display apparatus can include the capacitor CST, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6’, the eighth transistor T8’, and the ninth transistor T9, and the OLED EL. The pixel 400 can have a similar configuration and similar operation as the pixel 100 of Figure 1 , except that the pixel 400 can not include the seventh transistor T7, the sixth transistor T6’ can receive the first write signal GW_P instead of the scan signal SS, and the eighth transistor T8’ can transfer the initialization voltage VINT instead of the reference voltage VREF to the first node N1.

[0087] In Figure 11In pixel 400, capacitor CST may include a first electrode coupled to a first node N1 and a second electrode coupled to a second node N2. First transistor T1 may include a gate receiving a first initialization signal GI_P, a first terminal receiving a first power supply voltage ELVDD, and a second terminal coupled to the first node N1. Second transistor T2 may include a gate receiving a second initialization signal GI_N, a first terminal receiving the first power supply voltage ELVDD, and a second terminal coupled to the second node N2. Third transistor T3 may include a gate receiving a first write signal GW_P, a first terminal coupled to a data line DL, and a second terminal coupled to the first node N1. Fourth transistor T4 may include a gate coupled to the second node N2 and a first terminal receiving the first power supply voltage. The first terminal of ELVDD and the second terminal coupled to the third node N3, the fifth transistor T5 may include a gate for receiving the second write signal GW_N, a first terminal coupled to the third node N3 and a second terminal coupled to the second node N2, the sixth transistor T6' may include a gate for receiving the first write signal GW_P, a first terminal for receiving the initialization voltage VINT and a second terminal coupled to the fourth node N4, the eighth transistor T8' may include a gate for receiving the transmit signal EM, a first terminal for receiving the initialization voltage VINT and a second terminal coupled to the first node N1, the ninth transistor T9 may include a gate for receiving the transmit signal EM, a first terminal coupled to the third node N3 and a second terminal coupled to the fourth node N4, and the OLED EL may include an anode coupled to the fourth node N4 and a cathode for receiving the second power supply voltage ELVSS.

[0088] In some example embodiments, such as Figure 11 As shown, the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6', the eighth transistor T8', and the ninth transistor T9 can be PMOS transistors, while the second transistor T2 and the fifth transistor T5 can be NMOS transistors. In this case, since the second transistor T2 and the fifth transistor T5, which are directly connected to the second node N2 (or the second electrode of the capacitor CST), are implemented using NMOS transistors, the leakage current from the second electrode of the capacitor CST can be reduced. Therefore, when the pixel 400 is driven at a low frequency below the normal frequency (e.g., approximately 60 Hz or approximately 120 Hz), the voltage at the second electrode of the capacitor CST can remain substantially unchanged, and thus the pixel 400 can be suitable for low-frequency driving.

[0089] Further, in the pixel 400, the voltage used to initialize the capacitor CST (i.e., the first power supply voltage ELVDD) and the voltage used to initialize the OLED EL (i.e., the initialization voltage VINT) can be different from each other, and when the capacitor CST is initialized, a gate-source voltage having a low absolute value (e.g., approximately 0 V) can be applied to the drive transistor or the fourth transistor T4 in the case of the pixel 400. Thus, in the pixel 400, the brightness of the OLED display device can be maintained at a substantially constant level, thereby preventing gradual increase in brightness at low frequency driving. Figure 11

[0090] In the following, examples will be described below with reference to Figure 12 to Figure 15 the pixel 400 operating Figure 11 at normal frequency driving.

[0091] Figure 12 is a timing diagram of an example operation of the pixel 400 at normal frequency driving, Figure 11 is a circuit diagram of an example operation of the pixel in the initialization period PINIT, Figure 13 is a circuit diagram of an example operation of the pixel 400 in the threshold voltage compensation period PVTH, and Figure 11 is a circuit diagram of an example operation of the pixel 400 in the emission period PEM. Figure 14 Figure 11 With reference to Figure 15 , when the OLED display device performs normal frequency driving to drive the display panel at a normal frequency (e.g., approximately 60 Hz or approximately 120 Hz), each frame period FP of the OLED display device can include an initialization period PINIT, a threshold voltage compensation period PVTH, and an emission period PEM. In the initialization period PINIT and the threshold voltage compensation period PVTH, an emission signal EM having an off level or a high level can be applied to the pixel 400. Figure 11 In the initialization period PINIT, as

[0092] and Figure 12

[0093] In the initialization period PINIT, as Figure 12 and Figure 13 ​​​As shown in FIG. 1, the first transistor T1 and the second transistor T2 can apply the first supply voltage ELVDD to the first node N1 and the second node N2, respectively, in response to the first initialization signal GI_P and the second initialization signal GI_N. The capacitor CST can be initialized or discharged based on the first supply voltage ELVDD at both the first node N1 and the second node N2. When the capacitor CST is initialized, a gate-source voltage of about 0 V can be applied to the fourth transistor T4. Accordingly, when the OLED display apparatus including the pixel 400 performs low-frequency driving, a gradual increase in luminance under low-frequency driving can be prevented.

[0094] In the threshold voltage compensation period PVTH, as shown in Figure 12 and Figure 14 The third transistor T3 can apply a data voltage VDAT provided through a data line DL to the first node N1 in response to a first write signal GW_P, and the fifth transistor T5 can diode-connect the fourth transistor T4 in response to a second write signal GW_N. Accordingly, the data voltage VDAT can be stored at a first electrode of the capacitor CST, and a voltage corresponding to the first supply voltage ELVDD minus the threshold voltage VTH of the fourth transistor T4 (or "ELVDD-VTH") can be stored at a second electrode of the capacitor CST. Further, the sixth transistor T6' can apply an initialization voltage VINT to the fourth node N4 in response to the first write signal GW_P, and the OLED EL can be initialized based on the initialization voltage VINT at the fourth node N4.

[0095] In the emission period PEM, as shown in Figure 12 and Figure 15As shown in FIG. 8, the eighth transistor T8’ can apply the initialization voltage VINT to the first node N1 in response to the emission signal EM, the fourth transistor T4 can generate the drive current based on the voltage of the second electrode of the capacitor CST, the ninth transistor T9 can couple the third node N3 to the fourth node N4 in response to the emission signal EM, and the OLED EL can emit light based on the drive current generated by the fourth transistor T4. The eighth transistor T8’ turned on in response to the emission signal EM can change the voltage of the first electrode of the capacitor CST from the data voltage VDAT to the initialization voltage VINT at the first node N1, and thus the voltage of the second electrode of the capacitor CST can be changed to a voltage (or “ELVDD-VTH+VINT-VDAT”) corresponding to the first power voltage ELVDD minus the threshold voltage VTH plus the initialization voltage VINT minus the data voltage VDAT by being coupled with the first electrode of the capacitor CST. Accordingly, the fourth transistor T4 can generate the drive current based on the data voltage VDAT and the initialization voltage VINT regardless of the threshold voltage VTH of the fourth transistor T4. In some example embodiments, the voltage level of the data voltage VDAT can be determined by considering the voltage level of the initialization voltage VINT so that the amount of the drive current can be determined regardless of the initialization voltage VINT.

[0096] In the following, example operations of the pixel 400 in low-frequency driving will be described below with reference to Figure 11 and Figure 16 Figure 11

[0097] Figure 16 is a timing diagram of the example operations of the pixel 400 in low-frequency driving. Figure 11

[0098] With reference to Figure 11 and Figure 16 , the OLED display apparatus performs low-frequency driving of driving a display panel of the OLED display apparatus at a low frequency (e.g., about 1 Hz) lower than a normal frequency (e.g., about 60 Hz or about 120 Hz) in at least one frame period (e.g., a first frame period FP1) among a plurality of consecutive frame periods FP1, FP2, …, FPN. The low-frequency frame period or the first frame period FP1 of the OLED display apparatus can include an initialization period PINIT, a threshold voltage compensation period PVTH, and an emission period PEM, and each of the remaining frame periods FP2, …, FPN among the plurality of frame periods FP1, FP2, …, FPN can include only the emission period PEM.

[0099] ​​​Since the first frame period FP1 of the plurality of frame periods FP1, FP2, …, FPN can include the three periods PINIT, PVTH, and PEM, and each of the remaining frame periods FP2, …, FPN can include only the emission period PEM, the emission signal EM applied in the emission period PEM can be provided at a normal frequency (e.g., about 60 Hz or about 120 Hz), while the first and second initialization signals GI_P and GI_N, the first and second write signals GW_P and GW_N, and the data voltage VDAT can be provided at a low frequency (e.g., about 1 Hz). Thus, when the display panel is driven at a low frequency, the power consumption of the OLED display apparatus can be reduced.

[0100] In Figure 16 the example of low-frequency driving shown in FIG. 4, the first frame period FP1 can include an initialization period PINIT, a threshold voltage compensation period PVTH, and an emission period PEM. In the initialization period PINIT, the first and second initialization signals GI_P and GI_N can be applied, and the capacitor CST can be initialized. In the threshold voltage compensation period PVTH, the first and second write signals GW_P and GW_N can be applied, the data voltage VDAT can be provided to the first electrode of the capacitor CST, and the first supply voltage ELVDD minus the threshold voltage VTH (i.e., ELVDD-VTH) can be stored at the second electrode of the capacitor CST so as to compensate for the threshold voltage VTH of the fourth transistor T4, and the OLED EL can be initialized based on the initialization voltage VINT. In the emission period PEM, the OLED EL can emit light. Each of the subsequent frame periods, i.e., the second to Nth frame periods FP2, …, FPN, can include only the emission period PEM in which the OLED EL can emit light.

[0101] In the pixel 400, the voltage for initializing the capacitor CST (i.e., the first supply voltage ELVDD) and the voltage for initializing the OLED EL (i.e., the initialization voltage VINT) can be different from each other, and when the capacitor CST is initialized, a gate-source voltage having a low absolute value (e.g., about 0 V) can be applied to the driving transistor or the fourth transistor T4. Thus, in the pixel 400, the brightness of the present OLED display apparatus can be maintained at a substantially constant level, thereby preventing gradual increase in brightness at low-frequency driving. Figure 11

[0102] Figure 17 is a block diagram illustrating an OLED display apparatus 500 according to an example embodiment.

[0103] Referring to Figure 17 ​The OLED display device 500 may include a display panel 510, a data driver 530, a scan driver 550, an emission driver 570, and a controller 590.

[0104] The display panel 510 may include a plurality of pixels PX. According to an example embodiment, each pixel PX may be associated with... Figure 1 100 pixels Figure 9 200 pixels Figure 10 300 pixels or Figure 11 There are 400 corresponding pixels. Each pixel PX can be a hybrid oxide polycrystalline (HOP) pixel suitable for low-frequency driving and capable of reducing power consumption. In a HOP pixel, at least one transistor can be implemented using an LTPS PMOS transistor, and at least another transistor can be implemented using an oxide NMOS transistor. Furthermore, in each pixel PX, the voltage used to initialize the capacitor and the voltage used to initialize the OLED can be different from each other, and a gate-source voltage with a low absolute value can be applied to the driving transistor. Therefore, a gradual increase in brightness under low-frequency driving can be prevented.

[0105] Data driver 530 can provide a data voltage VDAT to multiple pixels PX based on a data control signal DCTRL received from controller 590 and output image data ODAT. In some example embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a level start signal, and a load signal. In some example embodiments, data driver 530 and controller 590 can be implemented using a single integrated circuit (IC), and this single integrated circuit may be referred to as a timing controller embedded data driver (TED). In other example embodiments, data driver 530 and controller 590 can be implemented using separate integrated circuits.

[0106] The scan driver 550 can sequentially provide the plurality of first initialization signals GI P, the plurality of second initialization signals GI N, the plurality of first write signals GW P, the plurality of second write signals GW N, and / or the plurality of scan signals SS to the plurality of pixels PX row by row based on a scan control signal SCTRL received from the controller 590. In some example embodiments, the scan control signal SCTRL can include, but is not limited to, a scan start signal and a scan clock signal. In some example embodiments, the plurality of first initialization signals GI P, the plurality of first write signals GW P, and the plurality of scan signals SS can be signals suitable for PMOS transistors, and can be active low signals having a low level as an active level. The plurality of second initialization signals GI N and the plurality of second write signals GW N can be signals suitable for NMOS transistors, and can be active high signals having a high level as an active level. In some example embodiments, the first initialization signal GI P for a current pixel row can correspond to the first write signal GW P for a previous pixel row, and the second initialization signal GI N for the current pixel row can correspond to the second write signal GW N for the previous pixel row. Further, in some example embodiments, the scan signal SS for the current pixel row can be, but is not limited to, the first write signal GW P for a next pixel row. In some example embodiments, the scan driver 550 can be integrated or formed in a peripheral portion of the display panel 510. In other example embodiments, the scan driver 550 can be implemented using one or more integrated circuits.

[0107] The emission driver 570 can provide an emission signal EM to the plurality of pixels PX based on an emission control signal EMCTRL received from the controller 590. In some example embodiments, the emission signal EM can be sequentially provided to the plurality of pixels PX row by row. In other example embodiments, the emission signal EM can be a global signal provided to the plurality of pixels PX substantially simultaneously. In some example embodiments, the emission driver 570 can be integrated or formed in a peripheral portion of the display panel 510. For example, the emission driver 570 can be provided in a peripheral portion opposite to the scan driver 550. In other example embodiments, the emission driver 570 can be implemented using one or more integrated circuits.

[0108] The controller 590 (e.g., a timing controller (TCON)) can receive input image data IDAT and control signals CTRL from an external main processor (e.g., a graphics processing unit (GPU) or a graphics card). In some example embodiments, the control signals CTRL can include, but are not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc. The controller 590 can generate output image data ODAT, data control signals DCTRL, scan control signals SCTRL, and emission control signals EMCTRL based on the input image data IDAT and the control signals CTRL. The controller 590 can control the operation of the data driver 530 by providing the output image data ODAT and the data control signals DCTRL to the data driver 530, can control the operation of the scan driver 550 by providing the scan control signals SCTRL to the scan driver 550, and can control the operation of the emission driver 570 by providing the emission control signals EMCTRL to the emission driver 570.

[0109] In some example embodiments, the controller 590 can determine whether the input image data IDAT represents a still image, and can perform low-frequency driving of the display panel 510 at a low frequency lower than a normal frequency (e.g., an input frame frequency of the input image data IDAT) based on the input image data IDAT representing a still image. When performing the low-frequency driving, the controller 590 can provide the output image data ODAT to the data driver 530 at the low frequency. Accordingly, under the low-frequency driving, the data driver 530 can provide the data voltage VDAT to the display panel 510 at the low frequency, and thus power consumption of the OLED display apparatus 500 can be reduced. Further, in some example embodiments, under the low-frequency driving, the controller 590 can control the emission driver 570 to provide the emission signal EM at the normal frequency, and can control the scan driver 550 to provide the first initialization signal GI_P, the second initialization signal GI_N, the first write signal GW_P, and the second write signal GW_N at the low frequency, and to provide the scan signal SS at the normal frequency.

[0110] In other example embodiments, the controller 590 can receive a mode signal explicitly indicating the low-frequency driving from the main processor, and can perform the low-frequency driving in response to the mode signal. In this case, the output image data ODAT output from the controller 590 as well as the input image data IDAT provided from the main processor can all be provided at the low frequency suitable for the low-frequency driving. Accordingly, under the low-frequency driving, the input frame frequency of the input image data IDAT can be changed from the normal frequency to the low frequency.

[0111] Figure 18 An electronic device 1100 including an OLED display apparatus 1160 according to an example embodiment.

[0112] Referring to Figure 18 , the electronic device 1100 can include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and an OLED display device 1160. The electronic device 1100 can further include a plurality of ports for communication with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic components and / or devices, etc.

[0113] The processor 1110 can perform various computing tasks. The processor 1110 can be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 can be coupled to other components of the electronic device 1100 via an address bus, a control bus, a data bus, etc. Further, in some example embodiments, the processor 1110 can be further coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0114] The memory device 1120 can store data for operation of the electronic device 1100. For example, the memory device 1120 can include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nanofloating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.

[0115] The storage device 1130 can be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1140 can be an input device such as a keyboard, a keypad, a mouse, a touchscreen, etc., and an output device such as a printer, a speaker, etc. The power supply 1150 can supply power for operation of the electronic device 1100. The OLED display device 1160 can be coupled to other components of the electronic device 1100 through a bus and / or various communication links.

[0116] Each pixel of the OLED display apparatus 1160 can be an HOP pixel suitable for low frequency driving and capable of reducing power consumption. Further, in each pixel of the OLED display apparatus 1160, a voltage for initializing a capacitor and a voltage for initializing an OLED can be different from each other, and a gate-source voltage having a low absolute value can be applied to a driving transistor when the capacitor is initialized. Accordingly, a gradual increase in luminance under low frequency driving can be prevented.

[0117] The inventive concept of the present disclosure can be applied to any OLED display apparatus 1160 and any electronic device 1100 including the OLED display apparatus 1160. Examples of the electronic device 1100 can include, but are not limited to, a mobile phone, a smart phone, a wearable electronic device, a tablet computer, a television (TV), a digital TV, a three-dimensional (3D) TV, a personal computer (PC), a home appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game machine, and a navigation device.

[0118] The foregoing is a summary of example embodiments of the inventive concept and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily understand that modifications and variations of the example embodiments are possible without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, such modifications and variations are intended to be included within the scope of the inventive concept as defined by the claims. It should be understood that both the foregoing summary and the following detailed description are exemplary and explanatory only and are not intended to be restrictive. The disclosed example embodiments are intended to be protected within the scope of the following claims.

Claims

1. A pixel of an organic light emitting diode display apparatus, the pixel comprising: a capacitor including a first electrode coupled to a first node and a second electrode coupled to a second node; a first transistor including a gate receiving a first initialization signal, a first terminal receiving a first power voltage, and a second terminal coupled to the first node; a second transistor including a gate receiving a second initialization signal, a first terminal receiving the first power voltage, and a second terminal coupled to the second node; a third transistor including a first terminal coupled to a data line and a second terminal coupled to the first node; a fourth transistor including a gate coupled to the second node, a first terminal receiving the first power voltage, and a second terminal coupled to a third node; a fifth transistor including a first terminal coupled to the third node and a second terminal coupled to the second node; a sixth transistor including a gate receiving a scan signal, a first terminal receiving an initialization voltage, and a second terminal coupled to a fourth node; a seventh transistor including a gate receiving the scan signal, a first terminal receiving the initialization voltage, and a second terminal coupled to the first node; an eighth transistor including a gate receiving an emission signal, a first terminal receiving a reference voltage, and a second terminal coupled to the first node; a ninth transistor including a first terminal coupled to the third node and a second terminal coupled to the fourth node; and an organic light emitting diode including an anode coupled to the fourth node and a cathode receiving a second power voltage, wherein the initialization voltage for initializing the organic light emitting diode is different from the first power voltage for initializing the capacitor. 2.The pixel of claim 1, wherein the pixel includes at least one P-type metal oxide semiconductor transistor and at least one N-type metal oxide semiconductor transistor. 3.The pixel of claim 2, wherein the first transistor, the third transistor, the fourth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are P-type metal oxide semiconductor transistors, and wherein the second transistor and the fifth transistor are N-type metal oxide semiconductor transistors. 4.The pixel of claim 1, wherein the organic light emitting diode display apparatus is operable to perform normal frequency driving by driving the pixel at a normal frequency, and each frame period of the organic light emitting diode display apparatus under the normal frequency driving includes: an initialization period in which the capacitor is initialized; a threshold voltage compensation period in which a data voltage is provided to the first electrode of the capacitor through the data line and a threshold voltage of the fourth transistor is compensated; a bias period in which a bias voltage is applied to the fourth transistor and the organic light emitting diode is initialized; and an emission period in which the organic light emitting diode emits light. ​ ​ 5. The pixel of claim 4, wherein, In the initialization period, the first transistor applies the first supply voltage to the first node in response to the first initialization signal having a first level, and the second transistor applies the first supply voltage to the second node in response to the second initialization signal having a second level, the second initialization signal having an opposite polarity of the first initialization signal.

6. The pixel of claim 5, wherein in the initialization period, the capacitor is initialized based on the first supply voltage at the first node and the second node, and the first supply voltage is applied to the first terminal of the fourth transistor and the gate of the fourth transistor.

7. The pixel of claim 4, wherein, In the threshold voltage compensation period, the third transistor applies the data voltage provided through the data line to the first node in response to a first write signal having a first level applied to a gate of the third transistor, and the fifth transistor diode connects the fourth transistor in response to a second write signal having a second level applied to a gate of the fifth transistor, and wherein the second write signal has an opposite polarity of the first write signal.

8. The pixel of claim 7, wherein in the threshold voltage compensation period, the data voltage is stored at the first electrode of the capacitor, and the first supply voltage minus the threshold voltage of the fourth transistor is stored at the second electrode of the capacitor.

9. A pixel of an organic light emitting diode display apparatus, the pixel comprising: a capacitor including a first electrode coupled to a first node and a second electrode coupled to a second node; a first transistor including a gate receiving a first initialization signal, a first terminal receiving a first supply voltage, and a second terminal coupled to the first node; a second transistor including a gate receiving a second initialization signal, a first terminal receiving the first supply voltage, and a second terminal coupled to the second node; a drive transistor including a gate coupled to the second node, a first terminal receiving the first supply voltage, and a second terminal coupled to a third node; a fifth transistor including a first terminal coupled to the third node and a second terminal coupled to the second node; an emission transistor including a gate receiving an emission signal; an organic light emitting diode coupled to the emission transistor and including a cathode receiving a second supply voltage; and a sixth transistor including a first terminal receiving an initialization voltage and a second terminal coupled to the emission transistor and the organic light emitting diode, wherein the initialization voltage for initializing the organic light emitting diode is different from the first supply voltage for initializing the capacitor.

10. An organic light emitting diode display apparatus comprising a plurality of pixels, each of the plurality of pixels comprising: a capacitor including a first electrode coupled to a first node and a second electrode coupled to a second node; a first transistor including a gate receiving a first initialization signal, a first terminal receiving a first supply voltage, and a second terminal coupled to the first node; a second transistor including a gate receiving a second initialization signal, a first terminal receiving the first supply voltage, and a second terminal coupled to the second node; a drive transistor including a gate coupled to the second node, a first terminal receiving the first supply voltage, and a second terminal coupled to a third node; a fifth transistor including a first terminal coupled to the third node and a second terminal coupled to the second node; an emission transistor including a gate receiving an emission signal; an organic light emitting diode coupled to the emission transistor and including a cathode receiving a second supply voltage; and a sixth transistor including a first terminal receiving an initialization voltage and a second terminal coupled to the emission transistor and the organic light emitting diode, wherein the initialization voltage for initializing the organic light emitting diode is different from the first supply voltage for initializing the capacitor. a first transistor comprising a gate receiving a first initialization signal, a first terminal receiving a first supply voltage, and a second terminal coupled to the first node; a second transistor comprising a gate receiving a second initialization signal, a first terminal receiving the first supply voltage, and a second terminal coupled to the second node; a driving transistor comprising a gate coupled to the second node, a first terminal receiving the first supply voltage, and a second terminal coupled to a third node; a fifth transistor comprising a first terminal coupled to the third node, and a second terminal coupled to the second node; a driving transistor comprising a gate coupled to the second node, a first terminal receiving the first supply voltage, and a second terminal coupled to a third node; a fifth transistor comprising a first terminal coupled to the third node, and a second terminal coupled to the second node; a driving transistor comprising a gate coupled to the second node, a first terminal receiving the first supply voltage, and a second terminal coupled to a third node; a fifth transistor comprising a first terminal coupled to the third node, and a second terminal coupled to the second node; a driving transistor comprising a gate coupled to the second node, a first terminal receiving the first supply voltage, and a second terminal coupled to a third node; a fifth transistor comprising a first terminal coupled to the third node, and a second terminal coupled to the second node; a driving transistor comprising a gate coupled to the second node, a first terminal receiving the first supply voltage, and a second terminal coupled to a third node; a fifth transistor comprising a first terminal coupled to the third node, and a second terminal coupled to the second node; a driving transistor comprising a gate coupled to the second node, a first terminal receiving the first supply voltage, and a second terminal coupled to a third node; a fifth transistor comprising a first terminal coupled to the third node, and a second terminal coupled to the second node; a driving transistor comprising a gate coupled to the second node, a first terminal receiving the first supply voltage, and a second terminal coupled to a third node; a fifth transistor comprising a first terminal coupled to the third node, and a second terminal coupled to the second node; a driving transistor comprising a gate coupled to the second node, a first terminal receiving the first supply voltage, and a second terminal coupled to a third node; a fifth transistor comprising a first terminal coupled to the third node, and a second terminal coupled to the second node; a driving transistor comprising a gate coupled to the second node, a first terminal receiving the first supply voltage, and a second terminal coupled to a third node; a fifth transistor comprising a first terminal coupled to the third node, and a second terminal coupled to the second node; a driving transistor comprising a gate coupled to the second node, a first terminal receiving the first supply voltage, and a second terminal coupled to a third node; a fifth transistor comprising a first terminal coupled to the third node, and a second terminal

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