Display Devices

Abstract

The display device includes: a thin film transistor on a substrate, the thin film transistor including a first semiconductor layer and a first gate electrode overlapping the first semiconductor layer, wherein a first gate insulating layer is arranged between the first semiconductor layer and the first gate electrode; a storage capacitor, the storage capacitor including a lower electrode including a first lower layer and a first upper layer stacked on each other and an upper electrode including a second lower layer and a second upper layer stacked on each other, wherein the upper electrode overlaps the lower electrode and the second gate insulating layer is arranged between the upper electrode and the lower electrode; and a display element electrically connected to the thin film transistor, wherein the second upper layer has a thickness greater than a thickness of the first upper layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0139738 filed in the Korean Intellectual Property Office on November 4, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display device, and to a display device having improved resistance of a gate electrode of a thin film transistor and / or an electrode of a storage capacitor. Background Art

[0004] A display device is a device for visually displaying data. A display device can be used as a display in a small product such as a mobile phone or a display in a large product such as a television.

[0005] The display device may include a substrate including a display area and a non-display area. One or more gate lines and one or more data lines may be insulated from each other in the display area. The pixel area may be defined at the intersection between the gate line and the data line in the display area, and the pixel area may emit light by receiving an electrical signal to display an image to the outside. A thin film transistor and a pixel electrode electrically connected to the thin film transistor may be provided corresponding to each of the pixel areas, and a relative electrode may be provided in common with respect to the pixel area. For example, the non-display area may include various signal lines, a gate driver, a data driver, or a controller for transmitting an electrical signal to the display area.

[0006] The use of display devices and design efforts for quality improvement have been increasing. For example, in the context of display devices with high resolution, research is being actively conducted to improve quality.

[0007] It is to be understood that this background technology section is intended in part to provide a useful background for understanding the technology. However, this background technology section may also include ideas, concepts or perceptions that were not known or understood by a person skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0008] One or more embodiments include a display device having improved resistance of a gate electrode of a thin film transistor and / or an electrode of a storage capacitor. However, the above technical features are exemplary, and the scope of the present disclosure is not limited thereto.

[0009] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0010] According to one or more embodiments, a display device may include: a substrate; a thin film transistor on the substrate, the thin film transistor may include a first semiconductor layer and a first gate electrode overlapping the first semiconductor layer, wherein a first gate insulating layer may be disposed between the first semiconductor layer and the first gate electrode; a storage capacitor, the storage capacitor including a lower electrode including a first lower layer and a first upper layer stacked on each other and an upper electrode including a second lower layer and a second upper layer stacked on each other, wherein the upper electrode may overlap the lower electrode and the second gate insulating layer may be disposed between the upper electrode and the lower electrode; and a display element electrically connected to the thin film transistor, wherein the second upper layer may have a thickness greater than that of the first upper layer.

[0011] The lower electrode and the first gate electrode may include the same material.

[0012] The first upper layer may have a thickness in the range of about 40 nm to about 60 nm, and the second upper layer may have a thickness in the range of about 40 nm to about 140 nm.

[0013] At least one of the first lower layer and the second lower layer may have a thickness in the range of about 130 nm to about 1000 nm.

[0014] The first upper layer and the second upper layer may include tantalum (Ta).

[0015] The upper electrode may overlap the thin film transistor.

[0016] The display device may further include a thin film encapsulation layer on the substrate, the thin film encapsulation layer facing the substrate.

[0017] The display device may further include an encapsulation substrate on the substrate, and the encapsulation substrate may face the substrate.

[0018] The first lower layer and the second lower layer may include an aluminum alloy including a first element and aluminum (Al), and a content of the first element may be about 0.1 at % or less with respect to the aluminum alloy.

[0019] The first element may be selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt), dammium (Ds), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu).

[0020] The aluminum alloy may include a second element that may be different from the first element, and a total amount of the first element and the second element may be about 0.1 at % or less with respect to the aluminum alloy.

[0021] The first element may be selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt) and dammium (Ds), and the second element may be selected from the group consisting of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu).

[0022] According to one or more embodiments, a display device may include: a substrate; a first thin film transistor on the substrate, the first thin film transistor including a first semiconductor layer and a first gate electrode overlapping the first semiconductor layer, wherein a first gate insulating layer may be disposed between the first semiconductor layer and the first gate electrode; and a display element electrically connected to the first thin film transistor, wherein the first gate electrode may include a third lower layer and a third upper layer stacked on each other, the third lower layer may include an aluminum alloy including a first element and aluminum (Al), and a content of the first element in the third lower layer may be approximately 0.1 at % or less relative to the aluminum alloy.

[0023] The display device may further include a second thin film transistor on the substrate, the second thin film transistor including a second semiconductor layer and a second gate electrode overlapping the second semiconductor layer, wherein the first gate insulating layer may be disposed between the second semiconductor layer and the second gate electrode. The second gate electrode may include a fourth lower layer and a fourth upper layer stacked on each other, the fourth lower layer may include an aluminum alloy including the first element and aluminum (Al), and the content of the first element in the fourth lower layer may be about 0.1 at% or less relative to the aluminum alloy.

[0024] The third upper layer may have a thickness greater than a thickness of the fourth upper layer.

[0025] The third upper layer may have a thickness in the range of about 40 nm to about 140 nm, and the fourth upper layer may have a thickness in the range of about 40 nm to about 60 nm.

[0026] At least one of the third lower layer and the fourth lower layer may have a thickness in the range of about 130 nm to about 1000 nm.

[0027] The third upper layer and the fourth upper layer may include tantalum (Ta).

[0028] The first element may be selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt), dammium (Ds), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu).

[0029] The aluminum alloy may include a second element that may be different from the first element, and a total amount of the first element and the second element may be about 0.1 at % or less with respect to the aluminum alloy.

[0030] The first element may be selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt) and dammium (Ds), and the second element may be selected from the group consisting of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu).

[0031] Other aspects, features and advantages of the present disclosure will become better understood from the accompanying drawings, claims and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 is a plan view of a display device according to an embodiment;

[0034] Figure 2 is an equivalent circuit diagram of a pixel in a display device according to an embodiment;

[0035] Figure 3 is a schematic cross-sectional view showing a display device according to an embodiment;

[0036] Figure 4 is a graph showing resistivity change with respect to alloy ratio according to an embodiment;

[0037] Figure 5 is a graph showing a change in resistance with respect to the thickness of an aluminum alloy layer according to an embodiment;

[0038] Figure 6 is a diagram showing a change in resistance according to an embodiment;

[0039] Figure 7 is a schematic cross-sectional view showing a display device according to an embodiment;

[0040] Figure 8 is a schematic cross-sectional view showing a display device according to an embodiment;

[0041] Fig. 9 is a schematic cross-sectional view showing a display device according to an embodiment; and

[0042] FIG. 10A to FIG. 10E Schematic cross-sectional views for explaining processes in a method of manufacturing a display device in a process order according to an embodiment. DETAILED DESCRIPTION

[0043] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. In this regard, embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, embodiments are described below with reference to the drawings only to explain aspects of the description.

[0044] Some parts not related to the description may not be provided in order to describe the embodiments of the present disclosure, and the same drawing numbers refer to the same elements throughout the specification.

[0045] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0046] Example embodiments will be described in more detail below with reference to the accompanying drawings. Those components that are the same or correspond are given the same reference numerals regardless of the figure numbers, and redundant explanations may be omitted.

[0047] Although terms such as "first", "second", etc. may be used to describe various components, such components are not limited to the above terms. The above terms are only used to distinguish one component from another.

[0048] An expression used in the singular includes the expression in the plural unless it has an obviously different meaning in a given context.

[0049] In the specification, it is to be understood that the terms "comprises", "having" and "including" and their variations are intended to indicate the presence of the features, quantities, steps, actions, components, parts or a combination thereof disclosed in the specification, and are not intended to exclude the possibility that one or more other features, quantities, steps, actions, components, parts or a combination thereof may exist or may be added.

[0050] It will be understood that when a layer, region or component is referred to as being “formed on” another layer, region or component, it can be directly or indirectly formed on the other layer, region or component. For example, intervening layers, regions or components may be present.

[0051] For the sake of clarity and convenience of explanation, the size and thickness of the components in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings are arbitrarily explained for the sake of convenience of explanation, the following embodiments are not limited thereto.

[0052] Furthermore, in the specification, the phrase “in a plan view” means when an object portion is viewed from above, and the phrase “in a schematic cross-sectional view” means when a schematic cross section taken by vertically cutting the object portion is viewed from the side.

[0053] In addition, the term "overlap" or "overlapped" means that the first object can be above or below the second object or on one side of the second object, and vice versa. In addition, the term "overlap" may include stacking, stacking, facing or facing, extending on, covering or partially covering, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art. The terms "facing" and "facing" mean that the first element can be directly or indirectly opposite to the second element. In the case where a third element is between the first element and the second element, the first element and the second element can be understood to be indirectly opposite to each other, although still facing each other. When an element is described as "non-overlapping" or "not overlapping" with another element, this may include these elements being spaced apart from each other, offset from each other, or separated from each other, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art.

[0054] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0055] When the embodiment can be implemented differently, the specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously or in the reverse order of the described order.

[0056] In the specification, the phrase "A and / or B" means A, B, or A and B. In addition, the phrase "at least one of A and B" means A, B, or A and B.

[0057] In the following embodiments, when layers, regions, elements, etc. are referred to as being "connected", it will be understood that they may be directly connected or there may be intermediate portions between the layers, regions, or elements. For example, when layers, regions, elements, etc. are referred to as being "electrically connected", they may be directly electrically connected or the layers, regions, or elements may be indirectly electrically connected and there may be intermediate portions.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the embodiments belong. In addition, it will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an ideal or overly formal sense, unless explicitly defined as such herein.

[0059] Hereinafter, one or more embodiments will be described in detail with reference to the accompanying drawings.

[0060] Figure 1 is a plan view of a display device according to an embodiment.

[0061] refer to Figure 1 The display device 1 may include a substrate 110, a display area DA (in which an image may be implemented or displayed), and a non-display area NDA (in which an image may not be implemented or displayed). The display device 1 may provide an image by using light emitted from the display area DA.

[0062] exist Figure 1 In the embodiment, the display device 1 may include a display area DA having a square shape, however, the present disclosure is not limited thereto. For example, within the spirit and scope of the present disclosure, the display area DA may have a circular shape, an elliptical shape, or a polygonal shape, such as a triangle or a pentagon. Figure 1 The display device 1 may include a flat panel display device, however, for example, within the spirit and scope of the present disclosure, the display device 1 may be implemented as various types, such as a flexible display device, a foldable display device, a rollable display device.

[0063] According to an embodiment, although the display device 1 may be described as an organic light-emitting display device, the present disclosure is not limited thereto. In an embodiment, the display device 1 may include an inorganic light-emitting display (or an inorganic EL display device), or a quantum dot light-emitting display device. For example, the light-emitting layer of the display element included in the display device 1 may include an organic material; an inorganic material; a quantum dot; an organic material and a quantum dot; an inorganic material and a quantum dot; or an organic material, an inorganic material, and a quantum dot.

[0064] The pixel P may be in the display area DA. In the specification, each pixel P may represent a sub-pixel that emits light of a different color from other sub-pixels, and each pixel P may be, for example, one of a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. For example, within the spirit and scope of the present disclosure, for example, each pixel P may include a device such as a thin film transistor (TFT) and / or a capacitor.

[0065] The non-display area NDA may not provide an image, and may include a scan driver, a data driver (eg, which may provide electrical signals to the pixels P of the display area DA), and a power line (which may provide power such as a driving voltage and a common voltage).

[0066] Figure 2 is an equivalent circuit diagram of a pixel in a display device according to an embodiment.

[0067] refer to Figure 2 , each pixel P may include a pixel circuit PC electrically connected to the scan line SL and the data line DL, and an organic light emitting diode OLED electrically connected to the pixel circuit PC.

[0068] The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. The second thin film transistor T2, for example, a switching thin film transistor, may be electrically connected to the scan line SL and the data line DL, and may transmit a data signal Dm input through the data line DL to the first thin film transistor T1, for example, a driving thin film transistor, according to a scan signal Sn input through the scan line SL.

[0069] The storage capacitor Cst may be electrically connected to the second thin film transistor T2 and the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage transmitted from the second thin film transistor T2 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0070] The first thin film transistor T1 may be electrically connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED in response to a voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light with brightness according to the driving current.

[0071] Figure 2 An example is shown in which the pixel circuit PC includes two thin film transistors and one storage capacitor, but one or more embodiments are not limited thereto. For example, the pixel circuit PC may include three or more thin film transistors and / or two or more storage capacitors.

[0072] Figure 3 is a schematic cross-sectional view showing a display device according to an embodiment.

[0073] refer to Figure 3 , the display device according to the embodiment may include a first thin film transistor T1, a storage capacitor Cst, and an organic light emitting diode OLED (which is a display element) on a substrate 110. The display device may include a second thin film transistor T2.

[0074] In an embodiment, the storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2. The lower electrode CE1 may include a first lower layer GL1 and a first upper layer GH1 that may be stacked, and the upper electrode CE2 may include a second lower layer GL2 and a second upper layer GH2 that may be stacked. As an example, a thickness t2 of the second upper layer GH2 may be greater than a thickness t1 of the first upper layer GH1.

[0075] According to an embodiment, the first thin film transistor T1 may include a first semiconductor layer A1 and a first gate electrode G1. The first gate electrode G1 may include a third lower layer GL3 and a third upper layer GH3 that may be stacked. In an example, the third lower layer GL3 may include an aluminum alloy including aluminum (Al) and a first element, wherein the amount of the first element relative to the aluminum alloy may be about 0.1 at% (atomic %) or less.

[0076] In an embodiment, the second thin film transistor T2 may include a second semiconductor layer A2 and a second gate electrode G2. The second gate electrode G2 may include a fourth lower layer GL4 and a fourth upper layer GH4 that may be stacked. In an example, the fourth lower layer GL4 may include an aluminum alloy including aluminum (Al) and a first element, wherein the amount of the first element relative to the aluminum alloy may be about 0.1 at % or less.

[0077] In the following, reference will be made to Figure 3 Elements included in the display device are described in detail according to a stacking order.

[0078] Within the spirit and scope of the present disclosure, the substrate 110 may include a glass material, a ceramic material, a metal material, or a flexible or bendable material, etc. When the substrate 110 is flexible or bendable, the substrate 110 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0079] The substrate 110 may have a single layer or multi-layer structure of the above material(s), and the multi-layer structure may include an inorganic layer. In an implementation, the substrate 110 may have a structure including organic material / inorganic material / organic material.

[0080] A barrier layer (not shown) may be provided, placed or disposed between the substrate 110 and the buffer layer 111. The barrier layer may prevent or reduce impurities from penetrating from the substrate 110, for example, into the first semiconductor layer A1 or the second semiconductor layer A2. The barrier layer may include an inorganic material (such as an oxide material or a nitride material), an organic material, or an inorganic-organic composite material, and may have a single-layer or multi-layer structure including an inorganic material and an organic material.

[0081] The first semiconductor layer A1 and the second semiconductor layer A2 may be on the buffer layer 111. The first semiconductor layer A1 and the second semiconductor layer A2 may include amorphous silicon or polycrystalline silicon. In an embodiment, the first semiconductor layer A1 and the second semiconductor layer A2 may each include an oxide of at least one selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0082] The first semiconductor layer A1 and the second semiconductor layer A2 may each include a channel region and a drain region and a source region that may be at opposite sides of the channel region. Each of the first semiconductor layer A1 and the second semiconductor layer A2 may have a single layer or multi-layer structure.

[0083] The first gate insulating layer 113 and the second gate insulating layer 114 may be stacked on the substrate 110 to cover the first semiconductor layer A1 and the second semiconductor layer A2 or overlap the first semiconductor layer A1 and the second semiconductor layer A2. The first gate insulating layer 113 and the second gate insulating layer 114 may each include an insulating material, such as silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO).

[0084] The first gate electrode G1 may be on the second gate insulating layer 114 to at least partially overlap the first semiconductor layer A1. For example, the first gate insulating layer 113 and the second gate insulating layer 114 may be between the first semiconductor layer A1 and the first gate electrode G1. For example, the second gate electrode G2 may be on the first gate insulating layer 113 to at least partially overlap the second semiconductor layer A2. For example, the first gate insulating layer 113 may be between the second semiconductor layer A2 and the second gate electrode G2.

[0085] exist Figure 3 In the embodiment, the first gate electrode G1 may be on the second gate insulating layer 114, however, in an embodiment, the first gate electrode G1 may be on the upper surface of the first gate insulating layer 113. For example, the second gate electrode G2 may be on the upper surface of the second gate insulating layer 114. The first gate electrode G1 and the second gate electrode G2 may be on the same layer (coplanar) or on different layers (non-coplanar) as each other.

[0086] In an embodiment, in the first gate electrode G1, the third lower layer GL3 and the third upper layer GH3 may be stacked, wherein the third lower layer GL3 and the third upper layer GH3 may include materials different from each other. As an example, in the second gate electrode G2, the fourth lower layer GL4 and the fourth upper layer GH4 may be stacked, wherein the fourth lower layer GL4 and the fourth upper layer GH4 may include materials different from each other.

[0087] Within the spirit and scope of the present disclosure, the third upper layer GH3 and the fourth upper layer GH4 may include the same material, for example, titanium nitride (TiN), tantalum (Ta). The third lower layer GL3 and the fourth lower layer GL4 may include aluminum (Al) or an aluminum alloy.

[0088] The lower electrode CE1 of the storage capacitor Cst may be on the first gate insulating layer 113, wherein the first upper layer GH1 of the lower electrode CE1 may include the same material as the fourth upper layer GH4 of the second gate electrode G2, and the first lower layer GL1 of the lower electrode CE1 may include the same material as the fourth lower layer GL4 of the second gate electrode G2. For example, the lower electrode CE1 may include a first lower layer GL1 and a first upper layer GH1 stacked on each other. The upper electrode CE2 of the storage capacitor Cst may overlap with the lower electrode CE1 with the second gate insulating layer 114 therebetween. The upper electrode CE2 may include a second lower layer GL2 and a second upper layer GH2 stacked on each other and generate capacitance. In this case, the second gate insulating layer 114 may serve as a dielectric layer of the storage capacitor Cst.

[0089] The interlayer insulating layer 115 may be on the second gate insulating layer 114 to cover or overlap the first gate electrode G1 and the upper electrode CE2 of the storage capacitor Cst. The interlayer insulating layer 115 may include an insulating material such as silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO).

[0090] The first source electrode S1 and the second source electrode S2, the first drain electrode D1 and the second drain electrode D2, and the data line DL (see Figure 2 ) may be on the interlayer insulating layer 115.

[0091] The first source electrode S1, the second source electrode S2, the first drain electrode D1, the second drain electrode D2, and the data line DL may each include, for example, a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and may have a single-layer or multi-layer structure including the above materials. As an example, the first source electrode S1, the second source electrode S2, the first drain electrode D1, the second drain electrode D2, and the data line DL may each have a multi-layer structure including Ti / Al / Ti. The first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2 may be electrically connected to the source region or the drain region of the first semiconductor layer A1 and the second semiconductor layer A2 via the contact hole.

[0092] The first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2 may be covered by an inorganic protective layer (not shown). The inorganic protective layer may have a material including silicon nitride (SiN x ) and silicon oxide (SiO x An inorganic protective layer may be introduced to cover and protect the wiring on the interlayer insulating layer 115.

[0093] A planarization layer 118 may be provided to cover or overlap the first source electrode S1 , the second source electrode S2 , the first drain electrode D1 , and the second drain electrode D2 , and an organic light emitting diode OLED may be on the planarization layer 118 .

[0094] The planarization layer 118 may include a single layer or a multilayer structure including an organic material and may provide a flat upper surface. The planarization layer 118 may include a general polymer (benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS)), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoride polymer, a p-xylene polymer, a vinyl alcohol polymer, and / or a blend thereof.

[0095] The organic light emitting diode OLED may be on the planarization layer 118. The organic light emitting diode OLED may include: a pixel electrode 210, an intermediate layer 220 including an organic light emitting layer, and an opposite electrode 230.

[0096] The pixel electrode 210 may include a (semi) transmissive electrode or a reflective electrode. In an embodiment, the pixel electrode 210 may include a reflective layer (which includes but is not limited to Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and / or compounds thereof), and / or a transparent or semi-transparent electrode layer on the reflective layer. The transparent or semi-transparent electrode layer may include a material selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), at least one of the group consisting of indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In an implementation, the pixel electrode 210 may include ITO / Ag / ITO.

[0097] In the display area DA (see Figure 1 ), the pixel defining layer 119 may be on the planarization layer 118. The pixel defining layer 119 may increase the distance between the edge of the pixel electrode 210 and the opposing electrode 230 on the pixel electrode 210 to prevent arcing at one or more edges of the pixel electrode 210.

[0098] For example, within the spirit and scope of the present disclosure, the pixel defining layer 119 may include one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, BCB, and phenolic resin, and may be manufactured by a spin coating method.

[0099] The intermediate layer 220 of the organic light emitting diode OLED may include an organic light emitting layer. The organic light emitting layer may include an organic material including a fluorescent material or a phosphorescent material emitting red, green, blue or white light. The organic light emitting layer may include a low molecular weight organic material or a polymer organic material, and a functional layer (such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL) and an electron injection layer (EIL)) may be arranged, placed or set below the organic light emitting layer and on the organic light emitting layer. The intermediate layer 220 may correspond to each of the pixel electrodes 210. However, one or more embodiments are not limited thereto. The intermediate layer 220 may be modified in various ways, for example, the intermediate layer 220 may be arranged, placed or set throughout the pixel electrodes 210.

[0100] The counter electrode 230 may include a transmissive electrode or a reflective electrode. In an embodiment, the counter electrode 230 may be a transparent or semi-transparent electrode and may be provided as a metal film including Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg and / or a compound thereof having a small work function. A transparent conductive oxide (TCO) layer (such as ITO, IZO, ZnO or In 2 O 3 ) may be provided on the metal film. The counter electrode 230 may extend over the display area DA (see Figure 1 ) is arranged, placed or disposed, and is arranged, placed or disposed on the intermediate layer 220 and the pixel defining layer 119. The opposite electrode 230 may be integrally provided with respect to the organic light emitting diode OLED to correspond to the pixel electrode 210.

[0101] In an embodiment, the first gate electrode G1, the second gate electrode G2, the lower electrode CE1 and the upper electrode CE2 of the storage capacitor Cst may each have a structure in which a lower layer and an upper layer may be stacked. This will refer to Figure 3 The structure and reference shown in Figures 4 to 6 The description given is described in detail.

[0102] Figure 4 : is a graph showing a change in resistivity due to annealing at a temperature of about 450° C. for about 30 minutes while changing the ratio of the first element and the second element added to the aluminum alloy.

[0103] Figure 5 Graph showing variation in surface resistance (Rs) of the lower electrode CE1 of the storage capacitor Cst according to the thickness of the first lower layer GL1, wherein the storage capacitor Cst may include a first upper layer GH1 including tantalum (Ta) and a first lower layer GL1 including aluminum (Al) or an aluminum alloy.

[0104] Figure 6 Graph showing a change in surface resistance of the first upper layer GH1 in the lower electrode CE1 according to a subsequent buffered oxide etching (BOE) process in an embodiment in which the first upper layer GH1 includes tantalum (Ta) and the first lower layer GL1 includes aluminum (Al) or an aluminum alloy.

[0105] In the first gate electrode G1, the third lower layer GL3 and the third upper layer GH3 may be stacked, wherein the third lower layer GL3 and the third upper layer GH3 may include materials different from each other. For example, in the second gate electrode G2, the fourth lower layer GL4 and the fourth upper layer GH4 may be stacked, wherein the fourth lower layer GL4 and the fourth upper layer GH4 may include materials different from each other. For example, within the spirit and scope of the present disclosure, the third upper layer GH3 and the fourth upper layer GH4 may include the same material, for example, titanium nitride (TiN), tantalum (Ta). The third lower layer GL3 and the fourth lower layer GL4 may include aluminum (Al) or an aluminum alloy. The thickness t3 of the third upper layer GH3 may be greater than the thickness t4 of the fourth upper layer GH4.

[0106] Similar to the first gate electrode G1 and the second gate electrode G2, the lower electrode CE1 of the storage capacitor Cst may include a first lower layer GL1 and a first upper layer GH1 stacked on each other, wherein the first lower layer GL1 and the first upper layer GH1 may include materials different from each other, and the upper electrode CE2 may include a second lower layer GL2 and a second upper layer GH2 stacked on each other, wherein the second lower layer GL2 and the second upper layer GH2 may include materials different from each other. For example, within the spirit and scope of the present disclosure, the first upper layer GH1 and the second upper layer GH2 may include the same material as each other, for example, titanium nitride (TiN), tantalum (Ta). The first lower layer GL1 and the second lower layer GL2 may include aluminum (Al) or an aluminum alloy. The thickness t1 of the first upper layer GH1 may be less than the thickness t2 of the second upper layer GH2.

[0107] According to an embodiment, the second lower layer GL2 of the upper electrode CE2 in the storage capacitor Cst and the first lower layer GL1 of the lower electrode CE1 in the storage capacitor Cst may each include aluminum (Al) or an aluminum alloy.

[0108] The upper electrode CE2 and the lower electrode CE1 of the storage capacitor Cst may include molybdenum (Mo) which may be less damaged due to post-processing. However, in this case, molybdenum (Mo) has a large resistance because the resistivity value is about 570 μΩcm (when the temperature is about 20° C.), and thus the display quality may be degraded when used for a high-resolution display. For example, when the thickness of the lower electrode CE1 is increased to reduce the resistance, due to the physical properties of molybdenum (Mo), the tensile stress increases as the thickness increases, and defects may be caused.

[0109] However, when the second lower layer GL2 of the upper electrode CE2 and the first lower layer GL1 of the lower electrode CE1 include aluminum (Al) as in the embodiment, the resistivity value of aluminum (Al) may be about 3.25 μΩcm, and thus, a low resistance of the lower electrode CE1 may be achieved (see FIG. Figure 4 ). For example, the upper electrode CE2 and the lower electrode CE1 of the storage capacitor Cst including aluminum (Al) may be used in a high-resolution display.

[0110] The aluminum alloy included in the first lower layer GL1 may include a first element. In an embodiment, the aluminum alloy in the first lower layer GL1 may include a second element that may be different from the first element. The first element and the second element may be selected from nickel (Ni), palladium (Pd), platinum (Pt), dammium (Ds), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu) (Group 10 elements of the periodic table and lanthanum). The additive materials (such as the first element and the second element) that may be included in the entire aluminum alloy are about 0.1at% (atomic %) or less.

[0111] refer to Figure 4 , resistivity values ​​after heat treatment can be obtained in each of pure aluminum (Al), an aluminum alloy containing about 2 at % of the first element and / or the second element, and an aluminum alloy containing about 0.1 at % of the first element and / or the second element.

[0112] The resistivity value of pure aluminum (Al) not including the first element and / or the second element may be about 3.25 μΩcm, the resistivity value of an aluminum alloy containing about 2 at% of the first element and / or the second element may be about 3.90 μΩcm, and the resistivity value of an aluminum alloy containing about 0.1 at% of the first element and / or the second element may be about 3.08 μΩcm. For example, when the first element and / or the second element included in the aluminum alloy is about 0.1 at% or less, the resistivity value of the aluminum alloy may be less than the resistivity value of pure aluminum (Al).

[0113] In an embodiment, when the first lower layer GL1 includes an aluminum alloy containing approximately 0.1 at % or less of the first element and / or the second element, small protrusions (hillocks) may not be generated in a subsequent annealing process, and the resistivity value according to heat treatment at a high temperature may be approximately 3.08 μΩcm, and thus low resistance may be achieved.

[0114] In an embodiment, the first element may be nickel (Ni) and the second element may be lanthanum (La), and Al, nickel (Ni) ranging from about 0.01 at % to about 0.05 at %, and lanthanum (La) ranging from about 0.02 at % to about 0.05 at % may form an aluminum alloy.

[0115] In an embodiment, the first lower layer GL1 of the storage capacitor Cst may have a thickness in the range of about 130 nm to about 1000 nm.

[0116] refer to Figure 5When the thickness of the first lower layer GL1 is about 130 nm or more, the surface resistance after annealing is reduced due to the heat treatment at a temperature of about 450° C. for about 1 hour. When the thickness of the first lower layer GL1 is about 1000 nm or more, a processing defect may occur due to a step formed on the first gate insulating layer 113 and the second gate insulating layer 114. For example, when the thickness of the first gate insulating layer 113 and the thickness of the second gate insulating layer 114 are increased to reduce defects caused by the step, the capacitance of the storage capacitor Cst may be reduced.

[0117] The first lower layer GL1 of the lower electrode CE1 in the storage capacitor Cst is as described above, but the third lower layer GL3 of the first gate electrode G1, the fourth lower layer GL4 of the second gate electrode G2, and the second lower layer GL2 of the upper electrode CE2 of the storage capacitor Cst may have the same structure as the first lower layer GL1.

[0118] In an embodiment, the first upper layer GH1 of the lower electrode CE1 in the storage capacitor Cst may include tantalum (Ta). The first upper layer GH1 may include tantalum (Ta) to prevent the lower electrode CE1 from being corroded by hydrogen fluoride (HF) in a subsequent process (e.g., a cleaning process such as a buffered oxide etching (BOE) process). For example, generation of a small protrusion of aluminum (Al) included in the first lower layer GL1 during an annealing process at a high temperature (e.g., in a range of about 400° C. to about 580° C.) may be prevented. Diffusion of a metal component at an interface between the first upper layer GH1 and the first lower layer GL1 may be prevented.

[0119] refer to Figure 6 , the surface resistance of the first upper layer GH1 can be constantly maintained at about 20Ω / □, and therefore, the thickness of the first upper layer GH1 can also be constantly maintained. When the third upper layer GH3 and the fourth upper layer GH4 include titanium (Ti), diffusion of the metal component can occur at the interface between the upper layer and the lower layer during the subsequent annealing process. In this case, an aluminum-titanium alloy can be generated at the interface and can cause an increase in the resistance of the lower electrode CE1 of the storage capacitor Cst. Titanium (Ti) can be easily corroded by hydrogen fluoride (HF) used as a cleaning solution in a cleaning process such as buffered oxide etching (BOE), and therefore, when the surface of the first lower layer GL1 is exposed and contacts with hydrogen fluoride (HF), the aluminum component in the first lower layer GL1 can react with the hydrogen fluoride (HF) and the surface of the first lower layer GL1 can be damaged.

[0120] However, when the first upper layer GH1 includes tantalum (Ta), diffusion of the metal component at the interface between the first upper layer GH1 and the first lower layer GL1 may not be sufficiently achieved. For example, tantalum (Ta) reacts less with hydrogen fluoride (HF) than titanium (Ti), and thus, the surface of the first lower layer GL1 may be protected even when a buffered oxide etch (BOE) cleaning process is performed.

[0121] In a comparative example, the lower electrode CE1 of the storage capacitor Cst may include molybdenum (Mo), and in this case, the lower electrode CE1 may not be damaged during a cleaning process such as a buffered oxide etching (BOE) process, however, resistance may be greatly increased and the lower electrode CE1 may not be used with high resolution. As the thickness of the first lower layer GL1 increases, tensile stress increases due to physical properties of molybdenum (Mo) and may cause defects.

[0122] Unlike the above example, according to an embodiment, the lower electrode CE1 may include not only a single layer of molybdenum (Mo), but may include a first lower layer GL1 and a first upper layer GH1. For example, the first upper layer GH1 may include tantalum (Ta), and thus, low resistance may be achieved without being damaged during a cleaning process such as a buffered oxide etching (BOE) process.

[0123] Although the first upper layer GH1 of the lower electrode CE1 of the storage capacitor Cst is as described above, the third upper layer GH3 of the first gate electrode G1, the fourth upper layer GH4 of the second gate electrode G2, and the second upper layer GH2 of the upper electrode CE2 of the storage capacitor Cst may have the same or similar structure as the first upper layer GH1.

[0124] refer to Figure 3 , the thickness t2 of the second upper layer GH2 of the upper electrode CE2 may be greater than the thickness t1 of the first upper layer GH1 of the lower electrode CE1.

[0125] In this case, damage to the first lower layer GL1 and the second lower layer GL2 during the process of forming the contact holes of, for example, the first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2 can be prevented. The thickness t2 of the second upper layer GH2 may be greater than the thickness t1 of the first upper layer GH1, and thus, the second lower layer GL2 of the upper electrode CE2 of the storage capacitor Cst, which may be frequently exposed during the process, may be protected like the first lower layer GL1 of the lower electrode CE1.

[0126] In an embodiment, the thickness t2 of the second upper layer GH2 may be in the range of about 40 nm to about 140 nm, and the thickness t1 of the first upper layer GH1 may be in the range of about 40 nm to about 60 nm.

[0127] When the thickness t1 of the first upper layer GH1 and the thickness t2 of the second upper layer GH2 are equal to or less than about 40 nm, diffusion of aluminum (Al) may occur at the interface between the first lower layer GL1 and the first upper layer GH1 and at the interface between the second lower layer GL2 and the second upper layer GH2 after the annealing process, and the boundary may be blurred.

[0128] Considering the consumption amount during the dry etching process, the thickness of the second upper layer GH2 and the first upper layer GH1 may be set to be equal to or less than about 140 nm and to be set to be equal to or less than about 60 nm, respectively, wherein unnecessary portions may be selectively removed in order to manufacture a circuit pattern. When the thickness of the second upper layer GH2 and the first upper layer GH1 are equal to or greater than about 140 nm and equal to or greater than about 60 nm, respectively, unnecessary portions may be generated outside the original functions of the second upper layer GH2 and the first upper layer GH1 for protecting the second lower layer GL2 and the first lower layer GL1, and thus, resistance may be greatly increased.

[0129] Figure 4 is a graph showing a change in resistivity according to an embodiment.

[0130] In detail, Figure 4 1 is a graph showing a change in resistivity due to annealing at a temperature of about 450° C. for about 30 minutes while changing the ratio of a first element and a second element added to an aluminum alloy.

[0131] The first element and the second element may be selected from nickel (Ni), palladium (Pd), platinum (Pt), dammium (Ds), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu) (Group 10 elements and lanthanum elements in the periodic table).

[0132] refer to Figure 4 , the resistivity value after heat treatment can be obtained in each of the cases of pure aluminum (Al), an aluminum alloy containing about 2 at% of the first element and / or the second element therein, and an aluminum alloy containing about 0.1 at% of the first element and / or the second element therein. The resistivity value is a unique value of the material and can be obtained by Figure 5 and Figure 6 The surface resistance shown in is obtained by multiplying the corresponding thickness.

[0133] When the additive material (such as the first element and the second element) may be contained at about 0.1 at % in the entire aluminum alloy, the resistivity value may be the lowest, for example, about 3.08 μΩcm.

[0134] In the comparative example, when an aluminum alloy in which an additive material (such as a first element and a second element) may be contained is about 0.1 at% relative to the entire aluminum alloy, that is, pure aluminum (Al) is used, a small protrusion of aluminum (Al) may occur in a subsequent annealing process. When the additive material (such as a first element and a second element) included in the entire aluminum alloy is about 2 at%, the resistivity value according to the heat treatment may increase.

[0135] Therefore, in the display device according to the embodiment, the added material (such as the first element and the second element) that may be included in the first lower layer GL1 is approximately 0.1at% relative to the entire aluminum alloy, and in this case, the generation of small protrusions in the subsequent annealing process can be prevented, and the resistivity value according to the heat treatment can be greatly reduced.

[0136] Figure 5 and Figure 6 4 are graphs each showing a change in resistance according to an embodiment.

[0137] refer to Figure 5 , the first upper layer GH1 including tantalum (Ta) may have a thickness of about 100 nm, and the thickness of the first lower layer GL1 including aluminum (Al) or an aluminum alloy is about 110 nm, about 130 nm, about 150 nm, and about 170 nm, that is, as the thickness of the first lower layer GL1 increases, the surface resistance may be gradually reduced to about 0.47Ω / □, about 0.39Ω / □, about 0.33Ω / □, and about 0.29Ω / □. The first upper layer GH1 including tantalum (Ta) has a resistance of about 20Ω / □, and the first lower layer GL1 including aluminum (Al) or an aluminum alloy has a resistance of about 0.5Ω / □, and therefore, the surface resistance of the lower electrode CE1 (in which the first upper layer GH1 and the first lower layer GL1 may be electrically connected in parallel) may be set according to the surface resistance of the first lower layer GL1 (which may be much smaller than the surface resistance of the first upper layer GH1), and the surface resistance of the lower electrode CE1 may be obtained as follows. Figure 5 The results shown in .

[0138] In a comparative example, when the first upper layer GH1 includes tantalum (Ta) as in an embodiment and the first lower layer GL1 does not include aluminum (Al) or an aluminum alloy, both the first upper layer GH1 and the first lower layer GL1 may have a single-layer structure including molybdenum (Mo). In this case, as the thickness of the single layer increases, the tensile stress also increases and causes defects. The first upper layer GH1 may include titanium (Ti) instead of tantalum (Ta), and in this case, diffusion of the metal component at the interface may occur during a subsequent annealing process.

[0139] Therefore, in the display device of the embodiment, the first upper layer GH1 may include tantalum (Ta) and the first lower layer GL1 may include aluminum (Al) or an aluminum alloy, and then, generation of defects due to thickness increase may be prevented, and surface resistance after heat treatment may be greatly reduced. Diffusion of metal components at the interface during a subsequent annealing process may be prevented.

[0140] In detail, Figure 6 Graph showing a change in surface resistance of the first upper layer GH1 in the lower electrode CE1 according to a subsequent buffered oxide etching (BOE) process in an embodiment in which the first upper layer GH1 may include tantalum (Ta) and the first lower layer GL1 may include aluminum (Al) or an aluminum alloy.

[0141] Figure 6 It is shown that the surface resistance of the first upper layer GH1 changes in the case where the subsequent buffered oxide etching (BOE) process is not performed (reference), performed once, twice, and three times, wherein the first upper layer GH1 has a thickness of about 100 nm. When the thickness of the first upper layer GH1 changes, the surface resistance also changes. In detail, the thickness and the resistance are inversely proportional to each other, that is, the resistance increases when the thickness decreases. However, in Figure 6 In the embodiment of the present invention, the surface resistance of the first upper layer GH1 can be constantly maintained at about 20Ω / □, and therefore, the thickness of the first upper layer GH1 can also be constantly maintained. For example, tantalum (Ta) can be used to prevent corrosion damage caused by hydrogen fluoride (HF) in a subsequent buffered oxide etching (BOE) process.

[0142] In a comparative example, when the first upper layer GH1 includes tantalum (Ta) as in the embodiment and the first lower layer GL1 does not include aluminum (Al) or an aluminum alloy, the first upper layer GH1 may include titanium (Ti), and in this case, corrosion caused by hydrogen fluoride (HF) may occur in a subsequent buffered oxide etching (BOE) process.

[0143] Therefore, in the display device according to the embodiment, when the first upper layer GH1 includes tantalum (Ta) and the first lower layer GL1 includes aluminum (Al) or an aluminum alloy, corrosion caused by hydrogen fluoride (HF) can be prevented due to tantalum (Ta) in a subsequent buffered oxide etching (BOE) process, and the generation of small protrusions of aluminum (Al) included in the first lower layer GL1 and the diffusion of metal components at the interface can be prevented in a subsequent annealing process.

[0144] Figure 7 2 is a schematic cross-sectional view showing a display device according to an embodiment. Figure 7 In the drawings, the same reference numerals denote Figure 3 The same components as the components of the

[0145] refer to Figure 7 , in the display device of the embodiment, the storage capacitor Cst may overlap with the first thin film transistor T1.

[0146] The upper electrode CE2 of the storage capacitor Cst may overlap with the first thin film transistor T1. For example, the first gate electrode G1 of the first thin film transistor T1 may serve as the upper electrode CE2 of the storage capacitor Cst.

[0147] The lower electrode CE1 of the storage capacitor Cst may overlap the upper electrode CE2 with the second gate insulating layer 114 therebetween. In this case, the second gate insulating layer 114 may serve as a dielectric layer of the storage capacitor Cst.

[0148] The lower electrode CE1 of the storage capacitor Cst may include a first lower layer GL1 and a first upper layer GH1 stacked on each other, and the upper electrode CE2 of the storage capacitor Cst may include a second lower layer GL2 and a second upper layer GH2 stacked on each other. Figure 7 As shown in the enlarged view in FIG. 2 , the thickness t2 of the second upper layer GH2 may be greater than the thickness t1 of the first upper layer GH1 .

[0149] For example, the first upper layer GH1 and the second upper layer GH2 may include titanium nitride (TiN), tantalum (Ta), and the first lower layer GL1 and the second lower layer GL2 may include aluminum (Al) or an aluminum alloy. The aluminum alloy included in the first lower layer GL1 and the second lower layer GL2 may include a first element. In an embodiment, the aluminum alloy in the first lower layer GL1 and the second lower layer GL2 may include a second element that may be different from the first element. The first element and the second element may be selected from nickel (Ni), palladium (Pd), platinum (Pt), dammium (Ds), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu) (Group 10 elements and lanthanum elements in the periodic table). The added material (eg, the first element and the second element) may be included in the entire aluminum alloy at about 0.1 at % or less.

[0150] Figure 8 and Fig. 9 2 is a schematic cross-sectional view showing a display device according to an embodiment. Figure 8 and Fig. 9 In the drawings, the same reference numerals denote Figure 3 The same components as the components of the

[0151] In detail, Figure 8 To show that including Figure 3 Schematic cross-sectional view of a display device having a thin film encapsulation layer 300 on an organic light emitting diode OLED.

[0152] Since the organic light emitting diode OLED may be easily damaged by external moisture or oxygen, the organic light emitting diode OLED may be covered and protected by the thin film encapsulation layer 300. The thin film encapsulation layer 300 may cover the display area DA (eg, Figure 1 The thin film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. For example, the thin film encapsulation layer 300 may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330.

[0153] The first inorganic encapsulation layer 310 may cover or overlap the opposing electrode 230, and may include silicon oxide, silicon nitride and / or silicon trioxynitride. Although not shown in the drawings, other layers, such as a capping layer, may be provided between the first inorganic encapsulation layer 310 and the opposing electrode 230 if required within the spirit and scope of the present disclosure. The first inorganic encapsulation layer 310 may be formed along the structure below it, and therefore, the first inorganic encapsulation layer 310 may have an uneven upper surface. The organic encapsulation layer 320 may cover or overlap the first inorganic encapsulation layer 310, and unlike the first inorganic encapsulation layer 310, the organic encapsulation layer 320 may have a flat upper surface. In detail, the organic encapsulation layer 320 may flatten the upper surface of the portion corresponding to the display area DA. The organic encapsulation layer 320 may include one or more materials selected from the group consisting of polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. The second inorganic encapsulation layer 330 may cover the organic encapsulation layer 320 and may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0154] Even when cracks may occur in the thin film encapsulation layer 300, the cracks may be disconnected between the first inorganic encapsulation layer 310 and the organic encapsulation layer 320 or between the organic encapsulation layer 320 and the second inorganic encapsulation layer 330 due to the multi-layer structure in the thin film encapsulation layer 300. In this way, generation of a permeation path through which external moisture or oxygen may pass to the display area DA may be prevented or reduced.

[0155] In detail, Fig. 9 To show that including Figure 3 Schematic cross-sectional view of a display device of an organic light emitting diode OLED on an encapsulation substrate 400.

[0156] refer to Fig. 9 , the display device may include a packaging substrate 400 facing the substrate 110. In the non-display area NDA (eg Figure 1In the non-display area), by way of example, the substrate 110 and the encapsulation substrate 400 may be combined with each other by a sealing material (such as a frit).

[0157] The display device has been described, but the present disclosure is not limited thereto. For example, a method of manufacturing a display device may also be included in the scope of the present disclosure.

[0158] FIG. 10A to FIG. 10E Schematic cross-sectional views for explaining processes in a method of manufacturing a display device in a process order according to an embodiment.

[0159] refer to Fig. 10A , the buffer layer 111 and the initial semiconductor layer 120 may be sequentially arranged, placed or disposed on the substrate 110 .

[0160] For example, the buffer layer 111 may include silicon oxide (SiO x ) or silicon nitride (SiN x ), and can be manufactured by a deposition method (such as a chemical vapor deposition (CVD) method, a sputtering method).

[0161] The initial semiconductor layer 120 may include amorphous silicon or an oxide semiconductor. The initial semiconductor layer 120 may be deposited by a chemical vapor deposition method. When the initial semiconductor layer 120 includes amorphous silicon, after forming the initial semiconductor layer 120, the initial semiconductor layer 120 may be crystallized by various methods (such as a rapid thermal annealing (RTA) method, a solid phase crystallization (SPC) method, an excimer laser annealing (ELA) method, a metal induced crystallization (MIC) method, a metal induced lateral crystallization (MILC) method, a sequential lateral solidification (SLS) method), for example, to form a polycrystalline silicon layer.

[0162] refer to Fig. 10B , the initial semiconductor layer 120 may be patterned to obtain a first semiconductor layer A1 and a second semiconductor layer A2, and a first gate insulating layer 113 may be formed on the entire surface of the substrate 110 to cover or overlap the first semiconductor layer A1 and the second semiconductor layer A2, and then a second gate electrode G2 and a lower electrode CE1 of the storage capacitor Cst may be formed on the first gate insulating layer 113.

[0163] The first gate insulating layer 113 may include an inorganic insulating material, such as silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5), hafnium oxide (HfO 2 ) and zinc oxide (ZnO), and may be formed, for example, by a deposition method such as a chemical vapor deposition (CVD) method, a sputtering method, however, the present disclosure is not limited thereto.

[0164] The second gate electrode G2 and the lower electrode CE1 of the storage capacitor Cst may include the same material, and may include stackable fourth lower layer GL4 and fourth upper layer GH4 and stackable first lower layer GL1 and first upper layer GH1 , respectively.

[0165] The first metal layer 130a and the second metal layer 130b may be formed and patterned on the entire surface of the substrate 110 to form the second gate electrode G2 and the lower electrode CE1 of the storage capacitor Cst. The first metal layer 130a and the second metal layer 130b may be formed, for example, by a deposition method such as a chemical vapor deposition method, a plasma enhanced CVD (PECVD) method, a low pressure CVD (LPCVD) method, a physical vapor deposition (PVD) method, a sputtering method, an atomic layer deposition (ALD) method, however, the deposition method is not limited thereto.

[0166] refer to Fig. 10C , a second gate insulating layer 114 may be formed on the entire surface of the substrate 110 to cover or overlap the second gate electrode G2 and the lower electrode CE1 of the storage capacitor Cst, and then the first gate electrode G1 and the upper electrode CE2 of the storage capacitor Cst may be formed on the second gate insulating layer 114.

[0167] The second gate insulating layer 114 may include an inorganic insulating material, such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO), and may be formed, for example, by a deposition method such as a chemical vapor deposition (CVD) method, a sputtering method, however, the present disclosure is not limited thereto.

[0168] The first gate electrode G1 and the upper electrode CE2 of the storage capacitor Cst may include the same material, and may include a third lower layer GL3 and a third upper layer GH3 that may be stacked and a second lower layer GL2 and a second upper layer GH2 that may be stacked, respectively.

[0169] The third metal layer 140a and the fourth metal layer 140b may be formed and patterned on the entire surface of the substrate 110 to form the first gate electrode G1 and the upper electrode CE2 of the storage capacitor Cst. The third metal layer 140a and the fourth metal layer 140b may be generated, for example, by a deposition method such as a chemical vapor deposition method, a plasma enhanced CVD (PECVD) method, a low pressure CVD (LPCVD) method, a physical vapor deposition (PVD) method, a sputtering method, an atomic layer deposition (ALD) method, however, the deposition method is not limited thereto.

[0170] refer to Fig. 10D , an interlayer insulating layer 115 may be formed on the entire surface of the substrate 110 to cover or overlap the first gate electrode G1 and the upper electrode CE2 of the storage capacitor Cst, and a contact hole exposing the source region and / or the drain region of the first semiconductor layer A1 and the second semiconductor layer A2 may be formed. Thereafter, a metal layer embedded in the contact hole may be formed and patterned to form the source electrodes S1 and S2 and / or the drain electrodes D1 and D2.

[0171] The interlayer insulating layer 115 may include an inorganic insulating material, such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO), and may be formed, for example, by a deposition method such as a chemical vapor deposition method, a sputtering method, however, the present disclosure is not limited thereto.

[0172] The source electrodes S1 and S2 and the drain electrodes D1 and D2 may each include a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and may have a single layer or multilayer structure including the above materials. For example, the source electrodes S1 and S2 and the drain electrodes D1 and D2 may each have a multilayer structure including Ti / Al / Ti.

[0173] refer to Fig. 10E , a planarization layer 118 may be formed on the interlayer insulating layer 115 and an organic light emitting diode OLED may be formed on the planarization layer 118 .

[0174] The planarization layer 118 may include a single layer or a multilayer structure including an organic material or an inorganic material. The planarization layer 118 may include a general polymer (benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoride polymer, a p-xylene polymer, a vinyl alcohol polymer and / or a blend thereof. For example, within the spirit and scope of the present disclosure, the planarization layer 118 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO). After the planarization layer 118 is arranged or disposed, chemical and mechanical polishing may be performed to provide a flat upper surface.

[0175] According to the display device of the embodiment, the first upper layer GH1 may include tantalum (Ta) and the first lower layer GL1 may include aluminum (Al) or an aluminum alloy, and then, generation of defects due to thickness increase may be prevented and surface resistance after heat treatment may be greatly reduced. Corrosion caused by hydrogen fluoride (HF) in a subsequent buffered oxide etching (BOE) process may be prevented by tantalum (Ta), and generation of small protrusions of aluminum (Al) included in the first lower layer GL1 and diffusion of metal components at the interface may be prevented during a subsequent annealing process.

[0176] According to an embodiment, a display device having improved resistance of a gate electrode of a thin film transistor and / or an electrode of a storage capacitor may be implemented. However, the scope of the present disclosure is not limited to the above effects.

[0177] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. A display device, comprising: substrate; A thin film transistor on the substrate, the thin film transistor comprising: a first semiconductor layer; and a first gate electrode overlapping the first semiconductor layer, wherein a first gate insulating layer is disposed between the first semiconductor layer and the first gate electrode; A storage capacitor, the storage capacitor comprising: a lower electrode including a first lower layer and a first upper layer stacked on each other; and an upper electrode including a second lower layer and a second upper layer stacked on each other, wherein the upper electrode overlaps the lower electrode, and a second gate insulating layer is disposed between the upper electrode and the lower electrode; and a display element electrically connected to the thin film transistor, wherein the second upper layer has a thickness greater than a thickness of the first upper layer, and The first upper layer and the second upper layer include tantalum. 2 . The display device of claim 1 , wherein the lower electrode and the first gate electrode comprise the same material.

3. The display device according to claim 1, wherein: The thickness of the first upper layer is in the range of 40 nm to 60 nm, The thickness of the second upper layer is in the range of 40 nm to 140 nm, and At least one of the first lower layer and the second lower layer has a thickness in a range of 130 nm to 1000 nm. 4 . The display device according to claim 1 , wherein the first lower layer and the second lower layer each include an aluminum alloy including a first element and aluminum, and an amount of the first element is 0.1 at % or less with respect to the aluminum alloy.

5. The display device according to claim 4, wherein: The aluminum alloy includes a second element different from the first element, and The total amount of the first element and the second element is 0.1 at % or less with respect to the aluminum alloy.

6. A display device comprising: substrate; A first thin film transistor on the substrate, the first thin film transistor comprising: a first semiconductor layer; and a first gate electrode overlapping the first semiconductor layer, wherein a first gate insulating layer is disposed between the first semiconductor layer and the first gate electrode; A storage capacitor, the storage capacitor comprising: a lower electrode including a first lower layer and a first upper layer stacked on each other; and an upper electrode including a second lower layer and a second upper layer stacked on each other, wherein the upper electrode overlaps the lower electrode, and a second gate insulating layer is disposed between the upper electrode and the lower electrode; and a display element, the display element being electrically connected to the first thin film transistor, wherein: The first gate electrode includes a third lower layer and a third upper layer stacked on each other, the third lower layer comprises an aluminum alloy including the first element and aluminum, The amount of the first element in the third lower layer is 0.1 at % or less relative to the aluminum alloy, The second upper layer has a thickness greater than a thickness of the first upper layer, and The first upper layer and the second upper layer include tantalum.

7. The display device of claim 6, further comprising a second thin film transistor on the substrate, the second thin film transistor comprising: a second semiconductor layer; a second gate electrode overlapping the second semiconductor layer, The first gate insulating layer is disposed between the second semiconductor layer and the second gate electrode, wherein: The second gate electrode includes a fourth lower layer and a fourth upper layer stacked on each other, The fourth lower layer includes an aluminum alloy including the first element and aluminum, and An amount of the first element of the fourth lower layer is 0.1 at % or less with respect to the aluminum alloy. 8 . The display device of claim 7 , wherein the third upper layer has a thickness greater than a thickness of the fourth upper layer.

9. The display device of claim 7, wherein the third upper layer and the fourth upper layer include tantalum.

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