Clock data recovery system and apparatus, storage medium, electronic device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SANECHIPS TECH CO LTD
- Filing Date
- 2019-11-08
- Publication Date
- 2026-05-12
AI Technical Summary
Existing clock data recovery devices cannot efficiently recover clock data in high-speed serial communication systems, especially in high-order modulation scenarios where their performance is insufficient.
By combining a dual analog-to-digital converter module and a sampling clock module, the analog input signal is sampled to generate first and second output signals, and phase detection and filtering are performed to generate a sampling clock signal, thereby realizing clock data recovery.
It improves the efficiency of clock data recovery, reduces system complexity and cost, and supports high-performance clock data recovery in high-order modulation scenarios.
Smart Images
Figure CN112787662B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communications, and more specifically, to a clock data recovery system and apparatus, a storage medium, and an electronic device. Background Technology
[0002] The clock data recovery unit is used to estimate the correct sampling time for the receiver of a high-speed serial communication system (SERDES) and output the sampled data, as well as to mitigate inter-symbol interference (ISI) that may be introduced by estimation errors. Therefore, in a high-speed serial communication system, the clock data recovery unit is one of the functional modules that directly affects the performance of the system.
[0003] In related technologies, to improve data rates, high-speed serial communication systems are currently evolving in two directions: one is to adopt a faster symbol rate, i.e., shorten the symbol period; the other is to modulate more signal bits per transmission symbol, i.e., to use higher-order modulation. To meet the evolving needs of high-speed serial communication systems, the performance requirements for clock data recovery devices will also increase. Currently, the performance of clock data recovery devices in related technologies is still insufficient to meet the demands of increasingly sophisticated high-speed serial communication systems, or although clock data recovery devices are relatively reliable, they are not suitable for scenarios such as higher-order modulation.
[0004] Regarding the problem that clock data recovery devices cannot efficiently recover clock data in the aforementioned related technologies, no effective solution has yet been proposed in these technologies. Summary of the Invention
[0005] This invention provides a clock data recovery system and apparatus, storage medium, and electronic device to at least solve the problem that clock data recovery cannot be efficiently achieved by clock data recovery devices in related technologies.
[0006] According to one embodiment of the present invention, a clock data recovery system is provided, comprising:
[0007] The sampling clock module is configured to generate a first sampling clock signal and a second sampling clock signal;
[0008] The first analog-to-digital converter module is configured to acquire an analog input signal and the first sampling clock signal, and to sample the analog input signal according to the first sampling clock signal to obtain a first output signal.
[0009] The second analog-to-digital converter module is configured to acquire an analog input signal and the second sampling clock signal, and to sample the analog input signal according to the second sampling clock signal to obtain a second output signal.
[0010] The sampling clock module is further configured to acquire a sampling clock phase signal and generate a first sampling clock signal and a second sampling clock signal based on the sampling clock phase signal, wherein the sampling clock phase signal is a phase signal obtained after performing phase detection processing and filtering processing on the first output signal and the second output signal.
[0011] According to another embodiment of the present invention, a clock data recovery method is also provided, comprising:
[0012] The system acquires the first output signal from the first analog-to-digital converter module and the second output signal from the second analog-to-digital converter unit, and performs clock data recovery based on the first output signal and / or the second output signal.
[0013] Wherein, the first output signal is obtained by the first analog-to-digital converter module sampling the analog input signal according to the first sampling clock signal, and the second output signal is obtained by the second analog-to-digital converter module sampling the analog input signal according to the second sampling clock signal; both the first sampling clock signal and the second sampling clock signal are generated based on the sampling clock phase signal, which is the phase signal obtained after phase detection and filtering based on the first output signal and the second output signal.
[0014] According to another embodiment of the present invention, a clock data recovery apparatus is also provided, comprising:
[0015] The acquisition module is used to acquire the first output signal output by the first analog-to-digital conversion module and the second output signal output by the second analog-to-digital conversion unit, and to perform clock data recovery based on the first output signal and / or the second output signal;
[0016] Wherein, the first output signal is obtained by the first analog-to-digital converter module sampling the analog input signal according to the first sampling clock signal, and the second output signal is obtained by the second analog-to-digital converter module sampling the analog input signal according to the second sampling clock signal; both the first sampling clock signal and the second sampling clock signal are generated based on the sampling clock phase signal, which is the phase signal obtained after phase detection and filtering based on the first output signal and the second output signal.
[0017] According to another embodiment of the present invention, a storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.
[0018] According to another embodiment of the present invention, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.
[0019] Through this invention, the first analog-to-digital converter (ADC) module and the second ADC module included in the clock data recovery system can respectively output a first output signal and a second output signal based on the analog input signal and the corresponding first sampled clock signal and second sampled clock signal. Furthermore, the sampling clock module performs phase detection and filtering processing on the first and second output signals to obtain the phase signal, which is then used to regenerate the first and second sampled clock signals for signal output by the first and second ADC modules. Therefore, this invention can solve the problem of inefficient clock data recovery in related technologies, thereby improving the efficiency of clock data recovery. Attached Figure Description
[0020] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:
[0021] Figure 1 This is a schematic diagram (a) of the clock data recovery system provided according to an embodiment of the present invention;
[0022] Figure 2 This is a schematic diagram (II) of the clock data recovery system provided according to an embodiment of the present invention;
[0023] Figure 3 This is an internal schematic diagram of the phase detection module provided in an embodiment of the present invention;
[0024] Figure 4 This is a schematic diagram of the structure of a clock data recovery system provided according to a specific embodiment of the present invention;
[0025] Figure 5 This is a schematic diagram of the structure of a digital phase detection filter unit provided according to a specific embodiment of the present invention;
[0026] Figure 6 This is a signal schematic diagram of the first sampling clock and the second sampling clock provided according to a specific embodiment of the present invention;
[0027] Figure 7 This is a schematic diagram of the structure of the first analog-to-digital converter unit provided according to a specific embodiment of the present invention;
[0028] Figure 8This is a schematic diagram of the structure of the second analog-to-digital converter unit provided according to a specific embodiment of the present invention;
[0029] Figure 9 This is a schematic diagram of the structure of a digital equalizer provided according to a specific embodiment of the present invention;
[0030] Figure 10 This is a circuit diagram of a clock data recovery circuit provided according to a specific embodiment of the present invention;
[0031] Figure 11 This is a circuit diagram of a digital phase detection filter provided according to a specific embodiment of the present invention;
[0032] Figure 12 This is a signal schematic diagram of the first sampling clock and the second sampling clock provided according to a specific embodiment of the present invention;
[0033] Figure 13 This is a flowchart of a clock data recovery method provided according to an embodiment of the present invention;
[0034] Figure 14 This is a structural block diagram of a clock data recovery device provided according to an embodiment of the present invention. Detailed Implementation
[0035] The present invention will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in the present application can be combined with each other.
[0036] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0037] Example 1
[0038] This embodiment provides a clock data recovery system. Figure 1 This is a schematic diagram (I) of a clock data recovery system provided according to an embodiment of the present invention, as shown below. Figure 1 As shown, the clock data recovery system in this embodiment includes:
[0039] The sampling clock module 102 is configured to generate a first sampling clock signal and a second sampling clock signal;
[0040] The first analog-to-digital converter module 104 is configured to acquire an analog input signal and a first sampling clock signal, and to sample the analog input signal according to the first sampling clock signal to obtain a first output signal.
[0041] The second analog-to-digital converter module 106 is configured to acquire an analog input signal and a second sampling clock signal, and to sample the analog input signal according to the second sampling clock signal to obtain a second output signal.
[0042] The sampling clock module 102 is further configured to acquire a sampling clock phase signal and generate a first sampling clock signal and a second sampling clock signal based on the sampling clock phase signal, wherein the sampling clock phase signal is a phase signal obtained after phase detection and filtering based on the first output signal and the second output signal.
[0043] It should be further noted that the analog input signal corresponding to the first analog-to-digital converter (ADC) is the same as that of the first ADC. In this embodiment, the first output signal of the first ADC is the recovered data output by the system in this embodiment, and the first sampling clock signal output by the first ADC is the corresponding recovery clock.
[0044] It should be further noted that the various modules in the clock data recovery system of this embodiment can be implemented by hardware or by software modules with corresponding functions.
[0045] The clock data recovery system in the above embodiments, comprising a first analog-to-digital converter (ADC) and a second ADC, outputs a first output signal and a second output signal respectively based on the analog input signal and the corresponding first and second sampled clock signals. Furthermore, the sampling clock module performs phase detection and filtering on the first and second output signals to obtain the phase signal, which is then used to regenerate the first and second sampled clock signals for output by the ADC modules. Therefore, the clock data recovery system in this embodiment solves the problem of inefficient clock data recovery in related technologies, thereby improving clock data recovery efficiency.
[0046] Specifically, the clock data recovery system in this embodiment can support high-order modulation applications within high-speed serial communication systems that involve analog-to-digital converters (ADCs) in their circuit or system layout. Furthermore, this embodiment employs a second ADC module in conjunction with the first ADC module to achieve clock recovery, thereby significantly reducing the overall complexity of the clock data recovery system while performing clock recovery processing. Therefore, this embodiment achieves high-performance clock data recovery at a relatively low system cost.
[0047] In an optional embodiment, the system further includes:
[0048] The phase detection module 108 is configured to acquire a first output signal and a second output signal, and to perform phase detection processing and filtering processing on the first output signal and the second output signal to generate a sampled clock phase signal.
[0049] It needs to be further explained that, Figure 2 This is a schematic diagram (II) of a clock data recovery system according to an embodiment of the present invention. The clock data recovery system including the phase detection module is as follows: Figure 2 As shown.
[0050] In an optional embodiment, the phase detection module 108 includes:
[0051] The splicing unit 1080 is configured to acquire a first output signal and a second output signal, and splice the first output signal and the second output signal in the time domain to obtain a spliced signal;
[0052] Equalization unit 1082 is configured to perform equalization processing on spliced signals to obtain equalized spliced signals;
[0053] The phase detection unit 1084 is configured to perform phase detection processing on the equalized spliced signal to obtain a phase detection signal.
[0054] The filtering unit 1086 is configured to perform loop filtering on the phase detection signal to obtain the filtered phase detection signal.
[0055] The phase generation unit 1088 is configured to generate a sampled clock phase signal based on the filtered phase detection signal.
[0056] It needs to be further explained that, Figure 3 This is a schematic diagram of the internal structure of a phase detection module according to an embodiment of the present invention. The internal structure of the phase detection module is as follows: Figure 3 As shown.
[0057] In an alternative embodiment, the sampling rate of the first analog-to-digital conversion module is the same as the data symbol rate in the analog input signal.
[0058] In one optional embodiment, the sampling rate of the first analog-to-digital conversion module is the same as that of the second analog-to-digital conversion module; or, the sampling rate of the first analog-to-digital conversion module is different from that of the second analog-to-digital conversion module.
[0059] It should be further explained that the sampling rate of the second analog-to-digital converter (ADC) is usually less than or equal to the sampling rate of the first ADC. Since the sampling rate of the second ADC is less than that of the first ADC, the setup cost of the second ADC is lower. Therefore, the sampling rate of the second ADC can be set to be less than that of the first ADC to further reduce the system cost.
[0060] In one optional embodiment, the sampling signal precision of the first analog-to-digital conversion module 104 is the same as that of the second analog-to-digital conversion module 106; or, the sampling signal precision of the first analog-to-digital conversion module 104 is different from that of the second analog-to-digital conversion module 106.
[0061] It should be further explained that the sampling signal accuracy of the second analog-to-digital converter (ADC) is usually less than or equal to that of the first ADC. Since the sampling signal accuracy of the second ADC is less than that of the first ADC, the setup cost of the second ADC is lower. Therefore, the sampling signal accuracy of the second ADC can be set to be less than that of the first ADC to further reduce the system cost.
[0062] In an optional embodiment, the sampling clock phase of the first analog-to-digital conversion module 104 is different from the sampling clock phase of the second analog-to-digital conversion module 106.
[0063] In an optional embodiment, the first analog-to-digital conversion unit 104 is composed of a plurality of analog-to-digital converters employing a time-interleaved structure; the second analog-to-digital conversion unit 106 is composed of a plurality of analog-to-digital converters employing a time-interleaved structure.
[0064] The clock data recovery system in this embodiment will be further described below through specific examples. Specific Implementation Example 1
[0066] Figure 4 This is a schematic diagram of the structure of a clock data recovery system provided according to a specific embodiment of the present invention, as shown below. Figure 4 As shown, the clock data recovery system in this specific embodiment includes:
[0067] The system comprises a first analog-to-digital converter unit 11, a second analog-to-digital converter unit 12, a digital phase detection and filtering unit 13, a sampling clock generator unit 14, and a parameter configuration and status control unit 15.
[0068] During the operation of the aforementioned clock data recovery system, if... Figure 4 As shown, the first analog-to-digital converter unit 11 and the second analog-to-digital converter unit 12 respectively receive the input data signal Datain, and at the same time complete the sampling according to the first sampling clock c11 and the second sampling clock c12 generated by the sampling clock generator unit 14, so as to output the first sampled data d11 and the second sampled data d1 respectively.
[0069] The input data Datain mentioned above corresponds to the analog input signal in the above embodiment. The first sampling clock c11 and the second sampling clock c12 correspond to the first sampling clock signal and the second sampling clock signal in the above embodiment. The first sampled data d11 and the second sampled data d12 correspond to the first output signal and the second output signal in the above embodiment.
[0070] The rate of the first sampling clock c11 is the same as the data symbol rate of the input data signal Datain; the first analog-to-digital converter unit 11 can be implemented as a time-interleaved structure, and the first sampling clock c11 can be implemented as several clocks with different phases, the equivalent sampling rate of which is the same as the data symbol rate of the input Datain.
[0071] The rate of the second sampling clock c12 is less than or equal to the data symbol rate of the input data signal Datain; the second analog-to-digital converter unit 12 can be implemented as a time-interleaved structure, and the second sampling clock c12 can be implemented as several clocks with different phases, the equivalent sampling rate of which is less than or equal to the data symbol rate of the input Datain.
[0072] like Figure 4 As shown, after the first analog-to-digital converter unit 11 and the second analog-to-digital converter unit 12 output the first sampled data d11 and the second sampled data d12 respectively, the digital phase detection and filtering unit 13 completes phase detection based on the first sampled data d11 and the second sampled data d12; and performs digital loop filtering on the phase detection result to output the first phase information p11 required by the first analog-to-digital converter unit 11 and the second phase information p12 required by the second analog-to-digital converter unit 12.
[0073] Furthermore, the sampling clock generator unit 14 generates the first sampling clock c11 and the second sampling clock c12 required by the first analog-to-digital converter unit and the second analog-to-digital converter unit according to the first phase information p11 and the second phase information p12.
[0074] The first sampled data d11 and the first sampled clock c11 output by the first analog-to-digital converter unit 11 are the recovered data and recovered clock output by the clock data recovery system in this specific embodiment.
[0075] In addition, the above-mentioned parameter configuration and status control unit 15 configures and monitors the parameters and status of each unit.
[0076] Figure 5 This is a schematic diagram of the structure of a digital phase detection filter unit provided according to a specific embodiment of the present invention, such as... Figure 5As shown, the digital phase detection filter unit 13 uses a data splicer 131 to splice the first sampled data d11 and the second sampled data d12 output by the analog-to-digital converter unit 11 and the second analog-to-digital converter unit 12 in the time domain to output data d13.
[0077] Furthermore, the digital phase detection filtering unit 13 uses a digital equalizer 132 to perform digital equalization on the spliced data d13, outputting data d14. Based on this, the digital phase detection filtering unit 13 uses a digital phase detector 133 to perform digital phase detection on the signal d14 output by the digital equalizer, outputting a phase detection result sequence p0, and uses a loop filter 134 to perform loop filtering on the phase detection result sequence p0 to eliminate high-frequency phase detection noise, outputting a filtered sequence p1; finally, the digital phase detection filtering unit 13 uses a phase generator 135 to generate the first phase information p11 required by the first analog-to-digital converter unit 11 and the second phase information p12 required by the second analog-to-digital converter unit 12 based on the filtered sequence p1.
[0078] In this specific embodiment, the input data signal Datain is set to a 112Gbps PAM4 signal, and the baud rate of the input data signal Datain is 56Gbaud. Simultaneously, the first sampling clock c11 is set to four 14GHz four-phase clock signals, and the second sampling clock c12 is set to two 14GHz two-phase clock signals, with the phase of the first clock signal of the second sampling clock c12 lagging behind the phase of the first clock signal of the first sampling clock c11 by π / 4. Figure 6 This is a signal diagram of the first sampling clock and the second sampling clock provided according to a specific embodiment of the present invention. The distribution of the first sampling clock and the second sampling clock is as follows: Figure 6 As shown.
[0079] In this specific embodiment, Figure 7 This is a schematic diagram of the structure of the first analog-to-digital converter unit provided according to a specific embodiment of the present invention. Figure 8 This is a schematic diagram of the structure of the second analog-to-digital converter unit provided according to a specific embodiment of the present invention, as shown below. Figure 7 and 8 As shown, the first analog-to-digital converter unit 11 is implemented as a 4-channel time-interleaved analog-to-digital converter with an equivalent data conversion rate of 56GSps and an output bit width of 8 bits; the second analog-to-digital converter unit 12 is implemented as a 2-channel time-interleaved analog-to-digital converter with an equivalent data conversion rate of 28GSps and an output bit width of 4 bits.
[0080] In this specific embodiment, the splicing method of the data splicer 131 can be implemented as follows:
[0081] Let the sampled data d11 be a sequence [d11(1),d11(2),d11(3),...,d11(N),...], and let the sampled data d12 be a sequence [d12(1),d12(2),d12(3),...,d12(M),...], then the data d13 output by the data splicer 131 is a sequence:
[0082] [d11(1),d12(1),d11(2),(d11(2)+d11(3)) / 2,d11(3),d12(2),d11(4),(d11(4)+d11(5)) / 2,d11(5),...,d11(2N-1),d12(N),d11(2N),(d11(2N)+d11(2N+1)) / 2,d11(2N+1),...],
[0083] Furthermore, each of the above output data is saturated and truncated to a width of 4 bits.
[0084] In this specific embodiment, Figure 9 This is a schematic diagram of the structure of a digital equalizer according to a specific embodiment of the present invention, such as... Figure 9 As shown, the digital equalizer 132 can be implemented as an 8th-order FFE and a 2nd-order DFE. The digital phase detector 133 can be implemented as a Gardner digital phase detector. The loop filter 134 can be implemented as a second-order phase-locked loop. The phase generator 135 adjusts the phase represented by the phase information p11 to the position where the eye diagram is open, and adjusts the phase represented by the phase information p12 to the position of the eye diagram edge. Specific Implementation Example 2
[0086] Figure 10 This is a circuit diagram of a clock data recovery circuit provided according to a specific embodiment of the present invention, such as... Figure 10 As shown, the clock data recovery system in this specific embodiment includes:
[0087] First analog-to-digital converter 21, second analog-to-digital converter 22, digital phase detection filter 23, sampling clock generator 24, parameter configuration and status controller 25.
[0088] During the operation of the aforementioned clock data recovery system, if... Figure 9 As shown, the first analog-to-digital converter 21 and the second analog-to-digital converter 22 receive input data Data respectively, and at the same time complete sampling according to the first sampling clock c21 and the second sampling clock c22 generated by the sampling clock generator 24, so as to output the first sampled data d21 and the second sampled data d22 respectively.
[0089] The input data Data mentioned above corresponds to the analog input signal in the above embodiment. The first sampling clock c21 and the second sampling clock c22 correspond to the first sampling clock signal and the second sampling clock signal in the above embodiment. The first sampled data d21 and the second sampled data d22 correspond to the first output signal and the second output signal in the above embodiment.
[0090] like Figure 10 As shown, after the first analog-to-digital converter 21 and the second analog-to-digital converter 22 output the first sampled data d21 and the second sampled data d22 respectively, the digital phase detection filter 23 performs phase detection based on the first sampled data d21 and the second sampled data d22, and performs digital loop filtering on the phase detection result to output the first phase information p21 required by the analog-to-digital converter 21 and the second phase information p22 required by the second analog-to-digital converter 22.
[0091] Furthermore, the sampling clock generator 24 can generate the first sampling clock c21 and the second sampling clock c22 required by the first phase information p21 and the second phase information p22 as described above.
[0092] In this specific embodiment, the rate of the first sampling clock c21 is the same as the data symbol rate of the input data Data, and the rate of the second sampling clock c22 is less than or equal to the data symbol rate of the input data Data. The digital sampling signal d21 and the corresponding clock signal c21 output by the first analog-to-digital converter unit 21 serve as the recovered data and recovered clock output by the method described in this invention.
[0093] In addition, the parameter configuration and status control unit 25 in this specific embodiment configures and monitors the parameters and status of each unit.
[0094] In this specific embodiment, the configuration of the first analog-to-digital converter and the second analog-to-digital converter corresponds to that in the above specific embodiment 1, so it will not be described again here.
[0095] Figure 11 This is a circuit diagram of a digital phase detection filter provided according to a specific embodiment of the present invention, such as... Figure 11 As shown, the digital phase detection filter 23 uses a data splicer 231 to splice the first sampled data d21 and the second sampled data d22 output by the first analog-to-digital converter 21 and the second analog-to-digital converter 22 in the time domain to output data d23.
[0096] Furthermore, the digital phase detection filter uses a digital phase detector 232 to perform digital phase detection on the data d23, and outputs a phase detection result sequence p0-2. Based on this, the digital phase detection filter can use a loop filter 233 to perform loop filtering on the phase detection result sequence p0-2 to eliminate high-frequency phase detection noise, and output a filtered sequence p1-2. Finally, the digital phase detection filter uses a phase generator 234 to generate the first phase information p21 required by the analog-to-digital converter 21 and the second phase information p22 required by the second analog-to-digital converter 22 based on the filtered sequence p1-2.
[0097] In this specific embodiment, Data is set to a 28Gbps NRZ signal, and the data baud rate corresponding to Data is 28Gbaud. At the same time, the first sampling clock c21 is set to a 28GHz clock signal, the second sampling clock c22 is set to a 7GHz clock signal, and the phase of the second sampling clock c22 is 17.9ps later than the phase of the first sampling clock c21. Figure 12 This is a signal diagram of a first sampling clock and a second sampling clock provided according to a specific embodiment of the present invention. The first sampling clock and the second sampling clock are as follows: Figure 12 As shown.
[0098] Correspondingly, the first analog-to-digital converter 21 is implemented as a 28GSps Flash analog-to-digital converter with an output bit width of 4 bits; the second analog-to-digital converter 22 is implemented as a 7GSps Flash analog-to-digital converter with an output bit width of 3 bits.
[0099] In this specific embodiment, the splicing method of the data splicer 231 can be implemented as follows:
[0100] Let the sampled data d21 be a sequence [d21(1),d21(2),d21(3),...,d21(N),...], and let the sampled data d22 be a sequence [d22(1),d22(2),d22(3),...,d22(M),...]. Then the data d23 output by the data splicer 231 is a sequence, with 3 sample points in each row (group):
[0101] [d21(1),d22(1),d21(2)
[0102] d21(5),d22(2),d21(6)
[0103] d21(9),d22(3),d21(10) ...
[0105] d21(4M-3), d22(M), d21(4M-2)
[0106] ...],
[0107] Furthermore, each of the above output data is saturated and truncated to a width of 4 bits.
[0108] In this specific embodiment, the digital phase detector 232 can be implemented as a sub-rate band-band digital phase detector, performing band-band phase detection on each of the three signals output by the data splicer 231. The loop filter 233 can be implemented as a second-order phase-locked loop. The phase generator 234 can adjust the phase represented by the phase information p21 to the open position of the eye diagram and adjust the phase represented by the phase information p22 to the edge position of the eye diagram.
[0109] Example 2
[0110] This embodiment provides a clock data recovery method. Figure 13 This is a flowchart of a clock data recovery method provided according to an embodiment of the present invention, such as... Figure 13 As shown, the clock data recovery method in this embodiment includes:
[0111] S202, acquire the first output signal output by the first analog-to-digital converter module and the second output signal output by the second analog-to-digital converter unit, and perform clock data recovery based on the first output signal and / or the second output signal;
[0112] The first output signal is obtained by the first analog-to-digital converter module sampling the analog input signal according to the first sampling clock signal, and the second output signal is obtained by the second analog-to-digital converter module sampling the analog input signal according to the second sampling clock signal. Both the first sampling clock signal and the second sampling clock signal are generated based on the sampling clock phase signal, which is a phase signal obtained after phase detection and filtering based on the first output signal and the second output signal.
[0113] The clock data recovery method in the above embodiments solves the problem of inefficient clock data recovery in related technologies, thereby improving clock data recovery efficiency. The first analog-to-digital converter (ADC) and the second ADC can output a first output signal and a second output signal respectively based on the analog input signal and the corresponding first and second sampled clock signals. Furthermore, the sampling clock module performs phase detection and filtering on the first and second output signals to obtain the phase signal, which is then used to regenerate the first and second sampled clock signals for output by the ADC.
[0114] It should be further noted that the processor is the entity that performs the above step S202.
[0115] The remaining technical features and effects of the clock data recovery method in this embodiment correspond to the clock data recovery system in Embodiment 1, so they will not be repeated here.
[0116] In an optional embodiment, before obtaining the first output signal output by the first analog-to-digital conversion module and the second output signal output by the second analog-to-digital conversion unit in step S202 above, the method further includes:
[0117] Acquire the first output signal and the second output signal, and perform phase detection processing on the first output signal and the second output signal to generate a sampled clock phase signal.
[0118] In an optional embodiment, step S202 above, which involves acquiring a first output signal and a second output signal, and performing phase detection processing on the first output signal and the second output signal to generate a sampled clock phase signal, includes:
[0119] Acquire the first output signal and the second output signal, and concatenate the first output signal and the second output signal in the time domain to obtain the concatenated signal;
[0120] The spliced signal is subjected to equalization processing to obtain an equalized spliced signal;
[0121] Phase detection processing is performed on the equalized spliced signal to obtain a phase detection signal;
[0122] The phase detection signal is subjected to loop filtering to obtain the filtered phase detection signal;
[0123] The filtered phase detector signal is used to generate a sampled clock phase signal.
[0124] In an alternative embodiment, the sampling rate of the first analog-to-digital conversion module is the same as the data symbol rate in the analog input signal.
[0125] In one optional embodiment, the sampling rate of the first analog-to-digital conversion module is the same as that of the second analog-to-digital conversion module; or, the sampling rate of the first analog-to-digital conversion module is different from that of the second analog-to-digital conversion module.
[0126] In one optional embodiment, the sampling signal precision of the first analog-to-digital conversion module is the same as that of the second analog-to-digital conversion module; or, the sampling signal precision of the first analog-to-digital conversion module is different from that of the second analog-to-digital conversion module.
[0127] In one alternative embodiment, the sampling clock phase of the first analog-to-digital converter module is different from the sampling clock phase of the second analog-to-digital converter module.
[0128] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of the present invention.
[0129] Example 3
[0130] This embodiment provides a clock data recovery device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.
[0131] Figure 14 This is a structural block diagram of a clock data recovery device provided according to an embodiment of the present invention, such as... Figure 14 As shown, the clock data recovery device in this embodiment includes:
[0132] The acquisition module 302 is used to acquire the first output signal output by the first analog-to-digital conversion module and the second output signal output by the second analog-to-digital conversion unit, and to recover clock data based on the first output signal and / or the second output signal;
[0133] The first output signal is obtained by the first analog-to-digital converter module sampling the analog input signal according to the first sampling clock signal, and the second output signal is obtained by the second analog-to-digital converter module sampling the analog input signal according to the second sampling clock signal. Both the first sampling clock signal and the second sampling clock signal are generated based on the sampling clock phase signal, which is a phase signal obtained after phase detection and filtering based on the first output signal and the second output signal.
[0134] The remaining technical features and effects of the clock data recovery device in this embodiment correspond to the clock data recovery method in Embodiment 2, so they will not be repeated here.
[0135] In an optional embodiment, before acquiring the first output signal output by the first analog-to-digital conversion module and the second output signal output by the second analog-to-digital conversion unit, the acquisition module 302 further includes:
[0136] Acquire the first output signal and the second output signal, and perform phase detection processing on the first output signal and the second output signal to generate a sampled clock phase signal.
[0137] In an optional embodiment, the acquisition module 302 acquires a first output signal and a second output signal, and performs phase detection processing on the first output signal and the second output signal to generate a sampled clock phase signal, including:
[0138] Acquire the first output signal and the second output signal, and concatenate the first output signal and the second output signal in the time domain to obtain the concatenated signal;
[0139] The spliced signal is subjected to equalization processing to obtain an equalized spliced signal;
[0140] Phase detection processing is performed on the equalized spliced signal to obtain a phase detection signal;
[0141] The phase detection signal is subjected to loop filtering to obtain the filtered phase detection signal;
[0142] The filtered phase detector signal is used to generate a sampled clock phase signal.
[0143] In an alternative embodiment, the sampling rate of the first analog-to-digital conversion module is the same as the data symbol rate in the analog input signal.
[0144] In one optional embodiment, the sampling rate of the first analog-to-digital conversion module is the same as that of the second analog-to-digital conversion module; or, the sampling rate of the first analog-to-digital conversion module is different from that of the second analog-to-digital conversion module.
[0145] In one optional embodiment, the sampling signal precision of the first analog-to-digital conversion module is the same as that of the second analog-to-digital conversion module; or, the sampling signal precision of the first analog-to-digital conversion module is different from that of the second analog-to-digital conversion module.
[0146] In one alternative embodiment, the sampling clock phase of the first analog-to-digital converter module is different from the sampling clock phase of the second analog-to-digital converter module.
[0147] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.
[0148] Example 8
[0149] Embodiments of the present invention also provide a storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.
[0150] Optionally, in this embodiment, the storage medium may be configured to store a computer program for performing the following steps:
[0151] S1, acquire the first output signal output by the first analog-to-digital converter module and the second output signal output by the second analog-to-digital converter unit, and perform clock data recovery based on the first output signal and / or the second output signal;
[0152] The first output signal is obtained by the first analog-to-digital converter module sampling the analog input signal according to the first sampling clock signal, and the second output signal is obtained by the second analog-to-digital converter module sampling the analog input signal according to the second sampling clock signal. Both the first sampling clock signal and the second sampling clock signal are generated based on the sampling clock phase signal, which is a phase signal obtained after phase detection and filtering based on the first output signal and the second output signal.
[0153] Optionally, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.
[0154] Example 9
[0155] Embodiments of the present invention also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.
[0156] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.
[0157] Optionally, in this embodiment, the processor can be configured to perform the following steps via a computer program:
[0158] S1, acquire the first output signal output by the first analog-to-digital converter module and the second output signal output by the second analog-to-digital converter unit, and perform clock data recovery based on the first output signal and / or the second output signal;
[0159] The first output signal is obtained by the first analog-to-digital converter module sampling the analog input signal according to the first sampling clock signal, and the second output signal is obtained by the second analog-to-digital converter module sampling the analog input signal according to the second sampling clock signal. Both the first sampling clock signal and the second sampling clock signal are generated based on the sampling clock phase signal, which is a phase signal obtained after phase detection and filtering based on the first output signal and the second output signal.
[0160] Optionally, specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated here.
[0161] It will be apparent to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented herein, or they can be implemented as separate integrated system modules, or multiple modules or steps can be implemented as a single integrated system module. Thus, the present invention is not limited to any particular combination of hardware and software.
[0162] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A clock data recovery system, characterized in that, include: The sampling clock module is configured to generate a first sampling clock signal and a second sampling clock signal; The first analog-to-digital converter module is configured to acquire an analog input signal and the first sampling clock signal, and to sample the analog input signal according to the first sampling clock signal to obtain a first output signal. The second analog-to-digital converter module is configured to acquire an analog input signal and the second sampling clock signal, and to sample the analog input signal according to the second sampling clock signal to obtain a second output signal. The sampling clock module is further configured to acquire a sampling clock phase signal and generate a first sampling clock signal and a second sampling clock signal based on the sampling clock phase signal, wherein the sampling clock phase signal is a phase signal obtained after performing phase detection processing and filtering processing on the first output signal and the second output signal. The phase detection module is configured to acquire the first output signal and the second output signal, and perform the phase detection processing and the filtering processing on the first output signal and the second output signal to generate the sampled clock phase signal. The phase detection module includes: a splicing unit configured to splice the first output signal and the second output signal in the time domain to obtain a spliced signal; an equalization unit configured to perform equalization processing on the spliced signal to obtain an equalized spliced signal; a phase detection unit configured to perform phase detection processing on the equalized spliced signal to obtain a phase detection signal; a filtering unit configured to perform loop filtering processing on the phase detection signal to obtain a filtered phase detection signal; and a phase generation unit configured to generate the sampled clock phase signal based on the filtered phase detection signal.
2. The system according to claim 1, characterized in that, The sampling rate of the first analog-to-digital converter module is the same as the data symbol rate in the analog input signal.
3. The system according to claim 2, characterized in that, The sampling rate of the first analog-to-digital conversion module is the same as that of the second analog-to-digital conversion module; or, the sampling rate of the first analog-to-digital conversion module is different from that of the second analog-to-digital conversion module.
4. The system according to claim 2, characterized in that, The sampling signal precision of the first analog-to-digital converter module is the same as that of the second analog-to-digital converter module; or, the sampling signal precision of the first analog-to-digital converter module is different from that of the second analog-to-digital converter module.
5. The system according to claim 2, characterized in that, The sampling clock phase of the first analog-to-digital converter module is different from that of the second analog-to-digital converter module.
6. The system according to any one of claims 1 to 5, characterized in that, The first analog-to-digital conversion module consists of multiple analog-to-digital converters employing a time-interleaving structure; the second analog-to-digital conversion module consists of multiple analog-to-digital converters employing a time-interleaving structure.
7. A clock data recovery method, characterized in that, include: The first output signal from the first analog-to-digital converter module and the second output signal from the second analog-to-digital converter module are acquired, and clock data is recovered based on the first output signal and / or the second output signal. Wherein, the first output signal is obtained by the first analog-to-digital converter module sampling the analog input signal according to the first sampling clock signal, and the second output signal is obtained by the second analog-to-digital converter module sampling the analog input signal according to the second sampling clock signal; both the first and second sampling clock signals are generated based on a sampling clock phase signal, which is a phase signal obtained after phase detection and filtering of the first and second output signals; the phase detection process includes: splicing the first and second output signals in the time domain to obtain a spliced signal; performing equalization processing on the spliced signal to obtain an equalized spliced signal; performing phase detection processing on the equalized spliced signal to obtain a phase detection signal; performing loop filtering processing on the phase detection signal to obtain a filtered phase detection signal; and generating the sampling clock phase signal based on the filtered phase detection signal.
8. The method according to claim 7, characterized in that, Before acquiring the first output signal from the first analog-to-digital converter module and the second output signal from the second analog-to-digital converter module, the method further includes: The first output signal and the second output signal are acquired, and phase detection processing is performed on the first output signal and the second output signal to generate a sampled clock phase signal.
9. The method according to any one of claims 7 to 8, characterized in that, The sampling rate of the first analog-to-digital converter module is the same as the data symbol rate in the analog input signal.
10. The method according to claim 9, characterized in that, The sampling rate of the first analog-to-digital conversion module is the same as that of the second analog-to-digital conversion module; or, the sampling rate of the first analog-to-digital conversion module is different from that of the second analog-to-digital conversion module.
11. The method according to claim 9, characterized in that, The sampling signal precision of the first analog-to-digital converter module is the same as that of the second analog-to-digital converter module; or, the sampling signal precision of the first analog-to-digital converter module is different from that of the second analog-to-digital converter module.
12. The method according to claim 9, characterized in that, The sampling clock phase of the first analog-to-digital converter module is different from that of the second analog-to-digital converter module.
13. A clock data recovery device, disposed on the receiving side, characterized in that, The device includes: The acquisition module is used to acquire the first output signal output by the first analog-to-digital converter module and the second output signal output by the second analog-to-digital converter module, and to perform clock data recovery based on the first output signal and / or the second output signal; Wherein, the first output signal is obtained by the first analog-to-digital converter module sampling the analog input signal according to the first sampling clock signal, and the second output signal is obtained by the second analog-to-digital converter module sampling the analog input signal according to the second sampling clock signal; both the first and second sampling clock signals are generated based on a sampling clock phase signal, which is a phase signal obtained after phase detection and filtering of the first and second output signals; the phase detection process includes: splicing the first and second output signals in the time domain to obtain a spliced signal; performing equalization processing on the spliced signal to obtain an equalized spliced signal; performing phase detection processing on the equalized spliced signal to obtain a phase detection signal; performing loop filtering processing on the phase detection signal to obtain a filtered phase detection signal; and generating the sampling clock phase signal based on the filtered phase detection signal.
14. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the method described in any one of claims 7 to 12 when it is run.
15. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method as described in any one of claims 7 to 12.