Information processing apparatus, non-transitory storage medium, information processing method, and electronic circuit

Abstract

According to one embodiment, an information processing device includes a first processing circuit and a second processing circuit. The first processing circuit is configured to update a third vector based on a base equation. Each base equation is a partial derivative of an objective function with respect to any variable in the objective function. The second processing circuit is configured to update an element of a first vector and update an element of a second vector. Elements of the first vector that are less than a first value are set to the first value. Elements of the first vector that are greater than a second value are set to the second value.

Description

Technical Field

[0001] The embodiments described herein generally relate to information processing devices, non-transitory storage media, information processing methods, and electronic circuits. Background Technology

[0002] In combinatorial optimization problems, the optimal combination for a desired objective is selected from multiple combinations. Mathematically, combinatorial optimization problems can be attributed to the problem of maximizing or minimizing an objective function, which is a function with multiple discrete variables. Combinatorial optimization problems are common in various fields, including finance, logistics, transportation, design, manufacturing, and life sciences. However, due to the so-called "combinatorial explosion," the number of combinations increases exponentially with the problem size. Therefore, the optimal solution cannot always be computed. Furthermore, in many cases, computing approximate solutions close to the optimal solution is difficult.

[0003] There is a need for technologies that can compute solutions to combinatorial optimization problems in real time to solve problems across various fields and accelerate social, scientific and technological innovation. Summary of the Invention

[0004] The embodiments provide an information processing device, a non-transitory storage medium, an information processing method, and an electronic circuit that calculates solutions to combinatorial optimization problems in a real time period.

[0005] According to one embodiment, the information processing device includes a first processing circuit and a second processing circuit. The first processing circuit is configured to update a third vector based on fundamental equations. Each fundamental equation is a partial derivative of an objective function with respect to any variable in the objective function. The second processing circuit is configured to update elements of the first vector and update elements of the second vector. Elements of the first vector less than a first value are set to a first value. Elements of the first vector greater than a second value are set to a second value. Attached Figure Description

[0006] Figure 1 It is a diagram showing an example configuration of an information processing system;

[0007] Figure 2 It is a diagram showing a configuration example of the management server;

[0008] Figure 3 It is a diagram showing an example of data stored in the management server's storage device;

[0009] Figure 4 It is a block diagram that presents an example configuration of a computing server;

[0010] Figure 5 It is a diagram showing an example of data stored in the storage device of a computing server;

[0011] Figure 6 This is a graph showing the first example of the number of cuts required to solve the maximum cut problem multiple times;

[0012] Figure 7 This is a graph showing examples of bifurcation in algorithms where the absolute value of xi does not exceed 1;

[0013] Figure 8 This is a graph showing examples of bifurcation in algorithms where the absolute value of xi exceeds 1;

[0014] Figure 9 This is a second example of the number of cuts required to solve the maximum cut problem multiple times;

[0015] Figure 10 This is a diagram of the third example of the number of cuts required to solve the maximum cut problem multiple times;

[0016] Figure 11 This is a diagram of the fourth example of the number of cuts required to solve the maximum cut problem multiple times;

[0017] Figure 12 This is a diagram of the fifth example of the number of cuts required to solve the maximum cut problem multiple times;

[0018] Figure 13 This is a diagram of the sixth example of the number of cuts required to solve the maximum cut problem multiple times;

[0019] Figure 14 This is the seventh example of the number of cuts required to solve the maximum cut problem multiple times;

[0020] Figure 15 This is the eighth example of the number of cuts required to solve the maximum cut problem multiple times;

[0021] Figure 16 This is a diagram of the ninth example of the number of cuts required to solve the maximum cut problem multiple times;

[0022] Figure 17 This is a diagram of the tenth example of the number of cuts required to solve the maximum cut problem multiple times;

[0023] Figure 18 This is a diagram showing the eleventh example of the number of cuts required to solve the maximum cut problem multiple times;

[0024] Figure 19 This is a diagram showing the twelfth example of the number of cuts required to solve the maximum cut problem multiple times;

[0025] Figure 20 This is a diagram showing the thirteenth example of the number of cuts required to solve the maximum cut problem multiple times;

[0026] Figure 21 This is a schematic diagram illustrating an example of a multiprocessor configuration;

[0027] Figure 22 This is a graph showing the results of solving the fully connected N=3600 Ising problem using a PC cluster;

[0028] Figure 23 This is a schematic diagram illustrating an example configuration using a GPU;

[0029] Figure 24 This is a graph showing the results of solving the fully connected N=3600 Ising problem using a GPU;

[0030] Figure 25 It is a flowchart that presents an example process performed by an information processing system;

[0031] Figure 26 It is a flowchart that presents an example process performed by an information processing system;

[0032] Figure 27 It is a diagram showing an example of an algorithm implemented in an electronic circuit;

[0033] Figure 28 It is a block diagram that presents an example of the configuration of an electronic circuit;

[0034] Figure 29 This is a diagram that presents a first example of a method for calculating the product of a matrix and a vector;

[0035] Figure 30 This is a diagram illustrating examples of multiple parallelization methods;

[0036] Figure 31 It is a presentation circuit block MM k A diagram illustrating a configuration example;

[0037] Figure 32 It is the presentation circuit block TE k A diagram illustrating a configuration example;

[0038] Figure 33 It is a diagram illustrating an example configuration of multiple electronic circuits that can communicate with each other;

[0039] Figure 34 This is a diagram illustrating a second example of a method for calculating the product of a matrix and a vector;

[0040] Figure 35 It is a diagram showing examples of algorithms executed in each electronic circuit;

[0041] Figure 36 It is a timing diagram that presents an example of a process executed by multiple electronic circuits;

[0042] Figure 37 This is a diagram showing a more detailed configuration example of the communication channel;

[0043] Figure 38 It is a block diagram showing a configuration example of hardware that supports a ring topology;

[0044] Figure 39 This is a diagram showing an example timing sequence during the communication phase; and

[0045] Figure 40 This is a diagram showing an example timing sequence during the communication phase. Detailed Implementation

[0046] According to one embodiment, the information processing device includes a first processing circuit and a second processing circuit. The first processing circuit is configured to update a third vector based on fundamental equations. Each fundamental equation is a partial derivative of an objective function with respect to any variable in the objective function. The second processing circuit is configured to update elements of the first vector and update elements of the second vector. Elements of the first vector less than a first value are set to a first value. Elements of the first vector greater than a second value are set to a second value.

[0047] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Examples of specific components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over a second feature can include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature can be formed between the first and second features without direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Furthermore, when a first element is described as being “connected” or “coupled” to a second element, such descriptions include embodiments where the first and second elements are directly connected or coupled to each other, as well as embodiments where the first and second elements are indirectly connected or coupled to each other, with one or more other intermediate elements between the first and second elements.

[0048] Embodiments of the present invention will now be described with reference to the accompanying drawings.

[0049] Figure 1 This is a diagram showing a configuration example of the information processing system 100. Figure 1 The information processing system 100 includes a management server 1, a network 2, computing servers (information processing devices) 3a to 3c, cables 4a to 4c, and a switch 5. Furthermore, Figure 1This includes a client device 6 capable of communicating with the information processing system 100. Data communication between the management server 1, computing servers 3a to 3c, and the client device 6 is implemented by a network 2. For example, the network 2 is the Internet, which includes multiple interconnected computer networks. The communication medium used in the network 2 can be wired, wireless, or a combination thereof. Examples of communication protocols used in the network 2 include TCP / IP. However, any type of communication protocol can be used.

[0050] Furthermore, computing servers 3a to 3c are connected to switch 5 via cables 4a to 4c, respectively. Cables 4a to 4c and switch 5 provide interconnection between the computing servers. Computing servers 3a to 3c can transmit data via this interconnection. For example, switch 5 is an InfiniBand switch. For example, cables 4a to 4c are InfiniBand cables. However, wired LAN switches and cables can be used instead of InfiniBand switches and cables. The communication standards and protocols used in cables 4a to 4c and switch 5 are not limited. Examples of client devices 6 include laptops, desktop computers, smartphones, tablets, and in-vehicle devices.

[0051] Parallel and / or distributed processing can be used to solve combinatorial optimization problems. Therefore, some steps of the computational processing can be distributed to different computing servers 3a to 3c or processors within computing servers 3a to 3c. Furthermore, computing servers 3a to 3c and / or processors within computing servers 3a to 3c can perform similar processing for different variables in parallel.

[0052] For example, management server 1 transforms the user-input combinatorial optimization problem into a format that can be processed by each computation server. Management server 1 also controls these computation servers. Then, management server 1 collects the computation results from each computation server and transforms the aggregated results into a solution to the combinatorial optimization problem. Thus, the user can obtain a solution to their combinatorial optimization problem. The solution to the combinatorial optimization problem includes the optimal solution and approximate solutions that are sufficiently close to the optimal solution. The permissible transition between approximate and optimal solutions depends on the application.

[0053] exist Figure 1The diagram shows three computing servers. However, the number of computing servers in an information processing system is unlimited. The number of computing servers used to solve combinatorial optimization problems is also unlimited. For example, an information processing system may include only one computing server. Furthermore, only one of the multiple computing servers in an information processing system can be used to solve combinatorial optimization problems. Additionally, an information processing system may include more than hundreds of computing servers. Computing servers can be servers installed in data centers or desktop computers installed in offices. Furthermore, computing servers can be different types of computers installed in various locations. The type of information processing equipment used as computing servers is unlimited. For example, a computing server can be a general-purpose computer, a special-purpose electronic circuit, or a combination thereof.

[0054] Figure 2 This is a block diagram illustrating a configuration example for management server 1. For example, Figure 2 The management server 1 is a computer including a central processing unit (CPU) and memory. The management server 1 includes a processor 10, a storage device 14, communication circuitry 15, input circuitry 16, and output circuitry 17. The processor 10, storage device 14, communication circuitry 15, input circuitry 16, and output circuitry 17 are interconnected via a bus 20. The processor 10 includes a management service 11, a converter service 12, and a controller service 13 as internal components.

[0055] Processor 10 is an electronic circuit that performs arithmetic calculations and controls management server 1. For example, a CPU, microprocessor, ASIC, FPGA, PLD, or a combination thereof can be used as processor 10. Management service 11 provides an interface for users to perform various operations on management server 1 via client device 6. Examples of interfaces provided by management service 11 include API, CLI, or web pages. For example, users can input information related to combinatorial optimization problems, view solutions to combinatorial optimization problems, or download solutions to combinatorial optimization problems via management service 11. Converter service 12 converts the combinatorial optimization problem into a format that can be processed by each computing server. Controller service 13 sends control signals to each computing server. After controller service 13 collects calculation results from each computing server, converter service 12 aggregates multiple calculation results, thereby converting the results into a solution to the combinatorial optimization problem.

[0056] Storage device 14 stores various data, including programs, data required for program execution, and data generated by the programs, within management server 1. Here, programs include both the operating system (OS) and application programs. Storage device 14 can be volatile memory, non-volatile memory, or a combination thereof. Examples of volatile memory include DRAM and SRAM. Examples of non-volatile memory include NAND flash memory, NOR flash memory, resistive random access memory, and magnetoresistive random access memory. Alternatively, hard disk drives, optical discs, magnetic tapes, or external storage devices can be used as storage device 14.

[0057] Communication circuit 15 transmits data to each device connected to network 2. For example, communication circuit 15 is a NIC (Network Interface Card) that establishes a connection to a wired LAN. However, communication circuit 15 can be other types of communication circuits, such as those for wireless LANs. Input circuit 16 enables data to be input to management server 1. For example, input circuit 16 can have external ports such as USB or PCI-Express. Figure 2 In the example, operating device 18 is connected to input circuitry 16. Operating device 18 is a device that can be used to input information to management server 1. For example, operating device 18 is a keyboard, mouse, touch panel, or voice recognition device. However, other devices can also be used as operating device 18. Output circuitry 17 enables data to be output from management server 1. Output circuitry 17 may have external ports, such as HDMI or DisplayPort. Figure 2 In this example, display device 19 is connected to output circuit 17. Examples of display devices 19 include LCD (liquid crystal display), OLED (organic light-emitting diode display), and projector. However, any other device can be used as display device 19.

[0058] The administrator of management server 1 can perform various maintenance tasks using operating device 18 and display device 19. Operating device 18 and display device 19 can be embedded in management server 1. However, operating device 18 and display device 19 do not necessarily need to be connected to management server 1. For example, the administrator can perform maintenance tasks on management server 1 using a client device that has access to network 2.

[0059] Figure 3 This is a diagram illustrating an example of data stored in storage device 14 of management server 1. Figure 3The storage device 14 stores problem data 14A, calculation data 14B, management program 14C, conversion program 14D, and control program 14E. For example, problem data 14A includes data on a combinatorial optimization problem. For example, calculation data 14B includes calculation results collected from each computing server. For example, management program 14C is a program that provides the features of the aforementioned management service 11. For example, conversion program 14D is a program that provides the features of the aforementioned converter service 12. For example, control program 14E is a program that provides the features of the aforementioned controller service 13.

[0060] Figure 4 This is a block diagram illustrating an example configuration of a computing server. As an example, Figure 4 The configuration of computing server 3a is shown. Other computing servers may have configurations similar to or different from computing server 3a. For example, computing server 3a is an information processing device that independently or collaboratively computes the first, second, and third vectors. Furthermore, computing server 3a can compute a fourth vector, which can be obtained by transforming each element of the first vector using a sign function. For example, the value of each element in the third vector can be computed using equations derived from the energy equation of the Ising model. For example, each element in the third vector can be computed based on fundamental equations. Each fundamental equation is a partial derivative of the energy equation of the Ising model with respect to any variable.

[0061] The elements of the first vector are the variables x. i (i=1, 2, ..., N). The elements of the second vector are the variables y. i (i=1, 2, ..., N). The elements of the third vector are the variables z. i (i=1, 2, ..., N). The fourth vector can be obtained by transforming each element of the first vector using the first function. The first function is a function that takes a first value or a second value greater than the first value. The aforementioned symbolic function is an example of the first function. Variable x i y i and z i The details will be discussed later.

[0062] For example, computing server 3a includes communication circuitry 31, shared memory 32, processors 33A to 33D, storage device 34, and host bus adapter 35. Communication circuitry 31, shared memory 32, processors 33A to 33D, storage device 34, and host bus adapter 35 are interconnected via bus 36.

[0063] Communication circuit 31 transmits data with each device connected to network 2. For example, communication circuit 31 is a NIC (Network Interface Card) used to establish a connection to a wired LAN. However, communication circuit 31 can be other types of communication circuits, such as those for wireless LANs. Shared memory 32 is memory accessible from processors 33A to 33D. Examples of shared memory 32 include volatile memory such as DRAM and SRAM. However, other types of memory, such as non-volatile memory, can also be used as shared memory 32. Processors 33A to 33D can share data with each other via shared memory 32. Not all memory in computing server 3a must be configured as shared memory. For example, some memory in computing server 3a can be configured as local memory accessible from any processor.

[0064] Processors 33A to 33D are electronic circuits that perform computational processes. For example, a processor can be a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an FPGA (Field-Programmable Gate Array), an ASIC (Application-Specific Integrated Circuit), or a combination thereof. Furthermore, a processor can be a CPU core or a CPU thread. If the processor is a CPU, the number of sockets in the computing server 3a is unlimited. Additionally, the processor can be connected to other components of the computing server 3a via a bus such as PCI Express.

[0065] exist Figure 4 In the example, the computer server has four processors. However, each computing server can have a different number of processors. For example, depending on the computing server, different numbers and / or different types of processors can be implemented.

[0066] The multiply-accumulator 51 is configured to update each element in the third vector based on fundamental equations. Here, each fundamental equation is a partial derivative of the objective function with respect to any variable. The objective function can be derived based on the formulation of a combinatorial optimization problem. Here, the variables of the fundamental equations are elements of the first vector or elements of the fourth vector. The fourth vector can be computed by transforming each element in the first vector using a first function that takes a first value or a second value greater than the first value. The multiply-accumulator 51 can be implemented using processing circuitry (first processing circuitry).

[0067] For example, updater 50 is configured to: (1) update the elements of the first vector by adding the corresponding element of the second vector or the weighted value of the second vector to the elements of the first vector; (2) set the elements of the first vector whose value is less than the first value to the first value; (3) set the elements of the first vector whose value is greater than the second value to the second value; and (4) update the elements of the second vector by (i) adding the weighted product of the first coefficient (which monotonically increases or decreases based on the number of updates) and the corresponding element of the first vector and (ii) adding the weighted value of the corresponding element of the third vector.

[0068] For example, the energy equation of the Ising model can be used as the objective function. Here, the Ising model including multi-person interactions can be used. Furthermore, -1 can be used as the first value, and +1 can be used as the second value. However, other values ​​can be used as the first and / or second values. The updater 50 can also be implemented using processing circuitry (the second processing circuitry).

[0069] exist Figure 4 In the example, processors 33A to 33C correspond to updater 50, and processor 33D corresponds to multiply-accumulater 51. However, the updater / multiply-accumulater and Figure 4 The processor correspondence presented is merely an example. Therefore, the correspondence between updaters / multiply-accumulators and processors can differ. Furthermore, the number of processors assigned to updater 50 and multiply-accumulator 51 is unlimited. As described below, the same processor can play the roles of updater 50 and multiply-accumulator 51. If different types of processors (e.g., CPU, GPU, and FPGA) are implemented in the computing server, different types of processors can be assigned to updater 50 and multiply-accumulator 51.

[0070] Storage device 34 provides storage space for storing various types of data, including programs in computing server 3a, data required for executing programs, and data generated by programs. Here, programs include both the operating system (OS) and applications. Storage device 34 can be volatile memory, non-volatile memory, or a combination thereof. Examples of volatile memory include DRAM and SRAM. Examples of non-volatile memory include NAND flash memory, NOR flash memory, resistive random access memory, and magnetoresistive random access memory. Furthermore, hard disk drives, optical disks, magnetic tapes, or external storage devices can be used as storage device 34.

[0071] The host bus adapter 35 enables data communication between computing servers. The host bus adapter 35 is connected to the switch 5 via cable 4a. For example, the host bus adapter 35 is an HCA (Host Channel Adapter). By forming a high-speed interconnect with the host bus adapter 35, cable 4a, and switch 5, the speed of parallel computing processes can be accelerated.

[0072] Figure 5 This is a diagram illustrating an example of data stored in the storage device of a computing server. Figure 5 The storage device 34 stores computational data 34A, a computational program 34B, and a control program 34C. Computational data 34A may include data generated during computation or computational results. At least a portion of computational data 34A may be stored in different storage hierarchies, including shared memory 32, processor cache, and registers within the processor. The computational program 34B is a program that executes computational processes based on specific algorithms on each processor and stores data in shared memory 32 and storage device 34. The control program 34C controls computational server 3a based on instructions sent from controller service 13 of management server 1 and sends the computational results of computational server 3a to management server 1.

[0073] Next, we will explain the techniques related to the computation of combinatorial optimization problems. An example of an information processing device used to solve combinatorial optimization problems is the Ising machine. The Ising machine is an information processing device that calculates the ground-state energy of the Ising model. Traditionally, the Ising model has been used to model ferromagnetic materials and phase transition phenomena. Now, the Ising model is frequently used as a model for solving combinatorial optimization problems. The following equation (1) describes the energy of the Ising model.

[0074] [Mathematical Formula 1]

[0075]

[0076] Here, s i and s j It's spin. Spin is a binary variable that takes a value of +1 or -1. N is the number of spins. Additionally, h... i This corresponds to the local magnetic field interacting with each spin. J is a matrix that includes the coupling coefficients between the spins. Matrix J is a real symmetric matrix with its diagonal elements set to 0. Therefore, J in the above equations... ij Indicates the element in the i-th row and j-th column of matrix J.

[0077] The Ising model in equation (1) is a quadratic polynomial with spin as the variable. However, extended Ising models (including the Ising model with multi-body interactions) can be used, which include tertiary terms or higher. Details of the Ising model with multi-body interactions will be explained later.

[0078] If the Ising model in equation (1) is used, then the energy E Ising It can be used as an objective function. For example, it can be used to calculate the energy E. IsingThe solution minimized. The solution to the Ising model can be represented as a vector (s1, s2, ..., s...) with spin as its element. N The optimal solution is when the energy E Ising The vector (s1, s2, ..., s) that takes the minimum value N The value of ). However, the calculated solution to the Ising model does not necessarily have to be exactly the same as the optimal solution. The following is used to calculate the energy E that makes the Ising model. Ising A problem with smaller approximate solutions is called an Ising problem. In other words, an approximate solution is one that makes the value of the objective function closer to the optimal value.

[0079] Due to the spin s in equation (1) i Since the variables are binary, the equation (1+si) / 2 can be used to transform the discrete variables (bits) used in combinatorial optimization problems. Therefore, the solution to the combinatorial optimization problem can be computed by converting the combinatorial optimization problem into an Ising problem and using an Ising machine for computation. The problem that computes the solution that minimizes a quadratic object function with discrete variables (bits) (which take 0 or 1 as values) is called a QUBO (Quadratic Unconstrained Binary Optimization) problem. The Ising problem described in equation (1) is equivalent to the QUBO problem.

[0080] For example, quantum annealers, coherent ising machines, and quantum bifurcation machines have been proposed as hardware implementations of ising machines. Quantum annealers achieve quantum annealing using superconducting circuits. Coherent ising machines utilize oscillation phenomena in a network formed by optical parametric oscillators. Quantum bifurcation machines utilize quantum mechanical bifurcation phenomena in a network of parametric oscillators exhibiting the Kerr effect. These hardware implementations have the potential to significantly reduce computation time. However, it is difficult to scale and maintain stable operations in these implementations.

[0081] The solution to the Ising problem can be computed using a digital computer. Compared to the hardware implementations that utilize physical phenomena described above, scaling up in a digital computer is much easier. Furthermore, stable computation can be performed in a digital computer. An example of an algorithm that can be used to compute the solution to the Ising problem in a digital computer is simulated annealing (SA). Techniques have been developed to perform simulated annealing at much higher speeds. However, simulated annealing is a sequential update algorithm where each variable is updated sequentially. Therefore, it is difficult to accelerate the computation process through parallelization.

[0082] Considering the aforementioned problems, a simulated bifurcation algorithm has been proposed that can compute solutions to large-scale combinatorial optimization problems in a relatively short time. Below, an information processing device and electronic circuit for solving combinatorial optimization problems using the simulated bifurcation algorithm are described.

[0083] First, a brief explanation of the simulated forking algorithm. In the simulated forking algorithm, for two variables x... i and y i (i = 1, 2, ..., N) Solve numerically the following simultaneous ordinary differential equations (2). N variables x i Each of them corresponds to the spin s in the Ising model. i N variables y i Each of these corresponds to momentum. The variable x i and y i It can be a continuous variable.

[0084] [Mathematical Formula 2]

[0085]

[0086] Here, H is the Hamiltonian described in the following equation (3). The coefficient D corresponds to detuning. The coefficient p(t) corresponds to the pump amplitude. During the computation of the simulated bifurcation algorithm, the value of the coefficient p(t) increases according to the number of updates. The initial value of the coefficient p(t) can be set to 0. The coefficient p(t) is an example of the first coefficient. The coefficient K corresponds to the positive Kerr coefficient. Term f i The external force corresponds to the following equation (4). The z in equation (4) i It equals the partial derivative of the terms in equation (3), except for c.

[0087] [Mathematical Formula 3]

[0088]

[0089] Here, a constant can be used as the coefficient c. The value of coefficient c then needs to be determined before performing the computation using the simulated bifurcation algorithm. For example, for computational accuracy, coefficient c can be set to be close to J. （2） The inverse of the largest eigenvalue of the matrix. For example, the value c = 0.5D(N / 2n)^(1 / 2) can be used. Here, n represents the number of cut edges in the graph of the combinatorial optimization problem. Additionally, α(t) is a coefficient that increases along with the first coefficient p(t). For example, (p(t))^(1 / 2) can be used as α(t).

[0090] Combinatorial optimization problems with third-order or higher-order terms in the objective function can be solved by using the simulated bifurcation algorithm. The problem of finding a combination of variables that minimizes the objective function with third-order or higher-order terms is called the HOBO (Higher-Order Binary Optimization) problem. If the HOBO problem is handled, the following equation (5) can be used as the energy equation in the Ising model which is extended to a higher order.

[0091] [Mathematical Formula 4]

[0092]

[0093] Here, J (n) It is an nth-order tensor, which includes the local magnetic field h. i The general form of both the coupling coefficient matrix J and the tensor J. For example, the tensor J. (1) Corresponding to the local magnetic field h i The vector (referred to as the sixth vector). For an n-order tensor J with the same index value (n) The value of the element is 0. Equation (5) includes first-order, second-order, and third-order terms. Higher-order terms can be defined in a similar manner to those in equation (5). Equation (5) corresponds to the energy of the Ising model, which includes multi-person interactions.

[0094] Both QUBO and HOBO are examples of PUBO (polynomial unconstrained binary optimization). Therefore, combinatorial optimization problems classified as PUBOs with second-order objective functions are QUBO problems. Similarly, combinatorial optimization problems classified as PUBOs with third-order or higher objective functions are HUBO problems.

[0095] If the HOBO problem is solved using a simulated bifurcation algorithm, the Hamiltonian H in equation (3) above can be replaced by equation (6) below, and the external force f in equation (4) above can be replaced by equation (6) below. i The following equation (7) can be used as a substitute.

[0096] [Mathematical Formula 5]

[0097]

[0098] For example, this can be achieved by using the second equation z in (7). i To calculate each element in the third vector. The second equation z in (7) i It equals the partial derivative of the second equation in (6) with respect to any variable. Additionally, the second equation z in (7) i The elements of the first vector are used as variables.

[0099] Therefore, a Hamiltonian can include multi-body interaction terms (terms of a 3rd or higher order tensor). A Hamiltonian without multi-body interaction terms (terms of a 3rd or higher order tensor) can also be used. The second equation z in (7) i Here is an example of the fundamental equation, derived from the terms corresponding to the energy of the Ising model within the Hamiltonian. Therefore, the first value can be -1, and the second value can be 1. Furthermore, the objective function can include terms corresponding to the energy equation of the Ising model. In this case, the objective function can include multi-body interaction terms.

[0100] In the simulated bifurcation algorithm, after the value of the first coefficient p(t) increases from its initial value (e.g., 0) to a predetermined value, the value can be adjusted based on the variable x. i The sign of the spin s is used to determine the spin. i The value of . In the symbolic function, for x i >0, s(x) i )=1 holds true, while for x i <0, s(x) i The equation -1 holds true. Therefore, if the first coefficient p(t) increases to a certain value, the variable x can be transformed using a sign function. i To calculate spin s i The value of x. For example, a function defined as follows: when x i When not equal to 0, sgn(xi) = x i / |x i |, when x i When equal to 0, sgn(x) i =1 or -1.

[0101] Therefore, updater 50 can be configured to: convert elements of the first vector whose values ​​are less than a third value between the first and second values ​​to the first value; and convert elements of the first vector whose values ​​are greater than the third value to the second value, to compute a solution to the combinatorial optimization problem. For example, updater 50 can be configured to: convert elements of the first vector with positive values ​​to +1; and convert elements of the first vector with negative values ​​to -1, to compute a solution to the combinatorial optimization problem. Updater 50 computes solutions to combinatorial optimization problems (e.g., the spins of the Ising model). i The timing of the updater is unrestricted. Furthermore, the updater 50 can be configured to compute the solution to the combinatorial optimization problem when the value of the first coefficient p exceeds a threshold. If the Ising model is solved, the solution to the combinatorial optimization problem corresponds to the spin s of the Ising model. i .

[0102] For example, if the Symplectic Euler method is used, the differential equations defined by equations (2), (3), and (4), or equations (2), (5), and (7), can be solved. As indicated by equation (8) below, the differential equations can be rewritten as discrete difference equations.

[0103] [Mathematical Formula 6]

[0104]

[0105] Here, t corresponds to time. Additionally, Δt corresponds to the time step (time increment). The nonlinear term Kx... 2 (t+Δt) prevents variable x iIt diverges during the calculation process.

[0106] The computing server can update the variable x according to the algorithm in equation (8). i and y i (i=1, 2, ..., N). Therefore, the data updated by the computer server can include a first vector, a second vector, and a third vector. Here, the first vector (x1, x2, ..., x...) N () is a variable x with N variables. i The vector consists of elements (i = 1, 2, ..., N). The second vector consists of elements (y1, y2, ..., y). N ) is a variable y with N variables. i The vector (i = 1, 2, ..., N) is used as its elements. The third vector (z1, z2, ..., z...) is used as its elements. N () is a group of N variables z i (i = 1, 2, ..., N) are vectors with elements. The computation server can solve for each element z of the third vector. i (i = 1, 2, ..., N), each element x of the first vector i (i=1, 2, ..., N) and each element y of the second vector i (i=1, 2, ..., N).

[0107] Referring to (8), only a single index type appears in the terms, except for the product and sum of matrices or tensors. Terms with only a single index type in (8) can be computed in parallel, thereby reducing the total computation time.

[0108] In equation (8), time t and time step Δt are used to represent the relationship with the original differential equation. However, when the algorithm is implemented in software or hardware according to the Symplectic Euler method, time t and time step Δt do not need to be used as explicit parameters. For example, if the time step Δt is set to 1, the time step Δt can be eliminated from the implemented algorithm. If time t is not included as an explicit parameter during the implementation of the algorithm, then x in equation (8) i (t+Δt) can be interpreted as the updated x i The value of (t). Therefore, in the above equation and the following equation, "t" represents the value of the variable before the update, while "t + Δt" represents the value of the variable after the update.

[0109] The following section describes the results of solving combinatorial optimization problems using a simulated bifurcation algorithm implemented on a digital computer using the Symptotic Euler method. Below, the average and maximum number of cuts are presented when the baseline set G22 of the maximum cut problem (G-Set) is solved 1000 times. The maximum cut problem is to cut the nodes of a weighted graph into two groups, ensuring that the total value of the separated cut edges is maximized. The maximum cut problem is a type of combinatorial optimization problem.

[0110] Figure 6 The results are shown when using the algorithm according to (8) above. The calculation is performed by setting the time step Δt to 0.5. The results for 100 total time steps, 1,000 total time steps, 10,000 total time steps, 100,000 total time steps, and 1,000,000 total time steps are also shown. D=K=1, c=0.5D(N / 2n)^(1 / 2) are used as coefficients. The number of cut edges of the graphic used in G22, 19990, is substituted into n. The value of coefficient p (first coefficient) increases from 0 to 1 as the time step increases. In addition, the variable x i The initial value is set to 0. Furthermore, a pseudo-random number in the range [-0.1, 0.1] is used as the variable y. i The initial value.

[0111] exist Figure 6 The upper part of the graph shows the average number of cuts. Figure 6 The bottom diagram shows the maximum number of cuts. Figure 6 In the two graphs, the vertical axis corresponds to the number of cuts, and the horizontal axis corresponds to the time step. Figure 6 The horizontal dashed line Cmax in the two graphs indicates the maximum known number of cuts (13359) for G22. The closer the number of cuts is to the dashed line Cmax, the closer the result is to the optimal solution. (Reference) Figure 6 Even with a larger total time step, the maximum number of cuts cannot be achieved. One possibility for the solution calculated using the algorithm according to (8) to contain errors (differences from the optimal solution) is the use of continuous variables x. i Instead of using binary variables to represent spins s i .

[0112] Therefore, the algorithm in equation (8) can be improved to reduce the error. Specifically, if the variable x i If the absolute value of variable x exceeds 1 due to the update, then variable x i It can be set to sgn(x) i The value of x. That is, if x is updated after the update. i If >1 is true, then variable x i The value can be set to 1. Furthermore, if x is updated after the update... iIf <-1 is true, then variable x i The value of x can be set to -1. Therefore, by using the variable x i It can approximate spin s with higher precision. i For example, updater 50 can be configured to: set the values ​​of elements in the first vector whose values ​​are less than -1 to -1; and set the values ​​of elements in the first vector whose values ​​are greater than +1 to +1. By including this process, the algorithm becomes equivalent to [the algorithm described in x]. i =-1 and x i The physical model of N particles with a wall at position =+1. Figure 7 ).

[0113] Furthermore, if x is updated i If >1 holds true, then the coefficient r can be related to x. i variable y i Multiplication. For example, if the relation -1 < r <= 0 holds for the coefficient r, then the wall described above corresponds to a wall with a reflection coefficient of r. If the coefficient r is equal to 0, the algorithm becomes equivalent to having a reflection coefficient of r that results in a wall located at x. i =-1 and x i The physical model of a wall undergoing a perfectly inelastic collision with a value of +1. Therefore, updater 50 can be configured to update elements of a second vector corresponding to elements of the first vector whose values ​​are less than a first value or whose values ​​are greater than a second value, to the product of the original value of that element and a second coefficient in the second vector. For example, updater 50 can be configured to update elements of a second vector corresponding to elements of the first vector whose values ​​are less than -1 or whose values ​​are greater than 1, to the product of the original value of that element and a second coefficient in the second vector. Here, the second coefficient corresponds to the aforementioned coefficient r.

[0114] Furthermore, if x is updated i If >1 is true, then it is related to variable x. i The corresponding variable y i The value can be set to a pseudo-random number. For example, a random number in the range [-0.1, 0.1] can be used. Therefore, the updater 50 can be configured to set the value of the second vector corresponding to an element whose value is less than the first value, or the value of the second vector corresponding to an element whose value is greater than the second value, to a pseudo-random number.

[0115] If the update process is performed to ensure |x i If |<=1 holds true, then even if the nonlinear term kx is omitted... i 2 (t+Δt), x i The value will not diverge. Therefore, the algorithm according to (9) can be used instead of the algorithm according to (8).

[0116] [Mathematical Formula 7]

[0117]

[0118] In the algorithm according to (9), it is not necessary to use pseudo-random numbers. Similar to the equation in (8), the Hamiltonian equation is also solved according to the algorithm in (9). Therefore, the variable y i Corresponding to momentum. Therefore, by using the Symplectic Euler method, the solution can be computed stably without using small values ​​for the time step Δt. Furthermore, by using the algorithm according to (9), combinatorial optimization problems with third-order or higher-order objective functions can be solved. Figure 8 The diagram shows the algorithm based on (8) as a physical model.

[0119] Figure 9 The results are shown when the G22 of the G-set is solved 1000 times using the algorithm according to (9). Figure 9 In this case, algorithm (9) is used. The value of the second coefficient r is set to 0, and the time step Δt is set to 1. Other calculation conditions are the same as those in the previous case. Figure 6 Similarly. Since the nonlinear term is omitted in the algorithm according to (9), the time step Δt can be set to Figure 8 Twice as much.

[0120] exist Figure 9 The upper part of the graph shows the average number of cuts. Figure 9 The bottom diagram shows the maximum number of cuts. The correspondence between each axis and the definition of the horizontal dashed line Cmax are similar to... Figure 6 The data indicated by solid lines correspond to the results when the algorithm according to (9) is used in the calculation. On the other hand, the data indicated by dashed lines correspond to the results when the algorithm according to (8) is used in the calculation. That is, the dashed lines correspond to... Figure 6 The line in the middle.

[0121] refer to Figure 9 ,and Figure 6 In comparison, both the average number of cuts and the maximum number of cuts are closer to the optimal solution. However, in Figure 9 The results still show a discrepancy between the calculated value and the optimal solution. It can be inferred that the fundamental equation defining the elements of the third vector uses continuous variables x. i Instead of spins i The fact that this leads to error. In particular, if higher-order terms increase, then z... i The variable x in i Multiplication can increase the error. For example, if variables with an absolute value greater than 1 are repeatedly multiplied, the absolute value will be significantly greater than 1.

[0122] Therefore, algorithm (9) can be further improved to reduce the error. For example, as presented in equation (10) below, sgn(x i ) can replace the continuous variable x i And substituting into z i Here, sgn(x) i ) indicates the continuous variable x transformed by the sign function. i The value of . This value corresponds to the spin s i .

[0123] [Mathematical Formula 8]

[0124]

[0125] In equation (10), the coefficients of terms involving first-order tensors can be set to 1. Unlike equations (8) and (9), the algorithm according to (10) does not solve the Hamiltonian equation. Equation (10) can be interpreted as a dynamic system controlled by an external field. If the algorithm according to (10) is used to process HOMOs with higher-order objective functions, errors due to product operations can be prevented because z i The product of internal spins takes -1 or 1 as its value.

[0126] As presented in the algorithm of equation (10) above, the data computed by the computing server may include variables s. i (i=1, 2, ..., N) as the fourth vector (s1, s2, ..., s N The fourth vector can be computed by transforming each element of the first vector using a sign function. Therefore, the multiply-accumulator 51 can be configured to update the value of each element in the third vector using fundamental equations. Here, each fundamental equation is the partial derivative of the energy equation of the Ising model with respect to any variable. Here, the elements of the first vector, or the first vector computed by transforming its elements using a sign function, can be used as variables for each index i in the fundamental equations.

[0127] Figure 10 The results are shown when the G22 of the G-set is solved 1000 times using the algorithm according to (10). Apart from the algorithmic differences, the computational conditions (e.g., time step Δt and coefficients) are similar. Figure 9 .exist Figure 10 The upper part of the graph shows the average number of cuts. Figure 10 The bottom diagram shows the maximum number of cuts. The correspondence between each axis and the definition of the horizontal dashed line Cmax are similar to... Figure 6 and Figure 9The data indicated by solid lines correspond to the results when the algorithm according to (10) is used in the calculation. On the other hand, the data indicated by dashed lines correspond to the results when the algorithm according to (8) is used in the calculation. That is, the dashed lines correspond to... Figure 6 The line in the middle.

[0128] refer to Figure 10 Compared to the algorithm based on (8), this algorithm yields values ​​closer to the optimal solution for both the average number of cuts and the maximum number of cuts. (See reference...) Figure 10 The bottom graph can be obtained by using the algorithm according to (10) to obtain the maximum number of cuts 13359.

[0129] The following equation (11) presents a variation of the simulated bifurcation algorithm using the Symplectic Euler method.

[0130] [Mathematical Formula 9]

[0131]

[0132] In the algorithm according to (11), with external force f i The corresponding terms differ from the examples above. Here, the value z calculated by the fourth equation (11) is transformed using a symbolic function. i This normalizes the value to 1. Therefore, the multiply-accumulator 51 can be configured to base its value on the value z of the fundamental equation transformed by the first function. i The values ​​are calculated to update each element in the third vector. The values ​​of each fundamental equation, z, can be calculated using the elements of the first vector as variables. i For example, a symbolic function can be used as the first function. However, as mentioned later, other functions can also be used as the first function.

[0133] In equation (11), the function g(t) is used instead of the coefficient c. Typically, the elements z of the third vector... i The contribution to the calculation results varies depending on the problem. However, since the elements of the third vector in equation (11) are normalized to 1, it is not necessary to determine the value of the coefficient c for each problem. The following equation (12) can be used as the function g(t).

[0134] [Mathematical Formula 10]

[0135]

[0136] The value of the function in equation (12) increases monotonically with the number of updates, and then decreases monotonically. However, the aforementioned equation (12) is merely an example. Therefore, other functions with the first coefficient p(t) as a parameter can be used as the function g(t). Thus, the multiply accumulator 51 can be configured to update each element in the third vector by multiplying it with a second function having the first coefficient p as a parameter.

[0137] Figure 11 The results are shown when the algorithm of (11) is used to solve for G22 of the G-set 1000 times. Apart from the differences in the algorithm, the computational conditions (e.g., time step Δt and coefficients) are similar. Figure 9 .exist Figure 11 The upper part of the graph shows the average number of cuts. Figure 11 The bottom diagram shows the maximum number of cuts. The correspondence between each axis and the definition of the horizontal dashed line Cmax are similar to... Figure 6 and Figure 9 The data indicated by solid lines correspond to the results when the algorithm according to (11) is used in the calculation. On the other hand, the data indicated by dashed lines correspond to the results when the algorithm according to (8) is used in the calculation. That is, the dashed lines correspond to... Figure 6 The line in the middle.

[0138] refer to Figure 11 Compared to the algorithm based on (8), this algorithm yields values ​​closer to the optimal solution for both the average number of cuts and the maximum number of cuts. (Refer to...) Figure 11 The bottom graph, by using the algorithm according to (11), can obtain a maximum value of 13358 that is close to the maximum number of cuts of 13359.

[0139] In the algorithms (9) to (11), the fundamental equation (z) can be calculated by using constant coefficients (e.g., α=1). i The coefficient α in the term of the equation (i) that includes a first-order tensor. Furthermore, in the algorithms (9) to (11), coefficients that monotonically decrease or increase depending on the number of updates can be used as coefficients α in the term of the basic equation (i) that includes a first-order tensor. In this case, the term of the basic equation that includes a first-order tensor monotonically decreases or increases depending on the number of updates.

[0140] The algorithms in (9) and (10) include the coefficient c. To set the value of coefficient c to be close to J... （2） The inverse of the largest eigenvalue of a matrix needs to be calculated or estimated. （2）The largest eigenvalue of the matrix. The computation of the largest eigenvalue is very expensive. Furthermore, the estimation of the largest eigenvalue is not guaranteed to be accurate. Therefore, the coefficient c can be replaced by a function that takes different values ​​based on the number of updates, as presented in equation (12) above. Moreover, instead of the coefficient c, a function based on the first vector (x1, x2, ..., x...) can be used. N ) and the third vector (z1, z2, ..., z N The approximate value c1 calculated is shown in the following equation (13).

[0141] [Mathematical Formula 11]

[0142]

[0143] Referring to equation (13), both the numerator and denominator are norms of the vector. As in equation (13), the square root of the sum of the squares of each element in the vector (which is the L2 norm) can be used as the norm of the vector. However, a norm defined according to other rules can also be used instead, such as the sum of the absolute values ​​of the elements in the vector (L1 norm).

[0144] Therefore, updater 50 can be configured to update the elements of the second vector by: calculating the third coefficient c1 by dividing the first vector norm or the fourth vector norm by the third vector norm; adding a weighted product of the first coefficient p(t+Δt) and the corresponding elements of the first vector; and adding the elements of the third vector weighted by the third coefficient c1.

[0145] Alternatively, instead of the coefficient c, an approximation c'1 can be used, as shown in the following equation (14), defined by using an inner product.

[0146] [Mathematical Formula 12]

[0147]

[0148] Therefore, updater 50 can be configured to update the elements of the second vector by: calculating the third coefficient c'1, which is the absolute value of the first inner product between the first vectors divided by the second inner product between the first vector or the fourth vector and the third vector; adding the weighted product of the first coefficient p(t+Δt) and the corresponding elements of the first vector; and adding the elements of the third vector weighted by the third coefficient c'1.

[0149] Based on the first vector (x1, x2, ..., x) at each time point N ) and the third vector (z1, z2, ..., z NThe approximate values ​​c1 and c'1 are calculated using the values ​​of (x1, x2, ..., x). Therefore, the values ​​c1 and c'1 are coefficients of dynamic control, not constants like the coefficient c. The first vector (x1, x2, ..., x...) calculated during the variable update process can be used. N ) and the third vector (z1, z2, ..., z N The value of ). Therefore, using approximations c1 or c'1 does not significantly increase computational cost. In the Ising problem without a local magnetic field, if the first vector (x1, x2, ..., x) N ) is with J （2） If the eigenvectors corresponding to the largest eigenvalue are obtained, then the approximate values ​​c1 and c'1 become greater than the inverse of the largest eigenvalue. This accelerates the convergence of the solution.

[0150] Figure 12 The results are shown when the G22 of the G-set is solved 1,000 times using the algorithm according to (9), where the coefficient c is replaced by the approximation c1. Figure 13 The results are shown when the G22 of the G-set is solved 1,000 times using the algorithm according to (9), where the coefficient c is replaced by the approximation c′1. Figure 14 The results are shown when the G22 of the G-set is solved 1,000 times using the algorithm according to (10), where the coefficient c is replaced by the approximation c1. Figure 15 The results are shown when the G22 of the G-set is solved 1,000 times using the algorithm according to (10), where the coefficient c is replaced by the approximation c′1.

[0151] exist Figure 12 to Figure 15 The upper part of the graph shows the average number of cuts. Figure 12 to Figure 15 In the figure, the maximum number of cuts is shown at the bottom. The correspondence of each axis and the definition of the horizontal dashed line Cmax are similar to those in each of the above figures. The data indicated by the dashed line corresponds to the results when the algorithm according to (8) is used in the calculation. That is, the dashed line corresponds to Figure 6 The line in the middle.

[0152] refer to Figure 12 to Figure 15 Compared with the algorithm based on (8), both the average number of cuts and the maximum number of cuts are closer to the optimal solution. In particular, for the algorithm based on (10), the maximum number of cuts of 13359 is calculated using approximate values ​​c1 or c'1.

[0153] For the algorithm according to (9) and the algorithm according to (10), the approximate values ​​c1 and c'1 can be replaced by the approximate values ​​c2 or c'2 presented in the following equation (15).

[0154] [Mathematical Formula 13]

[0155]

[0156] Therefore, updater 50 can be configured to update the elements of the second vector by: calculating the third coefficient c2, which is equal to the norm of the fourth vector divided by the norm of the third vector; adding a weighted product of the first coefficient p(t+Δt) and the corresponding elements of the first vector; and adding the elements of the third vector weighted by the third coefficient c2. Here, the fourth vector is a vector calculated by transforming each element of the first vector using a sign function.

[0157] Furthermore, updater 50 can be configured to update the elements of the second vector by: calculating the third coefficient c'2, which is equal to the first inner product between the fourth vectors divided by the second inner product between the fourth and third vectors; adding the weighted product of the first coefficient p(t+Δt) and the corresponding elements of the first vector; and adding the elements of the third vector weighted by the third coefficient c2.

[0158] Regarding equation (15), the third vector (z1, z2, ..., z) calculated during the variable update process can be used. N Therefore, using approximate variables c2 and c′2 does not significantly increase computational cost.

[0159] Figure 16 The results are shown when the G22 of the G-set is solved 1,000 times using the algorithm according to (10), where the coefficient c is replaced by the approximation c2. Figure 17 The results are shown when the G22 of the G-set is solved 1,000 times using the algorithm according to (10), where the coefficient c is replaced by the approximation c′2.

[0160] exist Figure 16 and Figure 17 The upper part of the graph shows the average number of cuts. Figure 16 and Figure 17 In the figure, the maximum number of cuts is shown at the bottom. The correspondence of each axis and the definition of the horizontal dashed line Cmax are similar to those in each of the above figures. The data indicated by the dashed line corresponds to the results when the algorithm according to (8) is used in the calculation. That is, the dashed line corresponds to Figure 6 The line in the middle.

[0161] refer to Figure 16 and Figure 17 Compared with the algorithm based on (8), both the average number of cuts and the maximum number of cuts are closer to the optimal solution. In particular, for the algorithm based on (10), the maximum number of cuts of 13359 is calculated using approximate values ​​c2 or c'2.

[0162] If approximations c1, c'1, c2, and c'2 are computed using vector values ​​during algorithm execution, these values ​​can fluctuate rapidly depending on the time sequence. To reduce the fluctuation of approximations c1, c'1, c2, and c'2, values ​​obtained by transforming c1, c'1, c2, and c'2 according to predetermined rules can be used. For example, the rules presented in equation (16) below can be used for the transformation.

[0163] [Mathematical Formula 14]

[0164]

[0165] Here, a value less than 1 can be set as γ. In equation (16), c(t+Δt) can be substituted with the approximate value calculated according to the aforementioned equations (13) to (15). In equation (16), c(t+Δt) can be interpreted as the sampled value of the signal with a fluctuating component at each calculation timing. Then, d(t+Δt) can be interpreted as the value of c(t+Δt) filtered by a low-pass filter with a certain bandwidth.

[0166] Therefore, updater 50 can be configured to update the elements of the second vector by replacing the third coefficient with a fourth coefficient, wherein the fourth coefficient is the value of the third coefficient (approximate values ​​c1, c'1, c2, and c'2) transformed by a low-pass filter.

[0167] Figure 18 The results are shown when the G22 of the G-set is solved 1,000 times using the algorithm according to (9), where the coefficient c is replaced by the approximation c1 (third coefficient) transformed according to the rule of equation (16). Figure 19 The results are shown when the G22 of the G-set is solved 1,000 times using the algorithm according to (10), where the coefficient c is replaced by an approximation c1 (third coefficient) transformed according to the rule of equation (16). Figure 20 The results are shown when G22 of the G-set is solved 1,000 times using the algorithm according to (10), where the coefficient c is replaced by an approximation c2 (third coefficient) transformed according to the rule of equation (16). Figure 18 to Figure 20 In this case, the calculation is performed by setting 0 as the initial value of d(t) and using γ = 0.1.

[0168] exist Figure 18 to Figure 20 The upper part of the graph shows the average number of cuts. Figure 16 and Figure 17 In the figure, the lower part shows the maximum number of cuts. The correspondence of each axis and the definition of the horizontal dashed line Cmax are similar to those in each of the above figures. The data indicated by the dashed line corresponds to the results when the algorithm according to (8) is used in the calculation. That is, the dashed line corresponds to Figure 6 The line in the middle.

[0169] Reference Figure 18 and Figure 20 compared with the algorithm according to (8), closer to the optimal solution values are obtained for both the average number of cuts and the maximum number of cuts. In particular, in the examples of Figure 19 and Figure 20 , the maximum number of cuts 13359 was obtained in the calculation.

[0170] In the above examples, the simulated bifurcation algorithm was used to calculate the solution of the Ising model. However, the combinatorial optimization problems that can be solved by using the simulated bifurcation algorithm are not limited to the Ising problem. General combinatorial optimization problems with binary variables can be calculated by using the simulated bifurcation algorithm. For example, each of the above algorithms can be used to solve a combinatorial optimization problem in which the variables of the objective function are binary variables that take on a (first value) or b (second value) greater than a.

[0171] For example, if during the execution of the algorithm according to (9), after an update, the value of variable x i becomes less than "a", then the value of variable x i can be set to "a". Further, if after an update the value of variable x i becomes greater than b, then the value of variable x i can be set to b. Additionally, if after a certain number of updates the solution of the objective function is calculated, a function f(x i ) with a range of a or b can be used instead of the sign function. The value of the function f(x i ) can be determined by comparing the value of variable x i with a threshold v (a < v < b). For example, if x i < v, then f(x i ) = a holds. Further, if v < x i , then f(x i ) = b holds. For example, if x i = v, then f(x i ) = a or f(x i ) = b holds. Here, for example, (a + b) / 2 can be used as the threshold v. As the above function f(x i ), a first function that converts the elements of a first vector into a fourth vector can be used.

[0172] Above, an example of the simulated bifurcation algorithm implemented by the Symplectic Euler method and examples when calculating combinatorial optimization problems by each algorithm were described. Below, an example of the actual implementation of the algorithm is explained.

[0173] (Example of PC cluster implementation)

[0174] First, an example of a PC cluster implementation of the above algorithm is given. A PC cluster is a system with multiple computers connected together, enabling computational performance that is impossible to achieve using a single computer. For example, Figure 1 The information processing system 100 includes multiple computing servers and processors. Therefore, the information processing system 100 can be used as a PC cluster. For example, in a PC cluster, MPI (Message Passing Interface) can be used to implement parallel computing in a configuration where memory is distributed across multiple computing servers, as is the case with the information processing system 100. For example, by using MPI, a control program 14E for managing server 1, a computing program 34B for each computing server, and a control program 34C for each computing server can be implemented.

[0175] If the number of processors used in a PC cluster is Q, then each processor can compute the first vector (x1, x2, ..., x...). N L variables x in ) i Similarly, each processor can compute the second vector (y1, y2, ..., y...). N L variables y in ) i Therefore, processor #j (j=1, 2, ..., Q) computes the variable {x}. m |m=(j-1)L+1, (j-1)L+2,...,jL} and {y m |m=(j-1)L+1, (j-1)L+2,...,jL}。 Furthermore, the {y} calculated by processor #j is presented in the following equation (17). m The required tensor J for |m=(j-1)L+1,(j-1)L+2,...,jL} is (n) It can be stored in the processor's accessible memory space. Examples of such memory space include registers, caches, and RAM.

[0176] [Mathematical Formula 15]

[0177]

[0178] This section describes the scenario where each processor computes a uniform number of variables in both the first and second vectors. However, the number of variables computed by each processor in the first and second vectors can differ. For example, if the processors implemented in a computing server have performance differences, the number of variables each processor should compute can be determined based on the processor's performance.

[0179] Therefore, the information processing device (e.g., a computing server) can have multiple processors. At least one of the multiple processors can be used as updater 50. Therefore, updater 50 can include multiple processors. At least one of the multiple processors can be configured to compute some elements of the first vector and some elements of the second vector.

[0180] To update variable y i The value requires the first vector (x1, x2, ..., x...). N ) or the fourth vector (s1, s2, ..., s N The values ​​of all elements in the fourth vector (s1, s2, ..., s). Here, the values ​​of all elements in the fourth vector (s1, s2, ..., s) are... N A vector is obtained by converting each element of a first vector into a binary variable. For example, the symbolic function sgn() can be used for conversion to binary variables. Here, the Allgather function can be used to convert the first vector (x1, x2, ..., x...) into binary variables. N ) and the fourth vector (s1, s2, ..., s N The values ​​of all elements in the first vector (x1, x2, ..., x...) are shared among Q processors. N ) and the fourth vector (s1, s2, ..., s N The values ​​of the first vector (y1, y2, ..., y3) need to be shared between processors, but the values ​​of the second vector (y1, y2, ..., y3) are not shared between processors. N ) and tensor J (n) Data does not need to be shared between processors. For example, data can be shared between processors by using inter-processor communication or by allocating data to shared memory.

[0181] Processor #j calculates variable {z m The values ​​of |m=(j-1)L+1,(j-1)L+s,...,jL} are then used by the processor #j based on the calculated {z m Update the variable {y} with the values ​​of |m=(j-1)L+1,(j-1)L+s,...,jL}. m |m=(j-1)L+1, (j-1)L+s,...,jL}.

[0182] As presented by the equations above, the vector (z1, z2, ..., z...) N The calculation includes tensor J. (n) With vector (x1, x2, ..., x N The product or tensor J (n) With vector (s1, s2, ..., s NThe product of (Q, N, and L) is the product of (Q, N, and L). Therefore, the product sum operation is necessary in simulated bifurcation algorithms. The product sum operation is the most computationally expensive operation within the algorithm. Therefore, the product sum operation can become a bottleneck for improving computation speed. In PC cluster implementations, the product sum operation can be distributed across Q=N / L processors, enabling parallel execution of the product sum operation and reducing computation time.

[0183] Therefore, the information processing device (e.g., a computing server) can have multiple processors. At least one of the multiple processors can be used as a multiply-accumulate 51. Thus, the multiply-accumulate 51 can include multiple processors. At least one of the multiple processors can be configured to update some elements in the third vector. The updater 50 can also include multiple processors. Each of the multiple processors in the updater 50 can be configured to update some elements in the first vector and some elements in the second vector.

[0184] Figure 21 This is a schematic diagram illustrating an example of a multiprocessor configuration. Figure 21 The multiple computing nodes in the system correspond to multiple computing servers in the information processing system 100. For example, Figure 21 The high-speed link in the diagram corresponds to the interconnection between computing servers formed by cables 4a to 4c and switch 5. Figure 21 The shared memory in the diagram corresponds to shared memory 32. Figure 21 The processors in the text correspond to processors 33A to 33D in each computing server. Figure 21 The diagram shows multiple compute nodes. However, a system with a single compute node can be used instead.

[0185] Figure 21 This shows the data allocated to each component and the data transferred between components. Within each processor, the variable x is calculated. i 、(s i ), y i and z i The value of x. Furthermore, the variable x i or s i Transferred between the processor and shared memory. From the first vector (x1, x2, ..., x...). N ) and the second vector (y1, y2, ..., y N The tensors J of the two (n) A portion of the total L variables are stored in the shared memory of each computing node. If the algorithm according to (10) is executed, then instead of the first vector (x1, x2, ..., x...), the first vector (x1, x2, ..., x...) is... N ), the fourth vector (s1, s2, ..., s NThe first vector (x1, x2, ..., x...) can be stored in the shared memory of each computing node. N The variables are transmitted via high-speed links connecting the computing nodes. This is because, when using the Allgather function, the first vector (x1, x2, ..., x...) is required. N The values ​​of all elements in the array are used to update the variable y in each processor. i and z i In order to update the variable z according to the algorithm in (10) i The fourth vector (s1, s2, ..., s N The values ​​of all elements in the vector (s1, s2, ..., s) need to be accessible from each processor. Therefore, the fourth vector (s1, s2, ..., s) can be transmitted over a high-speed link. N ).

[0186] However, Figure 21 The data allocation and transfer presented are merely examples. For instance, multiple processors are executing the variable {z}. m The calculation of |m=(j-1)L+1,(j-1)L+2,...,jL} includes parallel product sum operations, with variable z i The values ​​can be shared between processors using shared memory or transfers between computing nodes. Thus, the vector (z1, z2, ..., z...) N The values ​​of elements in a variable y can be shared, thus implementing the variable y. i The computation is therefore unrestricted in PC cluster implementations, including data allocation, data transfer methods, and parallelization methods.

[0187] Information processing equipment (e.g., a computing server) may have shared memory accessible from multiple processors. The updater 50 can then save the elements of the updated first vector to the shared memory. Furthermore, the updater 50 can save the elements of the updated fourth vector to the shared memory by transforming each element of the updated first vector.

[0188] The following describes the results when the above algorithm is executed on a PC cluster. Figure 22 This is a graph showing the results when solving the fully connected N=3600 Ising problem (without local magnetic fields) using a PC cluster. Figure 22 In the fully connected Ising problem, uniformly distributed random numbers in the range [-1, 1] are used to determine the values ​​of the elements in the coupling coefficient matrix J. Furthermore, the total time step is set to 10,000. Figure 22 The upper bar chart shows the energy E when the aforementioned algorithm is used to solve the fully connected Ising problem 10 times. Ising The average value. On the other hand, in Figure 22The bar chart at the bottom shows the computation time in seconds when the aforementioned algorithm is used to solve the fully connected Ising problem 10 times.

[0189] For in Figure 22 The upper part and in Figure 22 The bar chart at the bottom, from left to right, presents ten results for each different condition. The results are:

[0190] (i) The result when using the algorithm according to (8);

[0191] (ii) Results when using the algorithm according to (9);

[0192] (iii) Results when using the algorithm according to (10);

[0193] (iv) Results when using the algorithm according to (11);

[0194] (v) The result when the approximation c1 is used instead of the coefficient c in the algorithm according to (9);

[0195] (vi) The result when the approximation c1 is used instead of the coefficient c in the algorithm according to (10);

[0196] (vii) The result when the approximation c2 is used instead of the coefficient c in the algorithm according to (10);

[0197] (viii) The result when the value obtained by transforming the approximation c1 according to rule (16) (the fourth coefficient) is used instead of the coefficient c in the algorithm according to (9);

[0198] (ix) The result when the value obtained by transforming the approximation c1 according to rule (16) (the fourth coefficient) is used instead of the coefficient c in the algorithm according to (10); and

[0199] (x) The result when the value obtained by transforming the approximation c2 according to rule (16) (the fourth coefficient) is used instead of the coefficient c in the algorithm according to (10).

[0200] In addition, Figure 22 The upper part and in Figure 22The bottom bar chart shows the results from left to right when the number of processors Q is 1, 36, and 72. If the number of processors Q is 1 or 36, the number of compute nodes in the PC cluster is 1. If the number of processors Q is 72, the number of compute nodes in the PC cluster is 2. For the cases using the algorithm according to (8), the cases using the algorithm according to (9), and the cases using the algorithm according to (10), the constant value 0.5D(3 / N)^(1 / 2) is used for the coefficient c. In addition, for the cases where the approximations c1 and c2 are transformed according to the rule of (16), the value of γ is set to 0.1.

[0201] refer to Figure 22 The upper bar graph, for results (ii) to (x), the energy E Ising The average value is lower than the result of (i). Therefore, the conditions corresponding to (ii) to (x) can produce solutions closer to the optimal solution. Additionally, refer to... Figure 22 The bar chart at the bottom confirms that parallel computing using a multi-processor configuration can significantly reduce computation time.

[0202] (GPU implementation example)

[0203] The computation of the aforementioned algorithm can be performed using a GPU (Graphics Processing Unit). Figure 23 This is a schematic diagram illustrating an example configuration that uses a GPU. Figure 23 This includes multiple GPUs connected via high-speed links. Each GPU comprises multiple cores that can access data stored in shared memory. Figure 23 In the configuration example, multiple GPUs are connected via high-speed links to form a GPU cluster. For example, if GPUs are installed on... Figure 1 For each computing server, the high-speed link corresponds to the interconnection formed by cables 4a to 4c and switch 5. Figure 23 The configuration example uses multiple GPUs. However, computations can be performed in parallel even using a single GPU. Figure 23 Each GPU in the system can perform operations with Figure 21 Each computing node in the system corresponds to a computation. Therefore, the processor of an information processing device (computing server) can be a core of a graphics processing unit (GPU).

[0204] In a GPU, the variable x i y i and tensor J (n) It can be defined as a device variable. The GPU can compute the tensor J in parallel using matrix-vector multiplication functions. (n) With the first vector (x1, x2, ..., x N The product or tensor J (n)With the fourth vector (s1, s2, ..., s N The product of ) is used to update the variable y. i The product between a tensor and a vector can be calculated by performing a product operation between matrices and vectors. Besides the product sum operation, the first vector (x1, x2, ..., x...)... N ) and the second vector (y1, y2, ..., y N The computation can be performed by each thread. This allows the computation process to be parallelized.

[0205] Figure 24 This is a graph showing the results when solving the fully connected N=3600 Ising problem using a GPU. Figure 24 The upper bar chart shows the average energy E when the fully connected Ising problem is solved ten times using each algorithm. Ising On the other hand, in Figure 24 The upper bar chart shows the average computation time in seconds when each algorithm is used to solve the fully connected Ising problem ten times.

[0206] exist Figure 24 The upper bar chart and in Figure 24 The bottom bar Figure two Each case includes four scenarios: the case using the algorithm according to (8), the case using the algorithm according to (9), the case using the algorithm according to (10), and the case using the algorithm according to (11). For the cases using the algorithm according to (8), the case using the algorithm according to (9), and the case using the algorithm according to (10), the constant 0.5D(3 / N)^(1 / 2) is used as the coefficient c. The total time step for each case is set to 10,000. Furthermore, for each algorithm, the left side corresponds to the result obtained using a PC cluster with a single compute node. For each algorithm, the right side corresponds to the result obtained using one GPU.

[0207] refer to Figure 24 The upper bar chart, compared with the case using the algorithm according to (8), shows that when using the algorithms (9) to (11), the energy E Ising The average value decreases. If the energy E Ising A lower average value increases the likelihood of calculating a solution close to the optimal one. (Refer to...) Figure 24 The bottom bar chart shows that parallel computing via GPUs reduces computation time compared to using a PC cluster with a single compute node. This is because GPUs offer higher levels of parallelism compared to general-purpose CPUs.

[0208] (Example of the processing flow)

[0209] Figure 25 and Figure 26 This includes a flowchart illustrating an example process performed by the information processing system 100. See below for reference. Figure 25 and Figure 26 Explain the process.

[0210] First, updater 50 sets the values ​​of constant coefficients and initializes the first vector, the second vector, and the first coefficient p (step S101). In step S101, the values ​​of constant coefficient D and Δt are set. If coefficient c is a constant, its value can also be set. For example, during the initialization of the first and second vectors, the value of each element can be set to a pseudo-random number in the range [-0.1, +0.1]. For example, 0 can be used as the initial value of the first coefficient p. Additionally, if the coefficient α used during the calculation of the elements of the third vector is a constant, coefficient α can be initialized in step S101. For example, 0 can be used as the initial value of coefficient α. Furthermore, in step S101, tensor J can be set... (n) The values ​​of the elements in the tensor J. When the combinatorial optimization problem is transformed into a format that can be processed by each computation server, the tensor J can be obtained. (n) The values ​​of the elements in the array are given. The algorithm for increasing the values ​​of coefficients p and α based on the number of updates was described above. However, instead, an algorithm for decreasing the values ​​of coefficients p and α based on the number of updates can be used.

[0211] Next, updater 50 updates the elements of the first vector by adding the weighted values ​​of the corresponding elements in the second vector to the elements in the first vector (step S102). For example, in step S102, this can be achieved by using x as presented in (9) to (11) above. i The equation is used to update the values ​​of the elements in the first vector.

[0212] Then, updater 50 sets the values ​​of elements in the first vector whose values ​​are less than -1 to -1 (step S103). Furthermore, updater 50 sets the values ​​of elements in the first vector whose values ​​are greater than +1 to +1 (step S104). Steps S103 and S104 can be executed simultaneously. Alternatively, step S103 can be executed after step S104.

[0213] Although not in Figure 25 As shown, in steps S103 and / or S104, updater 50 can update the elements of the second vector corresponding to the elements of the first vector whose absolute value is greater than 1 by multiplying a second coefficient r greater than -1 and equal to or less than 0 by the original value of the second vector. Furthermore, in steps S103 and / or S104, updater 50 can set the values ​​of the elements of the second vector corresponding to the elements of the first vector whose absolute value is greater than 1 to pseudo-random numbers with an absolute value less than 1.

[0214] Next, the multiplication accumulator 51 updates the value of each element in the third vector (step S105). For example, this can be achieved by using z as presented in (9) to (11) above. i The elements of the third vector are calculated using the equation (basic equation). The value of each element in the third vector can be updated according to the algorithm according to (10). In the algorithm according to (10), the value of the element in the first vector transformed by the first function (e.g., the sign function) can be used as z. i The variables in the equation. In this case, in step S105, by using the fourth vector (s1, s2, ..., s... N The fourth vector (s1, s2, ..., s) is used to calculate the values ​​of the elements in the third vector. N This can be obtained by converting the first vector updated in step S102 into a binary variable.

[0215] Then, updater 50 increases the value of the first coefficient p (step S106). For example, in step S106, a constant value can be added to the first coefficient p. Additionally, a non-constant variable can be added to the first coefficient p. Thus, the value of the first coefficient p increases monotonically with each update. If coefficient α is not a constant coefficient, a constant value can be added to coefficient α in step S106. Furthermore, in step S106, the value of the third coefficient can be updated according to the methods in (13) to (15). In step S106, the value of the fourth coefficient, obtained by transforming the third coefficient according to equation (16), can be calculated.

[0216] Next, updater 50 updates the value of the second vector by: (1) adding a weighted product of the first coefficient p and the corresponding element values ​​in the first vector; and (2) adding the weighted values ​​of the corresponding elements in the third vector to the values ​​of the elements in the second vector (step S107). For example, the values ​​of the elements in the second vector can be obtained by using y as presented in (9) to (11) above. i The equation is used to update the third vector. During the update of the second vector, at least the constant coefficient c, the third coefficient, or the fourth coefficient can be used to calculate the weighted values ​​of the corresponding elements in the third vector.

[0217] Then, updater 50 determines whether the number of updates for the first to third vectors, or the value of the first coefficient p, is greater than a threshold (step S108). The threshold value used in the determination in step S108 is not limited. The executed process branches depending on the result of the determination in step S108. If the result of the determination in step S108 is affirmative ("Yes" in step S108), the process proceeds to step S109. In step S109, updater 50 calculates the spin value by converting the values ​​of positive elements in the first vector to +1 and the values ​​of negative elements in the first vector x to -1. The process in step S109 can be executed by an information processing device other than a computing server, such as a management server. The first vector can then be transferred from the computing server to the management server. Furthermore, if the result of the determination in step S108 is negative ("No" in step S108), step S102 and subsequent processes are executed again.

[0218] exist Figure 25 and Figure 26 The flowchart presented is merely an example of a process that can be executed by the information processing system 100. The order in which steps S102 to S107 are executed may differ from that described above. For example, in the electronic circuit described below, the process of steps S102 to S107 is performed in accordance with... Figure 25 and Figure 26 The flowcharts presented in the document are executed in different sequences. Furthermore, at least any one of steps S101 to S109 can be executed in parallel by multiple processors, multiple information processing devices (computers), or multiple electronic circuits. The information processing system, information processing device (computer), or electronic circuit can be implemented such that in the third vector (variable z)... i During the update process of the elements of ), the first vector (x1, x2, ..., x) after the latest update N ) or the fourth vector (s1, s2, ..., s N All elements of ) can be accessed.

[0219] The spin values ​​in the computed Ising model can be displayed on a display device. Furthermore, the converter service 12 in management server 1 can convert combinations of spin values ​​into solutions to a combinatorial optimization problem. In this case, the management service 11 of management server 1 can present the solution to the combinatorial optimization problem to the display of the client device 6 used by the user.

[0220] A simulated bifurcation algorithm can be implemented using a program. In this case, a program can be implemented that enables a computer to perform calculations based on fundamental equations. Here, each fundamental equation is a partial derivative of an equation with respect to any variable. The corresponding program includes: steps for updating each element in a third vector based on fundamental equations having elements of a first or fourth vector as variables; steps for updating elements of a first vector by adding corresponding elements of a second vector or weighted values ​​of a second vector to elements of a first vector; steps for setting elements of a first vector whose values ​​are less than a first value to first values; steps for setting elements of a first vector whose values ​​are greater than a second value to second values; and steps for updating elements of a second vector by (i) adding a weighted product of a first coefficient (which monotonically increases or decreases based on the number of updates) and corresponding elements of a first vector, and (ii) adding weighted values ​​of corresponding elements of a third vector. Here, the fourth vector can be calculated by transforming the first vector using a first equation. The first equation transforms the elements of the first vector into a first value or a second value greater than a first value. For example, this program is stored in storage device 34 of a computing server. The computing server can provide the functions of the aforementioned information processing device by executing this program.

[0221] Additionally, a computer can execute a simulated bifurcation algorithm based on the following information processing method. This information processing method allows the computer to perform calculations based on fundamental equations, each of which is a partial derivative of an equation with respect to any variable. The information processing method includes: steps for updating each element in a third vector based on fundamental equations that use elements of a first or fourth vector as variables; steps for updating elements of a first vector by adding corresponding elements of a second vector or a weighted value of a second vector to the elements of a first vector; steps for setting elements of a first vector whose values ​​are less than a first value to a first value; steps for setting elements of a first vector whose values ​​are greater than a second value to a second value; and steps for updating elements of a second vector by (i) adding a first coefficient (which monotonically increases or decreases based on the number of updates) and a weighted product of corresponding elements of the first vector and (ii) adding a weighted value of corresponding elements of the third vector. Here, the fourth vector can be calculated by transforming the first vector using a first equation. The first equation transforms the elements of the first vector into a first value or a second value greater than the first value. The aforementioned computing server can be used as an information processing device.

[0222] (An example of the implementation of an electronic circuit)

[0223] As described above, the use of software enables the execution of simulated forking algorithms on information processing devices. However, at least a portion of the aforementioned algorithms can be implemented on electronic circuits, thereby significantly improving processing speed. Below are examples illustrating the implementation of simulated forking algorithms on electronic circuits. Examples of electronic circuits include FPGAs (Field-Programmable Gate Arrays). However, other types of electronic circuits, such as ASICs (Application-Specific Integrated Circuits), can also be used.

[0224] Figure 27 This is a diagram illustrating an example of an algorithm implemented in an electronic circuit. Figure 27 The pseudocode corresponding to the algorithm according to (10) above is shown below. The implementation of the algorithm according to (10) in an electronic circuit is described below. However, other algorithms described above, such as (9) and (11), can also be implemented in electronic circuits. Figure 27 (a) Presents the data used to update each variable x i y i and s i The process (i = 1, 2, ..., N) updates the variables from their values ​​at time "t" to their values ​​at time "t + Δt". For each of the N variables indicated by index "i", the update process is executed N times (loops 37 and 38). Figure 27 In (a), loop 37 calls the function JS(). The function JS() is... Figure 27 Defined in (b). The function JS() has rows i and vectors (s1, s2, ..., s) in matrix J. N () is used as a parameter. Furthermore, in Figure 27 In (a), loop 38 calls the function TE(). The function TE() is... Figure 27 Defined in (c). Furthermore, calls from the function TE() are in Figure 27 The functions FX() and FY() defined in (d). If electronic circuitry configured for parallel execution is used in the implementation of the algorithm, at least a portion of the process described as a loop (“for” statement) can be changed to a parallel execution process.

[0225] This can be explained in Figure 27 The algorithm described herein calculates the state of a dynamical system comprising a wall and multiple particles i (i = 1, 2, ..., N). Below, the process executed at each step of the algorithm is explained with reference to the dynamics of particle i. Figure 27 The algorithm consists of a part that computes the matrix-vector product (called the MM part) and a part that computes the time evolution (called the TE part).

[0226] The MM part calculates the momentum y caused by the interactions between other particles for each particle i. i The increment Δyi The TE part updates the position x for each particle i. i and momentum y i The process used to update the position and momentum of a particle corresponds to the calculation of the time evolution with respect to a time step Δt.

[0227] The TE part is achieved by adding Δy i And including the outdoor h i The effect of calculating momentum y i Then, depending on the particle's position x... i The amount δy i =FX(x i ) is added to momentum y i Next, depending on the particle's momentum y... i The quantity δx i =FY(y i ) is added to position x i Then, it is determined whether the particle collides with a completely inelastic wall at x = -1.0 and x = +1.0. If a collision occurs, an equivalent process of positioning the particle to either wall is performed. This process can be implemented using electronic circuitry. Figure 32 This is implemented using comparator comp1 and multiplexer MUX1. Furthermore, if the particle collides with a completely inelastic wall at x = -1.0 and x = +1.0, the momentum y... i It is set to 0.0. This process can be achieved by using electronic circuits. Figure 32 This is achieved using comparator comp2 and multiplexer MUX2. The binarization process is performed in the final part of the TE section. This process can be implemented using... Figure 32 It is implemented using comparator comp3 and multiplexer MUX3.

[0228] refer to Figure 27 Based on the algorithm, it can be deduced that if the variables (e.g., position and momentum) corresponding to N particles can be computed in parallel, the overall processing speed can be accelerated. However, during the implementation of the simulated bifurcation algorithm, the difference between the part where the computation of variables can be performed independently of other variables (in other words, the part that is easy to parallelize) and the part where there is a dependency on the variables of other particles (in other words, the part where parallelization is constrained) should be considered.

[0229] Here, we will discuss Figure 27 The computational complexity of the algorithm is as follows: The computational complexity of the TE part is O(N). On the other hand, the computational complexity of the MM part is O(N). 2The TE part includes some sequential processes. However, the TE part can be computed independently for each particle. Therefore, the process for the TE part can be accelerated by using pipelined or time-parallelized methods. The process for the MM part can be accelerated by using parallel processing elements (PEs) and a storage subsystem that provides the necessary data.

[0230] Below, we illustrate a configuration for accelerating computation by using multiple TE pipelines. By using multiple TE pipelines, the processes in the MM and TE parts can overlap in the time domain. (Reference) Figure 27 The algorithm requires executing the MM part of the process and calculating Δy for all indices i (i = 1, 2, ..., N). i To update the fourth vector (s1, s2, ..., s N ).therefore, Figure 27 The fourth vector (s1, s2, ..., s) in the algorithm N The data dependency is a barrier to the overlapping MM and TE parts of the process in the time domain. To solve this data dependency problem, the fourth vector (s1, s2, ..., s...) is used. N The values ​​of the elements in the array can be stored in a memory with a double-buffered structure. In the following text, the memory with the double-buffered structure will be referred to as the memory Smem.

[0231] Figure 28 This is a block diagram illustrating an example configuration of an electronic circuit. For execution... Figure 27 The loop processing in the algorithm, Figure 28 The electronic circuit 200 is configured to allow data to circulate within each component. In the electronic circuit 200, N particles are divided into Pb groups. Then, variables are calculated for each of the Pb groups, such as... Figure 29 As presented herein, electronic circuit 200 has at least Pb circuit blocks MMTE (MMTE1 to MMTE2). Pb The circuit block MMTE performs the MM partial process and the TE partial process for each of the Nb (Nb=N / Pb) particles belonging to each group. Furthermore, each circuit block MMTE is connected to the memory Smem.

[0232] The memory Smem provides access from each circuit block MMTE1 to MMTE PbGlobally accessible storage space. The memory Smem can include volatile memory, non-volatile memory, or a combination thereof. However, the type of memory used as the memory Smem is not limited. Each circuit block MMTE can be configured to concurrently or simultaneously write data to and read data from the memory Smem. The memory Smem comprises Pb regions (S... B1 S B2 S BPb Furthermore, each region in the memory Smem has a dual-buffer structure comprising an even-numbered buffer and an odd-numbered buffer. The even-numbered and odd-numbered buffers alternately perform the first and second operations. Different operations can be performed on the even-numbered and odd-numbered buffers within each cycle. Therefore, during a cycle in which one buffer is performing the first operation, the other buffer can perform the second operation. During the first operation, the buffer can store the fourth vector (s1, s2, ..., s...). N Broadcast to circuit blocks MMTE1 to MMTE Pb During the second operation, the buffer can store circuit blocks MMTE1 to MMTE. Pb The received updated variable s i Here, the buffer includes both even-numbered buffers and odd-numbered buffers.

[0233] Therefore, the first memory (memory Smem) of the electronic circuit can have Pb first regions and Pb second regions. The first and second regions can be configured such that when an element of the fourth vector is transferred from the first region to the Pb first circuits (circuit blocks MM)... k During broadcasting, from the second circuit (circuit block TE) k The elements of the fourth vector provided are stored in the second region. Furthermore, the first and second regions can be configured such that when the elements of the fourth vector are broadcast from the second region to Pb first circuits, they are stored from the second circuit (circuit block TE). k The elements of the fourth vector provided are stored in the first region.

[0234] MMTE circuit block k (k = 1, 2, ..., Pb) includes circuit block MM k Circuit block TE k Memory X Bk Memory Y Bk Memory H Bk and memory J Bk Memory X Bk Store Nb variables x i Memory Y Bk Store Nb variables y i Memory HBk Store Nb variables h i Memory J Bk Store Nb*N elements in matrix J. Circuit block MM k Connected to memory Smem and memory J Bk Circuit block MM k By using memory J Bk The Nb*N elements of the read J matrix and the fourth vector (s1, s2, ..., s) read from memory Smem N To perform the multiplication-accumulation (MAC) operation of the following equation (18). Thus, the circuit block MM... k Calculate δyi.

[0235] [Mathematical Formula 16]

[0236]

[0237] Circuit block TE k Connected to memory X Bk Memory Y Bk Memory H Bk Memory Smem and circuit block MM k Circuit block TE k Use from memory X Bk The variable x read i , from memory Y Bk The variable y to be read i From memory H Bk The variable h read i and the circuit module MM k The calculated Δy is then processed using a pipelined approach to execute the TE section of the circuit. This is then processed from the circuit block TE. k Output the updated variable x i y i and s i In addition, circuit block TE k The variable x to be updated i Write to memory X Bk The variable y to be updated i Write to memory Y Bk And the variable s to be updated i Write to region S in memory Smem Bk Through the circuit block TE k During execution, the updated variables are stored in each memory location.

[0238] The electronic circuit may include a first circuit (circuit block MM) and a second circuit (circuit block TE). For example, the first circuit is configured to update each element in a third vector based on fundamental equations, each fundamental equation being a partial derivative of an objective function with respect to any variable. Here, the variables in the fundamental equations may be elements of the first vector or elements of a fourth vector. The fourth vector can be computed by transforming each element in the first vector using a first function, where the first function takes a first value or a second value greater than the first value.

[0239] The second circuit can be configured to: (1) update the elements of the first vector by adding the corresponding elements of the second vector or the weighted value of the second vector to the elements of the first vector; (2) set the elements of the first vector whose values ​​are less than the first value to the first value; (3) set the elements of the first vector whose values ​​are greater than the second value to the second value; and (4) update the elements of the second vector by (i) adding the weighted product of the first coefficient (which monotonically increases or decreases based on the number of updates) and the corresponding elements of the first vector and (ii) adding the weighted value of the corresponding elements of the third vector.

[0240] Here, an example of an electronic circuit having multiple (Pb) first circuits and multiple (Pb) second circuits is described. However, an electronic circuit may have at least one first circuit and at least one second circuit.

[0241] The second circuit can be configured to: convert elements of the first vector whose values ​​are less than a first value and a third value between the first and second values ​​into first values; and convert elements of the first vector whose values ​​are greater than the third value into second values, to compute a solution to the objective function. Furthermore, the second circuit can be configured to compute a solution to the objective function when the number of updates for the first, second, and third vectors exceeds a threshold. Additionally, the second circuit can be configured to update elements of the second vector corresponding to elements of the first vector whose values ​​are less than the first value or whose values ​​are greater than the second value to the product of the original values ​​and the second coefficients of the elements in the second vector. Alternatively, the second circuit can be configured to set the values ​​of the second vector corresponding to elements of the first vector whose values ​​are less than the first value or whose values ​​are greater than the second value to pseudo-random numbers.

[0242] The first circuit can be configured to update the value of each element in the third vector by calculating the value of a fundamental equation having elements of a first vector as variables and transforming the calculated value of the fundamental equation with a first function. Furthermore, the first circuit can be configured to update the value of each element in the third vector by multiplying it by a second function having first coefficients as parameters.

[0243] The electronic circuit may include a first memory connected to a first input terminal of a first circuit and a second output terminal of a second circuit. The first memory is configured to store a fourth vector or a first vector. Here, the first output terminal of the first circuit is connected to the second input terminal of the second circuit.

[0244] In addition, the electronic circuit may include a first memory (memory Smem) and Pb (2 < Pb) first circuits (circuit blocks MM). k ) and Pb (2 < Pb) second circuits (circuit block TE) k In this configuration, each of the Pb first circuits is connected to the first memory at its first input terminal. The Pb second circuits are each connected to any one of the first circuits at its second input terminal and each connected to the first memory at its second output terminal.

[0245] like Figure 29 Each first circuit (circuit block MM) presented in the document k The third vector is configured to compute its element Δy by multiplying any first matrix of dimension N / Pb×Pc with any fifth vector. i Here, the first matrix can be obtained by dividing the N×N dimensional coupling coefficient matrix into Pb parts. The fifth vector can be obtained by dividing the fourth vector (s1, s2, ..., s...). N It is obtained by dividing it into Pb parts. In addition, each second circuit (circuit block TE) k () can be configured to be based on the element Δy of the third vector calculated by any of the first circuits. i To update N / Pb elements of the first vector, N / Pb elements of the second vector, and N / Pb elements of the fourth vector. Second circuit (circuit block TE) k The first circuit can be configured to store N / Pb elements of the fourth vector to be updated in the first memory. Furthermore, each first circuit can execute the element Δy of the third vector in multiple rounds. i The calculations are as follows. For example, each first circuit can divide a first matrix of dimension N / Pb×Pc into a second matrix of dimension Pr×Pc (J sub-matrices). In addition, each first circuit can divide a fifth vector into multiple sixth vectors (s sub-vectors).

[0246] Each first circuit can be configured to compute the elements of the third vector by performing a product operation between each second matrix (dimension Pr × Pc) and the corresponding sixth vector (Pc elements). Furthermore, each second circuit can be configured to set the elements of the first vector whose values ​​are less than a first value as the first value, and set the elements of the first vector whose values ​​are greater than a second value as the second value.

[0247] Therefore, the first circuit (circuit block MM) in an electronic circuitk The process corresponding to the multiplier-accumulator 51 described above is executed. Furthermore, the second circuit (circuit block TE) ​​in the electronic circuit... k ) Perform the process corresponding to the updater 50 described above.

[0248] The electronic circuit may include Pb secondary memories (memory X) Bk Pb third memory units (memory J) Bk Pb fourth memories (memory Y) Bk ) and Pb fifth memory (memory H) Bk Each second memory can be configured to store Nb = N / Pb elements of the first vector. Each third memory can be configured to store any first matrix. Each fourth memory can be configured to store N / Pb elements of the second vector. Each fifth memory can be configured to store N / Pb elements of the sixth vector.

[0249] Each second memory is connected to any second circuit (circuit block TE). k The second input and second output terminals of the third memory are connected to any of the first circuits (circuit blocks MM). k The first input terminal of the second circuit is connected to the second input terminal and the second output terminal of the second circuit. The fifth memory is connected to the second input terminal of the second circuit.

[0250] Figure 30 This is a diagram illustrating examples of multiple parallelization methods. Figure 30 The timing diagram includes several cases (a) to (d). Figure 30 In a timing diagram, the horizontal axis represents time. This time corresponds to the number of clock cycles and the number of steps executed.

[0251] exist Figure 30 In case (a), the process is executed sequentially by the processor. In case (a), the execution of the MM part requires N×N clock cycles per processing step. To execute the TE part in case (a), each processing step requires N×λ. TE One clock cycle. Here, λ TE Indicates the clock cycles required to perform the TE portion for each particle i.

[0252] exist Figure 30 In section (b), we present the application of Level I parallelization. In Level I parallelization, the circuit block MM... k This is used to perform multiplication and accumulation operations in parallel on rows Pr and columns Pc. Additionally, in Level I parallelization, the circuit block TE... k Used for the execution process of a production line.

[0253] likeFigure 29 The circuit block MM shown in the image k In each clock cycle, the product of the J submatrix (Pr×Pc dimensions) and the s subvector (Pc elements) is calculated. When N / Pc clock cycles have elapsed since the start of this product calculation, the circuit block MM... k The output is a subvector of Δy with Pr elements. This process of generating the Δy subvector over N / Pc clock cycles is called a single-stage process. Then, until Δy is obtained... i Up to all values ​​of (i = 1, 2, ..., N), the process consists of N / Pr stages. Therefore, for case (b), the processing speed of the MM part is increased by Pr × Pc times compared to case (a). Here, the submatrix indicates the matrix part that the algorithm is computing. Similarly, the subvector indicates the vector part that the algorithm is computing.

[0254] In case (b), circuit block TE k Based on the input x in each clock cycle i y i h i and Δy i The value is used to perform the calculation. Then, the circuit block TE k Output x after the pipeline wait time (λp). i y i h i and Δy i The updated value. Circuit block TE k Each round of the TE section process is executed in N+λp clock cycles. In case (b), the processing speed of the TE section is accelerated by approximately λ compared to case (a). TB times.

[0255] Case (c) presents an example of applying Level II parallelization. In Level II parallelization, circuit blocks MM are executed in parallel. k The process and circuit block TE k The process. In the first stage, circuit block MM k Calculate the Δy subvector with Pr elements. Then, in the second stage, the circuit block MM... k Calculate variable s i x i and y i The updated value can be calculated based on the Δy subvector with Pr elements. Therefore, in the second stage, a portion of the TE part is executed. In the second stage, circuit block MM... k With circuit block TE kThe calculation of variables in the process computes the next Δy subvector (Pr elements) in parallel. If Level II parallelization is applied, the process corresponding to N / Pr+1 stages needs to be executed. Furthermore, if Level II parallelization is applied, the circuit block TE... k It enters an idle state in the first stage. Additionally, circuit block MM... k It enters an idle state in the final stage.

[0256] Case (d) presents an example of applying Level III parallelization. To apply Level III parallelization, it is necessary to prepare each circuit block MM. k and circuit block TE k The Pb pairs. This pair is related to the circuit block MMTE. k Correspondingly. Figure 28 The electronic circuit 200 in the diagram presents an example configuration including Pb pairs. In case (d), the number of clock cycles required for each processing step is equal to N. cyc_step =(N / Pc)×(N / Pr / Pb+1)+λ. Here, λ is the waiting time in the processing step. Electronic circuit 200 needs to be in a waiting state for λ clock cycles in the last round. This ensures the latest vector (s1, s2, ..., s... N This is necessary for storage in memory Smem. (and...) Figure 30 Compared to cases (a) to (d), it can be inferred that the application of Level III parallelization is the most effective in reducing processing time.

[0257] Therefore, the first circuit (circuit block MM) in an electronic circuit k ) can be configured to, when the second circuit (circuit block TE) k ) based on the element Δy of the third vector i When calculating at least one of the N / Pb elements of the first vector, the N / Pb elements of the second vector, or the N / Pb elements of the fourth vector, the elements of the third vector to be used in the next round are calculated. When calculating the elements of the third vector in the next round, the second circuit may use at least one of the N / Pb elements of the first vector, the N / Pb elements of the second vector, or the N / Pb elements of the fourth vector.

[0258] The above provides an overview of electronic circuit 200. The following sections will describe the details of each circuit block.

[0259] Figure 31 This shows the circuit block MM. k A diagram illustrating a configuration example. Circuit block MM k This includes Pr circuit blocks (MAC) and a buffer ΔYbuf. Depending on the needs, the circuit block including Pr circuit blocks (MAC) is called circuit block JS. kThe output of each circuit block in the Pr MAC is input to the buffer ΔYbuf. During each clock cycle, the circuit block MAC is accessed from any region S in the memory Smem. Bk (k=1, 2, ..., Pb) Read the subvector s (Pc elements). To read the Pc elements of the subvector s in parallel, each region S in the memory Smem... Bk (k=1, 2, ..., Pb) is divided into Pc subregions. Each of the Pc subregions has a corresponding read port. Each region S in the memory Smem Bk (k=1, 2, ..., Pb) are connected to Pr circuit blocks MAC. By adopting this wiring (connection) topology, from each region S Bk The Pc elements of the s subvector read from (k=1, 2, ..., Pb) can be broadcast to Pr circuit blocks MAC. Figure 21 In the middle, the source other than S is not shown. B1 Wiring (connection) in areas outside the MAC of each circuit block.

[0260] The circuit block JSK, including Pr circuit blocks MAC, can be retrieved from memory J. Bk Read the submatrix J with dimensions Pr×Pc. Memory J Bk It has at least Pc regions. Memory J Bk Each of the Pc regions in the matrix J has a corresponding read port. Each read port is connected to a Pr circuit block MAC. Each of the Pc regions can store Pr elements J from matrix J per word. ij In each clock cycle, from memory J... Bk Read Pc elements J from the middle ij In relation to memory J Bk Point-to-point communication of data is performed in each read port corresponding to the region in the table. Therefore, Pr elements J are stored in each word. ij It can be transferred to different circuit blocks (MACs). By adopting this configuration, memory J can be effectively utilized. Bk The storage area and access ports, including read ports.

[0261] Pr circuit blocks MAC perform the product sum operation of (18). Then, every N / Pc clock cycles (the final clock cycle of each stage), Pr circuit blocks MAC output and write Pr values ​​of Δyi in parallel. The buffer ΔYbuf outputs Pr values ​​of Δyi sequentially during the next stage. Therefore, the buffer ΔYbuf is a parallel input / sequential output buffer. Figure 28The electronic circuit 200 includes a total of Pb×Pr×Pc MAC arithmetic circuits. Each MAC arithmetic circuit is connected to the memory J. Bk The read port (port J) corresponding to any region in the data. in ) and any region S in memory Smem Bk The read port (port S) corresponding to any subregion in (k=1, 2, ..., Pb) in In addition, the MAC arithmetic circuitry includes a multiplier and an adder (decoder 47) for each read port. Details of decoder 47 will be described later.

[0262] Figure 32 This shows the circuit block TE. k A diagram showing an example configuration. Figure 32 circuit block TE in k This includes the input ports xin, yin, hin, and Δyin. Furthermore, Figure 32 circuit block TE in k This includes the output ports xout, yout, and sout. The circuit block TE can be configured using a feedforward combinational circuit. k Circuit block TE k It also includes adders ADD1 to ADD4, multiplier MULFX1, arithmetic circuit FX, arithmetic circuit FY, multiplexers MUX1 to MUX3, and comparators comp1 to comp3. Adders ADD1 to ADD4 and multiplier MUL1 each have at least two input terminals and an output terminal. Arithmetic circuit FX is configured to perform... Figure 27 The arithmetic operation of the function FX(nx) defined in (d). The arithmetic circuit FY is configured to perform the operation in Figure 27 Arithmetic operations of the function FY(ny) defined in (d). Multiplexer MUX1 has at least three input terminals, one control terminal, and one output terminal. Multiplexers MUX2 and MUX3 each have at least two input terminals, one control terminal, and one output terminal.

[0263] Circuit block TE k The input ports Δyin and yin are respectively connected to the first input terminal of adder ADD1 and the second input terminal of adder ADD2. The output terminal of adder ADD1 is connected to the first input terminal of adder ADD2. The first input terminal of adder ADD2 is connected to the output terminal of adder ADD1. Furthermore, the output terminal of multiplier MUL is connected to the second input terminal of adder ADD2. The first input terminal of multiplier MUL is connected to circuit block TE. k The input port is hin.

[0264] Furthermore, the first input terminal of adder ADD3 is connected to the output terminal of adder ADD2. The output terminal of arithmetic circuit FX is connected to the second input terminal of adder ADD3. Arithmetic circuit FY and multiplexer MUX2 are connected to the output terminal of adder ADD3. The second input terminal of adder ADD4 is connected to the output terminal of arithmetic circuit FY. Input port hin is connected to the first input terminal of multiplier MUL1. Additionally, counter 52 is connected to the second input terminal of multiplier MUL1. Counter 52 is configured to output a second value that monotonically increases according to the number of clock cycles. For example, cΔt×a is used as the second value. Figure 27 As shown in (a), the value of "a" increases with the number of updates. Since the number of updates is proportional to the number of clock cycles, the value of cΔt×a increases monotonically with the number of clock cycles.

[0265] The second input terminals of the arithmetic circuit FX and the adder ADD4 are connected to the circuit block TE. k The input port xin. Multiplexer MUX1 and comparators comp1 to comp3 are connected to the output terminals of adder ADD4. The output terminals of comparators comp1 to comp3 are each connected to the control terminals of multiplexers MUX1 to MUX3.

[0266] Adder ADD1 will add circuit block TE k The sum of the input signals Δyin and yin is output to line ny1. Adder ADD2 will output the sum of the signals provided by lines ny1 and nh1 to line ny2. Multiplier MUL1 will output the sum of the signals from circuit block TE. k The signal provided by the input port hin is multiplied by cΔt×a. Adder ADD3 outputs the sum of the signals provided by lines δy and ny2 to line ny3. The arithmetic circuit FX is provided to circuit block TE. k The input port xin executes the signal. Figure 27 The operation of function FX(nx) in (d) is performed. The arithmetic circuit FX outputs the calculation result to line δy. Adder ADD3 will take the result from line δx and circuit block TE. k The input port xin provides the signal and outputs it to line nx1. The arithmetic circuit FY performs operations on the signal provided from the output terminal of adder ADD3. Figure 27 The operation of function FY(ny) in (d). The arithmetic circuit FY outputs the calculation result to line δx.

[0267] Comparators comp1 through comp3 are each connected to the output terminal of adder ADD4 via line nx1. Therefore, the signal from adder ADD4 is supplied to comparators comp1 through comp3 respectively. Comparators comp1 and comp2 determine whether particle i is at position x after the update process. i <-1 or x i >1.0. This corresponds to the process of determining whether particle i has collided with the wall. Comparator comp3 is configured based on the position x of particle i after the update process. i Determine spin s i The symbol.

[0268] The three input terminals of multiplexer MUX1 are respectively connected to the output terminal (line nx1) of adder ADD4, the component providing the constant signal +1, and the component providing the constant signal -1. Furthermore, the control terminal of multiplexer MUX1 is connected to the output terminal of comparator comp1. The output terminal of multiplexer MUX1 is connected to circuit block TE. k The output port xout. The multiplexer MUX1 is configured to output a signal from line nx1, a constant signal +1, or a constant signal -1 to the output port xout, depending on the control signal provided from comparator comp1.

[0269] The two input terminals of multiplexer MUX2 are respectively connected to the output terminal (line ny3) of adder ADD3 and the element providing the constant signal 0. Furthermore, the control terminal of multiplexer MUX2 is connected to the output terminal of comparator comp2. The output terminal of multiplexer MUX2 is connected to circuit block TE. k The output port yout. The multiplexer MUX2 is configured to output either a signal or a constant signal 0 from the adder ADD3 to the output port yout based on the control signal provided by the comparator comp2.

[0270] The two input terminals of multiplexer MUX3 are connected to components providing a constant signal +1 and a constant signal 0, respectively. Furthermore, the control terminals of multiplexer MUX3 are connected to the output terminals of comparator comp3. The output terminals of multiplexer MUX3 are connected to circuit block TE. k The output port is sou. The multiplexer MUX3 is configured to output a constant signal +1 or a constant signal 0 to the output port sou based on the control signal provided from the comparator comp3.

[0271] Therefore, each second circuit (circuit block TE) kIt may include a counter, a first adder (adder ADD1), a first multiplier (multiplier MUL1), a second adder (adder ADD2), a first arithmetic circuit (arithmetic circuit FX), a third adder (adder ADD3), a second arithmetic circuit (arithmetic circuit FY), a fourth adder (adder ADD4), a first comparator (comparator comp1), and a first multiplexer.

[0272] The counter is configured to output a second value that monotonically increases or decreases depending on the number of clock cycles. The first adder is connected at its input to the fourth memory (memory Y). BK ) and the first circuit (circuit block MM) k The first multiplier is connected to the fifth memory (memory H) at its input. Bk The first arithmetic circuit is connected to the first adder and the first multiplier at its input. The second adder is connected to the first adder and the first multiplier at its input. The first arithmetic circuit is connected to the second memory (memory X) at its input. Bk Furthermore, the first arithmetic circuit is configured to output a third value that monotonically increases or decreases depending on the number of clock cycles. For example, (-D+p)Δt can be used as the third value. The third adder is connected at its input to the second adder and the first arithmetic circuit. The second arithmetic circuit is connected at its input to the third adder. Furthermore, the second arithmetic circuit is configured to output a weighted signal from the input of the third adder. The fourth adder is connected at its input to the second memory and the second arithmetic circuit. The first comparator is connected at its input to the fourth adder. The first multiplexer is connected at its input to the fourth adder. Furthermore, the first multiplexer is configured to output a first constant signal of a first value (e.g., -1) or a second constant signal of a second value (e.g., +1) to the second memory based on the input of the first comparator.

[0273] In addition, each second circuit (circuit block TE) k The input may include a second comparator (comparator comp2) and a second multiplexer (multiplexer MUX2). The second comparator is connected at its input to a fourth adder (adder ADD4). The second multiplexer is connected at its input to a third adder (adder ADD3). The second multiplexer is configured to output data to a fourth memory (memory Y) based on the input from the second comparator. Bk It outputs a third signal (e.g., a constant signal 0) or a signal from a third adder.

[0274] In addition, each second circuit (circuit block TE) kIt is not necessary to include a second comparator (comparator comp2) and a second multiplexer (multiplexer MUX2). In this case, the output terminal of the third adder (adder ADD3) is connected to the output port yout. Therefore, the output signal of the third adder is provided to the fourth memory (memory Y). Bk ).

[0275] In addition, each second circuit (circuit block TE) k This may include a third comparator (comparator comp3) and a third multiplexer (multiplexer MUX3). The third comparator is connected at its input to a fourth adder (adder ADD4). The third multiplexer is configured to output a second constant signal or a third constant signal (e.g., constant signal 0) with a second value (e.g., +1) to a first memory (memory Smem) based on the input from the third comparator.

[0276] Typically, spin s i Use binary values ​​of -1 or +1. If these values ​​are represented using signed binary digits, at least two bits of information are required. However, spins... i It can be encoded as a binary variable using 0 or 1 as its value. If this encoding is used, a single bit of information can be used to represent the spin value. This reduces the amount of data transmitted and the storage space consumed in the signal line. Therefore, a signal line that transmits single-bit information instead of multiple bits can be used as line 39 ( Figure 28 Here, line 39 will come from circuit block TE. k Spin s of (k=1, 2, ..., Pb) i The updated value is transferred to memory Smem. Furthermore, in memory Smem, each spin s i The values ​​can each be stored in a 1-bit storage device. Alternatively, signal lines that transmit single-bit information instead of multiple-bit information can be used as line 40 (…). Figure 28 Here, line 40 will read the spins s from memory Smem. i The value is transmitted to circuit block MM k (k=1, 2, ..., Pb). The circuit block MUL (located in the input stage of circuit block MAC1) Figure 31 Encoding is performed on signed binary numbers. Therefore, regardless of whether 1 bit of information is transmitted in the signal line and the spin s i Regardless of the fact that the value is stored in 1-bit format, the circuit's functionality is unrestricted.

[0277] Here, for reference Figure 31 Describe the circuit that converts a single bit of information into a signed binary number. Figure 31Decoder 47 describes the detailed configuration of circuit block MUL located at the input stage of circuit block MAC1. Decoder 47 includes a multiplexer MUX and a multiplier. The multiplexer MUX includes at least two input terminals, one control terminal, and one output terminal. The multiplier includes two input terminals and an output terminal. Components providing a constant signal +cΔt and a constant signal -cΔt are respectively connected to the two input terminals of the multiplexer MUX. Furthermore, it is connected to any region S in memory Smem. Bk The read port (port S) corresponding to any subregion in (k=1, 2, ..., Pb) in The input terminal of the multiplier (MUX) is connected to the control terminal of the multiplier. Furthermore, the output terminal of the multiplier is connected to the second input of the multiplier. Additionally, the first input terminal of the multiplier is connected to the memory J. Bk The read port (port J) corresponding to any region in the data. in When from port S in When the provided signal is 1, the multiplexer MUX outputs a signal corresponding to the value +cΔt from its output terminal. Furthermore, when the signal from port S... in When the provided signal is 0, the multiplexer MUX outputs a signal corresponding to the value -cΔt from its output terminal. The multiplier outputs the input signal of the multiplexer MUX and the signal from its port J from its output terminal Out. in The product of the input signals.

[0278] Therefore, the first memory (memory Smem) can be configured to store each element of the fourth vector in a 1-bit format. In this case, each first circuit (circuit block MM) k This includes a decoder configured to decode 1-bit information read from the first memory into a signed binary number.

[0279] However, the first memory (Memory Smem) can store each element of the fourth vector in signed binary digital format. In this case, the second circuit (Circuit Block TE) k The third multiplexer (MUX3) can output +1 or -1 depending on the input from the third comparator (comp3). It is not necessary to do so in every first circuit (circuit block MM). k The decoder is implemented in the first memory to decode the information read from the third memory. If the algorithm for calculating the elements of the third vector uses the elements of the first vector as variables, then each element of the first vector can be stored in the first memory.

[0280] (Examples of implementation of multiple electronic circuits)

[0281] If the simulated bifurcation algorithm is interpreted as a model of N particles, then it is an algorithm that repeatedly updates the positions and momentum of the N particles. Therefore, it can be interpreted as a model for calculating the time evolution of the positions and momentum of the N particles. Below, the state of particle i includes its position x. i and the momentum y of particle i i .

[0282] The process of calculating the states of N particles can be performed in parallel by using multiple electronic circuits. However, in order to use... Figure 27 (a) uses the algorithm to calculate the number of N particles in n cycle =u+1 state, requires N particles in n cycle =u's state. For example, suppose there are M electronic circuits. In this case, each electronic circuit can be based on N particles (all particles) in n cycle =u's state is used to calculate the N / M particles in n cycle =u+1 state. Here, each electronic circuit has a relationship with N particles in n cycle =Information about the state of u. However, each electronic circuit cannot operate without reference to the (NN / M) particles calculated by other electronic circuits in n. cycle Given the information of the state =u+1, calculate the N / M particles in n. cycle =u+2. Therefore, a configuration can be used where each electronic circuit can obtain information about the state of the particle calculated by other electronic circuits.

[0283] Figure 33 This is a diagram illustrating an example configuration of multiple electronic circuits that can communicate with each other. Figure 33 Electronic circuits 201 to 208 (HW_CIRCUIT #1-#8) are shown. Figure 33 This corresponds to the case when M=8. However, the number of electronic circuits M can take different values. Each of electronic circuits 201 to 208 includes an SB core circuit 41, a communication circuit ch1, and a communication circuit ch2. For example, an FPGA can be used as electronic circuits 201 to 208. However, an ASIC can also be used as electronic circuits 201 to 208. Therefore, the type of electronic circuit used as electronic circuits 201 to 208 is not limited. In addition to the elements of electronic circuit 200 described above, electronic circuits 201 to 208 may each include communication circuits ch1 and ch2, buffer memory bufL, and buffer memory bufR. Below, a computing system including multiple electronic circuits and details of each electronic circuit are explained, focusing on the differences from the aforementioned electronic circuit 200.

[0284] Figure 33The communication circuits ch1 and ch2 each have a transmit port TX and a receive port RX. The transmit port TX and the receive port RX can operate independently. Therefore, communication circuits ch1 and ch2 can perform full-duplex communication. The SB core circuit 41 includes a memory 43 (Smem), an arithmetic circuit 42 (SB core), a buffer memory bufL, and a buffer memory bufR. Memory 43 can store a vector (s1, s2, ..., s...) with N elements. N Buffer memories bufL and bufR are each connected to memory 43. Arithmetic circuit 42 (SB core) comprises Pb circuit blocks MM. k (First circuit), Pb circuit blocks TE k (Second circuit), Pb memory units X Bk (Second memory), Pb memory units J Bk (Third memory), Pb memory Y Bk (Fourth memory) and Pb memory H Bk (Fifth memory). Therefore, the arithmetic circuit 42 (SB core) and memory 43 correspond to the electronic circuit 200 described above.

[0285] Therefore, the electronic circuit may include a first communication circuit (communication circuit ch1), a second communication circuit (communication circuit ch2), a first buffer memory (bufL), and a second buffer memory (bufR). The first communication circuit includes a first transmitting port (transmitting port TX of communication circuit ch1) and a first receiving port (receiving port RX of communication circuit ch1). The second communication circuit includes a second transmitting port (transmitting port TX of communication circuit ch2) and a second receiving port (receiving port RX of communication circuit ch2). The first buffer memory is connected to the first memory (memory 43) and the second circuit (circuit block TE). k The second receive port and the first transmit port are connected to the first memory and the second circuit (circuit block TE). k ), first receiving port and second transmitting port.

[0286] refer to Figure 33Electronic circuits 201 to 208 are connected to form a ring topology. Therefore, communication circuit ch2 of HW_CIRCUIT#h (h=1, 2, ..., M) is connected to communication circuit ch1 of HW_CIRCUIT#(h+1). Additionally, communication circuit ch2bz of HW_CIRCUIT#M is connected to communication circuit ch1 of HW_CIRCUIT#1. Connections between electronic circuits can be achieved via communication cables. Furthermore, communication between electronic circuits can be formed through wiring on the board. Therefore, connections between electronic circuits can be achieved in any manner. For example, instead of using physical connections for communication media, multiple electronic circuits can use wireless communication.

[0287] exist Figure 33 In this ring topology, data rings ringR and ringL are formed. Communication in ringR proceeds clockwise, while communication in ringL proceeds counter-clockwise. Figure 33 The topology is called a double-ring topology. Because there are clockwise and counterclockwise communication paths in a ring topology, it offers advantages over a single-ring topology that uses only a single communication path. Figure 33 The topology can achieve approximately twice the data transfer rate.

[0288] Therefore, the computing system can have multiple electronic circuits. The first transmitting port of the electronic circuit (the transmitting port TX of communication circuit ch1) is connected to the second receiving port of the adjacent electronic circuit (the receiving port RX of communication circuit ch2). Furthermore, the first receiving port of the electronic circuit (the receiving port RX of communication circuit ch1) is connected to the second transmitting port of the adjacent electronic circuit (the transmitting port TX of communication circuit ch2). By using multiple electronic circuits, a circular communication path can be formed in both clockwise and counterclockwise directions.

[0289] Figure 34 This is a diagram illustrating a second example of a method for calculating the product between a matrix and a vector. Figure 34 In this case, the process is executed concurrently in multiple electronic circuits. Figure 34 In the algorithm, the update process for each variable is executed until the counter variable n is reached. cycle The value is increased until a certain value is reached. In loop 44, the process of transmitting data at the transmit port TX of communication circuits ch1 and ch2 and receiving data at the receive port RX of communication circuits ch1 and ch2 is performed in each electronic circuit. In loop 45, a portion of the matrix-vector multiplication (product sum operation) is performed in each electronic circuit. In loop 46, the calculation process corresponding to the time evolution is performed in each electronic circuit.

[0290] Figure 35 It is a diagram showing examples of algorithms executed in each electronic circuit. Figure 35 This demonstrates the method for calculating matrix multiplication when the number of electronic circuits, M, is 8. For example... Figure 35 The presented method performs a product sum operation by dividing a matrix into M submatrices and a vector into M subvectors. For example, HW_CIRCUIT#h uses a matrix J with N / M rows and N columns. n To calculate N / M coupling terms (ΔY) h ).

[0291] As in Figure 27 As described in the description, for each HW_CIRCUIT#h (h=1, 2, ..., M), it is necessary to have a full-size vector (s1, s2, ..., s...) with N elements. N The corresponding data is used to perform the variable update process. Therefore, HW_CIRCUIT#h can send the updated N / M variables {s} to other electronic circuits connected to HW_CIRCUIT#h. m |m=(h-1)N / M+1,(h-1)N / M+2,...,hN / M}. This operation is called the sending mode. Furthermore, after the variable update is complete, HW_CIRCUIT#h can receive N / M variables updated by another electronic circuit connected to HW_CIRCUIT#h.

[0292] For example, if HW_CIRCUIT#1 is in transmit mode relative to the data ring ringR, then the updated variable {s m |m=1, 2, ..., N / M} is sent to HW_CIRCUIT#2. In this timing sequence, HW_CIRCUIT#2 is in receive mode relative to data ring R. Simultaneously, HW_CIRCUIT#1 can be in receive mode relative to data ring L. Therefore, HW_CIRCUIT#1 can receive the updated variable {s} from HW_CIRCUIT#2. m |m=N / M+1, N / M+2, ..., 2N / M}, HW_CIRCUIT#2 is in transmit mode relative to the data ring ringL. Then, HW_CIRCUIT#2 can send the variable {s} to HW_CIRCUIT#3. m |m=1,2,...,N / M} and variable {s} m|m = N / M+1, N / M+2, ..., 2N / M}. Therefore, the electronic circuit can send updated variables to other electronic circuits directly connected to it. Simultaneously, the electronic circuit can receive updated variables from other electronic circuits directly connected to it. Furthermore, the electronic circuit can forward variables updated by the first electronic circuit to the second electronic circuit.

[0293] As described above, the sending process and the receiving process, which includes data forwarding, can be executed by each electronic circuit. Therefore, the M electronic circuits can use the fourth vector (s1, s2, ..., s) in each iteration of the variable update process. N The latest value of ). However, in order to ensure that multiple electronic circuits connected to form a ring topology can obtain the same data in the update timing, the operation of multiple electronic circuits can be synchronized.

[0294] Figure 36 It is a timing diagram that presents an example of a process performed by multiple electronic circuits. Figure 36 The horizontal axis represents time. Each iteration period Tstep in this process includes a communication period Tcomm and a computation period Tcore. In the computation period Tcore, the updated value of each variable is calculated in arithmetic circuit 42 (SB core). Furthermore, the communication period Tcomm includes a communication phase equal to the number M of electronic circuits. For simplicity, the case where M electronic circuits operate synchronously is described. However, the number of synchronously operating electronic circuits can vary. The arithmetic circuit 42 of HW_CIRCUIT#h updates the variable {s} corresponding to N / M particles during the computation period Tcore. m |m=(h-1)N / M+1, (h-1)N / M+2,..., hN / M}.

[0295] Below, the process executed during one communication phase of the communication cycle Tcomm is described. Arithmetic circuit 42 will update the variable {s} m |m=(h-1)N / M+1,(h-1)N / M+2,...,hN / M} is divided into two groups (group S) h1 and group S h2 A group (group S) h1 The data is stored in the buffer memory bufL. Another group (group S) h2 It is stored in the buffer memory bufR.

[0296] Each electronic circuit (HW_CIRCUIT #1 to #M) can transmit data stored in buffer memory bufL to other electronic circuits via the transmit port TX of communication circuit ch1 using the data ring ringL. Furthermore, each electronic circuit (HW_CIRCUIT #1 to #M) can transmit data stored in buffer memory bufR to other electronic circuits via the transmit port TX of communication circuit ch2 using the data ring ringR. The transmission processes of data stored in buffer memory bufL and data stored in buffer memory bufR can be executed concurrently.

[0297] Furthermore, the data stored in buffer memories bufL and bufR can be stored in memory 43 (Smem). Therefore, the same data content as the data sent from the transmit port TX is stored in memory 43 (Smem). Moreover, the process of sending data stored in buffer memories bufL and bufR to the transmit port TX and the process of saving the corresponding data to memory 43 (Smem) can be performed concurrently. This operation is referred to as a "send and write" operation.

[0298] Therefore, the third circuit (e.g., SB core circuit 41) can be configured to consist of Pb second circuits (circuit blocks TE). k The updated fourth vector is divided into first data and second data. The first data, which is part of the fourth vector, is stored in the first buffer memory (bufL), and the second data, which is another part of the fourth vector, is stored in the second buffer memory (bufR). Furthermore, the third circuit can be configured to: transmit the first data stored in the first buffer memory from the first transmission port (transmission port TX of communication circuit ch1); transmit the second data stored in the second buffer memory from the second transmission port (transmission port TX of communication circuit ch2); save the first data stored in the first buffer memory to the first memory (memory 43), and save the second data stored in the second buffer memory to the first memory (memory 43).

[0299] When the processes of sending data stored in buffer memory bufL and sending data stored in buffer memory bufR are completed, each electronic circuit (HW_CIRCUIT #1 to #M) receives data sent from other electronic circuits and stores it in buffer memories bufR and bufL. Therefore, each electronic circuit (HW_CIRCUIT #1 to #M) saves the data received via the receive port RX of communication circuit ch2 to buffer memory bufL. The receive port RX of communication circuit ch2 is connected to the data ring ringL.

[0300] Furthermore, each electronic circuit (HW_CIRCUIT #1 to #M) saves the data received via the receive port RX of communication circuit ch1 to the buffer memory bufR. The receive port RX of communication circuit ch1 is connected to the data ring ringR. The process of receiving data at the receive port RX (data ring ringL) of communication circuit ch2 and the process of receiving data at the receive port RX (data ring ringR) of communication circuit ch1 can be executed concurrently. The operation of receiving data before data transmission, as described above, is called the "send first, receive later" strategy.

[0301] Therefore, the third circuit (e.g., SB core circuit 41) can be configured to: store the third data received from the second receiving port (the receiving port RX of the communication circuit ch2) into the first buffer memory (bufL); store the fourth data received from the first receiving port (the receiving port RX of the communication circuit ch1) into the second buffer memory (bufR); store the third data into the first memory (memory 43); and store the fourth data into the first memory (memory 43).

[0302] The processes executed in a single communication phase include data transmission processes at data rings ringR and ringL (which may include the process of storing data into memory 43) and data reception processes at data rings ringR and ringL. By repeating the communication phase process M times (which is equal to the number of electronic circuits), the M electronic circuits can obtain the vector (s1, s2, ..., s) in each iteration of the variable update process (calculation period Tcore). N The latest value of ). The latest vector (s1, s2, ..., s N The data is stored in memory 43 (Smem).

[0303] exist Figure 33 In this process, data is sent directly from the buffer memory bufL to the transmit port TX of communication circuit ch1. Furthermore, data received at the receive port RX of communication circuit ch2 is also sent directly to the buffer memory bufL. Figure 33 In this process, data is directly sent from the buffer memory bufR to the transmit port TX of communication circuit ch2. Furthermore, data received at the receive port RX of communication circuit ch1 is also directly sent to the buffer memory bufR. However, as... Figure 36 As presented, additional memory can be allocated between the communication circuit (communication circuit ch1 or ch2) and the buffer memory (bufL or bufR).

[0304] Figure 37 This is a diagram illustrating a more detailed configuration example of the communication channel. Besides...Figure 33 In addition to the components of electronic circuits 201 to 208, Figure 37 HW_CIRCUIT#h also includes memories 44a, 44b, 45a, and 45b. Figure 37 The transmitter TX PHY corresponds to the aforementioned transmit port TX. Similarly, the receiver RX PHY corresponds to the aforementioned receive port RX. Memory 44a is connected between the transmit port TX of communication circuit ch1 and the buffer memory bufL. Memory 44b is connected between the transmit port TX of communication circuit ch2 and the buffer memory bufR. Memory 45a is connected between the receive port RX of communication circuit ch1 and the buffer memory bufR. Memory 45b is connected between the receive port RX of communication circuit ch2 and the buffer memory bufL. Memory 44a and 44b correspond to the TX FIFO memory. On the other hand, memories 45a and 45b correspond to the RX FIFO memory. Here, the FIFO memory is a first-in, first-out (FIFO) type memory. Figure 37 In the figure, arithmetic circuit 42 (SB core) and memory 43 (Smem) are not shown.

[0305] Data stored in buffer memory bufL by arithmetic circuit 42 (SB core) is sent from the transmit port TX of communication circuit ch1 to HW_CIRCUIT#(h-1) via memory 44a (TX FIFO memory). Data stored in buffer memory bufR by arithmetic circuit 42 (SB core) is sent from the transmit port TX of communication circuit ch2 to HW_CIRCUIT#(h+1) via memory 44b (TX FIFO memory). Data received at the receive port RX of communication circuit ch1 is sent to buffer memory bufR via memory 45a (RX FIFO memory). Data received at the receive port RX of communication circuit ch2 is sent to buffer memory bufL via memory 45b (RX FIFO memory). Therefore, the communication channel includes a combination of transmit port TX, TX FIFO memory, and buffer memory, or a combination of receive port RX, RX FIFO memory, and buffer memory.

[0306] The driving frequency F of the SB core circuit 41 SB Kernel It can be equal to the driving frequency F of the communication channel. IOPHY Furthermore, the drive frequency F of the SB core circuit 41 SB Kernel The driving frequency F of the communication channel can be used. IOPHYThey are different. Memory types 44a, 44b, 45a, and 45b (TX FIFO memory and RX FIFO memory) can use uneven read / write speeds during communication to form a streaming data buffer. For example, the write port of the TX FIFO memory can be controlled by a frequency F... SB Kernel Driven. Furthermore, the read port of the TXFIFO memory can be controlled by a frequency F. IOPHY Driven. Furthermore, the read port of the RX FIFO memory can be controlled by a frequency F. IOPHY Driven. The write port of the RX FIFO memory can be driven by a frequency F. SB Kernel drive.

[0307] Figure 38 This is a block diagram showing a configuration example of hardware that supports a ring topology. Figure 38 Arithmetic circuitry 42 (SB core) and memory 43 (Smem) are presented. Arithmetic circuitry 42 includes circuit blocks MMTE1 to MMTE of the aforementioned electronic circuitry 200. Pb Corresponding features and components. In the aforementioned electronic circuit 200, the memory Smem employs a double-buffer structure to address data dependency issues. However, in Figure 33 and Figure 37 In the implementation examples presented, which include multiple electronic circuits, buffer memories bufL and bufR resolve the data dependency problem. Therefore, Figure 38 The memory 43 in the memory does not necessarily have to be a memory with a double buffer structure.

[0308] Next, a method for synchronizing the operation of multiple electronic circuits is described. The multiple electronic circuits do not necessarily need to be started simultaneously. Furthermore, the clocks of the multiple electronic circuits do not need to be synchronized. The method for autonomously synchronizing the operating timing of multiple electronic circuits when they are started in different sequences is explained below. In this case, the clocks of the multiple electronic circuits are not synchronized. First, the case where the multiple electronic circuits are synchronized is explained ( Figure 39 The timeline). Then, it is explained in different time sequences ( Figure 40 The timeline shows the sequential activation of each electronic circuit. Figure 39 and Figure 40 In the time graph, the horizontal axis corresponds to time.

[0309] exist Figure 39In the timing diagram, the SB core circuit 41 of HW_CIRCUIT#h writes the data stored in buffer memories bufL and bufR to the TX FIFO (memories 44a and 44b). This operation is called Twrite_TX FIFO. During this timing, the transmitter TX PHY's transmission operation begins. The transmitter TX PHY reads data from the TX FIFO. Then, the transmitter TX PHY simultaneously transmits data from ports TX of communication circuits ch1 and ch2. This operation is called Tread_TX FIFO.

[0310] If data is not stored in the TX FIFO, the transmitter TX PHY will not read data from the TX FIFO. This occurs at a physical delay λ. PHY Subsequently, the transmitted data is stored in the RX FIFO corresponding to communication circuit ch2 of HW_CIRCUIT#(h-1) and the RX FIFO corresponding to communication circuit ch1 of HW_CIRCUIT#(h+1). Here, the physical delay λ PHY This includes the internal latency of the transmitter's TX PHY, the internal latency of the receiver's RX PHY, and delays caused by transmission lines. Physical delay λ PHY This can include the waiting time at the photoelectric conversion element during reception and transmission.

[0311] After data is written to the TX FIFOs (memories 44a and 44b), the SB core circuit 41 can begin the receiving process. Writing data to the TX FIFOs corresponds to the transmitting process. After the receiver RX PHY receives data, it writes the corresponding data to the RX FIFOs (memories 45a and 45b). Then, the SB core circuit 41 writes the data stored in the RX FIFOs (memories 45a and 45b) to the buffer memories bufL and bufR. The SB core circuit 41 is stallable. Therefore, if data is not stored in either RX FIFO (either memory 45a or 45b), the SB core circuit 41 can enter a waiting state (stallable state) and not write data to the buffer memories bufL and bufR. Figure 39 In the timing diagram, before entering the reception process, the SB core circuit 41 is writing data received by the receiver RX PHY into the RX FIFO. Therefore, the RX FIFO will not become empty, thus preventing the SB core circuit 41 from entering a pause state.

[0312] exist Figure 40In the timing diagram, the SB core circuit 41 of HW_CIRCUIT#h performs the transmit operation (data is written to the TXFIFO), regardless of the operating state of other electronic circuits (HW_CIRCUIT). The transmitter TXPHYs of communication circuits ch1 and ch2 check whether any data exists in the TX FIFO (memories 44a and 44b). If data exists, the transmitter TX PHYs of communication circuits ch1 and ch2 read the data from the TX FIFO at any time and transmit the corresponding data. At the physical delay λ... PHY Subsequently, the data read from the TX FIFO of HW_CIRCUIT#h is stored in the RX FIFO corresponding to communication circuit ch2 of HW_CIRCUIT#(h-1) and the RX FIFO corresponding to communication circuit ch1 of HW_CIRCUIT#(h+1). The receiver RX PHY in communication circuit ch2 of HW_CIRCUIT#(h-1) and the receiver RX PHY in communication circuit ch1 of HW_CIRCUIT#(h+1) are in receiving mode, regardless of control from the host side (SB core circuit 41 side). Therefore, the receiver RX PHY is set to automatic operation mode. In this case, if the receiver RX PHY receives any data, the received data is written to the RX FIFO regardless of timing.

[0313] After data is written into the TX FIFO (memories 44a and 44b) by the SB core circuit 41, the receiver RX PHY of HW_CIRCUIT#h begins the receiving process. Here, writing data into the TX FIFO corresponds to the transmission process. However, if the data is not stored in the RX FIFO corresponding to either communication circuit ch1 or communication circuit ch2 of HW_CIRCUIT#h, the SB core circuit 41 can temporarily enter a waiting state (pause state). Then, if the data is stored in both the RX FIFO corresponding to communication circuit ch1 and the RX FIFO corresponding to communication circuit ch2, the SB core circuit 41 can resume the receiving process. Therefore, both HW_CIRCUIT#(h-1) and HW_CIRCUIT#(h+1) begin transmitting data. Then, after a physical delay λ has elapsed since both electronic circuits have completed data transmission... PHY After the specified period, the data is stored in the two RX FIFOs. In this case, the SB core circuit 41 exits the waiting state (pause state) and resumes the receive operation. The SB core circuit 41 can write the data stored in the RX FIFOs (memories 45a and 45b) into the buffer memories bufL and bufR.

[0314] exist Figure 40 In the timing diagram, the processes of entering and exiting the waiting state (pause state) are repeated. That is, an electronic circuit (HW_CIRCUIT) that has no data in the RX FIFO (memories 45a and 45b) can enter the waiting state. If data received from other electronic circuits is stored in the corresponding electronic circuit's RX FIFO, that electronic circuit exits the waiting state. By repeating the above operation, the operation of multiple electronic circuits can be synchronized. Through the synchronized operation of multiple electronic circuits, the timing difference can be reduced to a duration shorter than the length of a single communication phase.

[0315] Therefore, the electronic circuit may include a first FIFO memory (memory 44a), a second FIFO memory (memory 45a), a third FIFO memory (memory 45b), and a fourth FIFO memory (memory 44b). The first FIFO memory is connected between the first transmit port (transmit port TX of communication circuit ch1) and the first buffer memory (bufL). The second FIFO memory is connected between the first receive port (receive port RX of communication circuit ch1) and the second buffer memory (bufR). The third FIFO memory is connected between the second receive port (receive port RX of communication circuit ch2) and the first buffer memory. The fourth FIFO memory is connected between the second transmit port (transmit port TX of communication circuit ch2) and the second buffer memory. The third circuit may be configured to transition to a waiting state when no data is stored in either the second or fourth FIFO memory. Furthermore, the third circuit may be configured to exit the waiting state when data is stored in both the second and fourth FIFO memories.

[0316] Several implementation examples of the simulated forking algorithm have been described above. However, other configurations can be used to implement the simulated forking algorithm. Furthermore, electronic circuits or information processing devices for executing the simulated forking algorithm can be prepared by combining the above implementation examples. By using the electronic circuits or information processing devices according to the above embodiments, solutions to combinatorial optimization problems can be found in real-time. Furthermore, by using the electronic circuits or information processing devices according to the above embodiments, the optimal solution to the combinatorial optimization problem or an approximate solution closer to the optimal solution can be calculated.

[0317] In particular, by using the aforementioned information processing equipment, programs, methods, electronic circuits, and computing systems, polynomial unconstrained binary optimization (PUBO), including higher-order binary optimization (HOBO), can be solved. If information processing equipment, programs, methods, electronic circuits, and computing systems capable of handling objective functions with third-order or higher-order terms are used, it is no longer necessary to introduce penalty functions to transform objective functions with higher-order terms into quadratic functions. Therefore, by providing the aforementioned information processing equipment, programs, methods, electronic circuits, and computing systems, various combinatorial optimization problems can be solved more easily.

[0318] Embodiments of this disclosure may include the following examples.

[0319] (Example 1)

[0320] An information processing device, comprising:

[0321] A first processing circuit is configured to update a third vector based on fundamental equations, each fundamental equation being a partial derivative of an objective function with respect to any variable in the objective function, and the variable of the objective function being an element of a first vector or an element of a fourth vector, the fourth vector being computed by transforming each element in the first vector using a first function, wherein the first function takes a first value or a second value greater than the first value;

[0322] The second processing circuit is configured as follows:

[0323] The elements of the first vector are updated by adding the corresponding element of the second vector or the weighted value of the second vector to the elements of the first vector;

[0324] Set the elements of the first vector that are less than the first value to the first value;

[0325] Set the elements of the first vector that are greater than the second value to the second value; and

[0326] The elements of the second vector are updated by adding a weighted product between the first coefficient and the corresponding elements of the first vector, and adding the weighted value of the corresponding elements of the third vector, wherein the first coefficient monotonically increases or decreases based on the number of updates.

[0327] (Example 2)

[0328] According to the information processing device described in Example 1, wherein,

[0329] The second processing circuit is configured to: convert elements of the first vector that are less than a third value between the first and second values ​​into the first value; and convert elements of the first vector that are greater than the third value into the second value, in order to calculate the solution to the combinatorial optimization problem.

[0330] (Example 3)

[0331] According to the information processing device described in Example 2, wherein,

[0332] The second processing circuit is configured to calculate the solution to the combinatorial optimization problem when the number of updates to the first coefficient or the first, second, and third vectors exceeds a threshold.

[0333] (Example 4)

[0334] The information processing device according to any one of Examples 1 to 3, wherein,

[0335] The second processing circuit is configured to update the element of the second vector corresponding to the element of the first vector that is less than the first value or the element of the first vector that is greater than the second value to the product of the original value of that element in the second vector and the second coefficient.

[0336] (Example 5)

[0337] The information processing device according to any one of Examples 1 to 3, wherein,

[0338] The second processing circuit is configured to set a pseudo-random number to an element of a second vector corresponding to an element of the first vector that is less than a first value, or to an element of the second vector corresponding to an element of the first vector that is greater than a second value.

[0339] (Example 6)

[0340] The information processing device according to any one of Examples 1 to 3, wherein,

[0341] The second processing circuit is configured to update the elements of the second vector corresponding to the elements of the first vector whose absolute value is greater than 1 by multiplying a second coefficient greater than -1 and equal to or less than 0 by the original value of the second vector.

[0342] (Example 7)

[0343] The information processing device according to any one of Examples 1 to 6, wherein,

[0344] The first processing circuit is configured to update each element in the third vector based on the value of the fundamental equation transformed by the first function, wherein the value of the fundamental equation is calculated by using the elements of the first vector as variables.

[0345] (Example 8)

[0346] According to the information processing device described in Example 7, wherein...

[0347] The first processing circuit is configured to update each element in the third vector by multiplying it by a second function having a first coefficient as a parameter.

[0348] (Example 9)

[0349] The information processing device according to any one of Examples 1 to 8, wherein,

[0350] The second processing circuit is configured to update the elements of the second vector by: calculating the third coefficient by dividing the first vector norm or the fourth vector norm by the third vector norm; adding a weighted product between the corresponding elements of the first coefficient and the first vector; and adding the elements of the third vector weighted by the third coefficient.

[0351] (Example 10)

[0352] The information processing device according to any one of Examples 1 to 8, wherein,

[0353] The second processing circuit is configured to update the elements of the second vector by: calculating a third coefficient, which is the absolute value of the first inner product between the first vectors divided by the second inner product between the first vector or the fourth vector and the third vector; adding a weighted product between the first coefficient and the corresponding elements of the first vector; and adding the elements of the third vector weighted by the third coefficient.

[0354] (Example 11)

[0355] The information processing device according to any one of Examples 1 to 8, wherein,

[0356] The second processing circuit is configured to update the elements of the second vector by: calculating a third coefficient equal to the norm of the fourth vector divided by the norm of the third vector; adding a weighted product between the corresponding elements of the first coefficient and the first vector; and adding elements of the third vector weighted by the third coefficient.

[0357] (Example 12)

[0358] The information processing device according to any one of Examples 1 to 8, wherein,

[0359] The second processing circuit is configured to update the elements of the second vector by: calculating a third coefficient equal to the first inner product between the fourth vectors divided by the second inner product between the fourth and third vectors; adding a weighted product between the first coefficient and corresponding elements of the first vector; and adding elements of the third vector weighted by the third coefficient.

[0360] (Example 13)

[0361] The information processing apparatus according to any one of Examples 9 to 12, wherein,

[0362] The second processing circuit is configured to update the elements of the second vector by using a fourth coefficient instead of the third coefficient, the fourth coefficient being the value of the third coefficient converted by a low-pass filter.

[0363] (Example 14)

[0364] The information processing apparatus according to any one of Examples 9 to 13, wherein,

[0365] The first value is -1, the second value is 1, and the objective function includes terms corresponding to the energy equation of the Ising model.

[0366] (Example 15)

[0367] According to the information processing device described in Example 14, wherein...

[0368] The objective function includes multi-person interaction terms.

[0369] (Example 16)

[0370] The information processing apparatus according to any one of Examples 1 to 14, wherein,

[0371] The terms in the fundamental equations that include the first-order tensor decrease or increase monotonically depending on the number of updates.

[0372] (Example 17)

[0373] The information processing device according to any one of Examples 1 to 16 further includes:

[0374] Multiple processors;

[0375] At least one of the multiple processors used as a second processing circuit is configured to compute some elements of the first vector and some elements of the second vector.

[0376] (Example 18)

[0377] According to the information processing device described in Example 17, wherein

[0378] At least one of the multiple processors used as the first processing circuit is configured to update some elements in the third vector.

[0379] (Example 19)

[0380] The information processing device according to Example 17 or 18 further includes:

[0381] Shared memory accessible from multiple processors, wherein

[0382] The updater is configured to save the elements of the first vector to be updated or the fourth vector to be updated to shared memory.

[0383] (Example 20)

[0384] The information processing apparatus according to any one of Examples 17 to 19, wherein,

[0385] Multiple processors are the cores of the graphics processing unit.

[0386] (Example 21)

[0387] A non-transitory computer-readable medium storing a computer program that causes a computer to perform processes including the following:

[0388] The third vector is updated based on the basic equations with elements of the first or fourth vector as variables. Each basic equation is a partial derivative of the objective function with respect to any variable in the objective function, and the variables of the objective function are elements of the first vector or the fourth vector. The fourth vector is calculated by transforming each element in the first vector using the first function, which takes a first value or a second value greater than the first value.

[0389] The elements of the first vector are updated by adding the corresponding element of the second vector or the weighted value of the second vector to the elements of the first vector;

[0390] Set the elements of the first vector that are less than the first value to the first value;

[0391] Set the elements of the first vector that are greater than the second value to the second value; and

[0392] The elements of the second vector are updated by adding a weighted product between the first coefficient and the corresponding elements of the first vector, and adding the weighted value of the corresponding elements of the third vector, wherein the first coefficient monotonically increases or decreases based on the number of updates.

[0393] (Example 22)

[0394] An information processing method includes the following steps:

[0395] The third vector is updated based on the fundamental equations with elements of the first or fourth vector as variables, each fundamental equation being a partial derivative of the objective function with respect to any variable in the objective function, and the variables of the objective function being elements of the first or fourth vector, the fourth vector being computed by transforming each element in the first vector using a first function, wherein the first function takes a first value or a second value greater than the first value;

[0396] The elements of the first vector are updated by adding the corresponding element of the second vector or the weighted value of the second vector to the elements of the first vector;

[0397] Set the elements of the first vector that are less than the first value to the first value;

[0398] Set the elements of the first vector that are greater than the second value to the second value; and

[0399] The elements of the second vector are updated by adding a weighted product between the first coefficient and the corresponding elements of the first vector, and adding the weighted value of the corresponding elements of the third vector, wherein the first coefficient monotonically increases or decreases based on the number of updates.

[0400] (Example 23)

[0401] An electronic circuit, comprising:

[0402] A first circuit is configured to update a third vector based on fundamental equations having elements of a first vector or a fourth vector as variables, each fundamental equation being a partial derivative of an objective function with respect to any variable in the objective function, and the variables of the objective function being elements of the first vector or the fourth vector, the fourth vector being computed by transforming each element in the first vector using a first function, wherein the first function takes a first value or a second value greater than the first value;

[0403] The second circuit is configured as follows:

[0404] The elements of the first vector are updated by adding the corresponding element of the second vector or the weighted value of the second vector to the elements of the first vector;

[0405] Set the elements of the first vector that are less than the first value to the first value;

[0406] Set the elements of the first vector that are greater than the second value to the second value; and

[0407] The elements of the second vector are updated by adding a weighted product between the first coefficient and the corresponding elements of the first vector, and adding the weighted value of the corresponding elements of the third vector, wherein the first coefficient monotonically increases or decreases based on the number of updates.

[0408] (Example 24)

[0409] According to the electronic circuit described in Example 23, wherein,

[0410] The second circuit is configured to: convert elements of the first vector that are less than a first value and a value between the second value and a third value into the first value; and convert elements of the first vector that are greater than the third value into the second value, in order to compute a solution to the combinatorial optimization problem.

[0411] (Example 25)

[0412] According to the electronic circuit described in Example 23 or 24, wherein,

[0413] The second circuit is configured to compute a solution to the combinatorial optimization problem when the number of updates to the first coefficient or the first, second, and third vectors exceeds a threshold.

[0414] (Example 26)

[0415] The electronic circuit according to any one of Examples 23 to 25, wherein,

[0416] The second circuit is configured to update the element of the second vector corresponding to an element of the first vector that is less than a first value or an element of the first vector that is greater than a second value to the product of the original value of that element in the second vector and the second coefficient.

[0417] (Example 27)

[0418] The electronic circuit according to any one of Examples 23 to 25, wherein,

[0419] The second processing circuit is configured to set a pseudo-random number to an element of a second vector corresponding to an element of the first vector that is less than a first value, or to an element of the second vector corresponding to an element of the first vector that is greater than a second value.

[0420] (Example 28)

[0421] The electronic circuit according to any one of Examples 23 to 27, wherein,

[0422] The first circuit is configured to update each element in the third vector based on the value of the fundamental equation transformed by the first function, wherein the value of the fundamental equation is calculated by using the elements of the first vector as variables.

[0423] (Example 29)

[0424] According to the electronic circuit described in Example 28, wherein,

[0425] The first circuit is configured to update each element in the third vector by multiplying it by a second function having a first coefficient as a parameter.

[0426] (Example 30)

[0427] The electronic circuit according to any one of Examples 23 to 29 further includes:

[0428] A first memory, connected to a first input terminal of a first circuit and a second output terminal of a second circuit, is configured to store either a fourth vector or a first vector, wherein...

[0429] The first output terminal of the first circuit is connected to the second input terminal of the second circuit.

[0430] (Example 31)

[0431] The electronic circuit according to Example 30, wherein,

[0432] The first memory is configured to store each element of the fourth vector in a 1-bit format,

[0433] The first circuit includes a decoder configured to decode the 1-bit information read from the first memory into a signed binary number.

[0434] (Example 32)

[0435] The electronic circuit according to Example 30, wherein,

[0436] The first circuit is configured to calculate the elements of the third vector to be used in the next round when the second circuit calculates the elements in the first vector, the second vector, or the fourth vector based on the elements of the third vector.

[0437] (Example 33)

[0438] The electronic circuit according to any one of Examples 30 to 32, further comprising:

[0439] Pb (Pb is an integer equal to or greater than 2) first circuits; and

[0440] Pb (2 < Pb) second circuits, wherein,

[0441] Each of the Pb first circuits is connected to the first memory at a first input terminal, and

[0442] Each of the Pb second circuits: is connected to any one of the first circuits in the first circuit at a second input terminal; and is connected to the first memory at a second output terminal.

[0443] (Example 34)

[0444] The electronic circuit according to Example 33, wherein,

[0445] Each first circuit is configured to calculate the elements of the third vector by multiplying any first matrix of dimension N / Pb × Pc by any fifth vector, the first matrix is obtained by dividing an N×N dimensional coupling coefficient matrix into Pb parts, and the fifth vector can be obtained by dividing the fourth vector into Pb parts,

[0446] Each second circuit is configured to: update N / Pb elements of the first vector, N / Pb elements of the second vector, and N / Pb elements of the fourth vector based on the elements of the third vector calculated by any one of the first circuits, and store the N / Pb elements of the updated fourth vector in the first memory.

[0447] (Example 35)

[0448] According to the electronic circuit described in Example 34, wherein...

[0449] Each first circuit is configured to divide a first matrix of dimension N / Pb×Pc into a second matrix of dimension Pr×Pc, divide the fifth vector into multiple sixth vectors, and compute the elements of the third vector by performing a product operation between each second matrix and the corresponding sixth vector.

[0450] (Example 36)

[0451] The electronic circuit according to Example 34 or 35 further includes:

[0452] Pb second memories, each configured to store N / Pb elements of the first vector;

[0453] Pb third memories, each configured to store any of the first matrices;

[0454] Pb fourth memories, each configured to store N / Pb elements of the second vector; and

[0455] Pb fifth memories, each configured to store N / Pb elements of the sixth vector, where

[0456] Each second memory is connected to the second input and second output of any second circuit, each third memory is connected to the first input of any first circuit, each fourth memory is connected to the second input and second output of any second circuit, and each fifth memory is connected to the second input of any second circuit.

[0457] (Example 37)

[0458] According to the electronic circuit described in Example 36, wherein...

[0459] The second circuit includes:

[0460] A counter is configured to output a second value that monotonically increases or decreases depending on the clock cycle.

[0461] The first adder is connected to the fourth memory and the first circuit;

[0462] The first multiplier is connected to the fifth memory and the counter;

[0463] The second adder is connected to the first adder and the first multiplier;

[0464] A first arithmetic circuit connected to a second memory is configured to output a third value that increases or decreases monotonically depending on the clock cycle;

[0465] The third adder is connected to the second adder and the first arithmetic circuit;

[0466] The second arithmetic circuit is connected to the third adder and is configured to output a weighted signal from the input of the third adder;

[0467] The fourth adder is connected to the second memory and the second arithmetic circuit;

[0468] The first comparator is connected to the fourth adder; and

[0469] The first multiplexer is connected to the fourth adder and is configured to output a first constant signal of a first value or a second constant signal of a second value to the second memory based on the input of the first comparator.

[0470] (Example 38)

[0471] According to the electronic circuit described in Example 37, wherein...

[0472] Each second circuit includes:

[0473] The second comparator is connected to the fourth adder;

[0474] The second multiplexer is connected to the third adder and is configured to output a third signal to the fourth memory or output a signal from the third adder based on the input from the second comparator.

[0475] (Example 39)

[0476] According to the electronic circuit described in Example 38, wherein,

[0477] Each second circuit includes:

[0478] A third comparator is connected to a fourth adder; and

[0479] The third multiplexer is configured to output either a second constant signal or a third constant signal of a second value to the first memory based on the input from the third comparator.

[0480] (Example 40)

[0481] The electronic circuit according to any one of Examples 36 to 39, wherein...

[0482] The first memory has Pb first regions and Pb second regions.

[0483] The first and second regions are configured such that when an element of the fourth vector is broadcast from the first region to Pb first circuits, an element of the fourth vector provided from the second circuit is stored in the second region.

[0484] The first and second regions are configured such that when an element of the fourth vector is broadcast from the second region to Pb first circuits, the element of the fourth vector provided from the second circuit is stored in the first region.

[0485] (Example 41)

[0486] The electronic circuit according to any one of Examples 30 to 40 further includes:

[0487] A first communication circuit includes a first transmitting port and a first receiving port;

[0488] The second communication circuit includes a second transmitting port and a second receiving port;

[0489] A first buffer memory is connected to a first memory, a second circuit, a second receive port, and a first transmit port; and

[0490] The second buffer memory is connected to the first memory, the second circuit, the first receiving port, and the second transmitting port.

[0491] (Example 42)

[0492] The electronic circuit according to Example 41 further includes a third circuit, which is configured to:

[0493] The fourth vector, updated by Pb second circuits, is divided into first data and second data;

[0494] The first data, which is part of the separated fourth vector, is stored in the first buffer memory;

[0495] The second data, which is another part of the separated fourth vector, is stored in the second buffer memory;

[0496] The first data stored in the first buffer memory is sent from the first transmission port;

[0497] The second data stored in the second buffer memory is sent from the second transmission port;

[0498] The first data stored in the first buffer memory is saved to the first memory; and

[0499] The second data stored in the second buffer memory will be saved to the first memory.

[0500] (Example 43)

[0501] According to the electronic circuit described in Example 42, wherein

[0502] The third circuit is configured as follows:

[0503] The third data received from the second receiving port is stored in the first buffer memory;

[0504] The fourth data received from the first receiving port is stored in the second buffer memory;

[0505] Store the third data in the first memory; and

[0506] The fourth data is stored in the first memory.

[0507] (Example 44)

[0508] The electronic circuit according to any one of Examples 40 to 43 further includes:

[0509] A first FIFO memory is connected between a first transmit port and a first buffer memory;

[0510] A second FIFO memory is connected between the first receiving port and the second buffer memory;

[0511] A third FIFO memory is connected between the second receive port and the first buffer memory; and

[0512] A fourth FIFO memory is connected between the second transmit port and the second buffer memory, wherein,

[0513] The third circuit is configured to transition to a waiting state when data is not stored in both the second and fourth FIFO memories, and to exit the waiting state when data is stored in both the second and fourth FIFO memories.

[0514] (Example 45)

[0515] A computing system, comprising:

[0516] Multiple electronic circuits according to any one of Examples 40 to 44,

[0517] The first transmitting port of the electronic circuit is connected to the second receiving port of the adjacent electronic circuit.

[0518] The first receiving port of the electronic circuit is connected to the second transmitting port of the adjacent electronic circuit, thereby forming a ring communication path in both clockwise and counterclockwise directions.

[0519] The terminology used in the embodiments should be interpreted broadly. For example, the term "processor" can include a general-purpose processor, a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a controller, a microcontroller, and a state machine. Depending on the context, "processor" can refer to an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), etc. "Processor" can also refer to a combination of processing devices such as multiple microprocessors, a combination of a DSP and a microprocessor, and one or more microprocessors that work in conjunction with a DSP core.

[0520] As another example, the term "memory" can include any electronic component capable of storing electronic information. "Memory" can refer to random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable PROM (EEPROM), non-volatile random access memory (NVRAM), flash memory, and magnetic or optical data storage devices. Data stored in the devices mentioned above can be read by a processor. If the processor performs a read, a write, or both read and write operations on the memory, the memory can be considered to be in electrical communication with the processor. The memory can be integrated with the processor. Again, in this case, the memory can be considered to be in electrical communication with the processor.

[0521] The terms "storage device" or "storage equipment" can include any device that can store data using magnetic technology, optical technology, or non-volatile memory. For example, storage can be an HDD, optical disc, SSD, etc.

[0522] Although certain embodiments have been described, these embodiments are given by way of example only and are not intended to limit the scope of the invention. In fact, the novel embodiments described herein can be embodied in various other forms; furthermore, various omissions, substitutions, and changes can be made to the forms of the embodiments described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the invention.

[0523] List of reference numerals

[0524] 1. Management Server

[0525] 2. Network

[0526] 3a, 3b, 3c Computing Servers

[0527] 4a, 4b, 4c cables

[0528] 5 switches

[0529] 6. Client devices

[0530] 10 processors

[0531] 11 Management Services

[0532] 12 Converter Services

[0533] 13 Controller Services

[0534] 14 Storage devices

[0535] 14A Problem Data

[0536] 14B Calculation Data

[0537] 14C Management Procedures

[0538] 14D Conversion Program

[0539] 14E, 34C control programs

[0540] 15, 31 Communication circuits

[0541] 16 Input Circuit

[0542] 17 Output Circuit

[0543] 18 Operating equipment

[0544] 19 Display devices

[0545] 20 bus

[0546] 32 Shared memory

[0547] 33A, 33B, 33C, and 33D processors

[0548] 34 Storage devices

[0549] 34A Calculation Data

[0550] 34B Calculation Program

[0551] 35 Host Bus Adapter

[0552] 37, 38, 44, 45, 46 (repeated)

[0553] Lines 39 and 40

[0554] 41 SB core circuit

[0555] 42 Arithmetic Circuits (SB Core)

[0556] Memory modules 43, 44a, 44b, 45a, and 45b

[0557] 47 decoders

[0558] 50 Updater

[0559] 51 Multiply-Accumulator

[0560] 52-counter

[0561] 100 Information Processing System

[0562] Electronic circuits 200, 201, 202, and 208

Claims

1. An information processing device, comprising: A plurality of first processors, wherein each first processor is configured to update a first number of elements in a third vector based on a fundamental equation, each of the fundamental equations being a partial derivative of an objective function with respect to any variable in the objective function, and the variable of the objective function being an element of a first vector or an element of a fourth vector, the fourth vector being computed by transforming each element in the first vector using a first function, the first function taking a first value or a second value greater than the first value; Multiple second processors, each configured to compute a second number of elements in the first vector and a second number of elements in the second vector by: The element of the first vector is updated by adding the corresponding element of the second vector or the weighted value of the second vector to the element of the first vector; Set the elements of the first vector that are less than the first value to the first value; Set the elements of the first vector that are greater than the second value to the second value; as well as The elements of the second vector are updated by adding a weighted product between the first coefficient and the corresponding elements of the first vector to the corresponding elements of the second vector, and adding a weighted value of the corresponding elements of the third vector to the corresponding elements of the second vector, wherein the first coefficient monotonically increases or decreases based on the number of updates; and A shared memory, connected to the plurality of first processors and the plurality of second processors, and configured to store the first vector or the fourth vector; Each of the first processors is configured to compute an element of the corresponding third vector based on the partial derivative of the objective function using either the first vector or the fourth vector read from the shared memory; Each of the second processors is configured as follows: The first vector and the second vector are updated by using the third vector calculated by the corresponding first processor, and the updated first vector is stored in the shared memory; or The first vector, the second vector, and the fourth vector are updated by using the third vector calculated by the corresponding first processor, and the updated fourth vector is stored in the shared memory.

2. The information processing device according to claim 1, wherein, Each of the second processors is configured to update the element of the second vector corresponding to an element of the first vector that is less than the first value or an element of the first vector that is greater than the second value to the product of the original value of that element in the second vector and the second coefficient.

3. The information processing device according to claim 1, wherein, Each of the first processors is configured to update the elements in the corresponding third vector based on the value of the fundamental equation transformed by the first function, wherein the value of the fundamental equation is calculated using the elements of the first vector as variables.

4. The information processing device according to claim 1, wherein, Each of the second processors is configured to update the corresponding element of the second vector by: calculating a third coefficient by dividing the first vector norm or the fourth vector norm by the third vector norm; and adding a weighted product between the first coefficient and the corresponding element of the first vector to the corresponding element of the second vector. And add the elements of the third vector, weighted by the third coefficient, to the corresponding elements of the second vector.

5. The information processing device according to claim 1, wherein, Each of the second processors is configured to update the elements of the second vector by: calculating a third coefficient, which is the absolute value of a first inner product between the first vectors divided by a second inner product between the first vector or the fourth vector and the third vector; and adding a weighted product between the first coefficient and corresponding elements of the first vector to corresponding elements of the second vector. And add the elements of the third vector, weighted by the third coefficient, to the corresponding elements of the second vector.

6. The information processing device according to claim 4, wherein, Each of the second processors is configured to update elements of the second vector by using a fourth coefficient instead of the third coefficient, the fourth coefficient being the value of the third coefficient transformed by a low-pass filter.

7. The information processing device according to claim 1, wherein, The first value is -1, the second value is 1, and the objective function includes terms corresponding to the energy equation of the Ising model.

8. The information processing device according to claim 7, wherein, The objective function includes multi-body interaction terms.

9. The information processing device according to claim 1, wherein, The first quantity is equal to the number of variables in the objective function divided by the number of the first processors, and the second quantity is equal to the number of variables in the objective function divided by the number of the second processors.

10. The information processing device according to claim 1, wherein, The number of the first processors is the same as the number of the second processors.

11. The information processing device according to claim 1, wherein, The number of the first processors is different from the number of the second processors.

12. A non-transitory computer-readable medium storing a computer program executable by a computer, the computer comprising a plurality of first processors and a plurality of second processors, wherein, The execution of the computer program causes: Each of the first processors updates a first number of elements in a third vector based on a fundamental equation having elements of a first vector or a fourth vector as variables, each of the fundamental equations being a partial derivative of an objective function with respect to any variable in the objective function, and the variables of the objective function being elements of the first vector or the fourth vector, the fourth vector being computed by transforming each element in the first vector using a first function, the first function taking a first value or a second value greater than the first value; Each of the second processors calculates the second number of elements in the first vector and the second number of elements in the second vector by performing the following operations: The element of the first vector is updated by adding the corresponding element of the second vector or the weighted value of the second vector to the element of the first vector; Set the elements of the first vector that are less than the first value to the first value; Set the elements of the first vector that are greater than the second value to the second value; as well as The elements of the second vector are updated by adding the weighted product between the first coefficient and the corresponding element of the first vector to the corresponding element of the second vector and adding the weighted value of the corresponding element of the third vector to the corresponding element of the second vector, wherein the first coefficient is monotonically increased or decreased based on the number of updates; Each of the first processors is configured to compute an element of the corresponding third vector based on the partial derivative of the objective function using the first vector or the fourth vector read from the shared memory, wherein the shared memory is connected to the plurality of first processors and the plurality of second processors; Each of the second processors is configured as follows: The first vector and the second vector are updated by using the third vector calculated by the corresponding first processor, and the updated first vector is stored in the shared memory; or The first vector, the second vector, and the fourth vector are updated by using the third vector calculated by the corresponding first processor, and the updated fourth vector is stored in the shared memory.

13. The non-transitory computer-readable medium according to claim 12, wherein, The first quantity is equal to the number of variables in the objective function divided by the number of the first processors, and the second quantity is equal to the number of variables in the objective function divided by the number of the second processors.

14. The non-transitory computer-readable medium according to claim 12, wherein, The number of the first processors is the same as the number of the second processors.

15. The non-transitory computer-readable medium according to claim 12, wherein, The number of the first processors is different from the number of the second processors.

16. An information processing method, comprising the following steps: Each of a plurality of first processors updates a first number of elements in a third vector based on a fundamental equation having elements of a first vector or a fourth vector as variables, each of the fundamental equations being a partial derivative of an objective function with respect to any variable in the objective function, and the variables of the objective function being elements of the first vector or the fourth vector, the fourth vector being computed by transforming each element in the first vector using a first function, the first function taking a first value or a second value greater than the first value; Each of the plurality of second processors calculates a second number of elements in the first vector and a second number of elements in the second vector by performing the following operations: The elements of the first vector are updated by adding the corresponding element of the second vector or the weighted value of the second vector to the elements of the first vector; Set the elements of the first vector that are less than the first value to the first value; Set the elements of the first vector that are greater than the second value to the second value; as well as The elements of the second vector are updated by adding the weighted product between the first coefficient and the corresponding element of the first vector to the corresponding element of the second vector and adding the weighted value of the corresponding element of the third vector to the corresponding element of the second vector, wherein the first coefficient is monotonically increased or decreased based on the number of updates; The method further includes: Each of the first processors calculates an element of the corresponding third vector based on the partial derivative of the objective function using either the first vector or the fourth vector read from the shared memory, wherein the shared memory is connected to the plurality of first processors and the plurality of second processors; Each of the second processors updates the first vector and the second vector by using the third vector calculated by the corresponding first processor, and stores the updated first vector in the shared memory; or Each of the second processors updates the first vector, the second vector, and the fourth vector by using the third vector calculated by the corresponding first processor, and stores the updated fourth vector in the shared memory.

17. The information processing method according to claim 16, wherein, The first quantity is equal to the number of variables in the objective function divided by the number of the first processors, and the second quantity is equal to the number of variables in the objective function divided by the number of the second processors.

18. The information processing method according to claim 16, wherein, The number of the first processors is the same as the number of the second processors.

19. The information processing method according to claim 16, wherein, The number of the first processors is different from the number of the second processors.

20. An electronic circuit, comprising: A plurality of first circuits, wherein each first circuit is configured to update a first number of elements in a third vector based on a fundamental equation having elements of a first vector or a fourth vector as variables, each of the fundamental equations being a partial derivative of an objective function with respect to any variable in the objective function, and the variables of the objective function being elements of the first vector or elements of the fourth vector, the fourth vector being computed by transforming each element in the first vector using a first function, the first function taking a first value or a second value greater than the first value; Multiple second circuits, each configured to compute a second number of elements in the first vector and a second number of elements in the second vector by performing the following operations: The element of the first vector is updated by adding the corresponding element of the second vector or the weighted value of the second vector to the element of the first vector; Set the elements of the first vector that are less than the first value to the first value; Set the elements of the first vector that are greater than the second value to the second value; as well as The elements of the second vector are updated by adding the weighted product between the first coefficient and the corresponding element of the first vector to the corresponding element of the second vector and adding the weighted value of the corresponding element of the third vector to the corresponding element of the second vector, wherein the first coefficient is monotonically increased or decreased based on the number of updates; A first memory, connected to a first input of each of the first circuits and a second output of each of the second circuits, is configured to store the first vector or the fourth vector; A second memory, which is connected to the second input and the second output of each of the second circuits, is configured to store the first vector; as well as A fourth memory, which is connected to the second input and the second output of each of the second circuits, is configured to store the second vector; Each of the first circuits is configured to calculate an element of the third vector based on the partial derivative of the objective function using either the first vector or the fourth vector read from the first memory; Each of the second circuits is configured as follows: The first vector and the second vector are updated by using the third vector calculated by the corresponding first circuit, and the updated first vector is stored in the first memory; or The first vector, the second vector, and the fourth vector are updated by using the third vector calculated by the corresponding first circuit, and the updated fourth vector is stored in the first memory.

21. The electronic circuit according to claim 20, wherein, Each of the second circuits is configured to update the element of the second vector corresponding to an element of the first vector that is less than the first value or an element of the first vector that is greater than the second value to the product of the original value of that element in the second vector and the second coefficient.

22. The electronic circuit according to claim 20, wherein, Each of the first circuits is configured to update the elements in the corresponding third vector based on the value of the fundamental equation transformed by the first function, wherein the value of the fundamental equation is calculated using the elements of the first vector as variables.

23. The electronic circuit according to claim 20, wherein, The first memory is configured to store each element of the fourth vector in a 1-bit format. Each of the first circuits includes a decoder configured to decode the 1-bit information read from the first memory into a signed binary number.

24. The electronic circuit according to claim 20, wherein, Each of the first circuits is configured to calculate the elements of the third vector to be used in the next round when the corresponding second circuit calculates at least one of the elements in the first vector, the elements in the second vector, or the elements in the fourth vector based on the elements of the third vector.

25. The electronic circuit according to claim 20, wherein, Each of the first circuits is configured to compute elements of the third vector using either a first vector or a fifth vector, the fifth vector being obtained by dividing the fourth vector into M parts, where M represents the number of the second circuits.

26. The electronic circuit according to claim 25, wherein, Each of the first circuits is configured to divide the fifth vector into a plurality of sixth vectors, and to compute elements of the third vector using the sixth vectors.

27. The electronic circuit according to claim 26, wherein, The second memory is one of M second memories, each of which is configured to store the second number of elements of the first vector; The fourth memory is one of M fourth memories, each of which is configured to store the second number of elements of the second vector; as well as The electronic circuit further includes M fifth memories, each of which is configured to store the second number of elements of the sixth vector, wherein... Each of the fifth memories is connected to the second input terminal of the second circuit.

28. The electronic circuit according to claim 20, wherein, The first quantity is equal to the number of variables in the objective function divided by the number of the first circuits, and the second quantity is equal to the number of variables in the objective function divided by the number of the second circuits.

29. The electronic circuit according to claim 20, wherein, The number of the first circuit is the same as the number of the second circuit.

30. The electronic circuit according to claim 20, wherein, The number of the first circuits is different from the number of the second circuits.

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