Power line carrier communication system, power line carrier communication method and air-conditioning system

Abstract

The present invention discloses a power carrier communication system, a power carrier communication method, and an air conditioning system. The system comprises: at least two host computers and at least one slave computer; the host computer comprises: a first controller chip, an input end of which is connected to a power supply system via a first power module, and an output end of which is connected to a first end of a first transceiver; wherein the first power module is also connected to a multiplexing bus; a first transceiver, a second end of which is connected to the multiplexing bus; and a slave computer comprises: a second controller chip, an input end of which is connected to the multiplexing bus via a second power module, and an output end of which is connected to a first end of a second transceiver; wherein the second power module is also connected to the multiplexing bus; and a second transceiver, a second end of which is connected to the multiplexing bus. The present invention enables two-to-one or many-to-one communication between the host computer and the slave computer, while enabling selective power supply from the host computer to the slave computer.

Description

Technical Field

[0001] The present invention relates to the field of electronic power technology, and in particular to a power line carrier communication system, a power line carrier communication method and an air conditioning system. Background Art

[0002] Currently, there are two main 485 communication methods in the industry: one is a four-core twisted pair cable, with two cables used for communication and the other two for power; the other is a two-core twisted pair cable, which uses time-sharing for communication and power. The four-core method requires rewiring, lacks reverse protection for power and ground connections, and requires more stringent after-sales installation and factory wiring.

[0003] A two-core power cable and a time-sharing multiplexing scheme for power supply and communication are used. The upper computer requires a larger instantaneous current power supply capacity, and the lower computer requires a larger energy storage capacitor, which takes up space. In addition, the existing 485 communication scheme has poor resistance to differential mode interference and is prone to erroneous data, resulting in communication failure. Therefore, when the wired controller controls the indoor unit, it can only achieve one-to-one control, and cannot achieve two-to-one control or multiple-to-one control.

[0004] With regard to the problem in the prior art that a wired controller can only realize one-to-one control of indoor units, but cannot realize two-to-one control or multiple-to-one control, no effective solution has been proposed yet. Summary of the Invention

[0005] The embodiments of the present invention provide a power line carrier communication system, a power line carrier communication method, and an air conditioning system to solve the problem in the prior art that a wired controller can only control one indoor unit, but cannot control two indoor units or multiple indoor units.

[0006] To solve the above technical problems, the present invention provides a power line carrier communication system, wherein the system includes at least two host computers and at least one slave computer; the host computer includes:

[0007] A first controller chip, whose input end is connected to the power supply system through a first power module, and whose output end is connected to the first end of the first transceiver; wherein the first power module is also connected to the multiplexing bus;

[0008] The first transceiver has a second end connected to the multiplexed bus and is used to transmit communication signals between the first controller chip and the multiplexed bus through modulation and demodulation;

[0009] The lower computer includes:

[0010] a second controller chip, whose input end is connected to the multiplexing bus through a second power module, and whose output end is connected to the first end of the second transceiver; wherein the second power module is also connected to the multiplexing bus;

[0011] The second transceiver has a second end connected to the multiplexing bus and is used to transmit communication signals between the second controller chip and the multiplexing bus through modulation and demodulation.

[0012] Furthermore, the first transceiver includes:

[0013] a first on-off keying modulator, configured to modulate the binary signal output by the first controller chip to generate an on-off keying signal; wherein the on-off keying signal is a square wave signal having a pulse width equal to the baud rate duration of the binary signal;

[0014] a first differential signal generator, configured to generate a differential signal based on the on-off keying signal generated by the first on-off keying modulator, and transmit the differential signal to the multiplexed bus;

[0015] a first differential signal demodulator, configured to demodulate the differential signal transmitted on the multiplexed bus to generate an on-off keying signal;

[0016] The first on-off keying demodulator is configured to generate a binary signal based on the on-off keying signal generated by the first differential signal demodulator, and transmit the binary signal to the first controller chip.

[0017] Furthermore, the first on-off keying modulator includes:

[0018] A voltage-controlled oscillator, used to generate a local oscillator signal of a preset frequency;

[0019] A mixer is configured to generate an on-off keying signal based on the local oscillator signal and the binary signal.

[0020] Furthermore, the mixer outputs an on-off keying signal of a preset frequency when the value of the binary signal output by the first controller chip is 1, and outputs a low-level signal when the value of the binary signal output by the first controller chip is 0.

[0021] Furthermore, the first on-off keying demodulator includes:

[0022] Baud rate timer, used to generate baud rate duration and transmit it to the clock sampler;

[0023] The clock sampler is used to sample and detect the on-off keying signal within each baud rate duration, and determine the flag bit according to the value of the detected on-off keying signal;

[0024] A buffer is used to generate a binary signal based on the flag bit of the clock sampler.

[0025] Furthermore, the clock sampler is further configured to:

[0026] Performing multiple sampling detections on the on-off keying signal within each baud rate duration;

[0027] Each time a high level is detected within a baud rate duration, the flag is set to 1;

[0028] When a low level is detected at least once within a baud rate period, the flag position is set to 0.

[0029] Furthermore, the first transceiver further includes:

[0030] The first logic controller is used to control the frequency of the local oscillation signal generated by the voltage-controlled oscillator or the baud rate duration generated by the baud rate timer.

[0031] Furthermore, the first controller chip is also connected to the first power module via a control line, and the first controller chip is used to generate a random number to determine whether the first power module has power supply authority through the random number.

[0032] Furthermore, the second transceiver includes:

[0033] A second on-off keying modulator, configured to modulate the binary signal output by the second controller chip to generate an on-off keying signal;

[0034] a second differential signal generator, configured to generate a differential signal based on the on-off keying signal generated by the second on-off keying modulator, and transmit the differential signal to the multiplexed bus;

[0035] a second differential signal demodulator, configured to demodulate the differential signal transmitted on the multiplexed bus to generate an on-off keying signal;

[0036] The second on-off keying demodulator is configured to generate a binary signal based on the on-off keying signal generated by the second differential signal demodulator, and transmit the binary signal to the second controller chip.

[0037] Furthermore, the system further comprises:

[0038] a first isolation circuit, provided between the first power module and the multiplexed bus, for blocking the communication signal on the communication bus from being coupled to the first power module;

[0039] The second isolation circuit is provided between the second power supply module and the multiplexing bus, and is used to block the communication signal on the communication bus from being coupled to the second power supply module.

[0040] Furthermore, the first isolation circuit includes:

[0041] a first unidirectional element, disposed between the first terminal of the first power module and the first line of the multiplex bus, with an anode connected to the first terminal of the first power module and a cathode connected to the first line of the multiplex bus;

[0042] a first inductor, disposed between the first unidirectional element and the first line of the multiplexed bus;

[0043] a second unidirectional element, provided between the second terminal of the first power module and the second line of the multiplex bus, with an anode connected to the second terminal of the first power module and a cathode connected to the second line of the multiplex bus;

[0044] A second inductor is provided between the second unidirectional element and the second line of the multiplexing bus.

[0045] Furthermore, the second isolation circuit includes:

[0046] a third one-way element, a fourth one-way element, a fifth one-way element, and a sixth one-way element;

[0047] After the anode of the third unidirectional element is connected to the cathode of the fifth unidirectional element, the first line of the multiplexing bus is connected;

[0048] After the anode of the fourth unidirectional element is connected to the cathode of the sixth unidirectional element, the second line of the multiplexing bus is connected;

[0049] After the cathode of the third unidirectional element is connected to the cathode of the fourth unidirectional element, it is connected to the first terminal of the second power module;

[0050] After the anode of the fifth unidirectional element is connected to the anode of the sixth unidirectional element, the anode is connected to the second terminal of the second power module;

[0051] Furthermore, the second isolation circuit further includes:

[0052] a third inductor, a first end of which is connected to the first line of the multiplexing bus, and a second end of which is connected between the anode of the third unidirectional element and the cathode of the fifth unidirectional element;

[0053] A fourth inductor has a first end connected to the second line of the multiplexing bus, and a second end connected between the anode of the fourth unidirectional element and the cathode of the sixth unidirectional element.

[0054] Furthermore, the system further comprises:

[0055] a first capacitor provided between the first output terminal of the first transceiver and the first line of the multiplexing bus;

[0056] a second capacitor provided between the first output terminal of the first transceiver and the second line of the multiplexing bus;

[0057] The first capacitor and the second capacitor are used to couple the communication signal on the multiplexed bus to the first transceiver, or to couple the communication signal sent by the first transceiver to the multiplexed bus.

[0058] Furthermore, the system further comprises:

[0059] a third capacitor provided between the first output terminal of the second transceiver and the first line of the multiplexing bus;

[0060] a fourth capacitor, provided between the first output terminal of the second transceiver and the second line of the multiplexing bus;

[0061] The third capacitor and the fourth capacitor are used to couple the communication signal on the multiplexed bus to the second transceiver, or to couple the communication signal sent by the second transceiver to the multiplexed bus.

[0062] The present invention further provides an air-conditioning system, comprising the above-mentioned power carrier communication system, wherein the upper computer is a wired controller and the lower computer is an air-conditioning system.

[0063] The present invention further provides a power carrier communication method, which is applied to a host computer in the above power carrier communication system, and the method comprises:

[0064] Modulating the signal output by the first controller chip and transmitting it to the multiplexing bus;

[0065] The communication signal transmitted by the multiplex bus is demodulated and then transmitted to the first controller chip.

[0066] Furthermore, the signal output by the first controller chip is modulated and transmitted to the multiplexing bus, including:

[0067] After modulating the binary signal output by the first controller chip, an on-off keying signal is generated; wherein the on-off keying signal is a square wave signal with a pulse width equal to the baud rate duration of the binary signal;

[0068] A differential signal is generated based on the on-off keying signal and transmitted to the multiplexing bus.

[0069] Furthermore, after demodulating the communication signal transmitted by the multiplexed bus, the demodulated signal is transmitted to the first controller chip, including:

[0070] Demodulating the differential signal transmitted on the multiplexed bus to generate an on-off keying signal;

[0071] A binary signal is generated based on the on-off keying signal generated by the first differential signal demodulator, and is transmitted to the first controller chip.

[0072] Furthermore, the method further comprises:

[0073] Generate a random number through a controller; wherein the controller is set in a host computer and connected to the first power module;

[0074] Whether the first power supply module has power supply authority is determined by the random number.

[0075] The present invention also provides another power carrier communication method, which is applied to a lower computer in the above power carrier communication system, and includes:

[0076] Modulating the signal output by the second controller chip and transmitting it to the multiplexing bus;

[0077] The communication signal transmitted by the multiplex bus is demodulated and then transmitted to the second controller chip.

[0078] The present invention also provides a computer-readable storage medium having a computer program stored thereon, and the program implements the above-mentioned power carrier communication method when executed by a processor.

[0079] By applying the technical solution of the present invention, modulation and demodulation are performed by the first transceiver so that the communication signal is transmitted between the first controller chip and the multiplexed bus, and modulation and demodulation are performed by the second transceiver so that the communication signal is transmitted between the second controller chip and the multiplexed bus, thereby avoiding the problem that the communication signal has poor resistance to differential mode interference, easily generates erroneous data, and causes communication failure. The communication signal is transmitted between the second controller chip and the multiplexed bus, realizing two-to-one or many-to-one communication between the upper computer and the lower computer, and realizing selective power supply of the upper computer to the lower computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] Figure 1 is a structural diagram of a power line carrier communication system according to an embodiment of the present invention;

[0081] Figure 2 is an internal circuit diagram of a host computer according to an embodiment of the present invention;

[0082] Figure 3 is an internal circuit diagram of a lower computer according to an embodiment of the present invention;

[0083] Figure 4 is a structural diagram of a first transceiver according to an embodiment of the present invention;

[0084] Figure 5 is an internal circuit diagram of a first on-off keying modulator according to an embodiment of the present invention;

[0085] Figure 6 is an internal circuit diagram of a first on-off keying demodulator according to an embodiment of the present invention;

[0086] Figure 7 is an internal circuit diagram of a host computer according to another embodiment of the present invention;

[0087] Figure 8 is an internal circuit diagram of a slave computer according to another embodiment of the present invention;

[0088] Figure 9 is a flow chart of a power line carrier communication method according to an embodiment of the present invention;

[0089] Figure 10 FIG. 4 is a flow chart of a power line carrier communication method according to another embodiment of the present invention. DETAILED DESCRIPTION

[0090] To make the objectives, technical solutions, and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings. It is apparent that the embodiments described are only some, not all, of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0091] The terms used in the embodiments of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The singular forms "a," "an," "the," and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, and unless the context clearly indicates otherwise, "a plurality" generally includes at least two.

[0092] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0093] It should be understood that although the terms "first," "second," etc. may be used to describe controller chips in embodiments of the present invention, these controller chips should not be limited to these terms. These terms are merely used to distinguish controller chips disposed in different machines. For example, a first controller chip may also be referred to as a second controller chip, and similarly, a second controller chip may also be referred to as a first controller chip, without departing from the scope of embodiments of the present invention.

[0094] As used herein, the words "if" and "if" may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to the determination" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)," depending on the context.

[0095] It should also be noted that the terms "include," "comprises," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a product or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such product or device. In the absence of further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the product or device comprising the element.

[0096] The optional embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0097] Example 1

[0098] This embodiment provides a power line carrier communication system. Figure 1 FIG. 1 is a structural diagram of a power line carrier communication system according to an embodiment of the present invention. Figure 1 As shown, the system includes: the system includes at least two upper computers 1 and at least one lower computer 2; Figure 2 : is an internal circuit diagram of a host computer according to an embodiment of the present invention, such as Figure 2 As shown, the host computer 1 includes:

[0099] The first controller chip 11 has an input end connected to the power supply system through the first power module 13, and an output end connected to the first end of the first transceiver 12; Figure 1 As shown, the first power supply module 13 is also connected to the multiplex bus; the second end of the first transceiver 12 is connected to the multiplex bus, and is used to transmit the communication signal between the first controller chip 11 and the multiplex bus through modulation and demodulation.

[0100] Figure 3 : is an internal circuit diagram of a lower computer according to an embodiment of the present invention, such as Figure 3 As shown, the lower computer 2 includes: a second controller chip 21, the input end of the second controller chip 21 is connected to the multiplexing bus through a second power supply module 23, and the output end is connected to the first end of the second transceiver 22; the second power supply module 23 is also connected to the multiplexing bus; a second transceiver 22, the second end of the second transceiver 22 is connected to the multiplexing bus, and is used to transmit communication signals between the second controller chip 21 and the multiplexing bus through modulation and demodulation.

[0101] It should be noted that in this embodiment, the multiplexing bus can realize time-sharing multiplexing of the two functions of power supply and communication. One end of the first power supply module 13 in the host computer 1 is connected to the positive terminal L and the negative terminal N of the power supply system, and the other end is connected to the first line A of the multiplexing bus through the positive terminal OUTP1 and the second line A of the multiplexing bus through the negative terminal OUTN1, which is used to obtain electric energy from the power supply system, supply the multiplexing bus, and then supply the lower computer. The second power supply module 23 in the lower computer 2 is connected to the first line A of the multiplexing bus through the positive terminal INP and the second line B of the multiplexing bus through the negative terminal INN, which is used to obtain electric energy on the multiplexing bus.

[0102] The power carrier communication system of this embodiment performs modulation and demodulation by a first transceiver so that the communication signal is transmitted between the first controller chip and the multiplexed bus, and performs modulation and demodulation by a second transceiver so that the communication signal is transmitted between the second controller chip and the multiplexed bus, thereby avoiding the problem that the communication signal has poor resistance to differential mode interference, easily generates erroneous data, and causes communication failure. The communication signal is transmitted between the second controller chip and the multiplexed bus, realizing two-to-one or many-to-one communication between the upper computer and the lower computer, and realizing selective power supply from the upper computer to the lower computer.

[0103] In order to select one or several first power modules 13 to power the lower computer, as described above Figure 2 As shown in the figure, the first controller chip 11 includes a control pin PC, which is connected to the control pin PC of the first power module 13 through a control line, and is used to generate a random number to determine whether the first power module 13 has power supply authority through the random number, thereby realizing the selection of the power supply module.

[0104] Example 2

[0105] This embodiment provides another power line carrier communication system. Figure 4 FIG. 1 is a structural diagram of a first transceiver according to an embodiment of the present invention. In order to implement signal modulation and demodulation, as shown in FIG. Figure 4As shown, the first transceiver 12 includes: a first on-off keying modulator OOK Modulator1, which is used to input a binary signal 301 through the transmitting pin TX and modulate the binary signal 301 to generate an on-off keying signal 302; wherein the on-off keying signal 302 is a square wave signal with a pulse width of the baud rate duration of the binary signal 301; a first differential signal generator T1, which is used to generate two differential signals 401 and 402 based on the on-off keying signal 302, and transmit them to the first line A of the multiplexing bus and the second line B of the multiplexing bus respectively; a first differential signal demodulator R1, which is used to demodulate the differential signals 401 and 402 transmitted on the multiplexing bus to generate an on-off keying signal 202; a first on-off keying demodulator OOK Demodulator1, which is used to generate a binary signal 201 based on the on-off keying signal 202, and transmit it to the first controller chip 11 through the receiving pin RX.

[0106] Figure 5 FIG. 1 is an internal circuit diagram of a first on-off keying modulator according to an embodiment of the present invention. Figure 5 As shown, the first on-off keying modulator (OOK Modulator 1) includes a voltage-controlled oscillator (VCO) for generating a local oscillator (LO) signal 106 at a preset frequency; and a mixer (Mixer) for synthesizing a binary stream signal 301 inputted from an input port (In) and a local oscillator signal 106 inputted from a port (Lo) to generate an OOK signal 302, which is outputted from an output port (Out). When the value of the binary signal 301 outputted from the first controller chip is 1, the mixer outputs the on-off keying signal 302 at the preset frequency; and when the value of the binary signal 301 outputted from the first controller chip (11) is 0, the mixer outputs a low-level signal.

[0107] Figure 6 FIG. 1 is an internal circuit diagram of a first on-off keying demodulator according to an embodiment of the present invention. Figure 6 As shown, the first on-off keying demodulator includes: a baud rate timer Baud Rate Timer, used to generate a baud rate duration and transmit it to a clock sampler; a clock sampler Clock Sampler, used to sample and detect the on-off keying signal 202 within each baud rate duration, and determine a flag bit according to the value of the detected on-off keying signal; and a buffer 1-bit RX Buffer, used to generate a binary signal 201 based on the flag bit of the clock sampler Clock Sampler.

[0108] Since in actual applications, interference signals may exist in the signals transmitted by the multiplexed bus, resulting in errors in the ultimately generated binary signal, the clock sampler is further configured to: perform multiple sampling detections on the on-off keying signal within each baud rate duration; set a flag position to 1 when a high level is detected each time within a baud rate duration; and set a flag position to 0 when a low level is detected at least once within a baud rate duration.

[0109] Since the first on-off keying modulator OOK Modulator1 in the above scheme needs to have a certain frequency when generating the on-off keying signal 302, and the first on-off keying demodulator OOK Demodulator1 needs to have a certain baud rate duration when generating the binary signal 201, as described above, Figure 4 As shown, the first transceiver 12 further includes: a first logic controller Logic controller1, which is used to control the frequency of the local oscillation signal 106 generated by the voltage-controlled oscillator (VCO) or the baud rate duration generated by the baud rate timer (Baud Rate Timer); the first logic controller Logic controller1 is further used to output a first control signal 103 to control whether the first differential signal generator T1 is working, wherein the first control signal 103 includes a high-level signal for controlling the first differential signal generator T1 to work, and a low-level signal for controlling the first differential signal generator T1 to not work; and output a second control signal 104 to control whether the first differential signal demodulator R1 is working, wherein the second control signal 104 includes a high-level signal for controlling the first differential signal demodulator R1 to work, and a low-level signal for controlling the first differential signal demodulator R1 to not work. This enables the connection of a new device without powering off when an existing device on the bus is working, ensuring that no interference is generated on the multiplexed bus before the chip reaches normal operation.

[0110] The second transceiver 22 in the lower computer has the same structure and function as the first transceiver 12 in the upper computer 1. The second transceiver includes: a second on-off keying modulator, which is used to modulate the binary signal output by the second controller chip to generate an on-off keying signal; a second differential signal generator, which is used to generate a differential signal based on the on-off keying signal generated by the second on-off keying modulator and transmit it to the multiplexing bus; a second differential signal demodulator, which is used to demodulate the differential signal transmitted on the multiplexing bus to generate an on-off keying signal; and a second on-off keying demodulator, which is used to generate a binary signal based on the on-off keying signal generated by the second differential signal demodulator and transmit it to the second controller chip. The structure and function of the second on-off keying modulator are the same as those of the first on-off keying modulator OOK Modulator1 mentioned above, and the second on-off keying demodulator is the same as the first on-off keying demodulator OOK Demodulator1, and will not be repeated here.

[0111] Figure 7 FIG. 1 is an internal circuit diagram of a host computer according to another embodiment of the present invention. Since the multiplex bus is connected to the first power module, the communication signal on the multiplex bus may be coupled to the first power module, affecting the power supply. Therefore, Figure 7 As shown, the above-mentioned power carrier communication system also includes: a first isolation circuit 14, disposed between the first power module 13 and the multiplexed bus, for preventing communication signals on the communication bus from coupling to the first power module. The first isolation circuit 14 includes: a first unidirectional element D1, disposed between the first terminal of the first power module 13 and the first line A of the multiplexed bus, with its anode connected to the first terminal of the first power module 13 and its cathode connected to the first line of the multiplexed bus; a first inductor L1, disposed between the first unidirectional element and the first line of the multiplexed bus; a second unidirectional element D2, disposed between the second terminal of the first power module and the second line B of the multiplexed bus, with its anode connected to the second terminal of the second power module and its cathode connected to the second line of the multiplexed bus; and a second inductor L2, disposed between the second unidirectional element and the second line of the multiplexed bus. The large inductive reactance XL generated by the first inductor L1 and the second inductor L2 prevents high-frequency carrier communication signals on the two multiplexed buses from coupling to the first power module 13.

[0112] The communication signal on the multiplexed bus is generally of high frequency, and the capacitor has the characteristics of high pass and low resistance. Therefore, in order to couple the high frequency communication signal on the multiplexed bus to the first transceiver 12, and at the same time couple the communication signal sent by the first transceiver 12 to the multiplexed bus, Figure 7As shown, the above system also includes: a first capacitor C1, which is arranged between the first output terminal of the first transceiver 12 and the first line A of the multiplexing bus, and a second capacitor C2, which is arranged between the first output terminal of the first transceiver and the second line of the multiplexing bus; the first capacitor C1 and the second capacitor C2 are used to couple the communication signal on the multiplexing bus to the first transceiver 12, or to couple the communication signal sent by the first transceiver 12 to the multiplexing bus.

[0113] Figure 8 FIG. 1 is an internal circuit diagram of a lower computer according to another embodiment of the present invention. Since the multiplex bus is connected to the second power module, the communication signal on the multiplex bus may be coupled to the second power module, affecting the power supply. Therefore, Figure 8 As shown, the above-mentioned power carrier communication system further includes:

[0114] The second isolation circuit 24 is provided between the second power module and the multiplexing bus, and is used to block the communication signal on the communication bus from being coupled to the second power module.

[0115] To achieve non-polarity power supply, the second isolation circuit includes: a third unidirectional element D3, a fourth unidirectional element D4, a fifth unidirectional element D5, and a sixth unidirectional element D6; the anode of the third unidirectional element D3 is connected to the cathode of the fifth unidirectional element D5, and then connected to the first line A of the multiplexing bus; the anode of the fourth unidirectional element D4 is connected to the cathode of the sixth unidirectional element, and then connected to the second line of the multiplexing bus; the cathode of the third unidirectional element D3 is connected to the cathode of the fourth unidirectional element D4, and then connected to the first terminal of the second power module 23; the anode of the fifth unidirectional element D5 is connected to the anode of the sixth unidirectional element D6, and then connected to the second terminal of the second power module 23;

[0116] In order to achieve isolation, the above-mentioned second isolation circuit 24 also includes: a third inductor L3, whose first end is connected to the first line A of the multiplexing bus, and whose second end is connected between the anode of the third unidirectional element D3 and the cathode of the fifth unidirectional element D5; a fourth inductor L4, whose first end is connected to the second line B of the multiplexing bus, and whose second end is connected between the anode of the fourth unidirectional element D4 and the cathode of the sixth unidirectional element D6.

[0117] The communication signal on the multiplexed bus is generally of high frequency, and the capacitor has the characteristics of high pass and low resistance. Therefore, in order to couple the high frequency communication signal on the multiplexed bus to the first transceiver 12, and at the same time couple the communication signal sent by the first transceiver 12 to the multiplexed bus, Figure 8As shown, the above system also includes: a third capacitor C3, arranged between the first output terminal of the second transceiver 22 and the first line A of the multiplexed bus, and a fourth capacitor C4, arranged between the first output terminal of the second transceiver 22 and the second line B of the multiplexed bus; the third capacitor C3 and the fourth capacitor C4 are used to couple the communication signal on the multiplexed bus to the second transceiver 22, or to couple the communication signal sent by the second transceiver 22 to the multiplexed bus.

[0118] Example 3

[0119] This embodiment provides a power line carrier communication method, which is applied to a host computer in the above power line carrier communication system. Figure 9 FIG. 1 is a flow chart of a power line carrier communication method according to an embodiment of the present invention. Figure 9 As shown, the method includes:

[0120] S101, modulating the signal output by the first controller chip and transmitting the modulated signal to the multiplexing bus.

[0121] During specific implementation, the signal output by the first controller chip is modulated by the first transceiver and then transmitted to the multiplexing bus.

[0122] S102 , demodulating the communication signal transmitted by the multiplexed bus and transmitting the demodulated signal to the first controller chip.

[0123] In a specific implementation, the communication signal transmitted by the multiplexing bus is demodulated by the first transceiver and then transmitted to the first controller chip. The first end of the first transceiver is connected to the first controller chip, and the second end is connected to the multiplexing bus.

[0124] The power carrier communication method of this embodiment, by modulating and demodulating the communication signal, avoids the problem that the communication signal has poor resistance to differential mode interference, easily generates erroneous data, and causes communication failure. The communication signal is transmitted between the first controller chip and the multiplexed bus, thereby realizing two-to-one or many-to-one communication between the upper computer and the lower computer.

[0125] Specifically, step S102 includes: modulating the binary signal output by the first controller chip to generate an on-off keying signal; wherein the on-off keying signal is a square wave signal with a pulse width equal to the baud rate duration of the binary signal; generating a differential signal based on the on-off keying signal and transmitting it to the multiplexing bus. Modulating the binary signal output by the first controller chip to generate an on-off keying signal includes: generating a local oscillator signal of a preset frequency through a voltage-controlled oscillator; and generating an on-off keying signal based on the local oscillator signal and the binary signal through a mixer. Specifically, the mixer outputs an on-off keying signal of a preset frequency when the value of the binary signal output by the first controller chip is 1, and outputs a low-level signal when the value of the binary signal output by the first controller chip is 0.

[0126] Step S102 specifically includes: demodulating the differential signal transmitted on the multiplexed bus to generate an on-off keying signal; generating a binary signal based on the on-off keying signal generated by the first differential signal demodulator, and transmitting the binary signal to the first controller chip. Generating the binary signal based on the on-off keying signal generated by the first differential signal demodulator specifically includes: generating a baud rate duration using a baud rate timer and transmitting the baud rate duration to a clock sampler; sampling and detecting the on-off keying signal within each baud rate duration using the clock sampler, and determining a flag bit based on the value of the detected on-off keying signal; and generating a binary signal based on the flag bit of the clock sampler using a buffer.

[0127] Since in actual applications, there may be interference signals in the signals transmitted by the multiplexed bus, resulting in errors in the final generated binary signal, the communication signal transmitted by the multiplexed bus is demodulated and transmitted to the first controller chip, which also includes: multiple sampling detections of the on-off keying signal within each baud rate duration; each time a high level is detected within a baud rate duration, the flag position is set to 1; each time a low level is detected at least once within a baud rate duration, the flag position is set to 0.

[0128] Since the first on-off keying modulator OOK Modulator1 in the above scheme needs to have a certain frequency when generating the on-off keying signal 302, and the first on-off keying demodulator OOK Demodulator1 needs to have a certain baud rate duration when generating the binary signal 201, therefore, after the binary signal output by the first controller chip is modulated, the on-off keying signal is generated, or the baud rate duration is generated by the baud rate timer and transmitted to the clock sampler, the above steps also include: controlling the frequency of the local oscillator signal generated by the voltage-controlled oscillator or the baud rate duration generated by the baud rate timer through the first logic controller.

[0129] In order to select one or several first power modules 13 to power the lower computer, the above method also includes: generating a random number through a controller; wherein the controller is set in the upper computer and connected to the first power module; and determining whether the first power module has power supply authority through the random number.

[0130] Example 4

[0131] This embodiment provides another power carrier communication method, which is applied to the lower computer in the above power carrier communication system. Figure 10 FIG. 1 is a flow chart of a power line carrier communication method according to another embodiment of the present invention. Figure 10 As shown, the method includes:

[0132] S201, modulating the signal output by the second controller chip and transmitting it to the multiplexing bus;

[0133] During specific implementation, the signal output by the second controller chip is modulated by the second transceiver and then transmitted to the multiplexing bus.

[0134] S202 , demodulating the communication signal transmitted by the multiplexed bus and transmitting the demodulated signal to the second controller chip.

[0135] In a specific implementation, the communication signal transmitted by the multiplexing bus is demodulated by the second transceiver and then transmitted to the first controller chip. The first end of the second transceiver is connected to the second controller chip, and the second end is connected to the multiplexing bus.

[0136] The power carrier communication method of this embodiment, by modulating and demodulating the communication signal, avoids the problem that the communication signal has poor resistance to differential mode interference, easily generates erroneous data, and causes communication failure. The communication signal is transmitted between the second controller chip and the multiplexed bus, thereby realizing two-to-one or many-to-one communication between the upper computer and the lower computer.

[0137] It should be noted that, in this embodiment, the signal output by the second controller chip is modulated and then transmitted to the multiplexing bus;

[0138] In a specific implementation, the signal output by the second controller chip is modulated by the second transceiver and transmitted to the multiplexed bus. Also, the communication signal transmitted by the multiplexed bus is demodulated and transmitted to the second controller chip. The specific steps are the same as those in the above embodiment 3 and will not be repeated here.

[0139] Example 5

[0140] This embodiment provides another power carrier communication system, which includes: the system includes at least two host computers and at least one slave computer, wherein the connection block diagram of the at least two host computers and the at least one slave computer is as mentioned above. Figure 1 As mentioned above Figure 2 As shown in FIG, the host computer 1 includes a first power module 13, an isolation circuit 14, a first transceiver 12, and a first controller chip 11, the core components mentioned above. The slave computer 2 includes a second power module 23, a second isolation circuit 24, a second transceiver 22, and a second controller chip 21, the core components mentioned above.

[0141] As mentioned above Figure 7As shown in the figure, a first inductor L1 and a second inductor L2 are connected in series between the first power module 13 of the host computer 1 and the two multiplexed buses, respectively. The first inductor L1 and the second inductor L2 generate a large inductive reactance XL to block the high-frequency carrier communication signals on the two multiplexed buses from coupling to the first power module 13; a first capacitor C1 and a second capacitor C2 are connected in series between the first transceiver 12 and the two multiplexed buses, respectively. The first capacitor C1 and the second capacitor C2 generate a small capacitive reactance XC to couple the high-frequency carrier communication signals on the two multiplexed buses to the first transceiver 12, or couple the high-frequency carrier communication signals emitted by the first transceiver 12 to the two multiplexed buses; after the host computer 1 is powered on, it temporarily does not power the lower computer 2. The first controller chip 11 in the host computer 1 generates a random number to compete for the power supply authority of the first power module 13. The first controller chip 11 that obtains the power supply authority controls the first power module 13 connected thereto to power the two multiplexed buses, thereby powering the lower computer.

[0142] As mentioned above Figure 8 As shown in the figure, a third inductor L3 and a fourth inductor L4 are respectively connected in series between the second power supply module 23 of the lower computer and the two multiplexed buses, and the third inductor L3 and the fourth inductor L4 are used to block the high-frequency carrier communication signals on the two multiplexed buses from coupling to the second power supply module 23; a third capacitor C3 and a fourth capacitor C4 are respectively connected in series between the second transceiver 22 and the two multiplexed buses, and are used to couple the high-frequency carrier communication signals on the communication bus to the second transceiver 22, or couple the high-frequency carrier communication signals of the signal transceiver chip to the two multiplexed buses.

[0143] In order to avoid reverse connection of the power supply line, a unidirectional component group is further added between the second power supply module 23 and the multiplexing bus to achieve non-polarity power supply.

[0144] As mentioned above Figure 4As shown in , the first transceiver 12 includes: a first on-off keying modulator OOKModulator1, a first on-off keying demodulator OOK Demodulator1, a first differential signal generator R1, a first differential signal demodulator T1, and a first logic controller Logic controller1. When the first controller chip 11 sends a communication signal to the multiplexing bus, the binary stream signal 301 sent by the first controller chip 11 enters the OOK Modulator 1 and is modulated into an OOK (on-off keying) signal 302. The OOK signal 302 enters the differential signal generator T through the transmitting pin TX to generate two differential carrier signals 401 and 402, which are respectively transmitted to the first line A of the multiplexing bus and the second line B of the multiplexing bus; when the first controller chip 11 receives a communication signal from the multiplexing bus, the two differential carrier signals 401 and 402 enter the differential signal demodulator R and are demodulated into the OOK signal 202. The OOK signal 202 enters the OOK Demodulator 1 and is restored to a binary stream signal, which is transmitted to the first controller chip 11 through the receiving interface RX.

[0145] As mentioned above Figure 5 As shown in FIG, OOK Modulator 1 includes a mixer and a voltage-controlled oscillator (VCO). The VCO generates a local oscillator (LO) signal 106 with a frequency of Fc based on the frequency information 105 output by the logic controller 1. The mixer synthesizes the binary stream signal 301 inputted from the input port In and the local oscillator signal 106 inputted from the port Lo to generate an OOK signal 302, which is outputted from the output port Out. The OOK signal 302 generated here is a square wave signal with a pulse width equal to the baud rate duration of the binary stream signal 301. When the value of the binary stream signal is 1, the OOK signal 302 with a frequency of Fc is outputted. When the value of the binary signal is 0, a continuous low level is outputted. The above steps realize the conversion of the binary stream signal 301 into the OOK 302 signal.

[0146] The differential signal generator T converts the OOK signal 302 into a differential signal. Based on the OOK signal 302, two sine / cosine signals 401 and 402 are generated with a phase difference of 180°. When the OOK signal 302 does not change, the two output sine / cosine signals 401 and 402 do not change. When the OOK signal 302 changes, the two output sine / cosine signals 401 and 402 change accordingly.

[0147] The differential signal demodulator demodulates the differential signals 401 and 402 into an OOK signal 202. Based on two sine / cosine signals 401 and 402 with a phase difference of 180°, an OOK signal 202 is generated. The generated OOK signal 202 is a square wave signal with a pulse width of half the period of the differential signals 401 and 402. When the voltage difference Vdif between the two sine / cosine signals 401 and 402 with a phase difference of 180° exceeds a set value Vt, the value of the OOK signal 202 is high. When the voltage difference Vdif between the two sine / cosine signals 401 and 402 with a phase difference of 180° is lower than the set value Vt, the value of the OOK signal 202 is low.

[0148] As mentioned above Figure 6 As shown in FIG, OOK Demodulator 1 includes a clock sampler, a baud rate timer, and a 1-bit RX buffer.

[0149] The clock sampler internally stores an invalid flag position 0, a valid flag position 1, and an integrator, and is used to sample and detect the OOK signal 202 with a baud rate duration as a sampling period to determine whether the detected signal value is a high level or a low level. If it is a high level, the valid flag position of the integrator is set to 1; if it is a low level, the valid flag position of the integrator is set to 0. The clock sampler is also used to determine whether the input signal is an interference signal and implement the interference signal filtering function. Specifically, multiple samplings are performed within a sampling period to determine whether the signal values detected within a sampling period are all high levels. If so, the OOK signal 202 is determined to be a normal signal, and the integrator records the valid flag position 1 and then clears it to zero. If not, the input signal is determined to be an interference signal, and the integrator's flag position is set to 0 and then cleared to zero.

[0150] The 1-bit RX buffer outputs a 1-bit binary digit 1 when the valid flag position of the integrator is 1, and outputs a 1-bit binary digit 0 when the valid flag position of the integrator is 0.

[0151] The baud rate timer is used to generate a baud rate duration based on the baud rate duration information 102 output by the logic controller, provide it to the clock sampler, and determine whether a baud rate duration has been reached. Each time the baud rate duration is reached, the 1-bit RX buffer is controlled to output a 1-bit binary digit.

[0152] The power carrier communication system of this embodiment can realize 485 non-polarity communication and high-power non-polarity power supply, and can be widely applied to all products using 485 communication.

[0153] The system embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, i.e., they may be located in one place or distributed across multiple network elements. Some or all of these modules may be selected to achieve the objectives of this embodiment based on actual needs.

[0154] Example 6

[0155] This embodiment provides an air-conditioning system, including the power carrier communication system in the above embodiment. In this air-conditioning system, the upper computer is a wire controller and the lower computer is an air conditioner. Through the above power carrier communication system, two-to-one or many-to-one communication between the upper computer and the lower computer is achieved, and selective power supply from the upper computer to the lower computer is achieved.

[0156] Example 7

[0157] This embodiment provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the power carrier communication method of the embodiment is implemented.

[0158] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0159] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A power carrier communication system, characterized in that: The system includes at least two host computers and at least one slave computer; the host computer includes: A first controller chip, whose input end is connected to the power supply system through a first power module, and whose output end is connected to the first end of the first transceiver; wherein the first power module is also connected to the multiplexing bus; The first transceiver has a second end connected to the multiplexed bus and is used to transmit communication signals between the first controller chip and the multiplexed bus through modulation and demodulation; The lower computer includes: a second controller chip, whose input end is connected to the multiplexing bus through a second power module, and whose output end is connected to the first end of the second transceiver; wherein the second power module is also connected to the multiplexing bus; The second transceiver has a second end connected to the multiplexing bus and is used to transmit communication signals between the second controller chip and the multiplexing bus through modulation and demodulation.

2. The system according to claim 1, wherein: The first transceiver includes: a first on-off keying modulator, configured to modulate the binary signal output by the first controller chip to generate an on-off keying signal; wherein the on-off keying signal is a square wave signal having a pulse width equal to the baud rate duration of the binary signal; a first differential signal generator, configured to generate a differential signal based on the on-off keying signal generated by the first on-off keying modulator, and transmit the differential signal to the multiplexed bus; a first differential signal demodulator, configured to demodulate the differential signal transmitted on the multiplexed bus to generate an on-off keying signal; The first on-off keying demodulator is configured to generate a binary signal based on the on-off keying signal generated by the first differential signal demodulator, and transmit the binary signal to the first controller chip.

3. The system according to claim 2, characterized in that The first on-off keying modulator comprises: A voltage-controlled oscillator, used to generate a local oscillator signal of a preset frequency; A mixer is configured to generate an on-off keying signal based on the local oscillator signal and the binary signal.

4. The system according to claim 3, characterized in that The mixer outputs an on-off keying signal of a preset frequency when the value of the binary signal output by the first controller chip is 1, and outputs a low-level signal when the value of the binary signal output by the first controller chip is 0.

5. The system according to claim 2, wherein: The first on-off keying demodulator comprises: Baud rate timer, used to generate baud rate duration and transmit it to the clock sampler; The clock sampler is used to sample and detect the on-off keying signal within each baud rate duration, and determine the flag bit according to the value of the detected on-off keying signal; A buffer is used to generate a binary signal based on the flag bit of the clock sampler.

6. The system according to claim 5, characterized in that The clock sampler is further configured to: Performing multiple sampling detections on the on-off keying signal within each baud rate duration; Each time a high level is detected within a baud rate duration, the flag is set to 1; When a low level is detected at least once within a baud rate period, the flag position is set to 0.

7. The system according to claim 3 or 5, characterized in that The first transceiver further includes: A first logic controller is used to control the frequency of a local oscillator signal generated by a voltage-controlled oscillator or the baud rate duration generated by a baud rate timer; wherein the voltage-controlled oscillator is arranged in a first on-off keying modulator to generate a local oscillator signal of a preset frequency; the baud rate timer is arranged in a first on-off keying demodulator to generate a baud rate duration and transmit it to a clock sampler in the first on-off keying demodulator.

8. The system according to claim 1, wherein: The first controller chip is also connected to the first power module via a control line. The first controller chip is used to generate a random number to determine whether the first power module has power supply authority through the random number.

9. The system according to claim 1, wherein: The second transceiver includes: A second on-off keying modulator, configured to modulate the binary signal output by the second controller chip to generate an on-off keying signal; a second differential signal generator, configured to generate a differential signal based on the on-off keying signal generated by the second on-off keying modulator, and transmit the differential signal to the multiplexed bus; a second differential signal demodulator, configured to demodulate the differential signal transmitted on the multiplexed bus to generate an on-off keying signal; The second on-off keying demodulator is configured to generate a binary signal based on the on-off keying signal generated by the second differential signal demodulator, and transmit the binary signal to the second controller chip.

10. The system according to claim 1, wherein: The system further comprises: a first isolation circuit, provided between the first power module and the multiplexed bus, for blocking the communication signal on the communication bus from being coupled to the first power module; The second isolation circuit is provided between the second power supply module and the multiplexing bus, and is used to block the communication signal on the communication bus from being coupled to the second power supply module.

11. The system according to claim 10, wherein: The first isolation circuit includes: a first unidirectional element, disposed between the first terminal of the first power module and the first line of the multiplex bus, with an anode connected to the first terminal of the first power module and a cathode connected to the first line of the multiplex bus; a first inductor, disposed between the first unidirectional element and the first line of the multiplexed bus; a second unidirectional element, provided between the second terminal of the first power module and the second line of the multiplex bus, with an anode connected to the second terminal of the first power module and a cathode connected to the second line of the multiplex bus; A second inductor is provided between the second unidirectional element and the second line of the multiplexing bus.

12. The system according to claim 10, wherein: The second isolation circuit includes: a third one-way element, a fourth one-way element, a fifth one-way element, and a sixth one-way element; After the anode of the third unidirectional element is connected to the cathode of the fifth unidirectional element, the first line of the multiplexing bus is connected; After the anode of the fourth unidirectional element is connected to the cathode of the sixth unidirectional element, the second line of the multiplexing bus is connected; After the cathode of the third unidirectional element is connected to the cathode of the fourth unidirectional element, it is connected to the first terminal of the second power module; After the anode of the fifth unidirectional element is connected to the anode of the sixth unidirectional element, it is connected to the second terminal of the second power module.

13. The system according to claim 12, wherein: The second isolation circuit further includes: a third inductor, a first end of which is connected to the first line of the multiplexing bus, and a second end of which is connected between the anode of the third unidirectional element and the cathode of the fifth unidirectional element; A fourth inductor has a first end connected to the second line of the multiplexing bus, and a second end connected between the anode of the fourth unidirectional element and the cathode of the sixth unidirectional element.

14. The system according to claim 1, wherein: The system further comprises: a first capacitor provided between the first output terminal of the first transceiver and the first line of the multiplexing bus; a second capacitor provided between the first output terminal of the first transceiver and the second line of the multiplexing bus; The first capacitor and the second capacitor are used to couple the communication signal on the multiplexed bus to the first transceiver, or to couple the communication signal sent by the first transceiver to the multiplexed bus.

15. The system according to claim 1, wherein: The system further comprises: a third capacitor provided between the first output terminal of the second transceiver and the first line of the multiplexing bus; a fourth capacitor, provided between the first output terminal of the second transceiver and the second line of the multiplexing bus; The third capacitor and the fourth capacitor are used to couple the communication signal on the multiplexed bus to the second transceiver, or to couple the communication signal sent by the second transceiver to the multiplexed bus.

16. An air conditioning system, comprising the power carrier communication system according to any one of claims 1 to 15, characterized in that: The upper computer is a wired controller, and the lower computer is an air conditioner.

17. A power line carrier communication method, applied to a host computer in a power line carrier communication system according to any one of claims 1 to 15, characterized in that: The method comprises: Modulating the signal output by the first controller chip and transmitting it to the multiplexing bus; The communication signal transmitted by the multiplex bus is demodulated and then transmitted to the first controller chip.

18. The method according to claim 17, characterized in that Modulating the signal output by the first controller chip and transmitting it to the multiplexing bus includes: After modulating the binary signal output by the first controller chip, an on-off keying signal is generated; wherein the on-off keying signal is a square wave signal with a pulse width equal to the baud rate duration of the binary signal; A differential signal is generated based on the on-off keying signal and transmitted to the multiplexing bus.

19. The method according to claim 17, wherein After demodulating the communication signal transmitted by the multiplexed bus, the demodulated signal is transmitted to the first controller chip, including: Demodulating the differential signal transmitted on the multiplexed bus to generate an on-off keying signal; A binary signal is generated based on the on-off keying signal generated by the first differential signal demodulator, and is transmitted to the first controller chip.

20. The method according to claim 17, wherein The method further comprises: Generate a random number through a controller; wherein the controller is set in a host computer and connected to the first power module; Whether the first power supply module has power supply authority is determined by the random number.

21. A power carrier communication method, applied to a lower computer in a power carrier communication system according to any one of claims 1 to 15, characterized in that: The method comprises: Modulating the signal output by the second controller chip and transmitting it to the multiplexing bus; The communication signal transmitted by the multiplex bus is demodulated and then transmitted to the second controller chip.

22. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 17 to 21 is implemented.

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