A digital communication bus level detection circuit
By designing a digital communication bus level detection circuit, detecting external VDDIO levels and shaping signals, the problem of logic level chaos in the internal chip is solved, and correct digital communication and communication is achieved, saving chip area.
Patent Information
- Application Number
- CN202110145178.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-02-02
- Publication Date
- 2025-04-04
- Estimated Expiration
- 2041-02-02
AI Technical Summary
The existing digital communication bus SDA and SCL lines in the internal chip are difficult to accurately detect external VDDIO levels due to the influence of semiconductor process, temperature and power supply voltage, resulting in logic levels confusion, which may lead to communication failure or errors.
A digital communication bus level detection circuit is designed, connected to external VDDIO through an external port, and a level detector is used to detect the high level of the SCL or SDA pin, and it is used as the logic high level of the waveform shaping circuit to shape the external serial clock and data signal. The level conversion circuit uses the power supply VDD of the internal communication circuit as the logic high level to convert the signal to adapt to the internal communication logic.
It realizes the correct communication and communication between the inside and outside, avoids the need to increase the additional interface power pins and chip area, and ensures the correctness and stability of digital communication.
Smart Images
Figure CN112798852B_ABST
Abstract
Description
[Technical field]
[0001] The present invention relates to the technical field of digital communication bus, and in particular to a digital communication bus level detection circuit. [Background technology]
[0002] The current digital communication bus SDA (serial data line) SCL (serial clock line) has an open-drain or open-collector structure. The client needs to pull up the resistor (R1 / R2) and then connect to the external interface level VDDIO. Since the internal chip circuit is affected by the semiconductor process, temperature and chip power supply voltage VDD, it needs to know the level gradient of the external VDDIO, otherwise the logic level will be confused, resulting in communication failure or error. The existing practice is to directly add a dedicated pin in the internal chip as an interface for internal and external communication power to indicate the logic level of SDA and SCL, which not only increases the chip layout area, but also increases the package size and the number of pins, which is very costly.
[0003] Therefore, it is necessary to propose a new technical solution to solve the above problems. [Summary of the invention]
[0004] One of the purposes of the present invention is to provide a digital communication bus level detection circuit, which forms a correct communication exchange between the inside and the outside, does not require additional interface power pins, and saves chip area.
[0005] According to one aspect of the present invention, the present invention provides a digital communication bus level detection circuit, which includes: an external port 1, which is connected to an external port power supply VDDIO; an internal serial clock pin 2, which is connected to an external serial clock line SCL to receive an external serial clock signal SCL; an internal serial data pin 3, which is connected to an external serial data line SDA to receive an external serial data signal SDA; a first pull-up resistor R1, which is connected between the internal serial clock pin 2 and the external port 1; a second pull-up resistor R2, which is connected between the internal serial data pin 3 and the external port 1; a level detector, which is used to detect a high level of the internal serial clock pin 2 or the internal serial data pin 3, and convert it into a high level. The detected high level is used as a reference high level VDT, and the reference high level VDT is output through the first output terminal of the level detector; a waveform shaping circuit, whose first input terminal receives the external serial clock signal SCL, whose second input terminal receives the external serial data signal SDA, and whose third input terminal receives the reference high level VDT, and the waveform shaping circuit uses the reference high level VDT as a logic high level, shapes the external serial data signal SDA to obtain a rectangular pulse, and the rectangular pulse is the shaped external serial data signal SDAP, and shapes the external serial clock signal SCL to obtain a rectangular pulse, and the rectangular pulse is the shaped external serial clock signal SCLP.
[0006] Furthermore, the digital communication bus level detection circuit also includes a level conversion circuit, a first input end of the level conversion circuit is connected to the shaped external serial clock signal SCLP, a second input end of the level conversion circuit is connected to the shaped external serial data signal SDAP, and a power supply end of the level conversion circuit is connected to the power supply VDD of the internal communication circuit 140. The level conversion circuit uses the power supply VDD of the internal communication circuit 140 as a logic high level, performs level conversion on the shaped external serial data signal SDAP to obtain an internal serial data signal SDAin, and performs level conversion on the shaped external serial clock signal SCLP to obtain an internal serial clock signal SCLin, wherein the internal serial data signal SDAin is connected to an internal serial data line in the internal communication circuit, and the internal serial clock signal SCLin is connected to an internal serial clock line in the internal communication circuit.
[0007] Further, the waveform shaping circuit includes a first Schmitt trigger and a second Schmitt trigger, wherein the first Schmitt trigger is connected to the external serial clock signal SCL, and its power supply end is connected to the reference high level VDT. The first Schmitt trigger uses the reference high level VDT as the logic high level to shape the external serial clock signal SCL to obtain an ideal rectangular pulse, which is the shaped external serial clock signal SCLP, and the shaped external serial clock signal SCLP is output by the output end of the first Schmitt trigger 122; the input end of the second Schmitt trigger is connected to the external serial data signal SDA, and its power supply end is connected to the reference high level VDT. The second Schmitt trigger uses the reference high level VDT as the logic high level to shape the external serial data signal SDA to obtain an ideal rectangular pulse, which is the shaped external serial data signal SDAP, and the shaped external serial data signal SDAP is output by the output end of the second Schmitt trigger 124. .
[0008] Furthermore, the level conversion circuit includes a first level converter and a second level converter, the input end of the first level converter is connected to the shaped external serial clock signal SCLP, and the power supply end thereof is connected to the power supply VDD of the internal communication circuit. The first level converter uses the power supply VDD of the internal communication circuit as a logic high level and performs level conversion on the shaped external serial clock signal SCLP to obtain an internal serial clock signal SCLin; the input end of the second level converter is connected to the shaped external serial data signal SDAP, and the power supply end thereof is connected to the power supply VDD of the internal communication circuit. The second level converter uses the power supply VDD of the internal communication circuit as a logic high level and performs level conversion on the shaped external serial data signal SDAP to obtain an internal serial data signal SDAin.
[0009] Furthermore, the external port 1 is any external port of a digital communication bus.
[0010] Furthermore, the level gradient of the power supply VDD of the internal communication circuit is greater than or equal to the external port power supply VDDIO.
[0011] Furthermore, the first input end of the level detector is connected to the internal serial clock pin 2 to receive the external serial clock signal SCL, the second input end of the level detector is connected to the internal serial data pin 3 to receive the external serial data signal SDA, the second output end of the level detector outputs the external serial clock signal SCL received by its first input end, and the third output end of the level detector outputs the external serial data signal SDA received by its second input end; the first input end of the shaping circuit is connected to the second output end of the level detector to receive the external serial clock signal SCL; the second input end of the shaping circuit is connected to the third output end of the level detector to receive the external serial data signal SDA.
[0012] Furthermore, the level detector stores the reference high level VDT through an internal capacitor; the level value of the reference high level VDT is approximately equal to the external port power supply VDDIO.
[0013] Compared with the prior art, the digital communication bus level detection circuit in the present invention firstly detects the high level of the SDA pin or the SCL pin by means of any external port, the SDA pin or the SCL pin of the digital communication bus, and uses it as the logic high level of the waveform shaping circuit, and the waveform shaping circuit converts the external serial clock signal SCL and the external serial data signal SDA into adaptive correct logic levels; then, the level conversion circuit uses the power supply VDD of the internal communication circuit as the logic level to obtain the internal serial data signal SDAin and the internal serial clock signal SCLin, and provides them to the internal communication circuit for use, thereby achieving the purpose of correctly configuring the internal digital communication logic level, forming correct communication between the inside and the outside, and not requiring additional interface power pins, but also saving chip area.
Brief Description of the Drawings
[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:
[0015] Figure 1 FIG. 4 is a circuit diagram of a digital communication bus level detection circuit in one embodiment of the present invention. [Specific implementation method]
[0016] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0017] The term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the words "connected", "connected", and "connected" herein that indicate electrical connection all refer to direct or indirect electrical connection.
[0018] Please refer to Figure 1 As shown, it is a circuit diagram of a digital communication bus level detection circuit in one embodiment of the present invention. Figure 1 The digital communication bus level detection circuit shown includes an external port 1, an internal serial clock pin 2, an internal serial data pin 3, a first pull-up resistor R1, a second pull-up resistor R2, a level detector 110, a waveform shaping circuit 120, a level conversion circuit 130 and an internal communication circuit 140.
[0019] Among them, the external port (or external communication power interface) 1 is connected to the external port power supply (or external port level) VDDIO; the internal serial clock pin 2 is connected to the external serial clock line SCL to receive the external serial clock signal SCL; the internal serial data pin 3 is connected to the external serial data line SDA to receive the external serial data signal SDA; the first pull-up resistor R1 is connected between the internal serial clock pin 2 and the external port 1; the second pull-up resistor R2 is connected between the internal serial data pin 3 and the external port 1.
[0020] The first input terminal of the level detector 110 is connected to the internal serial clock pin 2 to receive the external serial clock signal SCL, and the second input terminal is connected to the internal serial data pin 3 to receive the external serial data signal SDA. The level detector 110 is used to detect the high level of the internal serial clock pin 2 or the internal serial data pin 3, and use the detected high level as the reference high level VDT, which is output through the first output terminal of the level detector 110. Specifically, the level detector 110 stores the reference high level VDT through an internal capacitor; the level value of the reference high level VDT is approximately equal to the external port power supply VDDIO. In addition, Figure 1 In the specific embodiment shown, the second output terminal of the level detector 110 outputs the external serial clock signal SCL received at the first input terminal thereof, and the third output terminal thereof outputs the external serial data signal SDA received at the second input terminal thereof.
[0021] The first input terminal of the waveform shaping circuit 120 is connected to the second output terminal of the level detector 110 to receive the external serial clock signal SCL, the second input terminal thereof is connected to the third output terminal of the level detector 110 to receive the external serial data signal SDA, and the third input terminal thereof is connected to the first output terminal of the level detector 110 to receive the reference high level VDT. The waveform shaping circuit 120 uses the reference high level VDT as the logic high level to shape the external serial data signal SDA to obtain an ideal rectangular pulse, which is the shaped external serial data signal SDAP, and shapes the external serial clock signal SCL to obtain an ideal rectangular pulse, which is the shaped external serial clock signal SCLP. That is, the logic high levels of the shaped external serial data signal SDAP and the shaped external serial clock signal SCLP are the reference high level VDT.
[0022] exist Figure 1 In the specific embodiment shown, the waveform shaping circuit 120 includes a first Schmitt trigger 122 and a second Schmitt trigger 124. The input end of the first Schmitt trigger 122 is connected to the second output end of the level detector 110 to receive the external serial clock signal SCL, and its power supply end is connected to the reference high level VDT. The first Schmitt trigger 122 uses the reference high level VDT as the logic high level to shape the external serial clock signal SCL to obtain an ideal rectangular pulse, which is the shaped external serial clock signal SCLP. The shaped external serial clock signal SCLP is output from the output end of the first Schmitt trigger 122. The input end of the second Schmitt trigger 124 is connected to the third output end of the level detector 110 to receive the external serial data signal SDA. The power supply end is connected to the reference high level VDT. The second Schmitt trigger 124 uses the reference high level VDT as the logic high level to shape the external serial data signal SDA to obtain an ideal rectangular pulse. The ideal rectangular pulse is the shaped external serial data signal SDAP. The shaped external serial data signal SDAP is output from the output end of the second Schmitt trigger 124.
[0023] The first input end of the level conversion circuit 130 is connected to the output end of the first Schmitt trigger 122 to receive the shaped external serial clock signal SCLP, the second input end thereof is connected to the output end of the second Schmitt trigger 124 to receive the shaped external serial data signal SDAP, and the power end thereof is connected to the power supply VDD of the internal communication circuit 140 (or the internal chip power supply). The level conversion circuit 130 uses the power supply VDD of the internal communication circuit 140 as the logic high level, performs level conversion on the shaped external serial data signal SDAP to obtain the internal serial data signal SDAin, and performs level conversion on the shaped external serial clock signal SCLP to obtain the internal serial clock signal SCLin. The internal serial data signal SDAin is connected to the internal serial data line in the internal communication circuit 140, and the internal serial clock signal SCLin is connected to the internal serial clock line in the internal communication circuit 140. That is, the logic high level of the internal serial data signal SDAin and the internal serial clock signal SCLin is the power supply VDD of the internal communication circuit 140. In this way, during internal and external digital communication, the levels of the external serial clock signal SCL and the external serial data signal SDA can achieve the equivalent levels of the internal serial clock signal SCLin and the serial data signal SDAin, achieving the correct digital serial port logic signal and realizing the purpose of communication.
[0024] exist Figure 1 In the specific embodiment shown, the level conversion circuit 130 includes a first level converter 132 and a second level converter 134, wherein the input end of the first level converter 132 is connected to the output end of the first Schmitt trigger 122 to receive the shaped external serial clock signal SCLP, and the power supply end thereof is connected to the power supply VDD of the internal communication circuit 140. The first level converter 132 uses the power supply VDD of the internal communication circuit 140 as a logic high level to perform level conversion on the shaped external serial clock signal SCLP to obtain an internal serial clock signal SCLin; the input end of the second level converter 134 is connected to the output end of the second Schmitt trigger 124 to receive the shaped external serial data signal SDAP, and the power supply end thereof is connected to the power supply VDD of the internal communication circuit 140. The second level converter 134 uses the power supply VDD of the internal communication circuit 140 as a logic high level to perform level conversion on the shaped external serial data signal SDAP to obtain an internal serial data signal SDAin.
[0025] It should be noted that the external port 1 is any external port of the digital communication bus; the level gradient of the power supply VDD of the internal communication circuit 140 is greater than or equal to the external port power supply VDDIO.
[0026] In summary, in the digital communication bus level detection circuit of the present invention:
[0027] First, with the help of any external port of the digital communication bus, the SDA pin (i.e., the internal serial data pin 3) or the SCL pin (i.e., the internal serial clock pin 2), the level detector 110 detects the high level of the SDA pin or the SCL pin, and this high level is called an internal reference voltage (or reference high level VDT), which serves as the logic high level of the waveform shaping circuit 120. The waveform shaping circuit 120 converts the external serial clock signal SCL and the external serial data signal SDA into adaptive correct logic levels (i.e., the shaped external serial clock signal SCLP and the shaped external serial data signal SDAP) and outputs them, thereby generating a reliable adaptive level output that changes with the external port power supply VDDIO through self-detection.
[0028] Then, the level conversion circuit 130 uses the power supply VDD of the internal communication circuit 140 as the logic level, converts the shaped external serial clock signal SCLP and the shaped external serial data signal SDAP into the internal serial clock signal SCLin and the internal serial data signal SDAin respectively, and provides them to the internal communication circuit 140 for use. Since the logic high level of the internal serial data signal SDAin and the internal serial clock signal SCLin is consistent with the power supply VDD of the internal communication circuit 140, the purpose of correctly configuring the internal digital communication logic level is achieved, and correct communication between the inside and the outside is formed (or the internal and external communication is correct), which does not require additional interface power pins and saves chip area. In addition, the present invention is not easily affected by the process, temperature and the power supply VDD of the internal communication circuit 140, and the client can use a wide range of external port power VDDIO.
[0029] In the present invention, words such as “connect”, “connected”, “connected”, “connected”, etc. indicating electrical connection, if not otherwise specified, indicate direct or indirect electrical connection.
[0030] The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiment. Any equivalent modifications or changes made by ordinary technicians in this field based on the disclosure of the present invention should be included in the protection scope recorded in the claims.
Claims
1. A digital communication bus level detection circuit, characterized in that: It includes: An external port (1), which is connected to an external port power supply (VDDIO); An internal serial clock pin (2), which is connected to an external serial clock line (SCL) to receive an external serial clock signal (SCL); An internal serial data pin (3), which is connected to an external serial data line (SDA) to receive an external serial data signal (SDA); A first pull-up resistor (R1) connected between the internal serial clock pin (2) and the external port (1); A second pull-up resistor (R2) connected between the internal serial data pin (3) and the external port (1); A level detector, which is used to detect a high level of the internal serial clock pin (2) or the internal serial data pin (3), and use the detected high level as a reference high level (VDT), wherein the reference high level (VDT) is output through a first output terminal of the level detector; A waveform shaping circuit, wherein a first input terminal receives the external serial clock signal (SCL), a second input terminal receives the external serial data signal (SDA), and a third input terminal receives the reference high level (VDT). The waveform shaping circuit uses the reference high level (VDT) as a logic high level, shapes the external serial data signal (SDA) to obtain a rectangular pulse, which is the shaped external serial data signal (SDAP), and shapes the external serial clock signal (SCL) to obtain a rectangular pulse, which is the shaped external serial clock signal (SCLP); A level conversion circuit, wherein a first input end is connected to the shaped external serial clock signal (SCLP), a second input end is connected to the shaped external serial data signal (SDAP), and a power supply end is connected to a power supply (VDD) of an internal communication circuit. The level conversion circuit uses the power supply (VDD) of the internal communication circuit as a logic high level, performs level conversion on the shaped external serial data signal (SDAP) to obtain an internal serial data signal (SDAin), and performs level conversion on the shaped external serial clock signal (SCLP) to obtain an internal serial clock signal (SCLin). The internal serial data signal (SDAin) is connected to the internal serial data line in the internal communication circuit, and the internal serial clock signal (SCLin) is connected to the internal serial clock line in the internal communication circuit; the first input end of the level detector is connected to the internal serial clock pin (2) to receive the external serial clock signal (SCL), and the second input end of the level detector is connected to the internal serial data pin (3) to receive the external serial data signal (SDA); the second output end of the level detector outputs the external serial clock signal (SCL) received by its first input end, and the third output end of the level detector outputs the external serial data signal (SDA) received by its second input end; the first input end of the shaping circuit is connected to the second output end of the level detector to receive the external serial clock signal (SCL); and the second input end of the shaping circuit is connected to the third output end of the level detector to receive the external serial data signal (SDA).
2. The digital communication bus level detection circuit according to claim 1, characterized in that: The waveform shaping circuit includes a first Schmitt trigger and a second Schmitt trigger, The first Schmitt trigger is connected to the external serial clock signal (SCL), and its power supply terminal is connected to a reference high level (VDT). The first Schmitt trigger uses the reference high level (VDT) as a logic high level to shape the external serial clock signal (SCL) to obtain an ideal rectangular pulse, which is the shaped external serial clock signal (SCLP). The shaped external serial clock signal (SCLP) is output from the output terminal of the first Schmitt trigger; The input end of the second Schmitt trigger is connected to the external serial data signal (SDA), and the power supply end thereof is connected to a reference high level (VDT). The second Schmitt trigger uses the reference high level (VDT) as a logic high level to shape the external serial data signal (SDA) to obtain an ideal rectangular pulse. The ideal rectangular pulse is the shaped external serial data signal (SDAP). The shaped external serial data signal (SDAP) is output from the output end of the second Schmitt trigger.
3. The digital communication bus level detection circuit according to claim 1, characterized in that: The level conversion circuit includes a first level converter and a second level converter. The input end of the first level converter is connected to the shaped external serial clock signal (SCLP), and the power end thereof is connected to the power supply (VDD) of the internal communication circuit. The first level converter uses the power supply (VDD) of the internal communication circuit as a logic high level to perform level conversion on the shaped external serial clock signal (SCLP) to obtain an internal serial clock signal (SCLin); The input end of the second level converter is connected to the shaped external serial data signal (SDAP), and the power supply end thereof is connected to the power supply (VDD) of the internal communication circuit. The second level converter uses the power supply (VDD) of the internal communication circuit as a logic high level and performs level conversion on the shaped external serial data signal (SDAP) to obtain an internal serial data signal (SDAin).
4. The digital communication bus level detection circuit according to claim 1, characterized in that: The external port (1) is any external port of a digital communication bus.
5. The digital communication bus level detection circuit according to claim 1, characterized in that: The level gradient of the power supply (VDD) of the internal communication circuit is greater than or equal to the external port power supply (VDDIO).
6. The digital communication bus level detection circuit according to claim 1, characterized in that: The level detector stores the reference high level (VDT) through an internal capacitor; The level value of the reference high level (VDT) is equal to the external port power supply (VDDIO).
Citation Information
Patent Citations
Digital communication bus level detection circuit
CN215728389U