Voltage Feedback Continuity Fault Detection in Voltage Regulators

Abstract

Embodiments of the present disclosure disclose voltage feedback continuity fault detection in a voltage regulator. A controller for a power converter includes: a first sensing terminal and a second sensing terminal for sensing an output voltage of the power converter; a bridge circuit configured to electrically couple the first sensing terminal to the second sensing terminal in a first state and electrically decouple the first sensing terminal from the second sensing terminal in a second state; and a control circuit system configured to set the bridge circuit to the first state during a portion of a voltage ramp-up of the power converter, and to determine whether an open circuit or short circuit fault condition exists at the first sensing terminal or the second sensing terminal based on a voltage across the bridge circuit in the first state.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a controller for a power converter, a method of operating a controller for a power converter, and an electronic system. Background Art

[0002] Voltage regulators typically have a feedback path for sensing the voltage close to the regulation loop. Catastrophic failure can occur if an open or short-circuit continuity defect occurs in the feedback path. Most voltage regulators implement overvoltage / undervoltage, overcurrent, and overtemperature protection as the primary means of protecting the regulator from component failure or manufacturing errors. Open or short-circuit faults in the feedback path used to sense the regulator's output voltage are often detected as a combination of other fault types, such as overtemperature and / or overvoltage. However, this approach generally cannot guarantee reliable detection of all open and short-circuit fault conditions in the voltage sensing feedback path.

[0003] Therefore, there is a need for improved voltage feedback continuity fault detection in a voltage regulator. Summary of the Invention

[0004] According to an embodiment of a controller for a power converter, the controller includes: a first sensing terminal and a second sensing terminal for sensing an output voltage of the power converter; a bridge circuit configured to electrically couple the first sensing terminal to the second sensing terminal in a first state and to electrically decouple the first sensing terminal from the second sensing terminal in a second state; and a control circuit system configured to set the bridge circuit to a first state during a portion of a voltage ramp-up of the power converter and to determine whether an open circuit or short circuit fault condition exists at the first sensing terminal or the second sensing terminal based on a voltage across the bridge circuit in the first state.

[0005] According to an embodiment of a method of operating a controller for a power converter, the method includes: sensing an output voltage of the power converter across a first sensing terminal and a second sensing terminal of the controller; during a portion of a voltage ramp of the power converter, setting a bridge circuit of the controller to a first state to electrically couple the first sensing terminal to the second sensing terminal; during a later portion of the voltage ramp, setting the bridge circuit to a second state to electrically decouple the first sensing terminal from the second sensing terminal; and determining whether an open circuit or short circuit fault condition exists at the first sensing terminal or the second sensing terminal based on the voltage across the bridge circuit in the first state.

[0006] According to an embodiment of an electronic system, the electronic system includes: a microprocessor; a memory coupled to the microprocessor; a power converter configured to regulate a power supply voltage of the microprocessor; and a controller for the power converter, the controller including: a first sensing terminal and a second sensing terminal for sensing the power supply voltage; a bridge circuit configured to electrically couple the first sensing terminal to the second sensing terminal in a first state and to electrically decouple the first sensing terminal from the second sensing terminal in a second state; and a control circuit system configured to set the bridge circuit to a first state during a portion of a voltage ramp of the power converter and to determine whether an open circuit or short circuit fault condition exists at the first sensing terminal or the second sensing terminal based on a voltage across the bridge circuit in the first state.

[0007] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The elements in the drawings are not necessarily to scale relative to each other. The same reference numerals denote corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. The embodiments are depicted in the drawings and described in detail in the following description.

[0009] Figure 1 A block diagram of an embodiment of a controller for a power converter is shown.

[0010] Figure 2 A schematic diagram of an embodiment of a bridge circuit included in a power converter controller is shown.

[0011] Figure 3 A schematic diagram of another embodiment of a bridge circuit is shown.

[0012] Figure 4 A table showing different fault conditions that can be detected using the voltage feedback continuity fault detection technique described herein.

[0013] Figure 5 A block diagram illustrating an embodiment of a digital controller implementation of a power converter controller is shown.

[0014] Figure 6 Various waveforms are shown that occur when a fault is detected during the voltage feedback continuity fault detection technique.

[0015] Figure 7 Various waveforms are shown that occur when no fault is detected during the voltage feedback continuity fault detection technique.

[0016] Figure 8 Shown include Figure 1A block diagram of an embodiment of an electronic system including one or more power converters is shown. DETAILED DESCRIPTION

[0017] The described embodiments provide a voltage feedback continuity fault detection technique for a power converter. The voltage feedback continuity fault detection technique involves monitoring the voltage feedback line of the power converter to detect continuity faults such as open circuits or short circuits. The voltage feedback continuity fault detection technique described herein allows the power converter to be shut down quickly to avoid damage and reports the actual source of the problem.

[0018] The term "power converter" as used herein broadly refers to any type of power converter or voltage regulator (VR) that provides one or more regulated voltages to one or more electronic loads such as an Ethernet switch, an ASIC (application-specific integrated circuit), a memory device, a processor such as a central processing unit (CPU), a microprocessor, a graphics processing unit (GPU), a digital signal processor (DSP), an artificial intelligence (AI) accelerator, an image processor, a network or packet processor, a coprocessor, a multi-core processor, a front-end processor, a baseband processor, etc. For example, the power converter can be a buck converter, a boost converter, a buck-boost converter, a switched capacitor voltage regulator, a step-down converter, etc. The power converter can be implemented as a power device module.

[0019] The term "power device module" as used herein refers to a packaged functional component that includes at least one power switch of a power stage for converting voltage from one level to another, for example, as done in power conversion and voltage regulation. The power device module may also include a driver circuit for driving the at least one power switch. The power device module may additionally include a controller for controlling the driver circuit to implement a power converter. The controller and / or driver functions may alternatively be implemented outside the power device module. The driver circuit for at least one power switch included in the power device module may also be outside the power device module. Various passive components such as capacitors and / or inductors that constitute the power converter may be included in the power device module, surface mounted to the power device module, located on a separate board, etc. Various embodiments of the power converter, the method of controlling the power converter, and the electronic system including the power converter are described in more detail below.

[0020] Figure 1An embodiment of a controller 100 for a power converter (VR) 102 is shown. The VR controller 100 can be implemented as an analog controller or a digital controller. For ease of illustration, the power converter 102 is shown as a buck converter that includes one or more power stages 104 coupled to a load 106. For example, the power converter 102 can include a single power stage 104 in a single-phase implementation or more than one power stage 104 in a multi-phase implementation. The VR controller 100 includes control circuitry 108 for controlling each power stage 104 included in the power converter 102 to regulate a supply voltage (Vout) for the load 106.

[0021] The load 106 powered by the power converter 102 may be a high-performance integrated circuit, such as a microprocessor, a graphics processor, a network processor, etc., or other types of integrated circuits requiring voltage regulation, such as POLs (point-of-load), memories, etc. The power converter 102 may provide one or more regulated supply voltages, depending on the configuration of the power converter 102 and the number of power stages / phases 104.

[0022] The controller 100 of the power converter 102 also includes a current sensing and balancing circuit 110 for sensing the phase current (Iph) delivered by each power stage 104 at a corresponding current sensing terminal Isen of the VR controller 100 and converting the sensed current information into phase current information. The current sensing and balancing circuit 110 also converts the phase current information into adjustments to the duty cycle generated by the VR controller 100 (the duty cycle generated by the VR controller 100 for each individual power stage 104) to adjust the phase currents so that they remain balanced in the case of multi-phase operation.

[0023] The VR controller 100 also includes a voltage sensing circuit 112 for determining the error between the output voltage (Vout) and the target voltage (Vtgt). In the case of a digital controller, the voltage sensing circuit 112 converts the error voltage into a digital representation that is provided to the control circuit system 108. Again in the case of a digital controller, the control circuit system 108 of the VR controller 100 may include a pulse width modulator (PWM) for switching each power stage 104. The control circuit system 108 of the VR controller 100 adjusts the duty cycle and / or switching frequency of each power stage 104 based on the current information provided by the current sensing and balancing circuit 110 and the voltage information provided by the voltage detection circuit 112 to maintain the desired regulation of the output voltage Vout. The control circuit system 108 of the VR controller 100 can implement further control features such as feedforward control.

[0024] The VR controller 100 has a first voltage sensing terminal Vsenp and a second voltage sensing terminal Vsenn for sensing the output voltage Vout of the power converter 102. The voltage sensing terminals Vsenp and Vsenn of the VR controller 100 provide an interface for connection with corresponding voltage sensing lines 114. The first voltage sensing terminal Vsenp of the VR controller 100 may be a positive sensing terminal, and the second voltage sensing terminal Vsenn of the VR controller 100 may be a negative sensing terminal or a reference (ground) sensing terminal.

[0025] Although the regulator output voltage Vout is shown as being sensed across the output capacitor Cout, this is for ease of illustration and understanding only. The sense line 114 connected to the voltage sense terminals Vsenp, Vsenn of the VR controller 100 need not be directly connected to the output capacitor Cout as shown. For example, the voltage sense line 114 can be connected to the respective voltage sense terminals Vsenp, Vsenn of the VR controller 100 at one end and to the I / O (input / output) circuitry of the power stage 104 at the opposite end.

[0026] Typically, a voltage sense line 114 connected to the voltage sense terminals Vsenp and Vsenn of the VR controller 100 carries a voltage corresponding to the output voltage Vout of the power converter 102, such that the voltage sense circuit 112 can directly measure / sense the regulator output voltage Vout at the first voltage sense terminal Vsenp and the second voltage sense terminal Vsenn of the VR controller 100. The voltage sense terminals Vsenp and Vsenn of the VR controller 100 can be physically implemented as pins, connectors, terminal blocks, etc.

[0027] Included in or associated with the voltage sensing circuit 112 of the VR controller 100 is a bridge circuit 116 that is used by the control circuitry 108 of the VR controller 100 to implement the voltage feedback continuity fault detection techniques described herein. The bridge circuit 116 is configured to electrically couple a first voltage sensing terminal Vsenp of the VR controller 100 to a second voltage sensing terminal Vsenn of the VR controller 100 in a first state, and to electrically decouple the voltage sensing terminals Vsenp, Vsenn in a second state.

[0028] The control circuitry 108 of the VR controller 100 sets the bridge circuit 116 to a first state during a portion of the voltage ramp of the power converter 102 and determines whether an open circuit or short circuit fault condition exists at the first voltage sensing terminal Vsenp of the VR controller 100 or at the second voltage sensing terminal Vsenn of the VR controller 100 based on the voltage across the bridge circuit 116 in the first state. If no fault condition exists on the sense line 114 connected to the voltage sensing terminals Vsenp, Vsenn of the VR controller 100, the voltage across the bridge circuit 116 in the first state should rise above a threshold within a defined time window.

[0029] However, if a short circuit or open circuit fault exists on any of the voltage sense lines 114, the voltage across the bridge circuit 116 in the first state will not rise above the threshold within the defined time window. The control circuitry 108 of the VR controller 100 detects this voltage condition as a fault and may shut down the power converter 102 and / or report the fault condition to the load 106, for example.

[0030] If the control circuitry 108 of the VR controller 100 determines that the power converter output voltage Vout is ramping up properly, the control circuitry 108 sets the bridge circuit 116 to a second state during a later portion of the voltage ramp-up period, such that the bridge circuit 116 is disabled and does not interfere with the normal operation of the power converter 102. The bridge circuit 116 can be controlled in this manner during each ramp-up of the regulated voltage Vout to implement a voltage feedback continuity fault detection technique and determine whether an open circuit or short circuit fault condition exists at either of the voltage sense terminals Vsenp and Vsenn of the VR controller 100. For example, the power converter 102 may be powered / activated, but the load 106 may be inactive, such as in a sleep mode. In this condition, the power converter 102 provides little or no power to the load 106. When the load 106 resumes operation and a ramp-up of the regulated voltage Vout is required, the voltage feedback continuity fault detection technique can be executed again by the control circuitry 108 of the VR controller 100.

[0031] If there is no fault at either of the voltage sense terminals Vsenp, Vsenn of the VR controller 100, current should flow through the bridge circuit 116. However, if the output voltage Vout of the power converter 102 rises too much, the current through the bridge circuit 116 may become dangerously high. In one embodiment, the control circuitry 108 of the VR controller 100 implements a timer or state machine (SM) 118 for controlling the bridge circuit 116 during the ramp-up process of the power converter 102 to avoid excessive current conditions.

[0032] Figure 2 FIG2 shows an embodiment of a bridge circuit 116. According to this embodiment, the voltage sensing circuit 108 of the VR controller 100 includes a first I / O buffer 200 electrically connected to a first voltage sensing terminal Vsenp of the VR controller 100 and a second I / O buffer 202 electrically connected to a second voltage sensing terminal Vsenn of the VR controller 100. Each I / O buffer 200, 202 may include a current limiting resistor Rlim, diode clamps D1 / D2 for clamping the voltage to a certain level "VDD33," and a driver transistor Q1 such as a MOSFET. The bridge circuit 116 includes a switching device 204, a first resistor R1 electrically connected between the first voltage sensing terminal Vsenp of the VR controller 100 and the switching device 204, and a second resistor R2 electrically connected between the second voltage sensing terminal Vsenn of the VR controller 100 and the switching device 204. The first resistor R1 , the switching device 204 , and the second resistor R2 are electrically connected in series between the voltage sensing terminals Vsenp and Vsenn of the VR controller 100 .

[0033] The first resistor R1 forms a first resistor divider with the first I / O buffer 200, and the second resistor R2 forms a second resistor divider with the second I / O buffer 202. In one embodiment, the control circuitry 108 of the VR controller 100 utilizes the resistor divider to determine whether the voltage across the bridge circuit 116 in the first state rises above a threshold within a defined time window, and therefore whether any fault condition exists on the sense line 114 connected to the voltage sense terminals Vsenp, Vsenn of the VR controller 100.

[0034] As part of the voltage feedback continuity fault detection technique, the control circuitry 108 of the VR controller 100 provides a signal "en_osp" that determines the state of the switching device 204. For example, when the signal en_osp is active (e.g., logic high), the switching device 104 electrically couples the first voltage sensing terminal Vsenp of the VR controller 100 to the second voltage sensing terminal Vsenn of the VR controller 100, and the control circuitry 108 of the VR controller 100 determines whether an open circuit or short circuit fault condition exists at either of the voltage sensing terminals Vsenp and Vsenn based on the voltage across the bridge circuit 116 in this state. When the signal en_osp subsequently becomes inactive (e.g., logic low), the switching device 204 electrically decouples the first voltage sensing terminal Vsenp from the second voltage sensing terminal Vsenn, so that the bridge circuit 116 does not interfere with normal operation of the power converter 102.

[0035] Figure 3An embodiment of a switching device 204 of the bridge circuit 116 is shown. According to this embodiment, the switching device 204 includes a pMOS transistor P1 and an nMOS transistor N1. The switching device 204 may also include diode clamps D3 / D4 between each resistor R1, R2 of the bridge circuit 116 and the corresponding transistors P1, N1 of the switching device 204 to clamp the voltages at the upper and lower legs of the bridge circuit 116 to a certain level "VDD33".

[0036] The source of the pMOS transistor P1 and the drain of the nMOS transistor N1 are electrically connected to the first resistor R1. The source of the nMOS transistor N1 and the drain of the pMOS transistor P1 are electrically connected to the second resistor R2. Figure 3 In the illustrated embodiment, signal en_OSP generated by control circuitry 108 of VR controller 100 is a gate signal applied to the gate of pMOS transistor P1. An inverted version of signal en_OSP is applied to the gate of nMOS transistor N1. This causes both transistors P1 and N1 of switching device 204 to be simultaneously turned on or off. When both transistors P1 and N1 of switching device 204 are turned on, the first voltage sense terminal Vsenp of VR controller 100 is electrically coupled to the second voltage sense terminal Vsenn of VR controller 100. Conversely, when both transistors P1 and N1 of switching device 204 are turned off, the first voltage sense terminal Vsenp of VR controller 100 is electrically decoupled from the second voltage sense terminal Vsenn of VR controller 100 via switching device 204.

[0037] In the case where the control circuit system 108 of the VR controller 100 is a digital controller, the bridge circuit 116 may further include a level shifter 300. The level shifter 300 is configured to level-shift the signal en_OSP generated by the control circuit system 108 of the VR controller 100 from a lower voltage domain of the control circuit system 108 to a higher voltage domain of the voltage sensing terminals Vsenp and Vsenn of the VR controller 100. For example, the level shifter 300 may level-shift the signal en_OSP from 1.2V ( Figure 3 ”1P2” in FIG1 is shifted to 3.3V (“3P3”) of the voltage sensing terminals Vsenp and Vsenn of the VR controller 100.

[0038] Figure 4 1 shows an embodiment of a fault that may be detected by the VR controller 100 using the voltage feedback continuity fault detection technique described herein. Figure 4The first row of the table in shows different possible states detected by the control circuitry 108 of the VR controller 100 at the first voltage sensing terminal Vsenp of the VR controller 100. The states include an open circuit fault (“open”), a short circuit fault (“short(Gnd)”), and a normal / expected voltage level (“VSENP”) in the absence of a fault. Figure 4 The second row of the table in shows different possible states detected by the control circuit system 108 of the VR controller 100 at the second voltage sensing terminal Vsenn of the VR controller 100. The states include an open circuit fault (“open”), a short circuit fault (“short (Gnd)”), and a normal / expected voltage level (“Gnd”) in the absence of a fault. Figure 4 , the normal / expected voltage level at the second voltage sensing terminal Vsenn of the VR controller 100 is identified as ground (“Gnd”) because, according to this embodiment, the voltage sensing line 114 connected to the second voltage sensing terminal Vsenn of the VR controller 100 is coupled to ground.

[0039] Figure 4 The third row of the table in shows the voltage difference (in volts) between the voltage sensing terminals Vsenp, Vsenn of the VR controller 100 when the voltage sensing terminals Vsenp, Vsenn of the VR controller 100 are electrically coupled to each other through the bridge circuit 116 during the first portion of the voltage ramp-up of the power converter 102, which is measured / sensed by the voltage sensing circuit 112 of the VR controller 100. Figure 4 The fourth row of the table in shows whether the control circuit system 108 of the VR controller 100 generates a fault (“Fault”) or no fault (“OK”) signal based on the voltage difference measured / sensed by the voltage sensing circuit 112 when the voltage sensing terminals Vsenp, Vsenn of the VR controller 100 are electrically coupled by the switching device 204 during the first part of the voltage ramp of the power converter 102.

[0040] In one embodiment, the VR controller 100 includes an analog-to-digital converter (ADC) 120 for converting a voltage measured / sensed across the bridge circuit 116 when the voltage sense terminals Vsenp, Vsenn of the VR controller 100 are electrically coupled to a digital representation by the switching device 204. If an open circuit or short circuit fault condition exists at either of the voltage sense terminals Vsenp, Vsenn of the VR controller 100, the digital representation of the voltage measured / sensed across the bridge circuit 116 in this condition remains below a threshold value for a defined time window. If an open circuit or short circuit fault condition does not exist at the first voltage sense terminal Vsenp of the VR controller 100 and the second voltage sense terminal Vsenn of the VR controller 100 is grounded or shorted to ground, the digital representation of the voltage measured / sensed across the bridge circuit 116 in this condition rises above the threshold value during the defined time window because the second voltage sense terminal Vsenn of the VR controller 100 is referenced to ground according to this embodiment.

[0041] Detected by the VR controller and Figure 4 The conditions listed in the last row of the table in are described in the context of an example in which the current limiting resistors Rlim of the I / O buffers 200, 202 are each 40K ohms, the branch resistors R1 and R2 of the bridge circuit 116 are each 950 ohms, the threshold voltage of the drive transistor Q1 of the I / O buffers 200, 202 is 0.7V, and the threshold voltage for detecting a fault condition is 0.25V.

[0042] If the two sensing lines 114 connected to the voltage sensing terminals Vsenp and Vsenn of the VR controller 100 have an open circuit fault ( Figure 4 2 in FIG), the voltage measured / sensed across the bridge circuit 116 is 0V.

[0043] If the sensing line 114 connected to the first (positive) voltage sensing terminal Vsenp of the VR controller 100 has an open circuit fault, and the sensing line 114 connected to the second (reference) voltage sensing terminal Vsenp of the VR controller 100 is connected to the ground or has a short circuit fault to the ground ( Figure 4 3 and 4 in ), the voltage measured / sensed across the bridge circuit 116 is Where Vth is the threshold voltage.

[0044] If the sensing line 114 connected to the first voltage sensing terminal Vsenp of the VR controller 100 has a short-circuit fault to the ground, and the sensing line 114 connected to the second voltage sensing terminal Vsenp of the VR controller 100 has an open-circuit fault ( Figure 4 5 in ), the voltage measured / sensed across the bridge circuit 116 is

[0045] If the sensing line 114 connected to the first voltage sensing terminal Vsenp of the VR controller 100 has a short-circuit fault to the ground, and the sensing line 114 connected to the second voltage sensing terminal Vsenp of the VR controller 100 is connected to the ground or has a short-circuit fault to the ground ( Figure 4 6 and 7 in FIG), the voltage measured / sensed across the bridge circuit 116 is 0V.

[0046] If the sensing line 114 connected to the first voltage sensing terminal Vsenp of the VR controller 100 has no fault and the sensing line 114 connected to the second voltage sensing terminal Vsenp of the VR controller 100 has an open circuit fault ( Figure 4 8 in ), the voltage measured / sensed across the bridge circuit 116 is

[0047] If the sensing line 114 connected to the first voltage sensing terminal Vsenp of the VR controller 100 has no fault, and the sensing line 114 connected to the second voltage sensing terminal Vsenp of the VR controller 100 is grounded or has a short-circuit fault to ground ( Figure 4 9 and 10 in FIG), the voltage measured / sensed across the bridge circuit 116 is Vsenp.

[0048] Depending on the parameters selected for the values ​​selected from the current limiting resistor Rlim of I / O buffers 200, 202, the branch resistors R1 and R2 of bridge circuit 116, and the driver transistor Q1 of I / O buffers 200, 202, other measured / sensed voltage values ​​are possible for different fault conditions.

[0049] Figure 5 A digital controller embodiment of the control circuitry 108 of the VR controller 100 is shown for implementing the voltage feedback continuity fault detection technique described herein. According to this embodiment, the digital controller 500 includes a state machine (SM) or other logic ("OSP_SM") 502 for implementing a voltage measurement loop, start-up logic 504 for controlling when the state machine / logic 502 starts the voltage measurement loop, a timer 506 for determining the duration of the voltage measurement loop, and a comparator 508 for detecting a fault condition at either voltage sense terminal Vsenp, Vsenn of the VR controller 100 based on the voltage measurement results.

[0050] In one embodiment, the comparator output "osp_fault_o" indicates a fault condition at one or both of the voltage sense lines 114 connected to the voltage sense terminals Vsenp, Vsen of the VR controller 100 when the voltage across the bridge circuit 116 (Vsenp-Vsenn) remains below a threshold value for a certain number of measurements at the operating frequency (Fop) of the digital controller 500. For example, the comparator output osp_fault_o may trigger / activate when the bridge circuit voltage remains below a threshold value for 75 measurements at Fop=25 MHz.

[0051] The signal "st_active_i" marks that the power converter 102 is active, meaning that it is operating with a regulated output voltage Vout. One or more additional signals can be provided to the startup logic 504 of the digital controller 500. For example, the shutdown signal "st_shutdown_i" marks that a shutdown event has occurred and that the power converter 102 is disabling the output voltage Vout, and is also used to reinitialize the startup logic 504. The delay signal "st_ton_delay_i" is a signal indicating that the power converter 102 has received an operation command and waits for the required ton_delay time before starting the output voltage ramp-up. For example, the regulator output voltage Vout can have an initial bias at the beginning of the voltage ramp-up. The delay signal st_ton_delay_i can be used to ensure that the voltage feedback continuity fault detection technique starts at Vsenn-Vsenp=0V. Otherwise, the voltage measurement loop can start with a bias of 100mV or higher on Vout, for example.

[0052] The signal "vout_target_i[8:0]" may indicate a target profile for the regulator output voltage Vout during voltage ramp-up. The target voltage corresponds to the profile expected for Vout during voltage ramp-up, absent any fault conditions on the sense line 114 connected to the voltage sense terminals Vsenp and Vsenn of the VR controller 100. The startup logic 504 of the digital controller 500 may compare the target voltage signal vout_target_i[8:0] with the threshold signal "osp_thr_i[5:0]" to determine when to begin a defined time window during which the state machine / logic 502 implements a voltage measurement loop. In one embodiment, when the target voltage signal vout_target_i[8:0] exceeds the threshold signal osp_thr_i[5:0], the startup logic 504 instructs the state machine / logic 502 to begin the voltage measurement loop. The target voltage signal vout_target_i[8:0] is depicted as 9 bits in length, and the threshold signal osp_thr_i[5:0] is depicted as 6 bits in length. This is just an example. Different bit lengths can be used for either signal.

[0053] The signal "st_ss_i" is used to mark the output voltage ramp-up state (soft start) of the power converter. For example, when the voltage feedback continuity fault detection technique is not being performed, the duty cycle of the power stage 104 can be forced to a lower value than that used under normal operating conditions. For example, to avoid dangerous current levels at the load 106, for example, if the regulator output voltage Vout increases in an undesirable manner, the signal st_ss_i can be used by the digital controller 500 to output the signal "osp_limit_duty_o" to limit the PWM duty cycle of the power stage 104 when the voltage feedback continuity fault detection technique is being performed. For example, if the signal osp_limit_duty_o is in a first state, the PWM duty cycle of the power stage 104 can be limited to a first value, such as 12.5%, and if the signal osp_limit_duty_o is in a second state, the PWM duty cycle of the power stage 104 can be limited to a second value, such as 6.25%. If an open circuit fault exists and the regulator output current begins to increase abnormally while the voltage feedback continuity fault detection technique is being performed, the load 106 is less likely to be damaged because the PWM duty cycle is limited / limited according to this embodiment. An enable signal "lp0_osp_en" may be provided to enable or disable the voltage measurement loop implemented by the state machine / logic 502 of the digital controller 500.

[0054] Signals st_active_i, st_shutdown_i, st_ton_delay_i and st_ss_i are used to provide safe boot logic functionality so as not to trigger false OSP detection. Some status signals also enter the state machine / logic 502. Figure 5 The output voltage target represented by the signal vout_target_i[8:0] in FIG is compared with osp_thr only during the initial phase of st_ss_i, where Vout is expected to start rising and the power converter 102 is still in a phase where the output voltage Vout may be low enough to prevent catastrophic damage.

[0055] The signal "lp0_osp_timeout[2:0]" indicates the duration of the defined time window over which the state machine / logic 502 of the digital controller 500 implements the voltage measurement loop. Figure 5 The 3-bit signal shown, the duration of the time window can be set to one of 8 different values, such as 5μs, 6μs, 7μs, 8μs, 16μs, 32μs, 64μs and 128μs. By modifying the length and encoding of the bit value of the timeout signal lp0_osp_timeout[2:0], fewer or more values ​​and different values ​​can be used for the defined time window.

[0056] The defined time window (over which the state machine / logic 502 of digital controller 500 implements the voltage measurement loop) should be wide enough to detect a fault condition on any of the voltage sense lines 114 connected to the voltage sense terminals Vsenp and Vsenn of VR controller 100, but not so wide that the regulator output voltage Vout becomes dangerously high. In one embodiment, the defined time window is based on the ramp rate of power converter 102, such that the defined time window is longer for slower ramp rates and shorter for faster ramp rates. For example, if the output capacitor Cout of power converter 102 is relatively large, regulator 102 will start up slowly. With a slow ramp rate, more detection time is required to detect a fault condition on voltage sense line 114. A wider defined time window can be achieved by setting the timeout signal lp0_osp_timeout accordingly. If power converter 102 has a smaller output capacitance, the ramp rate is faster, and less detection time is required to identify a problem on voltage sense line 114. A narrower defined time window can be selected by setting the timeout signal lp0_osp_timeout accordingly. The defined time window can be programmable to increase system flexibility.

[0057] The state machine / logic 502 of the digital controller 500 implements a voltage measurement loop when activated / enabled by the startup logic 504. In response, the state machine / logic 502 sets the signal en_osp to a first value, which sets the bridge circuit 116 to a first state. The bridge circuit 116 electrically couples the first voltage sense terminal Vsenp of the VR controller 100 to the second voltage sense terminal Vsenn of the VR controller in the first state, as previously explained.

[0058] When the defined time window expires, the state machine / logic 502 of the digital controller 500 sets the signal en_osp to a second value, which sets the bridge circuit 116 to a second state. In the second state, the bridge circuit 116 electrically decouples the voltage sense terminals Vsenp and Vsenn of the VR controller 100, as also previously explained. The timer 506 indicates to the state machine / logic 502 when the defined time window has expired, causing the state machine / logic 502 to change the signal en_osp from one value to another, such as from a logic high value to a logic low value, or vice versa, to control the state of the bridge circuit 116.

[0059] As previously explained herein, the signal en_osp provided by the state machine / logic 502 of the digital controller 500 serves as a gate signal to control whether transistors P1 and N1 of the bridge circuit switching device 204 are turned on or off. When transistors P1 and N1 of the switching device 204 are turned on, the first voltage sensing terminal Vsenp of the VR controller 100 is electrically coupled to the second voltage sensing terminal Vsenn of the VR controller 100, and the voltage across the bridge circuit 116 begins to rise. The comparator 508 compares a digital or analog representation of the voltage across the bridge circuit 116 with a threshold defined by the threshold signal osp_thr_i. In the case of a digital representation, the digital controller 500 determines whether an open circuit or short circuit fault condition exists at the voltage sensing terminals Vsenp and Vsenn of the VR controller 100 based on the digital representation of the voltage across the bridge circuit 116, "vs_adc_i[11:3]." For example, the comparator 508 may compare the ADC output vs_adc_i[11:3] with the threshold signal osp_thr_i. The resolution of ADC can be selected according to needs.

[0060] If the voltage across the bridge circuit 116 remains below a threshold, e.g., for a particular number of measurements at the operating frequency (Fop) of the digital controller 500, the comparator 508 generates a fault indication signal "osp_fault_o." Alternatively or additionally, the VR controller 100 may shut down the power converter 102 in response to detecting a fault on any of the voltage sense lines 114. For added flexibility, the defined time windows and / or thresholds used as part of the voltage feedback continuity fault detection technique may be programmable.

[0061] Figure 6 Various waveforms are shown that occur when a fault is detected during the voltage feedback continuity fault detection technique. Figure 6 The actual output voltage Vout of the power converter 102, the target voltage signal vout_target_i[8:0], the threshold signal osp_thr_i[5:0], and the voltage (Vsenp-Vsenn) measured / sensed across the bridge circuit 116 during the voltage measurement loop implemented by the state machine / logic 502 of the digital controller 500 are plotted. Figure 6 The voltage feedback continuity fault detection technology is in the idle state ( Figure 6 "osp_idle" digital controller status in osp_idle_status ...

[0062] When the startup logic 504 of the digital controller 500 determines that the voltage feedback continuity fault detection technique should be initiated, the state machine / logic 502 of the digital controller 500 sets the signal en_osp to a first value, which sets the bridge circuit 116 to a first state. In the first state, the switching device 204 of the bridge circuit 116 electrically couples the first voltage sense terminal Vsenp of the VR controller 100 to the second voltage sense terminal Vsenn of the VR controller 100.

[0063] If the delay signal st_ton_delay_i is valid, the activation of the signal en_osp may be delayed, such as Figure 6 The dotted line portion of the signal en_osp is shown in ( Figure 6 The duty cycle of the power converter power stage 104 may be limited / restricted by using the signal osp_limit_duty_o as explained herein before ( Figure 6 In either case, after the state machine / logic 502 sets the signal en_osp to the first value, the comparator 508 determines when the target voltage signal vout_target_i[8:0] rises above the threshold voltage indicated by the threshold signal osp_thr_i[5:0]. At this point, the state machine / logic 502 begins the voltage measurement loop ( Figure 6 "OSP_MEAS" digital controller status in .

[0064] exist Figure 6 In the example shown, due to a fault on one or both of the sense lines 114 connected to the voltage sense terminals Vsenp, Vsen of the VR controller 100, the voltage Vsenp-Vsenn measured / sensed across the bridge circuit 116 via the voltage sensing circuit 112 of the VR controller 100 fails to rise above the threshold voltage indicated by the threshold signal OSP_Thr_I[5:0] during a defined time window indicated by the timeout signal lp0_osp_timeout[2:0]. At the end of the defined time window, the state machine / logic 502 stops the voltage measurement loop by changing the signal en_osp to a second value, which sets the bridge circuit 116 to the second state ( Figure 6 In the second state, the switching device 204 of the bridge circuit 116 electrically decouples the voltage sensing terminals Vsenp, Vsenn of the VR controller 100. The VR controller 100 may be in a defined time window ( Figure 6When the state machine / logic 502 enters the OSP Update state ( Figure 6 The result of the OSP sensing operation is transferred to avoid glitches or temporary results on the fault signal when the "OSP_UPDATE" digital controller state is selected.

[0065] In response to the voltage Vsenp-Vsenn failing to rise above the threshold voltage at the end of the defined time window, the comparator 508 of the digital controller 500 generates a fault indication signal osp_fault_o to indicate that a fault has occurred on one or both of the sense lines 114 connected to the voltage sense terminals Vsenp, Vsenn of the VR controller 100. As a precautionary measure, the power converter 102 may also be shut down ( Figure 6 The power converter 102 may enter a wait period before attempting to restart the voltage feedback continuity fault detection technique, for example, to determine whether the sense line fault has cleared ( Figure 6 The digital controller 500 implementing the voltage feedback continuity fault detection technique remains idle during the wait period ( Figure 6 "osp_idle" digital controller status in osp_idle_status ...

[0066] Figure 7 The waveform shown is Figure 6 Same as, but no fault is detected when voltage feedback continuity fault detection technique is used. Figure 6 Differently, during the defined time window indicated by the timeout signal lp0_osp_timeout[2:0], the voltage Vsenp-Vsenn measured / detected across the bridge circuit 116 by the voltage detection circuit 112 rises above the threshold voltage indicated by the threshold signal osp_thr_i[5:0] and remains above the threshold voltage for a predetermined duration, e.g., Figure 7 Therefore, no fault is detected on any of the sense lines 114 connected to the voltage sense terminals Vsenp, Vsenn of the VR controller 100. The VR controller 100 may maintain the voltage Vsenp-Vsenn above the threshold voltage for a predetermined duration ( Figure 6 When the output voltage Vout of the regulator 102 reaches the target voltage indicated by vout_target_i[8:0], the VR controller 100 may enter normal regulation ( Figure 7This may include lifting any restrictions on the duty cycle of the power converter power stage 104 implemented as part of the voltage feedback continuity fault detection technique.

[0067] Figure 8 An embodiment of an electronic system 800 is shown that includes one or more power converters 102 previously described herein. The electronic system 800 can be, for example, a system board such as a server board. The electronic system 800 can also include one or more microprocessors (e.g., CPUs) 802 and at least one memory 804 associated with each microprocessor 802. Each power converter 102 can regulate one or more voltages applied to the one or more microprocessors 802 and the associated memory 804. For example, the one or more power converters 102 can be a multiphase power converter including two or more power stages 104. In the case of a multiphase buck converter, each power stage 104 of the multiphase buck converter 102 includes a high-side transistor and a low-side transistor for coupling the phase to a corresponding one of the microprocessors 802 through an inductor.

[0068] As the power requirements of the microprocessor 802 change, the corresponding power converter 102 can dynamically activate or deactivate the power stages 104. In addition, during periods of low microprocessor usage, the corresponding power converter 102 can select a subset of the power stages 104 and deactivate the other power stages 104. This is commonly referred to as phase shedding. Each power converter 102 also includes a controller 100 for managing the operation of the respective power converter 102, including the implementation of the voltage feedback continuity fault detection technique described herein. The power converter 102 Figure 8 It is logically shown as a single unit in FIG, but may be implemented as a collection of separate components such as a power transistor die, a controller die, capacitors, inductors, etc.

[0069] In the case of a system board such as a server board, the electronic system 800 may further include a board manager 806 that communicates with each microprocessor 802, each memory 804, and each power converter 102. To this end, the electronic system 800 may include a first communication link 808 between the board manager 806 and each power converter 102, and a second communication link 810 between the board manager 806 and each microprocessor 802. For example, the communication links 808 and 810 may be implemented as serial or parallel buses, and the communication links 808 and 810 may be independent of each other. Each power converter 102 may transmit the fault information described herein via the corresponding communication link 808.

[0070] Although the present disclosure is not limited in this regard, the following numbered examples illustrate one or more aspects of the present disclosure.

[0071] Example 1. A controller for a power converter, the controller comprising: a first sensing terminal and a second sensing terminal for sensing an output voltage of the power converter; a bridge circuit configured to electrically couple the first sensing terminal to the second sensing terminal in a first state and to electrically decouple the first sensing terminal from the second sensing terminal in a second state; and a control circuit system configured to set the bridge circuit to a first state during a portion of a voltage ramp of the power converter and to determine whether an open circuit or short circuit fault state exists at the first sensing terminal or the second sensing terminal based on a voltage across the bridge circuit in the first state.

[0072] Example 2. The controller according to Example 1 further includes: a first I / O buffer electrically connected to the first sensing terminal; and a second I / O buffer electrically connected to the second sensing terminal, wherein the bridge circuit includes a switching device, a first resistor electrically connected between the first sensing terminal and the switching device, and a second resistor electrically connected between the second sensing terminal and the switching device, so that the first resistor, the switching device, and the second resistor are electrically connected in series between the first sensing terminal and the second sensing terminal, wherein the first resistor and the first I / O buffer form a first resistor divider, and wherein the second resistor and the second I / O buffer form a second resistor divider.

[0073] Example 3. The controller according to Example 2 further includes an analog-to-digital converter configured to convert a voltage across the bridge circuit in the first state into a digital representation that is lower than a threshold when an open circuit or short circuit fault state exists at the first sensing terminal or the second sensing terminal, and is higher than a threshold when no open circuit or short circuit fault state exists at the first sensing terminal and the second sensing terminal is grounded or shorted to ground.

[0074] Example 4. A controller according to Example 2 or 3, wherein the switching device includes a pMOS transistor and an nMOS transistor, wherein the source of the pMOS transistor and the drain of the nMOS transistor are electrically connected to the first resistor, and wherein the source of the nMOS transistor and the drain of the pMOS transistor are electrically connected to the second resistor.

[0075] Example 5. A controller according to any one of Examples 2 to 4, wherein the control circuit system is a digital controller, and wherein the bridge circuit further comprises a level shifter configured to level shift a gate signal generated by the digital controller for the switching device from a lower voltage domain of the digital controller to a higher voltage domain of the first sense terminal and the second sense terminal.

[0076] Example 6. A controller according to any one of Examples 1 to 5, wherein the control circuit system is configured to set the bridge circuit to the first state for a defined time window during a portion of the voltage ramp, and to set the bridge circuit to the second state after the defined time window expires.

[0077] Example 7. The controller of Example 6, wherein the control circuitry is configured to generate a fault indication signal and / or shut down the power converter if the voltage across the bridge circuit is below a threshold at the end of a defined time window.

[0078] Example 8. The controller of example 6 or 7, wherein the defined time window is based on a ramp rate of the power converter, such that the defined time window is longer for slower ramp rates and shorter for faster ramp rates.

[0079] Example 9. The controller of any of Examples 6 to 8, wherein the defined time window and / or threshold value is programmable.

[0080] Example 10. The controller of any of Examples 6 to 9, wherein the control circuitry is configured to limit a duty cycle of the power converter during a defined time window and to end the duty cycle limitation after expiration of the defined time window.

[0081] Example 11. The controller of any of Examples 6 to 10, wherein the control circuitry is configured to limit the duty cycle to 12.5% ​​or 6.25% during the defined time window.

[0082] Example 12. A controller according to any of Examples 1 to 11, wherein the control circuit system includes a comparator configured to compare a digital representation or an analog representation of the voltage across the bridge circuit in the first state with a threshold value, and wherein the control circuit system is configured to generate a fault indication signal and / or shut down the power converter if the output of the comparator is below the threshold value.

[0083] Example 13. A controller according to any one of Examples 1 to 12, further comprising an analog-to-digital converter configured to convert a voltage across the bridge circuit in a first state into a digital representation, and wherein the control circuit system is a digital controller configured to determine whether an open circuit or short circuit fault condition exists at the first sensing terminal or the second sensing terminal based on the digital representation of the voltage across the bridge circuit in the first state.

[0084] Example 14. A method of operating a controller for a power converter, the method comprising: sensing an output voltage of the power converter across a first sensing terminal and a second sensing terminal of the controller; during a portion of a voltage ramp of the power converter, setting a bridge circuit of the controller to a first state to electrically couple the first sensing terminal to the second sensing terminal; during a later portion of the voltage ramp, setting the bridge circuit to a second state to electrically decouple the first sensing terminal from the second sensing terminal; and determining whether an open circuit or short circuit fault condition exists at the first sensing terminal or the second sensing terminal based on the voltage across the bridge circuit in the first state.

[0085] Example 15. A method according to Example 14, wherein setting the bridge circuit in the first state includes setting the bridge circuit in the first state for a defined time window during a portion of the voltage ramp, and wherein setting the bridge circuit in the second state includes setting the bridge circuit in the second state after the defined time window expires.

[0086] EXAMPLE 16. The method of Example 15, further comprising generating a fault indication signal and / or shutting down the power converter if a voltage across the bridge circuit is below a threshold at the end of the defined time window.

[0087] Example 17. The method of Example 15 or 16, further comprising: limiting a duty cycle of the power converter during a defined time window; and ending the duty cycle limitation after expiration of the defined time window.

[0088] Example 18. An electronic system comprising: a microprocessor; a memory coupled to the microprocessor; a power converter configured to regulate a supply voltage for the microprocessor; and a controller for the power converter. The controller comprises: a first sense terminal and a second sense terminal for sensing the supply voltage; a bridge circuit configured to electrically couple the first sense terminal to the second sense terminal in a first state and to electrically decouple the first sense terminal from the second sense terminal in a second state; and control circuitry configured to set the bridge circuit to a first state during a portion of a voltage ramp of the power converter and to determine whether an open circuit or short circuit fault condition exists at the first sense terminal or the second sense terminal based on a voltage across the bridge circuit in the first state.

[0089] Example 19. An electronic system according to Example 18, wherein the control circuit system is configured to set the bridge circuit to the first state for a defined time window during a portion of the voltage ramp, and to set the bridge circuit to the second state after the defined time window expires.

[0090] Example 20. The electronic system of Example 19, wherein the control circuitry is configured to generate a fault indication signal and / or shut down the power converter if a voltage across the bridge circuit is below a threshold at the end of a defined time window.

[0091] Example 21. The electronic system of example 19 or 20, wherein the defined time window is based on a ramp rate of the power converter such that the defined time window is longer for slower ramp rates and shorter for faster ramp rates.

[0092] Example 22. The electronic system of any of Examples 19 to 21, wherein the control circuitry is configured to limit a duty cycle of the power converter during a defined time window and to end the duty cycle limitation after expiration of the defined time window.

[0093] Terms such as "first", "second", etc. are used to describe various elements, regions, sections, etc., and are not intended to be limiting. Throughout the description, the same terms refer to the same elements.

[0094] As used herein, the terms "having," "comprising," "including," and the like are open-ended terms that indicate the presence of elements or features, but do not preclude additional elements or features. The articles "a," "an," and "the" are intended to include both the singular and the plural, unless the context clearly indicates otherwise.

[0095] It will be understood that the features of the various embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0096] Although specific embodiments have been shown and described herein, it will be understood by those skilled in the art that a variety of alternative and / or equivalent embodiments may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Accordingly, the present invention is limited only by the claims and their equivalents.

Claims

1. A controller for a power converter, the controller comprising: a first sensing terminal and a second sensing terminal for sensing an output voltage of the power converter; a bridge circuit configured to electrically couple the first sensing terminal to the second sensing terminal in a first state and to electrically decouple the first sensing terminal from the second sensing terminal in a second state; as well as control circuitry configured to set the bridge circuit to the first state during a portion of a voltage ramp of the power converter, and to determine whether an open circuit or short circuit fault condition exists at the first sense terminal or the second sense terminal based on a voltage across the bridge circuit in the first state; wherein the bridge circuit comprises a switching device, a first resistor, and a second resistor connected in series between the first sensing terminal and the second sensing terminal, and Wherein the control circuitry is configured to control a state of the switching device to couple the first sense terminal to the second sense terminal in the first state and to electrically decouple the first sense terminal from the second sense terminal in the second state.

2. The controller according to claim 1, further comprising: a first I / O buffer electrically connected to the first sensing terminal; as well as a second I / O buffer electrically connected to the second sensing terminal, wherein the first resistor is electrically connected between the first sensing terminal and the switching device, and wherein the second resistor is electrically connected between the second sensing terminal and the switching device, wherein the first resistor and the first I / O buffer form a first resistor divider, The second resistor and the second I / O buffer form a second resistor divider.

3. The controller of claim 2 , further comprising an analog-to-digital converter configured to convert a voltage across the bridge circuit in the first state into a digital representation, the digital representation being below a threshold if an open or short fault condition exists at the first sense terminal or the second sense terminal, and the digital representation being above the threshold if no open or short fault condition exists at the first sense terminal and the second sense terminal is grounded or shorted to ground.

4. The controller of claim 2 , wherein the switching device comprises a pMOS transistor and an nMOS transistor, wherein a source of the pMOS transistor and a drain of the nMOS transistor are electrically connected to the first resistor, and wherein a source of the nMOS transistor and a drain of the pMOS transistor are electrically connected to the second resistor.

5. The controller of claim 2 , wherein the control circuitry is a digital controller, and wherein the bridge circuit further comprises a level shifter configured to level shift a gate signal generated by the digital controller for the switching device from a lower voltage domain of the digital controller to a higher voltage domain of the first and second sense terminals.

6. The controller of claim 1 , wherein the control circuitry is configured to set the bridge circuit to the first state for a defined time window during a portion of the voltage ramp, and to set the bridge circuit to the second state after expiration of the defined time window. 7 . A controller according to claim 6 , wherein the control circuitry is configured to generate a fault indication signal and / or shut down the power converter if the voltage across the bridge circuit is below a threshold at the end of the defined time window. 8 . The controller of claim 6 , wherein the defined time window is based on a ramp rate of the power converter such that the defined time window is longer for slower ramp rates and shorter for faster ramp rates.

9. The controller according to claim 7, wherein the defined time window and / or the threshold value are programmable. 10 . The controller of claim 6 , wherein the control circuitry is configured to limit a duty cycle of the power converter during the defined time window and to end duty cycle limiting after expiration of the defined time window. 11 . The controller of claim 10 , wherein the control circuitry is configured to limit the duty cycle to 12.5% ​​or 6.25% during the defined time window.

12. The controller of claim 1 , wherein the control circuitry includes a comparator configured to compare a digital or analog representation of the voltage across the bridge circuit in the first state with a threshold value, and wherein the control circuitry is configured to generate a fault indication signal and / or shut down the power converter if an output of the comparator is below the threshold value.

13. The controller of claim 1 , further comprising an analog-to-digital converter configured to convert the voltage across the bridge circuit in the first state into a digital representation, wherein the control circuitry is a digital controller configured to determine whether an open circuit or short circuit fault condition exists at the first sense terminal or the second sense terminal based on the digital representation of the voltage across the bridge circuit in the first state.

14. A method of operating a controller for a power converter, the method comprising: sensing an output voltage of the power converter across a first sensing terminal and a second sensing terminal of the controller; During a portion of a voltage ramp of the power converter, setting a bridge circuit of the controller in a first state to electrically couple the first sense terminal to the second sense terminal; During a later portion of the voltage ramp, setting the bridge circuit to a second state to electrically decouple the first sense terminal from the second sense terminal; as well as determining whether an open circuit or short circuit fault condition exists at the first sensing terminal or the second sensing terminal based on the voltage across the bridge circuit in the first state; wherein the bridge circuit comprises a switching device, a first resistor, and a second resistor connected in series between the first sensing terminal and the second sensing terminal, and Wherein setting the bridge circuit of the controller to be in the first state or the second state includes: controlling the state of the switching device to couple the first sensing terminal to the second sensing terminal in the first state, and electrically decoupling the first sensing terminal from the second sensing terminal in the second state.

15. The method of claim 14, wherein setting the bridge circuit to be in the first state comprises: The bridge circuit is set in the first state for a defined time window during a portion of the voltage ramp, wherein setting the bridge circuit in the second state comprises setting the bridge circuit in the second state after expiration of the defined time window.

16. The method according to claim 15, further comprising: If the voltage across the bridge circuit is below a threshold at the end of the defined time window, a fault indication signal is generated and / or the power converter is shut down.

17. The method according to claim 15, further comprising: limiting a duty cycle of the power converter during the defined time window; as well as The duty cycle limitation ends after the defined time window expires.

18. An electronic system comprising: microprocessor; a memory coupled to the microprocessor; a power converter configured to regulate a power supply voltage of the microprocessor; as well as A controller for the power converter, the controller comprising: A first sensing terminal and a second sensing terminal are used to sense the power supply voltage; a bridge circuit configured to electrically couple the first sensing terminal to the second sensing terminal in a first state and electrically decouple the first sensing terminal from the second sensing terminal in a second state; and control circuitry configured to: set the bridge circuit to the first state during a portion of a voltage ramp-up of the power converter, and determine whether an open circuit or short circuit fault condition exists at the first sense terminal or the second sense terminal based on a voltage across the bridge circuit in the first state; wherein the bridge circuit includes a switching device, a first resistor, and a second resistor connected in series between the first sense terminal and the second sense terminal, and Wherein the control circuitry is configured to control a state of the switching device to couple the first sense terminal to the second sense terminal in the first state and to electrically decouple the first sense terminal from the second sense terminal in the second state.

19. The electronic system of claim 18 , wherein the control circuitry is configured to set the bridge circuit to the first state for a defined time window during a portion of the voltage ramp, and to set the bridge circuit to the second state after expiration of the defined time window.

20. The electronic system of claim 19, wherein the control circuitry is configured to generate a fault indication signal and / or shut down the power converter if the voltage across the bridge circuit is below a threshold at the end of the defined time window.

21. The electronic system of claim 19, wherein the defined time window is based on a ramp rate of the power converter such that the defined time window is longer for slower ramp rates and shorter for faster ramp rates.

22. The electronic system of claim 19, wherein the control circuitry is configured to limit a duty cycle of the power converter during the defined time window and to end duty cycle limiting after expiration of the defined time window.

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