Pixel for display device and display device

Abstract

A pixel for a display device and a display device are provided. The pixel for the display device includes: a light-emitting element; a first transistor including a first electrode electrically connected to a first node and controlling a drive current; a second transistor electrically connected between a data line and the first node and turned on in response to a first scan signal supplied via a first scan line; a third transistor electrically connected between a second node and a third node electrically connected to the second electrode of the first transistor and turned on in response to the first scan signal; and a fourth transistor turned on in response to a second scan signal supplied via a second scan line and applying a bias voltage to the first transistor. The fourth transistor is turned on at a first frequency. The second and third transistors are turned on at a second frequency different from the first frequency.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0133995, filed on October 25, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiment relates to a display device, and to a pixel and a display device including the pixel. Background Art

[0003] The display device may include pixels. Each pixel may include a transistor, a light-emitting element electrically coupled to or connected to the transistor, and a capacitor. The transistor may be turned on in response to a corresponding signal provided via a line, and a predetermined drive current may be generated by the turned-on transistor. The light-emitting element may emit light in response to the drive current.

[0004] Recently, a method of driving a display device at a low frequency is being developed to improve the driving efficiency of the display device and minimize the power consumption of the display device. Therefore, when driving a display device at a low frequency, a method of improving display quality may be required.

[0005] It will be understood that this background in the technical section is intended, in part, to provide a useful background for understanding the technology. However, this background in the technical section may also include ideas, concepts, or cognitions that were not known or appreciated by those skilled in the art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the Invention

[0006] Embodiments relate to a pixel that can periodically apply a bias voltage to a driving transistor during low-frequency driving.

[0007] The embodiment relates to a display device having the above-described pixels and driven at various driving frequencies.

[0008] However, the objects of the disclosure are not limited to the aforementioned objects, and can be expanded in various forms without departing from the spirit and scope of the disclosure.

[0009] Embodiments may provide a pixel for a display device. The pixel may include: a light-emitting element; a first transistor, which may include a first electrode electrically connected to a first node electrically connected to a first power source and control a drive current based on a voltage at a second node; a second transistor, which may be electrically connected between a data line and the first node and may be turned on in response to a first scan signal supplied via a first scan line; a third transistor, which may be electrically connected between a second node and a third node and may be turned on in response to the first scan signal, the third node being electrically connected to the second electrode of the first transistor; and a fourth transistor, which may be turned on in response to a second scan signal supplied via a second scan line and may supply a bias voltage to the first transistor. The fourth transistor may be turned on at a first frequency, and the second and third transistors may be turned on at a second frequency different from the first frequency.

[0010] The second frequency may be lower than the first frequency.

[0011] In an embodiment, the second frequency may be equal to the image refresh rate and may be an equal division of the first frequency.

[0012] In an embodiment, the pixel may further include: a fifth transistor, which can be electrically connected between the first power supply and the first node and can be turned off in response to the emission control signal supplied through the emission control line; a sixth transistor, which can be electrically connected between the third node and the fourth node and can be turned off in response to the emission control signal, the fourth node being electrically connected to the first electrode of the light-emitting element; a seventh transistor, which can be electrically connected between the fourth node and the first initialization power supply and can be turned on in response to the second scan signal; an eighth transistor, which can be electrically connected between the second node and the second initialization power supply and can be turned on in response to the third scan signal supplied through the third scan line; and a storage capacitor, which is electrically connected between the first power supply and the second node.

[0013] In an embodiment, the fifth to seventh transistors may be turned on at a first frequency, and the eighth transistor may be turned on at a second frequency.

[0014] In an embodiment, the fourth transistor may be electrically connected between the emission control line and the third node, and may apply the emission control signal as a bias voltage to the third node in response to the second scan signal.

[0015] In an embodiment, the fourth transistor may be electrically connected between the emission control line and the first node, and may apply the emission control signal as a bias voltage to the third node in response to the second scan signal.

[0016] In an embodiment, the fourth transistor may be electrically connected between the bias power supply and the third node or between the bias power supply and the first node, and may apply the voltage of the bias power supply as the bias voltage to the third node or the first node in response to the second scan signal.

[0017] Embodiments may provide a pixel of a display device. The pixel may include: a light-emitting element; a first transistor, which may include a first electrode electrically connected to a first node electrically connected to a first power source and control a drive current based on a voltage at a second node; a second transistor, which may be electrically connected between a data line and the first node and may be turned on in response to a first scan signal supplied via a first scan line; a third transistor, which may be electrically connected between a second node and a third node and may be turned on in response to a second scan signal supplied via a second scan line, the third node being electrically connected to the second electrode of the first transistor; and a fourth transistor, which may be turned on in response to a third scan signal supplied via a third scan line and may apply a bias voltage to the first transistor. The fourth transistor may be turned on at a first frequency, the second transistor and the third transistor may be turned on at a second frequency lower than the first frequency, and the length of the on-period of the second transistor and the length of the on-period of the third transistor may be different from each other.

[0018] In an embodiment, the second frequency may be equal to the image refresh rate and correspond to an equal division of the first frequency.

[0019] The pixel may further include: a fifth transistor that may be electrically connected between the first power supply and the first node and may be turned off in response to an emission control signal supplied through the first emission control line; a sixth transistor that may be electrically connected between the third node and the fourth node and may be turned off in response to an emission control signal supplied through the second emission control line, the fourth node being electrically connected to the first electrode of the light-emitting element; a seventh transistor that may be electrically connected between the fourth node and the initialization power supply and may be turned on in response to a third scan signal supplied through a fourth scan line; and a storage capacitor that is electrically connected between the first power supply and the second node.

[0020] In an embodiment, the fifth transistor and the sixth transistor may be turned on at a first frequency.

[0021] In an embodiment, a portion of the off period of the fifth transistor may overlap with a portion of the on period of the sixth transistor, and the third transistor and the seventh transistor may be controlled simultaneously.

[0022] In an embodiment, the turn-on period of the fourth transistor may not overlap with the turn-on period of the third transistor and the turn-on period of the seventh transistor.

[0023] In an embodiment, the fourth transistor may be electrically connected between the first emission control line and the third node or between the first emission control line and the first node and may apply the emission control signal as a bias voltage to the third node or the first node in response to the third scan signal.

[0024] The fourth transistor may be electrically connected between the bias power supply and the third node or between the bias power supply and the first node and may apply a voltage of the bias power supply as a bias voltage to the third node or the first node in response to the third scan signal.

[0025] Embodiments may provide a display device. The display device may include: a pixel electrically connected to a first scan line, a second scan line, an emission control line, and a data line; a scan driver capable of supplying a second scan signal to the second scan line at a first frequency and supplying a first scan signal to the first scan line at a second frequency corresponding to an image refresh rate of the pixel; an emission driver capable of supplying an emission control signal to the emission control line at a first frequency; a data driver capable of supplying a data signal to a corresponding data line at a second frequency; and a timing controller capable of controlling driving of the scan driver, the emission driver, and the data driver. Among the pixels, a pixel that may be arranged in an i-th horizontal row (where “i” is a natural number) may include: a light emitting element; a first transistor that may include a first electrode electrically connected to a first node electrically connected to a first power source and control a driving current based on a voltage at a second node; a second transistor that may be electrically connected between a data line and the first node and may be turned on in response to a first scan signal supplied through an i-th first scan line; a third transistor that may be electrically connected between a second node and a third node and may be turned on in response to the first scan signal supplied through the i-th first scan line, the third node being electrically connected to the second electrode of the first transistor; and a fourth transistor that may be turned on in response to a second scan signal supplied through an i-th second scan line and may apply a bias voltage to the first transistor. The second frequency may be an equal fraction of the first frequency.

[0026] In an embodiment, the scan driver may include: a first scan driver that may supply a first scan signal to each of the first scan lines at a second frequency; and a second scan driver that may supply a second scan signal to each of the second scan lines at the first frequency.

[0027] In an embodiment, the first scan driver may supply a first scan signal during a display scan period of a frame cycle, and may not supply the first scan signal during a self-scan period of a frame cycle, the second scan driver may supply a second scan signal during the display scan period and the self-scan period, the emission driver may supply an emission control signal during the display scan period and the self-scan period, and the data signal may be written to the pixel during the display scan period.

[0028] In an embodiment, the pixels arranged in the i-th horizontal row may further include: a fifth transistor, which can be electrically connected between the first power supply and the first node and can be turned off in response to the emission control signal supplied through the i-th emission control line; a sixth transistor, which can be electrically connected between the third node and the fourth node and can be turned off in response to the emission control signal supplied through the i-th emission control line, and the fourth node is electrically connected to the first electrode of the light-emitting element; a seventh transistor, which can be electrically connected between the fourth node and the first initialization power supply and can be turned on in response to the second scan signal supplied through the i-th second scan line; an eighth transistor, which can be electrically connected between the second node and the second initialization power supply and can be turned on in response to the first scan signal supplied through the i-1-th first scan line; and a storage capacitor, which is electrically connected between the first power supply and the second node.

[0029] In an embodiment, the fourth transistor may be electrically connected between the i th emission control line and the third node. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other features will become more apparent by further describing embodiments thereof in detail with reference to the accompanying drawings, in which:

[0031] Figure 1 is a block diagram illustrating a display device according to an embodiment.

[0032] Figure 2A is an equivalent circuit diagram showing a pixel according to the embodiment.

[0033] Figure 2B It shows Figure 2A Equivalent circuit diagram of a variation of the pixel.

[0034] Figure 3A It shows Figure 2A A timing diagram showing an example of driving a pixel.

[0035] Figure 3B It shows Figure 2A A timing diagram showing an example of driving a pixel.

[0036] Figures 4A to 4Dis a timing diagram illustrating an example of start pulses supplied to an emission driver and a scan driver included in a display device according to an image refresh rate.

[0037] Figure 5 is a diagram illustrating an example of a method of driving a display device according to an image refresh rate.

[0038] Figure 6 and Figure 7 It is shown that the Figure 1 FIG1 is an equivalent circuit diagram of an example of a pixel in a display device.

[0039] Figure 8 It shows Figure 1 A block diagram of an example of a display device.

[0040] Figure 9 It is shown that the Figure 8 FIG1 is an equivalent circuit diagram of an example of a pixel in a display device.

[0041] Figure 10 It shows Figure 9 A timing diagram showing an example of driving a pixel.

[0042] Figure 11 It is shown that the Figure 8 FIG1 is an equivalent circuit diagram of an example of a pixel in a display device.

[0043] Figure 12A It shows Figure 11 A timing diagram showing an example of driving a pixel.

[0044] Figure 12B It shows Figure 11 A timing diagram showing an example of driving a pixel.

[0045] Figures 13 to 15 It shows Figure 11 Equivalent circuit diagram of a variation of the pixel.

[0046] Figures 16 to 19 It shows Figure 11 Equivalent circuit diagram of a variation of the pixel. DETAILED DESCRIPTION

[0047] The disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. However, the disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art.

[0048] For the purpose of describing the disclosed embodiments, some parts that are not related to the description may not be provided, and like reference numerals denote like elements throughout the specification.

[0049] When a layer, film, zone, substrate or region is referred to as "on" another layer, film, zone, substrate or region, it can be directly on the other layer, film, zone, substrate or region, or there can be an intermediate layer, intermediate film, intermediate zone, intermediate substrate or intermediate region therebetween. On the contrary, when a layer, film, zone, substrate or region is referred to as "directly on" another layer, film, zone, substrate or region, there can be no intermediate layer, intermediate film, intermediate zone, intermediate substrate or intermediate region therebetween. In addition, when a layer, film, zone, substrate or region is referred to as "below" another layer, film, zone, substrate or region, it can be directly below the other layer, film, zone, substrate or region, or there can be an intermediate layer, intermediate film, intermediate zone, intermediate substrate or intermediate region therebetween. On the contrary, when a layer, film, zone, substrate or region is referred to as "directly on" another layer, film, zone, substrate or region, there can be no intermediate layer, intermediate film, intermediate zone, intermediate substrate or intermediate region therebetween. Furthermore, "above" or "over" may include positioning above or below a target and does not necessarily imply a direction based on gravity.

[0050] For ease of description, spatially relative terms such as "below," "beneath," "below," "above," and "above" may be used herein to describe the relationship between one element or component and another element or component as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, where the device shown in the accompanying drawings is flipped over, a device positioned "below" or "beneath" another device may be placed "above" the other device. Thus, the illustrative term "below" may include both a position below and a position above. The device may also be oriented in other directions, and therefore, the spatially relative terms may be interpreted differently depending on the orientation.

[0051] Throughout this specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to the other element or “electrically connected” to the other element with one or more intermediate elements interposed therebetween. It will also be understood that when the terms “comprise” and / or “include” are used in this specification, they may indicate the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0052] In the accompanying drawings, the sizes and thicknesses of elements may be exaggerated for better understanding, clarity, and ease of description. However, the disclosure is not limited to the sizes and thicknesses shown. In the accompanying drawings, the thicknesses of layers, films, panels, regions, and other elements may be exaggerated for clarity. In the accompanying drawings, the thicknesses of some layers and regions may be exaggerated for better understanding and ease of description.

[0053] Furthermore, in the specification, the phrase “in a plan view” indicates when the target portion is viewed from above, and the phrase “in a schematic cross-sectional view” indicates when a schematic cross-section taken by vertically cutting the target portion is viewed from the side.

[0054] Additionally, the terms "superimposed" or "overlapping" indicate that a first object may be above or below or to one side of a second object, and vice versa. Additionally, the term "superimposed" may include layer, stack, face or facing, "extending over," covering or partially covering, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art. The terms "face" and "facing" indicate that a first element may be directly or indirectly opposite to a second element. In the event that a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other, while still facing each other. When an element is described as "not" superimposed with another element or "not to be superimposed with" another element, this may include the elements being spaced apart from each other, offset from each other, or separated from each other, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art.

[0055] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0056] In the specification and claims, for the purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a combined or separate sense and may be understood to be equivalent to "and / or". In the specification and claims, for the purposes of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0057] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first element discussed below can be named the second element without departing from the disclosed teachings. Similarly, the second element can also be named the first element.

[0058] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong. In addition, it will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an ideal or overly formal sense unless explicitly defined as such herein.

[0059] Hereinafter, disclosed embodiments will be described with reference to the accompanying drawings.

[0060] Figure 1 is a block diagram illustrating a display device according to an embodiment.

[0061] Reference Figure 1 , the display device 1000 may include a pixel unit 100 , scan drivers 200 and 300 , an emission driver 400 , a data driver 500 , and a timing controller 600 .

[0062] The scan drivers 200 and 300 may be divided into a first scan driver 200 and a second scan driver 300 according to their configuration and operation. However, the division of the scan drivers 200 and 300 is intended to facilitate description, and at least some of the scan drivers 200 and 300 and the emission driver 400 may be integrated into a single driving circuit, module, etc. according to design.

[0063] The display device 1000 can display one or more images at various image refresh rates (i.e., refresh rate, drive frequency, or screen display rate) depending on the driving conditions. The image refresh rate can be the frequency at which the data signal is actually written to the drive transistor of each pixel PX. For example, the image refresh rate can also be called a scan rate or screen display frequency, and can represent the frequency at which a displayed image is reproduced or refreshed per second.

[0064] In an embodiment, the image refresh rate may be an output frequency of the data driver 500 and / or the first scan driver 200 that may output a write scan signal. For example, the refresh rate for video driving may be a frequency of about 60 Hz or higher (e.g., about 120 Hz). Here, the scan signal output from the first scan driver 200 may be supplied to each horizontal row (pixel row) 60 times per second.

[0065] In an embodiment, the display device 1000 can adjust the output frequency of the first scan driver 200 and the second scan driver 300 and the output frequency of the data driver 500 corresponding thereto according to the driving conditions. For example, the display device 1000 can display one or more images according to various image refresh rates within a range of about 1 Hz to about 120 Hz. However, this is merely exemplary, and the display device 1000 can also display one or more images at an image refresh rate of about 120 Hz or higher (e.g., about 240 Hz or about 480 Hz).

[0066] The timing controller 600 may receive input image data IRGB and timing signals Vsync, Hsync, DE, and CLK from a host system such as an application processor (AP) through a predetermined interface.

[0067] The timing controller 600 may generate a data drive control signal DCS based on the input image data IRGB and timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK. The data drive control signal DCS may be supplied to the data driver 500. The timing controller 600 may rearrange the input image data IRGB and provide the rearranged data to the data driver 500.

[0068] The timing controller 600 may supply the gate start pulses GSP1 and GSP2 and the clock signal CLK to the first and second scan drivers 200 and 300 based on the timing signal.

[0069] The timing controller 600 may supply an emission start pulse ESP and a clock signal CLK to the emission driver 400 based on the timing signal. The emission start pulse ESP may control the first timing of the emission control signal. The clock signal CLK may be used to shift the emission start pulse ESP.

[0070] The first gate start pulse GSP1 may control a first timing of a scan signal (eg, a first scan signal) supplied from the first scan driver 200. The clock signal CLK may be used to shift the first gate start pulse GSP1.

[0071] The second gate start pulse GSP2 may control a first timing of a scan signal (eg, a second scan signal) supplied from the second scan driver 300. The clock signal CLK may be used to shift the second gate start pulse GSP2.

[0072] In an embodiment, the pulse widths of the first gate start pulse GSP1 and the second gate start pulse GSP2 may be different from each other. Therefore, the widths of the scan signals corresponding to the respective gate start pulses may also be different from each other.

[0073] The data driver 500 may convert the rearranged image data RGB into analog data signals. The data driver 500 may supply data signals to the data lines D in response to the data driving control signal DCS. The data signals supplied through the data lines D may be supplied to the pixels PX selected by the scan signal.

[0074] The data driver 500 may supply a data signal to the data line D during one frame period according to an image refresh rate. For example, the data driver 500 may supply a data signal to the data line D at the same frequency as the image refresh rate. Here, the data signal supplied through the data line D may be synchronized with the scan signal supplied through the first scan line S1.

[0075] The first scan driver 200 supplies a scan signal to the first scan line S1 in response to the first gate start pulse GSP1. For example, the first scan driver 200 may sequentially supply the scan signal to the first scan line S1. Here, each scan signal may be set to a gate-on voltage (e.g., a logic low voltage) so that the transistor included in the corresponding pixel PX may be turned on.

[0076] In an embodiment, the data signal may be supplied to the pixel PX in response to the first scan signal supplied through the first scan line S1 .

[0077] The first scan driver 200 may supply a scan signal to the first scan line S1 at the same frequency (e.g., a second frequency) as the image refresh rate of the display device 1000. In an embodiment, the second frequency may correspond to an output frequency of the first gate start pulse GSP1 that may be supplied from the timing controller 600 to the first scan driver 200.

[0078] The second frequency may be set to an equal division of the first frequency at which the transmit driver 400 may be driven. For example, the first frequency may be an integer multiple of the second frequency.

[0079] The first scan driver 200 may supply a scan signal to the first scan lines S1 during a display scan period of one frame. For example, the first scan driver 200 may supply at least one scan signal to each of the first scan lines S1 during the display scan period.

[0080] The second scan driver 300 may supply a scan signal to the second scan line S2 in response to the second gate start pulse GSP2. For example, the second scan driver 300 may sequentially supply the second scan signal to the second scan line S2. Here, each scan signal supplied from the second scan driver 300 may be set to a gate-on voltage (e.g., a logic low voltage) so that the transistor included in the corresponding pixel PX may be turned on.

[0081] In an embodiment, a voltage for applying a bias to the driving transistor of the pixel PX may be supplied in response to a second scan signal supplied through the second scan line S2. For example, when the second scan signal is supplied to the corresponding pixel PX, a predetermined bias voltage may be applied to the source electrode and / or drain electrode of the driving transistor of the pixel PX, and the driving transistor may be biased on.

[0082] The second scan driver 300 may supply a scan signal to the second scan line S2 at a first frequency, and the first frequency may be constant regardless of the frequency of the image refresh rate. Here, the first frequency may correspond to the output frequency of the second gate start pulse GSP2 that may be supplied from the timing controller 600 to the second scan driver 300.

[0083] The second scan driver 300 may supply a first frequency of a scan signal that is higher than the frequency of the image refresh rate. In an embodiment, the frequency of the image refresh rate (and the second frequency) may be set to equal parts of the first frequency. For example, the first frequency may be set to approximately twice the maximum refresh rate of the display device 1000 (i.e., the maximum drive frequency set in the display device 1000). When the maximum refresh rate of the display device 1000 is approximately 120 Hz, the first frequency may be set to approximately 240 Hz (i.e., the second frequency is 2 equal parts of the first frequency). Therefore, during one frame period, the scan operation of sequentially outputting the scan signal to the second scan line S2 may be periodically repeated several times at predetermined intervals.

[0084] For example, the second scan driver 300 may perform one scan during the display scan period and may perform at least one scan during the self-scan period according to the image refresh rate at all driving frequencies at which the display device 1000 can be driven. For example, the scan signal may be sequentially output to the corresponding second scan line S2 once during the display scan period and may be sequentially output to the corresponding second scan line S2 one or more times during the self-scan period.

[0085] When the image refresh rate decreases, the number of repetitions of an operation in which the second scan driver 300 may supply a scan signal to the corresponding second scan line S2 during one frame period may be increased.

[0086] The emission driver 400 may supply an emission control signal to the emission control line E in response to the emission start pulse ESP. For example, the emission driver 400 may sequentially supply the emission control signal to the emission control line E. When the emission control signal is sequentially supplied through the emission control line E, the pixel PX may become non-emitting on a horizontal line basis. For this operation, each emission control signal may be set to a gate-off voltage (e.g., a logic high voltage) so that some transistors (e.g., P-type transistors) included in the pixel PX may be turned off.

[0087] In an embodiment, similar to the second scan driver 300 , the emission driver 400 may supply emission control signals at a first frequency to the emission control lines E. Thus, the emission control signals supplied through the corresponding emission control lines E may be repeatedly supplied at predetermined intervals during one frame period.

[0088] Therefore, when the image refresh rate decreases, the number of repetitions of the operation of supplying the emission control signal during one frame period can be increased.

[0089] Each of the first scan driver 200, the second scan driver 300, and the emission driver 400 may be separately mounted on a substrate using a thin film process. Each of the first scan driver 200 and the second scan driver 300 may be located or disposed on both sides of the pixel unit 100. The emission driver 400 may also be located or disposed on both sides of the pixel unit 100. However, the disclosure is not limited thereto.

[0090] The pixel unit 100 may include a pixel PX, which may be positioned or disposed to be electrically coupled or connected to a data line D, scan lines S1 and S2, and an emission control line E. The pixel PX may be supplied with a voltage of a first power source VDD, a voltage of a second power source VSS, and a voltage of an initialization power source Vint from an external device.

[0091] In an embodiment, the scan lines S1 and S2 , the emission control line E, and the data line D electrically coupled or connected to each pixel PX may be set in various forms according to the circuit structure of the pixel PX.

[0092] The pixel PX located or arranged on the current horizontal row (or current pixel row) can be electrically coupled or connected to a scan line located or arranged on the previous horizontal row (or previous pixel row) and / or a scan line located or arranged on the next horizontal row (or next pixel row) according to the circuit structure of the pixel PX. For this operation, a dummy scan line and / or a dummy emission control line (not shown) can be additionally formed in the pixel unit 100.

[0093] Figure 2A is an equivalent circuit diagram showing a pixel according to the embodiment.

[0094] exist Figure 2A , for ease of description, a pixel is shown that can be located or set on the i-th horizontal row (wherein, “i” is a natural number) and can be electrically combined with or electrically connected to the j-th data line Dj (wherein, “j” is a natural number).

[0095] Reference Figure 2A , the pixel 10 may include a light emitting element LD, first to eighth transistors M1 to M8 , and a storage capacitor Cst.

[0096] A first electrode (anode electrode or cathode electrode) of the light emitting element LD may be electrically coupled to or connected to the fourth node N4, and a second electrode (cathode electrode or anode electrode) thereof may be electrically coupled to or connected to the second power supply VSS. The light emitting element LD may generate light having a predetermined brightness according to the amount of current supplied from the first transistor M1.

[0097] In an embodiment, the light emitting element LD may be an organic light emitting diode including an organic light emitting layer. In an embodiment, the light emitting element LD may be an inorganic light emitting element formed of an inorganic material. Alternatively, the light emitting element LD may have a form or structure in which the inorganic light emitting elements may be electrically coupled or connected in parallel and / or in series between the second power supply VSS and the fourth node N4.

[0098] A first electrode of the first transistor M1 (or driving transistor) may be electrically coupled to or connected to a first node N1, and a second electrode thereof may be electrically coupled to or connected to a third node N3. A gate electrode of the first transistor M1 may be electrically coupled to or connected to a second node N2. The first transistor M1 may control the amount of current flowing from the first power supply VDD to the second power supply VSS via the light-emitting element LD according to the voltage of the second node N2. For this operation, the voltage of the first power supply VDD may be set to a voltage higher than the voltage of the second power supply VSS.

[0099] The second transistor M2 may be electrically coupled or connected between the data line Dj and the first node N1. A gate electrode of the second transistor M2 may be electrically coupled or connected to the i-th first scan line S1i. The second transistor M2 may be turned on when a scan signal (e.g., a first scan signal) may be supplied through the i-th first scan line S1i, and may then be electrically coupled or connected to the data line Dj and the first node N1.

[0100] The third transistor M3 may be electrically coupled or connected between the second electrode (i.e., the third node N3) and the second node N2 of the first transistor M1. The gate electrode of the third transistor M3 may be electrically coupled or connected to the i-th first scan line S1i. When a scan signal is supplied through the i-th first scan line S1i, the third transistor M3 may be turned on, and then the second electrode of the first transistor M1 may be electrically coupled or connected to the second node N2. For example, the second transistor M2 and the third transistor M3 may be controlled simultaneously. When the third transistor M3 is turned on, the first transistor M1 may be electrically coupled or connected in a diode configuration. Therefore, writing data to the first transistor M1 and compensation of the threshold voltage may be performed together.

[0101] The fourth transistor M4 may be electrically coupled to or connected between the third node N3 and the i-th emission control line Ei. The gate electrode of the fourth transistor M4 may be electrically coupled to or connected to the i-th second scan line S2i. The fourth transistor M4 may be turned on when a scan signal (e.g., a second scan signal) is supplied via the i-th second scan line S2i, and may then supply the voltage of the i-th emission control line Ei to the third node N3. Here, an emission control signal (e.g., a gate-off voltage or a logic high voltage) may be supplied via the i-th emission control line Ei. For example, the gate-off voltage (i.e., the emission control signal) may be in a range of approximately 5V to approximately 7V.

[0102] Therefore, a predetermined high voltage may be applied as a bias voltage to the drain electrode (and source electrode) of the first transistor M1 through the turn-on operation of the fourth transistor M4 , and the first transistor M1 may have a turn-on bias state (ie, biased on).

[0103] The fifth transistor M5 may be electrically coupled to or connected between the first power supply VDD and the first node N1. A gate electrode of the fifth transistor M5 may be electrically coupled to or connected to the i-th emission control line Ei. The fifth transistor M5 may be turned off when an emission control signal is supplied through the i-th emission control line Ei, and may be turned on otherwise.

[0104] The sixth transistor M6 can be electrically coupled to or connected between the second electrode of the first transistor M1 (i.e., the third node N3) and the first electrode of the light-emitting element LD (i.e., the fourth node N4). The gate electrode of the sixth transistor M6 can be electrically coupled to or connected to the i-th emission control line Ei. The sixth transistor M6 can be turned off when an emission control signal is supplied via the i-th emission control line Ei, and can be turned on in other circumstances. Therefore, the fifth transistor M5 and the sixth transistor M6 can be controlled simultaneously.

[0105] The seventh transistor M7 can be electrically coupled or connected between the first electrode of the light-emitting element LD (i.e., the fourth node N4) and the first initialization power supply Vint1. The gate electrode of the seventh transistor M7 can be electrically coupled or connected to the i-th second scan line S2i. The seventh transistor M7 can be turned on when a scan signal is supplied via the i-th second scan line S2i, and can then supply the voltage of the first initialization power supply Vint1 to the first electrode of the light-emitting element LD (i.e., the fourth node N4).

[0106] When the voltage of the first initialization power supply Vint1 is supplied to the first electrode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD can be discharged. When the residual voltage charged in the parasitic capacitor is discharged (eliminated), unexpected fine light emission can be prevented. Therefore, the black rendering capability of the pixel 10 can be improved.

[0107] The eighth transistor M8 can be electrically coupled or electrically connected between the second node N2 and the second initialization power supply Vint2. The gate electrode of the eighth transistor M8 can be electrically coupled or electrically connected to the third scan line (or the (i-1)th first scan line S1i-1). The eighth transistor M8 can be turned on when a scan signal (e.g., a first scan signal) is supplied via the (i-1)th first scan line S1i-1, and can then supply the voltage of the second initialization power supply Vint2 to the second node N2 (i.e., the gate electrode of the first transistor M1). Thus, the gate voltage of the first transistor M1 can be initialized.

[0108] In an embodiment, the first initialization power source Vint1 and the second initialization power source Vint2 may generate different voltages. For example, a voltage for initializing the second node N2 and a voltage for initializing the fourth node N4 may be set to different voltages.

[0109] When the voltage of the second initialization power supply Vint2 to be supplied to the second node N2 is too low during low-frequency driving with an increasing length of a frame period, the variation of the hysteresis of the first transistor M1 in the corresponding frame period may worsen. Such hysteresis may cause a flickering phenomenon during low-frequency driving. Therefore, in a display device driven at a low frequency, the voltage of the second initialization power supply Vint2 may need to be higher than the voltage of the second power supply VSS.

[0110] During this low-frequency driving, when a turn-on bias is applied to the first transistor M1 using a signal that can be supplied via the data line Dj by the turn-on operation of the second transistor M2 (i.e., when the first transistor M1 is biased to be turned on), a severe deviation in hysteresis due to the difference between the grayscale values ​​of adjacent pixels may occur. As a result, a difference occurs between the offset amounts of the threshold voltages of the drive transistors in adjacent pixels, and thus motion blur (i.e., a ghosting phenomenon) caused by such a difference may be perceived.

[0111] In order to solve this problem, the pixel 10 and the display device having the pixel 10 according to the embodiment (eg, Figure 1 1000) can use the fourth transistor M4 to periodically apply a bias as a constant voltage to the drain electrode (and / or source electrode) of the first transistor M1. Therefore, the hysteresis deviation due to the grayscale difference between adjacent pixels can be removed, and thus the image blur due to the hysteresis deviation can be reduced (or eliminated).

[0112] In an embodiment, the first to eighth transistors M1 to M8 may be formed of polycrystalline silicon semiconductor transistors. For example, each of the first to eighth transistors M1 to M8 may include a polycrystalline silicon semiconductor layer (as an active layer (channel)) formed by a low-temperature polycrystalline silicon (LTPS) process. However, this is merely exemplary, and within the spirit and scope of the disclosure, at least one of the first to eighth transistors M1 to M8 may be replaced by an oxide semiconductor transistor or the like.

[0113] Figure 2B It shows Figure 2A Equivalent circuit diagram of a variation of the pixel.

[0114] Because in addition to the combination relationship of the fourth transistor M4, Figure 2B The Pixel 10' can be used with Figure 2A The pixels 10 are identical or similar to each other, so the same reference numerals are used to denote the same or corresponding components, and thus their repeated description will be omitted.

[0115] Reference Figure 2B , the pixel 10 ′ may include a light emitting element LD, first to eighth transistors M1 to M8 , and a storage capacitor Cst.

[0116] A first electrode of the fourth transistor M4 can be electrically coupled to or connected to the i-th emission control line Ei. A second electrode of the fourth transistor M4 can be electrically coupled to or connected to the first node N1 (i.e., the source electrode of the first transistor M1). When the fourth transistor M4 is turned on, a logic high voltage can be supplied to the i-th emission control line Ei. Therefore, when the fourth transistor M4 is turned on, a logic high voltage can be supplied to the source electrode of the first transistor M1 as a bias voltage, and the first transistor M1 can have an on-bias state.

[0117] like Figure 2A and Figure 2B As shown in , when one electrode of the fourth transistor M4 is electrically coupled to or connected to either one of the source electrode and the drain electrode of the first transistor M1 , the first transistor M1 may be biased on during a predetermined period.

[0118] Figure 3AIt shows Figure 2A A timing diagram showing an example of driving a pixel.

[0119] Reference Figure 2A and Figure 3A , the pixels 10 may be supplied with signals for displaying an image during the display scan period. The display scan period may include a period during which a data signal DVi corresponding to an output image may be written.

[0120] In the following, for the convenience of description, the following description can be made: the i-th emission control line Ei can be used as the emission control line Ei, the i-th first scan line S1i can be used as the first scan line S1i, the i-th second scan line S2i can be used as the second scan line S2i, and the i-1-th first scan line S1i-1 can be used as the previous first scan line S1i-1.

[0121] In an embodiment, the first scan signal supplied by the first scan lines S1i-1 and S1i may have a pulse width of 1 horizontal period (1H) or less. The first scan signal and the second scan signal supplied by the second scan line S2i may be defined as a logic low voltage, and the emission control signal for turning off the fifth transistor M5 and the sixth transistor M6 may be defined as a logic high voltage. However, this is merely exemplary, and the pulse width and logic level of the scan signal and the emission control signal are not limited thereto, and may be changed according to the pixel structure, the type of transistor, etc. within the spirit and scope of the disclosure.

[0122] The emission control signal may be supplied through the emission control line Ei. The emission control signal may be maintained during the first to third periods P1 to P3.

[0123] During the first period P1, an emission control signal may be supplied via the emission control line Ei, and a first scan signal may be supplied via the previous first scan line S1i-1. The fifth transistor M5 and the sixth transistor M6 may be turned off in response to the emission control signal. The eighth transistor M8 may be turned on in response to the first scan signal supplied via the previous first scan line S1i-1.

[0124] During the first period P1, the supply of driving current to the light-emitting element LD may be stopped. Since the eighth transistor M8 is turned on, the voltage of the second initialization power supply Vint2 may be supplied to the gate electrode of the first transistor M1 (i.e., the second node N2). Therefore, the gate voltage of the first transistor M1 may be initialized during the first period P1.

[0125] During the second period P2, the first scan signal can be supplied through the first scan line S1i (or the current first scan line). Therefore, the second transistor M2 and the third transistor M3 can be turned on. The second transistor M2 can be turned on so that the i-th data signal DVi can be supplied to the first node N1 through the data line Dj.

[0126] Since the second transistor M2 and the third transistor M3 may be turned on together, the first transistor M1 may be electrically coupled or connected in a diode configuration. For example, the second period P2 may be a data writing and threshold voltage compensation period.

[0127] During the third period P3, the second scan signal may be supplied through the second scan line S2i, and thus, the fourth transistor M4 and the seventh transistor M7 may be turned on.

[0128] When the seventh transistor M7 is turned on, the voltage of the first initialization power source Vint1 may be supplied to the fourth node N4. Therefore, the voltage of the first electrode (e.g., the anode electrode) of the light emitting element LD may be initialized, and the voltage of the parasitic capacitor formed in the light emitting element LD may be discharged (or removed).

[0129] When the fourth transistor M4 is turned on, the gate-off voltage (e.g., a logic high voltage) of the emission control signal can be supplied to the third node N3. The emission control signal (i.e., the logic high voltage of the emission control signal) can be in the range of about 5V to about 7V, and the first transistor M1 can be biased on during the third period P3. In an embodiment, the second scan signal can have a pulse width of about 4 horizontal periods (4H) or greater. Therefore, for a sufficient period of time, the logic high voltage of the emission control signal can be supplied to the first transistor M1.

[0130] In addition, during the third period P3, the first transistors M1 of all pixels arranged or arranged in the i-th pixel row can be biased on in response to the emission control signal, thereby eliminating the difference between the bias voltages. Therefore, the hysteresis deviation between pixels can be eliminated (or reduced).

[0131] For example, the turn-on period of the third transistor M3 and the turn-on period of the fourth transistor M4 may not overlap with each other.For example, the initialization / compensation period and the bias period of the first transistor M1 may be separated from each other.

[0132] Thereafter, during the fourth period P4, the emission control signal may be stopped and the fifth transistor M5 and the sixth transistor M6 may be turned on. When the fifth transistor M5 and the sixth transistor M6 are turned on, a driving current generated based on the data signal DVi may be supplied to the light-emitting element LD, and the light-emitting element LD may emit light at a brightness corresponding to the driving current. For example, the fourth period P4 may be an emission period.

[0133] For example, the display scan period may include an initialization period (e.g., a first period P1), a writing and compensation period (e.g., a second period P2), a bias period (e.g., a third period P3), and an emission period (e.g., a fourth period P4). In this case, the first to third periods P1 to P3 may correspond to non-emission periods of the pixel 10.

[0134] The operation corresponding to the display scan period may be implemented in response to the scan signal supplied through the first scan lines S1i-1 and S1i, and may be synchronized with a frequency at which the first scan driver 200 may be driven (eg, the frequency may be described as a second frequency).

[0135] Figure 2B The pixel 10' may also perform the same operation as described above during the display scan period.

[0136] Although for ease of description Figure 3A 1 and 2 show that a single first scan signal can be supplied through each of the first scan lines S1i-1 and S1i during the first period P1 and the second period P2, but the disclosure is not limited thereto. For example, a plurality of first scan signals can be supplied through each of the first scan lines S1i-1 and S1i. Even in this case, the actual operation process can be the same as Figure 3A The operation processes are the same, so their detailed descriptions will be omitted.

[0137] Figure 3B It shows Figure 2A A timing diagram showing an example of driving a pixel.

[0138] Reference Figure 2A and Figure 3B In order to maintain the brightness of an image that may be output during the display scan period, an emission control signal may be applied to one electrode (eg, the drain electrode or the third node N3) of the first transistor M1 during the self scan period.

[0139] A single frame may include at least one self-scan period according to the image frame rate. The self-scan period may include a bias period (e.g., a third period P3) and an emission period (e.g., a fourth period P4). In an embodiment, the operation corresponding to the self-scan period may be substantially the same as the operation of the display scan period, except that the first scan signal may not be supplied.

[0140] In an embodiment, during the self-scan period, the scan signal may not be supplied to the second transistor M2 and the third transistor M3. The scan signal may not be supplied to the eighth transistor M8. For example, during the self-scan period, the first scan signal supplied through the first scan lines S1i-1 and S1i may have a gate-off voltage (e.g., a logic high voltage).

[0141] Therefore, the self-scan period may not include an initialization period (eg, Figure 3A The first period P1) and the writing and compensation period (eg, Figure 3A The second period P2).

[0142] Since the second transistor M2 , the third transistor M3 , and the eighth transistor M8 remain turned off, the gate voltage of the first transistor M1 (ie, the voltage of the second node N2 ) may not be affected by driving in the self-scan period.

[0143] In other words, the fourth to seventh transistors M4 to M7 may be turned on at a first frequency, and the second, third, and eighth transistors M2 to M3 may be turned on at a second frequency, which may be different from the first frequency. For example, the second frequency may be lower than the first frequency.

[0144] During the non-emission period, during the third period P3, a second scan signal can be supplied via the second scan line S2i. The fourth transistor M4 can be turned on in response to the second scan signal. When the fourth transistor M4 is turned on, a logic high voltage of the emission control signal can be supplied to the third node N3. Therefore, since a conduction bias can be applied to the first transistor M1 during the third period P3, flickering during low-frequency driving can be improved.

[0145] The second scanning signal and the emission control signal can be supplied at the first frequency regardless of the image refresh rate. Therefore, even when the image refresh rate may change, the on-bias can always be applied periodically during the third period P3. Therefore, flicker can be improved according to various image refresh rates (for example, in low-frequency driving).

[0146] Thereafter, during the fourth period P4, the fourth transistor M4 may be turned off, and the fifth transistor M5 and the sixth transistor M6 may be turned on. Therefore, during the fourth period P4, the pixel 10 may emit light based on the data signal DVi supplied during the previous display scan period.

[0147] In an embodiment, during the self-scan period, the data driver 500 may not supply the data signal DVi to the pixel unit 100. Therefore, power consumption may be further reduced.

[0148] Despite Figures 2A to 3B In the embodiment of the present invention, a P-type transistor is described as being included in pixels 10 and 10', but the disclosure is not limited thereto, and at least one of the first to eighth transistors M1 to M8 may be an N-type transistor. The waveform of the scan signal or emission control signal supplied to each transistor may vary depending on the type of transistor.

[0149] Figures 4A to 4D is a timing diagram illustrating an example of start pulses supplied to an emission driver and a scan driver included in a display device according to an image refresh rate. Figure 5 is a diagram illustrating an example of a method of driving a display device according to an image refresh rate.

[0150] Reference Figure 1 、 Figure 2A 、 Figures 4A to 4D and Figure 5 , the output frequency of the first gate start pulse GSP1 may vary according to the image refresh rate RR.

[0151] In an embodiment, the pulse width of the emission start pulse ESP may be greater than the pulse widths of the first and second gate start pulses GSP1 and GSP2 .

[0152] In an embodiment, regardless of the driving frequency, the timing controller 600 may output the emission start pulse ESP and the second gate start pulse GSP2 at a predetermined frequency (e.g., a first frequency). For example, the output frequency of the emission start pulse ESP and the second gate start pulse GSP2 may be set to approximately twice the maximum refresh rate of the display device 1000.

[0153] The timing controller 600 may output the first gate start pulse GSP1 at the same frequency (e.g., the second frequency) as the frequency of the image refresh rate RR. One frame period of the display device 1000 may be determined by the output period of the first gate start pulse GSP1. For example, one frame period of the display device 1000 may be determined by the output period of the first gate start pulse GSP1 supplied to the pixel (e.g., Figure 2A 10) of the second transistor, the third transistor and the eighth transistor (ie, Figure 2A The scanning signal period of M2, M3 and M8 is determined.

[0154] In an embodiment, during the display scan period DSP, all emission start pulses ESP, the first gate start pulse GSP1 and the second gate start pulse GSP2 may be output. For example, during the display scan period DSP, each of the pixels PX may perform Figure 3A During the display scan period DSP, each of the pixels PX may store a data signal corresponding to an image to be displayed.

[0155] In an embodiment, during the self-scan period SSP, the emission start pulse ESP and the second gate start pulse GSP2 may be output. For example, during the self-scan period SSP, each of the pixels PX may perform Figure 3B During the self-scan period SSP, a predetermined high voltage for applying a bias may be supplied to each pixel (eg, Figure 2A 10) in the first transistor (eg, Figure 2A The first electrode and / or the second electrode of M1).

[0156] In an embodiment, the length of a single display scan period DSP may be substantially the same as the length of a single self-scan period SSP. However, the number of self-scan periods SSP included in one frame period may be determined according to the image refresh rate RR.

[0157] like Figure 4A and Figure 5 As shown in , when the display device 1000 is driven at an image refresh rate RR of approximately 120 Hz, the number of first gate start pulses GSP1 supplied during one frame period may be approximately half the number of second gate start pulses GSP2. Therefore, at an image refresh rate RR of approximately 120 Hz, one frame period may include a single display scan period DSP and a single self-scan period SSP.

[0158] The emission start pulse ESP may be supplied at the same frequency as the second gate start pulse GSP2. When the display device 1000 is driven at an image refresh rate RR of about 120 Hz, the pixel PX may alternately repeat emission and non-emission twice during a frame period.

[0159] like Figure 4B and Figure 5As shown in , when the display device 1000 is driven at an image refresh rate RR of approximately 80 Hz, the number of first gate start pulses GSP1 supplied during one frame period may be approximately 1 / 3 of the number of second gate start pulses GSP2. Therefore, when the display device 1000 is driven at an image refresh rate RR of approximately 80 Hz, one frame period may include one display scan period DSP and two consecutive self-scan periods SSP. Here, the pixel PX may alternately repeat emission and non-emission three times.

[0160] like Figure 4C and Figure 5 As shown in , when the display device 1000 is driven at an image refresh rate RR of approximately 60 Hz, the number of first gate start pulses GSP1 supplied during one frame period may be approximately 1 / 4 of the number of second gate start pulses GSP2. Therefore, when the display device 1000 is driven at an image refresh rate RR of approximately 60 Hz, one frame period may include one display scan period DSP and three consecutive self-scan periods SSP. Here, the pixel PX may alternately repeat emission and non-emission four times.

[0161] like Figure 4D and Figure 5 As shown in , when the display device 1000 is driven at an image refresh rate RR of approximately 48 Hz, the number of first gate start pulses GSP1 supplied during one frame period may be approximately 1 / 5 of the number of second gate start pulses GSP2. Therefore, when the display device 1000 is driven at an image refresh rate RR of approximately 48 Hz, one frame period may include one display scan period DSP and four consecutive self-scan periods SSP. Here, the pixel PX may alternately repeat emission and non-emission five times.

[0162] like Figure 5 As shown in , the light wave LW detected from the pixel unit 100 through the experiment may be output in the same period as that of the second gate start pulse GSP2.

[0163] Similar to the above method, the display device 1000 can be driven at various driving frequencies of about 60 Hz, about 30 Hz, about 24 Hz, about 12 Hz, about 8 Hz, about 6 Hz, about 5 Hz, about 4 Hz, about 3 Hz, about 2 Hz, and about 1 Hz by adjusting the number of self-scan periods SSP included in one frame period. In other words, the display device 1000 can support various image refresh rates RR having frequencies corresponding to equal parts of the first frequency.

[0164] As the driving frequency decreases, the number of self-scan periods SSP increases, and thus a turn-on bias having a predetermined magnitude may be periodically applied to each first transistor M1 included in the pixel unit 100. Therefore, brightness reduction, flickering, or image blurring occurring at low-frequency driving may be improved.

[0165] Figure 6 and Figure 7 It is shown that the Figure 1 FIG1 is an equivalent circuit diagram of an example of a pixel in a display device.

[0166] Because in addition to the configuration of the fourth transistor M4, Figure 6 and Figure 7 The pixels 11 and 11' can be connected with Figure 2A The pixels 10 are identical or similar to each other, so the same reference numerals are used to designate the same or corresponding components, and thus their repeated description will be omitted.

[0167] Reference Figure 6 and Figure 7 , each of the pixels 11 and 11 ′ may include a light emitting element LD, first to eighth transistors M1 to M8 , and a storage capacitor Cst.

[0168] like Figure 6 As shown in FIG, the fourth transistor M4 may be electrically coupled or connected between a predetermined bias power source VEH and a third node N3 (ie, a drain electrode of the first transistor M1). The fourth transistor M4 may be turned on in response to a second scan signal supplied through the second scan line S2i.

[0169] The bias power supply VEH may have a voltage level in the range of about 5 V to about 8 V. The voltage level of the bias power supply VEH may be easily controlled according to driving conditions of the display device 1000. The bias power supply VEH may be implemented as a DC voltage source, and thus the bias difference between the first transistors M1 may be further reduced.

[0170] like Figure 7 As shown in , the fourth transistor M4 may also be electrically coupled or electrically connected between a predetermined bias power supply VEH and the first node N1 (i.e., the source electrode of the first transistor M1). When one electrode of the fourth transistor M4 is electrically coupled or electrically connected to either the source electrode or the drain electrode of the first transistor M1, the first transistor M1 may be biased on during a predetermined period.

[0171] In an embodiment, Figure 6 and Figure 7 The pixels 11 and 11' can be connected with Figure 3A and Figure 3B The timing diagram is the same for the case of driving to display one image or multiple images.

[0172] Figure 8 It shows Figure 1 A block diagram of an example of a display device.

[0173] Because in addition to the configuration of the third scan driver 350, Figure 8 The display device can be used with Figure 1 Since the display devices are the same or similar to each other, the same reference numerals are used to designate the same or corresponding components, and their repeated descriptions will be omitted.

[0174] Reference Figure 8 , the display device 1001 may include a pixel unit 100 , a first scan driver 200 , a second scan driver 300 , a third scan driver 350 , an emission driver 400 , a data driver 500 , and a timing controller 600 .

[0175] The timing controller 600 may supply gate start pulses GSP1 , GSP2 , and GSP3 and a clock signal CLK to the first to third scan drivers 200 , 300 , and 350 based on the timing signals Vsync, Hsync, DE, and CLK.

[0176] The first gate start pulse GSP1 may control a first timing of a scan signal (eg, a first scan signal) output from the first scan driver 200. The second gate start pulse GSP2 may control a first timing of a scan signal (eg, a second scan signal) output from the second scan driver 300.

[0177] The third gate start pulse GSP3 may control a first timing of a scan signal (eg, a third scan signal) output from the third scan driver 350 .

[0178] In an embodiment, the pulse width of at least one of the first to third gate start pulses GSP1 to GSP3 may be different from the pulse widths of the remaining gate start pulses. Therefore, the width of the scan signal corresponding to the corresponding gate start pulse may also vary.

[0179] The data driver 500 may supply a data signal to the data line D in response to the data driving control signal DCS. The data signal supplied through the data line D may be supplied to the pixel PX selected by the scan signal.

[0180] The first scan driver 200 may supply a scan signal to the first scan line S1 in response to the first gate start pulse GSP1. The first scan driver 200 may supply the scan signal to the first scan line S1 at a second frequency corresponding to an image refresh rate. The first scan driver 200 may output the scan signal only during a display scan period.

[0181] The second scan driver 300 may supply a scan signal to the second scan line S2 in response to the second gate start pulse GSP2. In an embodiment, the second scan driver 300 may supply the scan signal to the second scan line S2 at a first frequency that is unrelated to the image refresh rate. For example, the second scan driver 300 may output the scan signal during a display scan period and a self-scan period.

[0182] The third scan driver 350 may supply the scan signal to the third scan line S3 in response to the third gate start pulse GSP3. The third scan driver 350 may supply the scan signal to the third scan line S3 at a second frequency.

[0183] The emission driver 400 may supply an emission control signal to the emission control line E in response to the emission start pulse ESP. The emission driver 400 may supply the emission control signal at a first frequency to the emission control line E. For example, the emission driver 400 may output the emission control signal during the display scan period and the self scan period.

[0184] However, since this is merely exemplary, some of the first scan driver 200, the second scan driver 300, and the third scan driver 350 may be driven at the first frequency, and the remaining scan drivers may be driven at the second frequency according to the structure of the pixel PX. Scan drivers may be reduced or added according to the structure of the pixel PX.

[0185] Figure 9 It is shown that the Figure 8 An equivalent circuit diagram of an example of a pixel in a display device, Figure 10 It shows Figure 9 A timing diagram showing an example of driving a pixel.

[0186] Because in addition to some combined components of the third transistor M3, Figure 9 The pixels can be Figure 2A Since the pixels 10 are identical or similar, the same reference numerals are used to indicate the same or corresponding components, and thus their repeated description will be omitted. Because except for the width of the signal supplied by the third scan line S3i, Figure 10 The timing diagram can be compared with Figure 3A The timing diagrams are the same or similar, so their repeated descriptions will be omitted.

[0187] Reference Figure 9 and Figure 10 , the pixel 12 may include a light emitting element LD, first to eighth transistors M1 to M8 and a storage capacitor Cst.

[0188] In an embodiment, the third transistor M3 and the second transistor M2 can be controlled in response to different scan signals. For example, the gate electrode of the third transistor M3 can be electrically coupled to or connected to the third scan line S3i, and the third transistor M3 can be turned on in response to the third scan signal supplied through the third scan line S3i.

[0189] During the display scan period, the pixel 12 may perform operations corresponding to the first period P1 to the fourth period P4. In an embodiment, the third scan signal supplied through the third scan line S3i may overlap with the first scan signal supplied through the first scan line S1i. The pulse width of the third scan signal may be greater than the pulse width of the first scan signal, and the length of the second period P2 during which data writing and threshold voltage compensation are performed may be increased.

[0190] For example, as the on-period of the third transistor M3 increases, the time required for threshold voltage compensation can increase. Before data is written, the difference between the gate voltage and the source voltage of the first transistor M1 can be reduced. Therefore, the image quality can be further improved.

[0191] Figure 11 It is shown that the Figure 8 FIG1 is an equivalent circuit diagram of an example of a pixel in a display device.

[0192] Reference Figure 11 , the pixel 13 may include a light emitting element LD, first to seventh transistors M1 to M7, and a storage capacitor Cst.

[0193] Since the light emitting element LD, the first transistor M1 and the second transistor M2 can be configured in the same manner as Figure 2A The configurations of the pixels 10 are substantially the same, and thus their repeated descriptions will be omitted.

[0194] The third transistor M3 may be electrically coupled or connected between the second electrode (i.e., the third node N3) of the first transistor M1 and the second node N2. The gate electrode of the third transistor M3 may be electrically coupled or connected to the i-th second scan line S2i. When a scan signal is supplied via the i-th second scan line S2i, the third transistor M3 may be turned on, and then the second electrode of the first transistor M1 may be electrically coupled or coupled to the second node N2. Therefore, when the third transistor M3 is turned on, the first transistor M1 may be electrically coupled or connected in a diode configuration.

[0195] In an embodiment, in a state in which the second transistor M2 is turned off and the third transistor M3 is turned on, the voltage of the initialization power source Vint may be supplied to the gate electrode of the first transistor M1 .

[0196] The fourth transistor M4 may be electrically coupled to or connected between the third node N3 and the i-th emission control line Ei. The gate electrode of the fourth transistor M4 may be electrically coupled to or connected to the (i+q)-th third scan line S3i+q. The fourth transistor M4 may be turned on when a scan signal (e.g., a third scan signal) is supplied via the (i+q)-th third scan line S3i+q (where q is a natural number), and may then supply the voltage of the (i)-th emission control line Ei to the third node N3. For example, the gate electrode of the fourth transistor M4 may be electrically coupled to or connected to the (i+5)-th third scan line S3i+5. The third scan signal supplied via the (i+5)-th third scan line S3i+5 may be a signal obtained by delaying the third scan signal that may be supplied via the (i)-th third scan line S3i by five horizontal periods (5H). However, this is merely exemplary, and the third scan line S3i+q electrically coupled to or connected to the gate electrode of the fourth transistor M4 is not limited thereto.

[0197] Here, a gate-off voltage (or a logic high voltage) may be supplied through the i-th emission control line Ei. For example, the gate-off voltage may be in the range of about 5V to about 7V.

[0198] Therefore, a predetermined high voltage may be applied to the drain electrode (and source electrode) of the first transistor M1 through the turn-on operation of the fourth transistor M4 , and the first transistor M1 may have a turn-on bias state.

[0199] The fifth transistor M5 may be electrically coupled to or connected between the first power supply VDD and the first node N1. A gate electrode of the fifth transistor M5 may be electrically coupled to or connected to the i-th emission control line Ei. The fifth transistor M5 may be turned off when an emission control signal may be supplied via the i-th emission control line Ei, and may be turned on otherwise.

[0200] The sixth transistor M6 can be electrically coupled to or electrically connected between the second electrode of the first transistor M1 (i.e., the third node N3) and the first electrode of the light-emitting element LD (i.e., the fourth node N4). The gate electrode of the sixth transistor M6 can be electrically coupled to or electrically connected to the i+pth emission control line Ei+p (where p is a natural number). The sixth transistor M6 can be turned off when an emission control signal can be supplied via the i+pth emission control line Ei+p, and can be turned on in other cases. Therefore, the on-period of the fifth transistor M5 and the on-period of the sixth transistor M6 can only partially overlap with each other.

[0201] For example, the gate electrode of the sixth transistor M6 can be electrically coupled to or electrically connected to the i+4th emission control line Ei+4. The emission control signal supplied through the i+4th emission control line Ei+4 can be a signal obtained by delaying the emission control signal supplied through the i-th emission control line Ei by 4 horizontal periods (4H). However, this is merely exemplary, and the emission control line Ei+p electrically coupled to or electrically connected to the gate electrode of the sixth transistor M6 is not limited thereto.

[0202] The seventh transistor M7 can be electrically coupled or connected between the first electrode of the light-emitting element LD (i.e., the fourth node N4) and the initialization power supply Vint. The gate electrode of the seventh transistor M7 can be electrically coupled or connected to the i-th third scan line S3i. The seventh transistor M7 can be turned on when a scan signal is supplied via the i-th third scan line S3i, and can then supply a voltage of the initialization power supply Vint to the first electrode of the light-emitting element LD and the fourth node N4.

[0203] In an embodiment, the turn-on periods of the seventh transistor M7 and the sixth transistor M6 may not overlap with each other.

[0204] In an embodiment, the fourth transistor M4 to the seventh transistor M7 may be turned on at a first frequency, and the second transistor M2 and the third transistor M3 may be turned on at a second frequency, where the second frequency is different from the first frequency. For example, the second frequency may be lower than the first frequency. For example, the second frequency may be an equal part of the first frequency (the first frequency may be equally divided by the second frequency).

[0205] because Figure 11 The pixel 13 includes a ratio Figure 2A The pixel 10 has fewer transistors, so the layout of the pixel can be simplified and can be conducive to achieving high resolution.

[0206] Figure 12A It shows Figure 11 A timing diagram showing an example of driving a pixel.

[0207] Reference Figure 11 and Figure 12A , a signal for displaying an image may be supplied to the pixel 13 during the display scan period. The display scan period may include a period during which a data signal DVi corresponding to an output image may be written.

[0208] In the following, for the convenience of description, the following description can be made: the i-th emission control line Ei can be used as the emission control line Ei, the i+p-th emission control line Ei+p can be used as the subsequent emission control line Ei+p, the i-th first scan line S1i can be used as the first scan line S1i, the i-th second scan line S2i can be used as the second scan line S2i, the i-th third scan line S3i can be used as the third scan line S3i, and the i+q-th third scan line S3i+q can be used as the subsequent third scan line S3i+q.

[0209] During the first period P1, an emission control signal may be supplied via the emission control line Ei, a second scan signal may be supplied via the second scan line S2i, and a third scan signal may be supplied via the third scan line S3i. The fifth transistor M5 may be turned off in response to the emission control signal. Since the second scan signal may be supplied via the second scan line S2i and the third scan signal may be supplied via the third scan line S3i, the third transistor M3 and the seventh transistor M7 may be turned on. Since the emission control signal may not be supplied via the subsequent emission control line Ei+p, the sixth transistor M6 may remain turned on.

[0210] During the first period P1, the supply of driving current to the light emitting element LD may be stopped. When the seventh transistor M7 is turned on, the voltage of the initialization power supply Vint may be supplied to the fourth node N4. For example, the voltage of the initialization power supply Vint may be supplied to the gate electrode of the first transistor M1 (i.e., the second node N2) through the third transistor M3 and the sixth transistor M6 that may be turned on.

[0211] Therefore, during the first period P1, voltage initialization (ie, discharge of the parasitic capacitor) may be performed on the first electrode of the light emitting element LD and gate voltage initialization of the first transistor M1 may be performed. For example, the first period P1 may be an initialization period.

[0212] After the first period P1, the emission control signal is supplied to the subsequent emission control line Ei+p, and the sixth transistor M6 can be turned off. During the first period P1, the fifth transistor M5 can be turned off and the sixth transistor M6 can be turned on. For example, the length of the first period P1 can be about 4 horizontal periods (4H) or longer.

[0213] Thereafter, during a second period P2, a first scan signal may be supplied via the first scan line S1i. The second transistor M2 may be turned on so that the i-th data signal DVi may be supplied to the first node N1 via the data line Dj. Since the third transistor M3 may be in an on state, the first transistor M1 may be electrically coupled or connected in a diode configuration. For example, the second period P2 may be a data writing and threshold voltage compensation period.

[0214] After that, the second scan signal may be stopped from being supplied to the second scan line S2i, and the third scan signal may be stopped from being supplied to the third scan line S3i. Thus, the third transistor M3 and the seventh transistor M7 may be turned off. In an embodiment, the third transistor M3 and the seventh transistor M7 may be controlled simultaneously.

[0215] During the third period P3, a third scan signal may be supplied via the subsequent third scan line S3i+q. The fourth transistor M4 may be turned on in response to the third scan signal. When the fourth transistor M4 is turned on, the gate-off voltage (e.g., a logic high voltage) of the emission control signal may be supplied to the third node N3. During the third period P3, the first transistor M1 may be biased on. In an embodiment, the third scan signal may have a pulse width of approximately 4 horizontal periods (4H) or longer. Therefore, for a sufficient period of time, the logic high voltage of the emission control signal may be supplied to the first transistor M1.

[0216] In addition, the on-period of the third transistor M3 and the on-period of the fourth transistor M4 may not overlap with each other. For example, the initialization / compensation period and the bias period of the first transistor M1 may be separated from each other. The on-period of the fourth transistor M4 and the on-period of the seventh transistor M7 may not overlap with each other.

[0217] After that, the supply of emission control signals to the emission control line Ei and the subsequent emission control line Ei+p can be sequentially stopped, and the fifth transistor M5 and the sixth transistor M6 can be sequentially turned on. When the fifth transistor M5 and the sixth transistor M6 are turned on, a drive current generated based on the data signal DVi can be supplied to the light-emitting element LD, and the light-emitting element LD can emit light at a brightness corresponding to the drive current. The fourth period P4 during which both the fifth transistor M5 and the sixth transistor M6 can be turned on can be an emission period.

[0218] The operation corresponding to the display scan period can be implemented according to the frequency of the scan signal supplied to the first scan line S1i. For example, the display scan period can be represented by the second frequency described above.

[0219] Figure 12B It shows Figure 11 A timing diagram showing an example of driving a pixel.

[0220] Reference Figure 11 and Figure 12B In order to maintain the brightness of an image that may be output during the display scan period, an emission control signal may be applied to one electrode (eg, the drain electrode or the third node N3) of the first transistor M1 during the self scan period.

[0221] The self-scan period may include a bias period (e.g., a third period P3) and an emission period (e.g., a fourth period P4). In an embodiment, the operation corresponding to the self-scan period may be substantially the same as that of the display scan period, except that the first scan signal and the second scan signal may not be supplied.

[0222] During the self-scan period, the scan signal may not be supplied to the second transistor M2 and the third transistor M3. For example, during the self-scan period, the first scan signal supplied through the first scan line S1i may have a gate-off voltage (eg, a logic high voltage).

[0223] Since the second transistor M2 and the third transistor M3 remain turned off, the gate voltage of the first transistor M1 may not be affected by the driving of the self-scan period.

[0224] For example, the fourth to seventh transistors M4 to M7 may be turned on at a first frequency, and the second and third transistors M2 and M3 may be turned on at a second frequency, which may be different from the first frequency. For example, the second frequency may be lower than the first frequency.

[0225] During the third period P3 of the self-scan period, a third scan signal may be supplied via the third scan line S3i. The fourth transistor M4 may be turned on in response to the third scan signal. When the fourth transistor M4 is turned on, a logic high voltage of the emission control signal may be supplied to the third node N3. Therefore, since a conduction bias may be applied to the first transistor M1 during the third period P3, flickering that occurs during low-frequency driving may be improved.

[0226] Thereafter, during the fourth period P4, the fifth transistor M5 and the sixth transistor M6 may be turned on. Therefore, during the fourth period P4, the pixel 13 may emit light based on the data signal DVi supplied during the previous display scan period.

[0227] Figures 13 to 15 It shows Figure 11 Equivalent circuit diagram of a variation of the pixel.

[0228] Because in addition to the configuration of the fourth transistor M4, Figures 13 to 15 The pixels 13', 14 and 14' can be connected with Figure 2A The pixels 10 are identical or similar to each other, so the same reference numerals are used to designate the same or corresponding components, and thus their repeated description will be omitted.

[0229] Reference Figures 13 to 15 , each of the pixels 13 ′, 14 , and 14 ′ may include a light emitting element LD, first to seventh transistors M1 to M7 , and a storage capacitor Cst.

[0230] like Figure 13 As shown in , the pixel 13' may include a fourth transistor M4 electrically coupled or electrically connected between the i-th emission control line Ei and the first node N1. When the fourth transistor M4 is turned on, a logic high voltage may be supplied to the source electrode of the first transistor M1 as a bias voltage, and the first transistor M1 may have a conductive bias state.

[0231] like Figure 14 As shown in FIG, the fourth transistor M4 of the pixel 14 can be electrically coupled or electrically connected between the bias power supply VEH and the third node N3 (i.e., the drain electrode of the first transistor M1). The fourth transistor M4 can be turned on in response to the third scan signal supplied through the i+qth third scan line S3i+q.

[0232] When the fourth transistor M4 is turned on, the voltage of the bias power source VEH may be supplied to the drain electrode of the first transistor M1 as a bias voltage, and the first transistor M1 may have a turn-on bias state.

[0233] like Figure 15 As shown in FIG, the fourth transistor M4 of the pixel 14' can be electrically coupled or electrically connected between the bias power supply VEH and the first node N1 (i.e., the source electrode of the first transistor M1). The fourth transistor M4 can be turned on in response to the third scan signal supplied through the i+qth third scan line S3i+q.

[0234] Figures 13 to 15 The pixels 13', 14 and 14' can be Figure 12A and Figure 12B driver to display one or more images.

[0235] Figures 16 to 19 It shows Figure 11 Equivalent circuit diagram of a variation of the pixel.

[0236] In addition to the coupling relationship between the third transistor M3 and the seventh transistor M7, Figures 16 to 19 The pixels 15, 15', 16 and 16' can be respectively Figure 11 、 Figure 13 、 Figure 14 and Figure 15 The pixels are the same, so the same reference numerals are used to indicate the same or corresponding components, and their repeated description will be omitted.

[0237] Reference Figures 16 to 19 , each of the pixels 15 , 15 ′, 16 , and 16 ′ may include a light emitting element LD, first to seventh transistors M1 to M7 , and a storage capacitor Cst.

[0238] In an embodiment, the gate electrode of the third transistor M3 and the gate electrode of the seventh transistor M7 may be electrically coupled or connected to the second scan line S2i. Therefore, the third transistor M3 and the seventh transistor M7 may be controlled together. Since the second scan signal supplied through the second scan line S2i may be driven at a second frequency corresponding to the image frame rate, the third transistor M3 and the seventh transistor M7 may be turned on at the second frequency.

[0239] The gate electrode of the fourth transistor M4 can be electrically coupled to or connected to the (i+q)th scan line S3i+q for supplying the third scan signal. The fourth transistor M4 can be turned on at a first frequency in a manner similar to that of the fifth transistor M5 and the sixth transistor M6. For example, a conduction bias can be supplied to the first transistor M1 at the first frequency.

[0240] In other words, the seventh transistor M7 can be turned on at the second frequency, and the fourth transistor M4 can be turned on at the first frequency to supply the conduction bias voltage during both the display scan period and the self-scan period. For example, the third scan signal can be supplied at the first frequency, and the second scan signal can be supplied at a second frequency lower than the first frequency. For example, the second frequency can be different from the first frequency.

[0241] In an embodiment, the third scan signal may have the same waveform as the second scan signal, and the third scan signal supplied by the i+qth third scan line S3i+q may correspond to a signal obtained by delaying the second scan signal supplied by the i-th second scan line S2i by q horizontal periods (qH). However, this is merely exemplary, and the pulse width of the third scan signal and the pulse width of the second scan signal may be different from each other. For example, the second scan signal may be supplied during approximately 5 horizontal periods (5H), and the third scan signal may be supplied during 6H.

[0242] like Figure 16 As shown in , the fourth transistor M4 of the pixel 15 can supply the emission control signal as a bias voltage to the third node N3 (ie, the drain electrode of the first transistor M1).

[0243] like Figure 17 As shown in , the fourth transistor M4 of the pixel 15 ′ may supply the emission control signal as a bias voltage to the first node N1 (ie, the source electrode of the first transistor M1 ).

[0244] like Figure 18 As shown in , the fourth transistor M4 of the pixel 16 can supply the voltage of the bias power supply VEH as a bias voltage to the third node N3 (ie, the drain electrode of the first transistor M1).

[0245] like Figure 19As shown in FIG, the fourth transistor M4 of the pixel 16 ′ can supply the voltage of the bias power supply VEH as a bias voltage to the first node N1 (ie, the source electrode of the first transistor M1 ).

[0246] As described above, the pixel and the display device having the pixel according to the embodiment can support displaying images at various driving frequencies by allowing one display scanning period and at least one self-scanning period to be included in one frame. For example, as the driving frequency decreases, the number of self-scanning periods can increase, thereby improving the reduction in brightness and the perception of flicker that occurs when driving at a low frequency.

[0247] By periodically applying a constant bias voltage for biasing the first transistor to conduction to the first transistor via the fourth transistor, hysteresis (i.e., the difference in threshold voltage shift) due to conduction bias differences (and grayscale differences) between adjacent pixels can be overcome, regardless of the data signal and image grayscale. Consequently, motion blur (i.e., ghosting) due to hysteresis can be improved (or eliminated).

[0248] However, the advantages of the disclosure are not limited to the aforementioned advantages, and can be expanded in various forms without departing from the spirit and scope of the disclosure.

Claims

1. A pixel for a display device, the pixel comprising: Light-emitting element; a first transistor including a first electrode electrically connected to a first node electrically connected to a first power source, and a gate electrode directly connected to a second node, the first transistor controlling a drive current based on a voltage at the second node; a second transistor electrically connected between the data line and the first node and turned on in response to a first scan signal supplied through the first scan line; a third transistor electrically connected between the gate electrode of the first transistor and a third node and turned on in response to the first scan signal, the third node being electrically connected to the second electrode of the first transistor; as well as a fourth transistor that is turned on in response to a second scan signal supplied through a second scan line and applies a bias voltage to the first electrode or the second electrode of the first transistor, wherein The fourth transistor is turned on at a first frequency, and The second transistor and the third transistor are turned on at a second frequency different from the first frequency.

2. The pixel according to claim 1, wherein The second frequency is lower than the first frequency.

3. The pixel according to claim 1, wherein The second frequency is equal to the image refresh rate and corresponds to an equal portion of the first frequency.

4. The pixel according to claim 1, further comprising: a fifth transistor electrically connected between the first power source and the first node and turned off in response to an emission control signal supplied through an emission control line; a sixth transistor electrically connected between the third node and a fourth node and turned off in response to the emission control signal, the fourth node being electrically connected to the first electrode of the light emitting element; a seventh transistor electrically connected between the fourth node and a first initialization power source and turned on in response to the second scan signal; an eighth transistor electrically connected between the second node and a second initialization power source and turned on in response to a third scan signal supplied through a third scan line; as well as A storage capacitor is electrically connected between the first power source and the second node.

5. The pixel according to claim 4, wherein: The fifth transistor to the seventh transistor are turned on at the first frequency, and The eighth transistor is turned on at the second frequency.

6. The pixel according to claim 4, wherein The fourth transistor is electrically connected between the emission control line and the third node, and applies the emission control signal as the bias voltage to the third node in response to the second scan signal.

7. The pixel according to claim 4, wherein: The fourth transistor is electrically connected between the emission control line and the first node, and applies the emission control signal as the bias voltage to the third node in response to the second scan signal.

8. The pixel according to claim 4, wherein The fourth transistor is electrically connected between a bias power supply and the third node or between the bias power supply and the first node, and applies a voltage of the bias power supply as the bias voltage to the third node or the first node in response to the second scan signal.

9. A pixel for a display device, the pixel comprising: Light-emitting element; a first transistor including a first electrode electrically connected to a first node electrically connected to a first power source, and a gate electrode directly connected to a second node, the first transistor controlling a drive current based on a voltage at the second node; a second transistor electrically connected between the data line and the first node and turned on in response to a first scan signal supplied through the first scan line; a third transistor electrically connected between the gate electrode of the first transistor and a third node and turned on in response to a second scan signal supplied through a second scan line, the third node being electrically connected to the second electrode of the first transistor; as well as a fourth transistor that is turned on in response to a third scan signal supplied through a third scan line and applies a bias voltage to the first electrode or the second electrode of the first transistor, wherein The fourth transistor is turned on at a first frequency, The second transistor and the third transistor are turned on at a second frequency lower than the first frequency, and A length of a turn-on period of the second transistor and a length of a turn-on period of the third transistor are different from each other.

10. The pixel according to claim 9, wherein: The second frequency is equal to the image refresh rate and corresponds to an equal portion of the first frequency.

11. The pixel according to claim 9, further comprising: a fifth transistor electrically connected between the first power source and the first node and turned off in response to an emission control signal supplied through a first emission control line; a sixth transistor electrically connected between the third node and a fourth node electrically connected to the first electrode of the light emitting element and turned off in response to an emission control signal supplied through a second emission control line; a seventh transistor electrically connected between the fourth node and an initialization power source and turned on in response to the third scan signal supplied through a fourth scan line; as well as A storage capacitor is electrically connected between the first power source and the second node.

12. The pixel according to claim 11, wherein The fifth transistor and the sixth transistor are turned on at the first frequency.

13. The pixel of claim 11 , wherein: A portion of the off period of the fifth transistor overlaps a portion of the on period of the sixth transistor, and The third transistor and the seventh transistor are controlled simultaneously.

14. The pixel according to claim 13, wherein: A turn-on period of the fourth transistor does not overlap with a turn-on period of the third transistor and a turn-on period of the seventh transistor.

15. The pixel according to claim 13, wherein: The fourth transistor is electrically connected between the first emission control line and the third node or between the first emission control line and the first node, and applies the emission control signal as the bias voltage to the third node or the first node in response to the third scan signal.

16. The pixel according to claim 13, wherein: The fourth transistor is electrically connected between a bias power supply and the third node or between the bias power supply and the first node, and applies a voltage of the bias power supply as the bias voltage to the third node or the first node in response to the third scan signal.

17. A display device, comprising: a pixel electrically connected to the first scan line, the second scan line, the emission control line, and the data line; a scan driver that supplies a second scan signal to the second scan line at a first frequency and supplies a first scan signal to the first scan line at a second frequency corresponding to an image refresh rate of the pixel; a transmit driver that supplies a transmit control signal to the transmit control line at the first frequency; a data driver for supplying a data signal to the data line at the second frequency; as well as A timing controller controls the driving of the scan driver, the emission driver and the data driver, Among the pixels, the pixels arranged in the i-th horizontal row include: Light-emitting element; a first transistor including a first electrode electrically connected to a first node electrically connected to a first power source, and a gate electrode directly connected to a second node, the first transistor controlling a drive current based on a voltage at the second node; a second transistor electrically connected between the data line and the first node and turned on in response to a first scan signal supplied through an i-th first scan line; a third transistor electrically connected between the gate electrode of the first transistor and a third node and turned on in response to the first scan signal supplied through the i-th first scan line, the third node being electrically connected to the second electrode of the first transistor; and a fourth transistor that is turned on in response to a second scan signal supplied through an i-th second scan line and applies a bias voltage to the first electrode or the second electrode of the first transistor, wherein the second frequency is an equal part of the first frequency, Here, i is a natural number.

18. The display device according to claim 17, wherein: The scanning driver comprises: a first scan driver that supplies the first scan signal to the first scan line at the second frequency; and The second scan driver supplies the second scan signal to the second scan line at the first frequency.

19. The display device according to claim 18, wherein: The first scan driver supplies the first scan signal during a display scan period of one frame period and does not supply the first scan signal during a self scan period of the one frame period, the second scan driver supplies the second scan signal during the display scan period and the self scan period, The emission driver supplies the emission control signal during the display scan period and the self scan period, and The data signal is written to the pixel during the display scanning period.

20. The display device according to claim 17, wherein The pixels arranged in the i-th horizontal row further include: a fifth transistor electrically connected between the first power source and the first node and turned off in response to an emission control signal supplied through an i-th emission control line; a sixth transistor electrically connected between the third node and a fourth node, the fourth node being electrically connected to the first electrode of the light emitting element, and turned off in response to the emission control signal supplied through the i-th emission control line; a seventh transistor electrically connected between the fourth node and a first initialization power source and turned on in response to the second scan signal supplied through the i-th second scan line; an eighth transistor electrically connected between the second node and a second initialization power source and turned on in response to a first scan signal supplied through an (i-1)th first scan line; and A storage capacitor is electrically connected between the first power source and the second node.

21. The display device according to claim 20, wherein The fourth transistor is electrically connected between the i-th emission control line and the third node.

Images