Nonvolatile memory device and method for selecting word line

Abstract

Various embodiments of the present disclosure relate to a nonvolatile memory device and a method for selecting a word line. A nonvolatile memory device includes a memory cell array coupled to a word line and a row decoder, the row decoder including a first pull-down stage and a second pull-down stage, the first pull-down stage and the second pull-down stage being arranged on opposite sides of the array, and for each first word line, the first pull-down stage and the second pull-down stage respectively include a corresponding first pull-down switch circuit and a corresponding second pull-down switch circuit, the first pull-down switch circuit and the second pull-down switch circuit are respectively coupled to a first point and a second point of the first word line. The row decoder also includes a pull-up stage, for each first word line, the pull-up stage includes a corresponding pull-up switch circuit, the pull-up switch circuit is electrically controllable so as to: in the step of deselecting the first word line, couple the first point to a power supply node; and in the step of selecting the first word line, decouple the first point from the power supply node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Application No. 102019000021165, filed on November 14, 2019, which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a nonvolatile memory device including an asymmetric row decoder and a method for selecting a word line. Background Art

[0004] As is known, there are various types of non-volatile memories today, such as phase change memories (PCM), in which information is stored using the properties of materials characterized by switching between phases of different electrical behavior. These materials can switch between a disordered, amorphous phase and an ordered, crystalline or polycrystalline phase; the different phases are characterized by different resistivity values ​​and are therefore associated with different values ​​of the stored data. For example, elements of Group VI of the periodic table, such as tellurium (Te), selenium (Se) or antimony (Sb), also called chalcogenides or chalcogenide materials, can be used to make phase change memory cells; in particular, alloys formed by germanium (Ge), antimony (Sb) and tellurium (Te), known as GST (having the chemical composition Ge). 2 Sb 2 Te 5 ), which is currently widely used in this type of memory cell.

[0005] The phase change may be obtained by locally increasing the cell temperature of the chalcogenide material through resistive electrodes (commonly referred to as "heaters") placed in contact with corresponding regions of the chalcogenide material.

[0006] An access (or selection) device (e.g., a bipolar transistor or a MOS transistor) is connected to the heater and selectively enables a programming current (also called a write current) to pass through the heater. This current generates, by the Joule effect, the heat required for the phase change, and in particular the heat required to switch from a high-resistivity state (called the RESET state) to a low-resistivity state (the so-called SET state), or vice versa.

[0007] During reading, the state of the chalcogenide material is detected by applying a voltage low enough not to cause detectable heating of the chalcogenide material, and then reading the value of the current flowing in the memory cell through a sense amplifier. Given that the current is proportional to the conductivity of the chalcogenide material, it is possible to determine which state the material is in, and thereby determine the data stored in the memory cell.

[0008] Having said that, Figure 1It is shown that a non-volatile memory device 1 generally comprises a memory array 2 formed by a plurality of memory cells 3 arranged in rows or word lines WL and columns or bit lines (also referred to as "local bit lines LBL").

[0009] Each memory cell 3 is formed of a storage element 3a and an access element 3b, which are connected in series between a corresponding local bit line LBL and a terminal at a reference potential (e.g., ground, GND). A word line WL is defined by the set of all control terminals of the access elements 3b aligned along the same row.

[0010] The memory element 3a comprises an element of phase-change material (for example a chalcogenide such as GST) and is therefore capable of storing data in the form of resistance levels associated with the different phases adopted by the material itself.

[0011] The access element 3b is, for example, a bipolar transistor whose base terminal is connected to the corresponding word line WL. In addition, the emitter terminal is connected to the first terminal of the storage element 3a, and the collector terminal is connected to the terminal at the reference potential. The second terminal of the storage element 3a is connected to the corresponding local bit line LBL. The access element 3b is controlled and biased so that a read current or a write current can pass through the storage element 3a when selected.

[0012] The column decoder 4 and the row decoder 5 enable the selection of the memory cell 3 based on an address signal received at the input (specified as a whole by AS) and a more or less complex decoding scheme. The address signal AS can be generated by the control logic CL, which also governs the column decoder 4 and the row decoder 5 so as to enable reading and writing (SET and RESET) of the memory cell 3 addressed by the address signal AS. Although not shown, the control logic CL also provides control signals to the column decoder 4 and the row decoder 5 in order to control the above-mentioned read / write operations.

[0013] In particular, the column decoder 4 and the row decoder 5 enable the word line WL and the local bit line LBL to be selected each time they are addressed, and thus enable the selected word line WL and the local bit line LBL to be biased at appropriate voltage values.

[0014] Furthermore, the column decoder 4 is configured to internally implement, each time it is selected, two different paths towards the local bit lines LBL of the memory array 2: a read path designed to selectively create a conductive path between each selected local bit line LBL and a read stage 7 comprising a plurality of sense amplifiers, and a write path designed to selectively create a conductive path between each selected local bit line LBL and a write stage 8 configured to provide the current required for the write operation (i.e. the current required for the so-called programming of the memory cell in the corresponding logical state), and thus for storing information. To this end, for each read path and programming path, the column decoder 4 comprises appropriate selection elements (in particular controlled transistors) connected so as to implement an address decoding system for selecting the memory cells 3, which address decoding system is generally hierarchical. Summary of the invention

[0015] In more detail, various circuit architectures are known that enable the implementation of the row decoder 5. Typically, Figure 2A and Figure 2B As shown, the row decoder 5 includes a right circuit system 10R and a left circuit system 10L which are arranged on the right and left sides of the memory array 2, respectively. Figure 2A and Figure 2B , the memory array 2 is qualitatively represented without showing the memory cells 3 or the local bit lines LBL, and only eight word lines WL adjacent to each other (respectively represented by WL <0> ,…,WL <7> In this regard, it is assumed that eight word lines WL <0> ,…,WL <7> The memory cells 3 connected thereto form a sub-portion 6 (i.e., a sub-array) of the memory array 2. The memory array 2 includes a plurality of sub-portions 6 (in Figure 2A and Figure 2B only a subsection of it can be seen in the image).

[0016] In the following, unless otherwise stated, reference is made to Figure 2A and Figure 2BThe row decoder 5 is described with reference to only the portion coupled to the sub-portion 6 shown. Furthermore, for the sake of brevity, unless otherwise noted, only the left circuit system 10L is described, and it is contemplated that the right circuit system 10R is identical and symmetrical to the left circuit system 10L, except for the differences described below. Corresponding components of the left circuit system 10L and the right circuit system 10R are designated by the same reference numerals except for the last letter, which is "L" in the case of the left circuit system 10L and "R" in the case of the right circuit system 10R, and corresponding components of the left circuit system 10L and the right circuit system 10R are designated by the same terms except for the adjective, which is "left" in the case of the left circuit system 10L and "right" in the case of the right circuit system 10R.

[0017] In detail, the left side circuit system 10L includes a first left side preselection transistor LY_NL and a second left side preselection transistor LX_NL, which are N-channel enhancement type MOSFETs, which are identical to each other and connected in series. In particular, the source terminal of the first left side preselection transistor LY_NL is connected to ground. In addition, the source terminal of the second left side preselection transistor LX_NL is connected to the drain terminal of the first left side preselection transistor LY_NL. The drain terminal of the second left side preselection transistor LX_NL defines the left common node NL.

[0018] The left circuit system 10L also includes a circuit for each word line WL <0> To WL <7> 1 and 12. In turn, each left decoder branch 12L comprises a respective left bottom cascode transistor 14L and a respective left select transistor 16L, which are N-channel enhancement type MOSFETs and are, for example, identical to the first left pre-select transistor LY_NL and the second left pre-select transistor LX_NL. The source terminal of the left select transistor 16L is connected to the left common node NL, which is associated with the sub-portion 6 as described above. Furthermore, the drain terminal of the left select transistor 16L is connected to the source terminal of the left bottom cascode transistor 14L, which in turn is connected to the corresponding word line WL.

[0019] Overall, the left decoding branch 12L of the left circuitry 10L forms a left pull-down stage 15L which is identical from a circuit point of view to the right pull-down stage 15R of the right circuitry 10R and is coupled to the sub-portion 6 .

[0020] The left circuit system 10L further includes a corresponding left pull-up stage 18L, which includes four left pull-up circuits 20L (in Figure 2A and Figure 2B Only the two left pull-up circuits 20L can be seen in the figure.

[0021] In detail, each left pull-up circuit 20L includes a corresponding left top cascode transistor 22L, a corresponding left bias transistor 24L and a corresponding left deselect transistor 26L, which are P-channel enhancement type MOSFETs and are identical to each other. The source terminal of the left bias transistor 24L and the source terminal of the left deselect transistor 26L are connected to a power supply terminal, which is set to a power supply voltage V in use. DD (e.g., equal to 1.8V in the read step and equal to 4.8V in the write step). The drain terminal of the left bias transistor 24L and the drain terminal of the left deselect transistor 26L are connected to the source terminal of the left top cascode transistor 22L, which has its drain terminal connected to the word line WL <0> , WL <2> , WL <4> and WL <6> The corresponding word line in .

[0022] like Figure 4A As shown, the left bias transistor 24L (in Figure 4A Only one of the left bias transistors 24L can be seen in the figure, forming the left current mirror 25L, because the gate terminal of the left bias transistor 24L is connected to the gate terminal of the left mirror transistor 29L (P-channel enhancement MOSFET), and the source terminal of the left mirror transistor 29L is set to the power supply voltage V DD , and the gate terminal of the left mirror transistor 29L is connected to the drain terminal, which is in turn connected to the left current generation 31L, which generates the current I charge , the current I charge is mirrored in the left bias transistor 24L. Additionally, as described below, signal DESELECT_L is present at the gate terminal of the left deselect transistor 26L.

[0023] Except for the drain terminals of the top right cascode transistors 22R, each of which is connected to the word line WL <1> , WL <3> , WL <5> and WL <7> , the right pull-up stage 18R of the right circuit system 10R is identical to the left pull-up stage 18L of the left circuit system 10L. Although not shown, the right bias transistor 24R forms a right current mirror (not shown). In addition, as described below, a signal DESELECT_R is present on the gate terminal of the right deselect transistor 26R.

[0024] The gate terminal of the left bottom cascode transistor 14L of the left circuit system 10L and the gate terminal of the right bottom cascode transistor 14R of the right circuit system 10R are set to a first cascode voltage VCASC (e.g., equal to 1.8V in the read step and equal to 2.4V in the write step).

[0025] The gate terminal of the left top cascode transistor 22L of the left circuit system 10L and the gate terminal of the right top cascode transistor 22R of the right circuit system 10R are set to a second cascode voltage VCASC_P (e.g., equal to 0V in the read step and equal to 2.4V in the write step).

[0026] In practice, for each sub-portion 6 of the memory array 2 (one of the sub-portions 6 is in Figure 2A and Figure 2B ), the row decoder 5 includes a corresponding left pull-down stage 15L of the left circuit system 10L (one of the left pull-down stages 15L is in Figure 2A ) and the corresponding right pull-down stage 15R of the right circuit system 10R (one of the right pull-down stages 15R is shown in FIG. Figure 2B The left pull-down stage 15L and the right pull-down stage 15R respectively define corresponding left common nodes NL (one of the left common nodes NL is in Figure 2A ) and the corresponding right common node NR (one of the right common nodes NR is in Figure 2B In addition, each left pull-down stage 15L is coupled to a corresponding second left pre-select transistor LX_NL. Similarly, each right pull-down stage 15R is coupled to a corresponding second right pre-select transistor LX_NR.

[0027] Furthermore, subsections 6 are grouped in groups of subsections 6 (one of which is in Figure 2A and Figure 2B As can be seen in the diagram, designated by 7), each group comprises a preset number of sub-portions 6 (eg, eight).

[0028] For each group 7, the row decoder 5 includes a corresponding first left preselect transistor LY_NL (one of the first left preselect transistors LY_NL is in Figure 2A ), the drain terminal of the first left preselect transistor LY_NL is connected to eight second left preselect transistors LX_NL (one of the second left preselect transistors LX_NL is in Figure 2A The drain terminals of the eight second left pre-select transistors LX_NL are respectively connected to eight left common nodes NL corresponding to the eight sub-sections 6. In addition, for each group 7, the row decoder 5 includes a corresponding first right pre-select transistor LY_NR (one of the first right pre-select transistors LY_NR is in Figure 2B ), the drain terminal of the first right preselect transistor LY_NR is connected to eight second right preselect transistors LX_NR (one of which is in Figure 2BThe source terminals of the eight second right preselect transistors LX_NR are shown in FIG. 1 , and the drain terminals of the eight second right preselect transistors LX_NR are respectively connected to eight right common nodes NR corresponding to the eight sub-portions 6.

[0029] In practice, as described below, the first left pre-select transistor, the second left pre-select transistor, the first right pre-select transistor, and the second right pre-select transistor enable selection of any sub-portion 6 of the memory array 2. Furthermore, the first left pre-select transistor LY_NL, the second left pre-select transistor LX_NL, and the entirety of the left pull-down stage 15L form a left local selection stage, while the first right pre-select transistor LY_NR, the second right pre-select transistor LX_NR, and the entirety of the right pull-down stage 15R form a right local selection stage.

[0030] like Figure 3 As shown, the row decoder 5 also includes a pre-decoding stage 30, which generates a signal sLY<7:0>, a signal sLX<7:0>, and a signal PX<7:0> based on the address signal AS, which enable a hierarchical structure for selecting the word line WL. In particular, this example relates to the case where the memory array 2 includes eight groups 7, each of which includes eight sub-parts 6, and each of which includes eight corresponding word lines WL. In addition, it is expected that the decoding stage 30 also generates signals DESELECT_L<7:0> and DESELECT_R<7:0> as described below.

[0031] In more detail, the signals sLY<7:0> and sLX<7:0> enable selection of one of the sixty-four subsections 6 of the memory array 2 , and the signal PX<7:0> enables selection of one of the eight word lines WL of the selected subsection 6 .

[0032] Specifically, the decoding stage 30 converts the i-th signal sLY (i=0, 1, ..., 7) is applied to the gate terminals of the pair formed by the first left preselect transistor LY_NL and the second right preselect transistor LY_NR of the i-th group 7. In addition, in each of the eight groups 7, the decoding stage 30 converts the j-th signal sLX <j>(j=0, 1, ..., 7) is applied to the gate terminals of the transistor pair formed by the j-th second left preselect transistor LX_NL and the j-th second right preselect transistor LX_NR. In other words, in each group 7, the j-th signal sLX <j>is supplied to the second preselect transistor corresponding to the jth subsection 6. In addition, for each of the sixty-four subsections 6, the decoding stage 30 converts the mth signal PX <m>(where m=0, 1, ..., 7) is applied to the gate terminals of the left selection transistor 16L of the mth left decoding branch 12L and the right selection transistor 16R of the mth right decoding branch 12R; in other words, in each sub-section 6, the mth signal PX <m>is provided to the mth word line WL <m>A corresponding second selection transistor.

[0033] In use, pre-decoding stage 30 activates (by setting it equal to logic value "1" instead of "0") only one of the eight signals sLY<7:0>, one of the eight signals sLYX<7:0>, and one of the eight signals PX<7:0> at a time.<i*> 、sLX<j*> and PX<m*> Specifying the activated signals sLY, sLX, and PX, we find that:

[0034] - In the first left preselect transistor LY_NL and the first right preselect transistor LY_NR, only the signal sLY is received at its own gate terminal<i*> The two transistors of are in the on state, which is equivalent to selecting the i*th group 7;

[0035] In the second left preselect transistor LX_NL and the second right preselect transistor LX_NR, only the signal sLX is received at its own gate terminal.<i*> The two transistors of are in the on state, which is equivalent to selecting the j*th sub-section 6 in the i*th group 7, and the j*th sub-section 6 is connected to a pair of transistors through the corresponding left pull-down stage 15L and right pull-down stage 15R;

[0036] - In the left selection transistor 16L of the left pull-down stage 15L corresponding to the j*th subsection 6 of the i*th group 7, only the signal PX is received on its own gate terminal<m*> The left selection transistor 16L and the corresponding left bottom cascode transistor 14L are in the on state, and

[0037] In the right selection transistor 16R of the right pull-down stage 15R corresponding to the j*th subsection 6 of the i*th group 7, only the signal PX is received on its own gate terminal<m*> The right side selection transistor 16R and the corresponding right side bottom cascode transistor 14L are in the on state.

[0038] In practice, the signal sLY<i*> 、sLX<j*> and PX<m*> Enables selection of the m*th word line WL of the j*th subsection 6 of the i*th group 7<m*> , the m*th word line WL<m*> By symmetrically arranging the word lines WL<m*> The first conductive path and the second conductive path at the end of the first conductive path are connected to ground. In addition to the corresponding left bottom cascode transistor 14L, the first conductive path also includes: a first left preselect transistor LY_NL, which receives the signal sLY on its own gate terminal<i*> A second left preselect transistor LX_NL, the second left preselect transistor LX_NL coupled to the first left preselect transistor LY_NL and receives a signal sLX on its own gate terminal<j*> and the left side of the pull-down stage 15L corresponding to the selected sub-portion 6, the left side of the select transistor 16L, the left side of the select transistor 16L receives the signal PX on its own gate terminal<m*> Likewise, in addition to the corresponding right bottom cascode transistor 14L, the second conductive path also includes a first right preselect transistor LY_NR which receives the signal sLY at its own gate terminal.<i*> A second right preselect transistor LX_NR, the second right preselect transistor LX_NR coupled to the first right preselect transistor LY_NR, and receives a signal sLX at its own gate terminal<j*> and the right side of the pull-down stage 15R corresponding to the selected sub-portion 6 select transistor 16R, the right side select transistor 16R receives the signal PX on its own gate terminal<m*> .

[0039] Thus, the first conductive path and the second conductive path enable the selected word line WL to be connected to the ground in a symmetrical manner. In this way, the voltage difference that the base terminal of the bipolar transistor forming the access element 3b coupled to the selected word line WL inevitably bears is reduced in consideration of the current flowing in the selected word line WL. In contrast, the unselected word line WL is disconnected from the ground, and, as described below, the unselected word line WL is set to a voltage corresponding to a high logic level.

[0040] exist Figure 4A The word line WL of the j*th subsection 6 of the i*th group 7 is shown in FIG. <0> An example of this is shown in FIG. 1 , which highlights the <0> In the coupled left pull-up circuit 20L, how does the left deselect transistor 26L receive the signal DESELECT_L having a high logic value at its own gate terminal?<i*> , so that no current flows in the left-side deselect transistor 26L. Therefore, it is found that the current I charge In the left bias transistor 24L, in the corresponding left top cascode transistor 22L, a signal PX is received at its gate terminal. <0> The select transistor 16L of FIG. 1 and the corresponding left bottom cascode transistor 14L and the receiving signal sLY<i*> The first left preselect transistor LX_NL is coupled to the second left preselect transistor LX_NL and receives the signal sLX<j*> In this way, the word line WL <0> At low voltage due to connection to ground.

[0041] In more detail, although Figure 4A It is not visible in the figure, but the gate terminals of all left-side deselect transistors 26L of the left-side pull-up circuit 20L of the i-th group 7 receive the same signal DESELECT_L , which is the same as the signal DESELECT_R present on the gate terminal of the right deselect transistor 26R of the right pull-up circuit 20R of group 7. In addition, the signal sLY and DESELECT_L (DESELEC_L Equal to DESELECT_R ) have the same logic value. Therefore, when selecting the m*th word line WL of the j*th sub-section 6 of the i*th group 7<m*> In the case of the j*th sub-portion 6 of the i*th group 7 and the m*th word line WL<m*> Different word lines are deselected because they are at a high voltage due to the disabling of the corresponding left select transistor 16L and right select transistor 16R and because they are coupled to the power supply terminal through the corresponding bias transistor (depending on whether the word line is an even word line or an odd word line, the left bias transistor 24L or the right bias transistor 24R).

[0042] In the i**th unselected group 7 (e.g., Figure 4B In the case shown in<i**> is low, thereby disabling the corresponding first left preselect transistor LY_NL and the corresponding first right preselect transistor LY_NR. In addition, the signal DESELECT_L<i**> is also low, thereby keeping the left deselect transistor 26L coupled to the i**th group 7 above threshold, thus raising the voltage on the odd word line connected thereto.<i**> is also low, so the right deselect transistor 26R coupled to the i**th group 7 is also above threshold, thereby raising the voltage on the even word line connected thereto.

[0043] For example, assuming that word line WL of j*th subsection 6 of i*th group 7 has been selected <0> , Figure 4B The word line WL of the j*th subsection 6 of the i**th group 7 is shown. <0> It can be noted that the word line WL <0> How to have a high voltage, and thus be deselected, because even if the corresponding left select transistor 16L is above the threshold, the first conductive path is interrupted due to the disabling of the first left preselect transistor LY_NL (and similarly, although in Figure 4B Similar considerations apply to the case (not shown) of any deselected j**th subsection 6 of the (selected) i*th group 7, in which the corresponding second left preselect transistor LX_NL and second right preselect transistor LX_NR are disabled.

[0044] In practice, the pull-up stage 18R of the right circuit system 10R and the pull-up stage 18L of the left circuit system 10L can be controlled to increase the voltage of the selected word line. However, the pull-up stage 18R of the right circuit system 10R and the pull-up stage 18L of the left circuit system 10L form a pull-up macro stage that is partially distributed in the right and left parts of the memory array 2 and has a high area occupation.

[0045] It is therefore an object of the present invention to provide a row decoder which will at least partially overcome the disadvantages of the prior art.

[0046] According to the present invention, there are provided a memory device and a method for selecting a word line as defined in the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] For a better understanding of the present invention, preferred embodiments of the present invention will now be described, by way of example only and not limitation, with reference to the accompanying drawings, in which:

[0048] Figure 1 shows a block diagram of a PCM device;

[0049] Figure 2A and Figure 2B A portion of the same circuit diagram showing a row decoder of known type;

[0050] Figure 3 A block diagram of a portion of a row decoder is shown;

[0051] Figure 4A and Figure 4B Shows Figure 2A and Figure 2B A circuit diagram of a portion of a row decoder shown in FIG.

[0052] Figure 5 A block diagram showing an example of the present memory device is shown;

[0053] Figure 6 Shows Figure 5 A circuit diagram of a portion of a row decoder of a memory device coupled to a pair of memory arrays (schematically represented) shown in FIG. ;

[0054] Figure 7 Shows Figure 5 a circuit diagram of a portion of a memory device shown in; and

[0055] Figure 8 A block diagram of an electronic device incorporating the present memory device is shown. DETAILED DESCRIPTION

[0056] The row decoder of the present invention originates from the observation of the applicant, who noticed how the pull-up circuits 20L, 20R can be concentrated because, unlike the left and right pull-down stages 15L, 15R, the pull-up circuits 20L, 20R do not have the task of discharging the word lines WL and can therefore be arranged asymmetrically without increasing the voltage drop on these word lines WL when these word lines WL are selected (i.e., active).

[0057] Having said this, Figure 5 A non-volatile memory device 100 is shown, which includes (although not shown) in an exemplary manner only with Figure 1 Furthermore, again in an exemplary manner, the nonvolatile memory device 100 includes a first right memory array 102A_R and a second right memory array 102B_R and a first left memory array 102A_L and a second left memory array 102B_L, each of which is similar to the memory array of reference 102A_R. Figure 1 The memory arrays 2 described are identical. As described in more detail below, the first and second right memory arrays 102A_R and 102B_R and the first and second left memory arrays 102A_L and 102B_L are arranged in a horizontally aligned manner.

[0058] The nonvolatile memory device 100 further includes a row decoder 105, which in turn includes a central deselection stage 118, which is arranged such that the first right memory array 102A_R and the second right memory array 102B_R are arranged on the right side of the central deselection stage 118, with the first right memory array 102A_R being inserted between the central deselection stage 118 and the second right memory array 102B_R. Likewise, the first left memory array 102A_L and the second left memory array 102B_L are arranged on the left side of the central deselection stage 118, with the first left memory array 102A_L being inserted between the central deselection stage 118 and the second left memory array 102B_L.

[0059] For each memory array, the row decoder 105 includes a right local selection stage 110R and a left local selection stage 110L, which extend on the right and left sides of the memory array, respectively. The left local selection stage 110L corresponding to the first left memory array 102A_L is arranged on the right side of the right local selection stage 110R corresponding to the second left memory array 102B_L. The right local selection stage 110R corresponding to the first right memory array 102A_R is arranged on the left side of the left local selection stage 110L corresponding to the second right memory array 102B_R.

[0060] In the following, in order to simplify the description, it is assumed that the first right memory array 102A_R and the second right memory array 102B_R and the first left memory array 102A_L and the second left memory array 102B_L are identical to each other. In addition, it is assumed that each of the first right memory array 102A_R and the second right memory array 102B_R and the first left memory array 102A_L and the second left memory array 102B_L includes the same number N group (e.g., equal to eight) Figure 7 The group (specified by 106) Figure 7 107 in the figure), hereinafter referred to as subarray 106. In addition, it is assumed that each group 107 includes a certain number N array (e.g., equal to eight) sub-arrays 106, each of which includes, for example, 1024 word lines. In addition, considering the sub-arrays 106 of any of the first right memory array 102A_R and the second right memory array 102B_R and the first left memory array 102A_L and the second left memory array 102B_L, the corresponding right local selection stage 110R and the left local selection stage 110L respectively include corresponding right pull-down stages (designated by 115R, one of which is in Figure 7 ) and the corresponding left pull-down stage (designated by 115L, where one left pull-down stage is Figure 7 ), the right pull-down stage and the left pull-down stage are, for example, Figure 2A The type shown, and Figure 2A The components of the right pull-down stage 115R and the components of the left pull-down stage 115L are hereinafter referred to as the same, except for the left common node and the right common node, which are again represented by NL and NR, respectively. Figure 2B The same reference numerals as used in the above are indicated by increasing one hundred. In addition, considering any subarray 106 of any of the first right memory array 102A_R and the second right memory array 102B_R and the first left memory array 102A_L and the second left memory array 102B_L, the corresponding right local selection stage 110R includes a plurality of first right pre-select transistors LY_NR, the number of which is equal to the number N of the groups 107. group , and for each of the first right pre-select transistors LY_NR, a plurality of second right selection transistors LX_NR are included, the number of which is equal to the number N of the sub-arrays 106 array The connection between the right pull-down stage 115R and the first right pre-select transistor LY_NR and the second right select transistor LX_NR is similar to the reference Figure 2B Likewise, considering any subarray 106 of any of the first right memory array 102A_R and the second right memory array 102B_R and the first left memory array 102A_L and the second left memory array 102B_L, the corresponding left local selection stage 110L includes a plurality of first left preselect transistors LY_NL, the number of which is equal to the number N of groups 107. group , and for each of the first left pre-select transistors LY_NL, a plurality of second left selection transistors LX_NL are included, the number of which is equal to the number N of the sub-arrays 106 array The connection between the left pull-down stage 115L and the first left pre-select transistor LY_NL and the second left select transistor LX_NL is similar to the reference Figure 2A Same as described.

[0061] In addition, it is assumed that the first right memory array 102A_R and the second right memory array 102B_R are traversed by a plurality of word lines, and thus the first right memory array 102A_R and the second right memory array 102B_R are shared between a plurality of word lines, which are hereinafter referred to as right word lines WL_dx. In addition, it is assumed that the first left memory array 102A_L and the second left memory array 102B_L are traversed by a plurality of word lines, and thus the first left memory array 102A_L and the second left memory array 102B_L are shared between a plurality of word lines, which are hereinafter referred to as left word lines WL_sx. The right word lines and the left word lines extend horizontally and are stacked vertically.

[0062] like Figure 6 As shown, for each subsection 106, the central deselection stage 118 includes 1024 corresponding central pull-up circuits 120 (in Figure 6 Only two of the central pull-up circuits 120 can be seen in the drawing, each of which is coupled to a corresponding word line pair formed by a left word line WL_sx and a right word line WL_dx.

[0063] For example, referring to the nth central pull-up circuit 120, it is coupled to the left word line WL_sx <n>and right word line WL_dx <n>, these word lines extend on the left and right sides of the central pull-up circuit 120, respectively.

[0064] In more detail, each central pull-up circuit 120 includes a corresponding left top cascode transistor 122L and a corresponding right top cascode transistor 122R, which are P-channel enhancement type MOSFETs and are identical to each other; furthermore, each central pull-up circuit 120 includes a corresponding left deselect transistor 126L and a corresponding right deselect transistor 126R, which are P-channel enhancement type MOSFETs and are identical to the left top cascode transistor 122L and the right top cascode transistor 122R. Further, each central pull-up circuit 120 includes a corresponding control circuit 199.

[0065] The gate terminal of the left top cascode transistor 122L and the gate terminal of the right top cascode transistor 122R are set to be at the second cascode voltage VCASC_P. The gate terminal of the left top cascode transistor 122L and the drain terminal of the right top cascode transistor 122R are respectively connected to the left word line WL_sx <n>and right word line WL_dx <n>The drain terminal of the left deselect transistor 126L and the drain terminal of the right deselect transistor 126R are connected to the source terminal of the left top cascode transistor 122L and the source terminal of the right top cascode transistor 122R, respectively. In addition, the source terminal of the left deselect transistor 126L and the source terminal of the right deselect transistor 126R are connected to the power supply voltage V DD .

[0066] In use, each control circuit 199 receives signals sLX, sLY and PX from the pre-decoding stage 30 (see reference 1). Figure 2A and Figure 2B The pre-decoding stage 30 does not generate the signal DESELECT). In this regard, considering any sub-array 106 of any of the first right memory array 102A_R and the second right memory array 102B_R and the first left memory array 102A_L and the second left memory array 102B_L, the corresponding right local selection stage 110R and the left local selection stage 110L are generated by the decoding stage 30 with the reference Figure 2A and Figure 2B In addition, the right local selection stages 110R of the first right memory array 102A_R and the second right memory array 102B_R and the left local selection stages 110L of the first left memory array 102A_L and the second left memory array 102B_L receive the same signals sLX, sLY, and PX.

[0067] In addition, each control circuit 199 generates a corresponding signal Vcomm <n>, the signal is applied to the gate terminal of the corresponding left deselect transistor 126L and the gate terminal of the corresponding right deselect transistor 126R. In other words, each central pull-up circuit 120 forms a pair of pull-up switch circuits, which respectively control the corresponding left word line WL_sx and the corresponding right word line WL_dx driven in the same manner.

[0068] Next, consider the symmetry of the nonvolatile memory device 100 and for simplicity, refer to Figure 7 The content shown only describes the selection / deselection of the right word line WL_dx. In addition, unless otherwise specified, reference will be made to the ordinary sub-array 106 of the ordinary group 107 of the first right memory array 102A_R in the following text, which is coupled to the signal sLY. <0> The first left preselect transistor LY_NL and the first right preselect transistor LY_NR driven by the signal sLX <0> The second left pre-select transistor LX_NL and the second right pre-select transistor LX_NR driven by the MOSFET are shown in FIG. Figure 7 , in which E sx and E dx The designated two points are arranged at the end of each right word line WL_dx crossing the portion of the first right memory array 102A_R, connected to the corresponding left decoding branch 112L (particularly, the drain terminal of the corresponding left bottom cascode transistor 114L) of the left pull-down stage 115L and the corresponding right decoding branch 112R (particularly, the drain terminal of the corresponding right bottom cascode transistor 114R) of the right pull-down stage 115R, respectively. In the following, point E sx and E dx are respectively called the left point E sx and right point E dx In addition, the left point E sx Than the right point E dx Closer to the center the selection stage 118 is deselected.

[0069] In practice, consider the corresponding left point E sx and the corresponding right point E dx The portion of the right word line WL_dx between the right word line WL_dx and the right word line WL_dx between the right word line WL_dx and the left ... dx Couple to the right common node NR / connect the right point E dx Decouple the right common node NR and the left point E sx Coupled to the left common node NL / connect the left point E sx Decoupled from the left common node NL. In addition, the left point E sx Connected to the drain terminal of the right top cascode transistor 122R of the corresponding central pull-up circuit 120 .

[0070] Although not shown in detail, the same considerations apply to the left word line WL_sx and the corresponding coupling to the left decoding branch 112L of the left pull-down stage 115L and the corresponding coupling to the right decoding branch 115R of the right pull-down stage 115R. In this case, taking the first left memory array 102A_L as an example, and if the right point E dx and left point E sx Designated is the end of the portion of each left word line WL_sx that crosses the first left memory array 102A_L (eg Figure 6 As shown, they are close to and away from the central deselection level 118, respectively, where the pull-down level is not shown for simplicity of representation), the right point E dx Connected to the drain terminal of the left top cascode transistor 122L of the corresponding central pull-up circuit 120 .

[0071] For the sake of completeness, Figure 6 A corresponding additional left point E is also shown for each right word line WL_dx sx ' and the corresponding additional right point E dx ', these two points define a portion of the right word line WL_dx that crosses the second right memory array 102B_R, and the two points are respectively coupled to the corresponding left decoding branches 112L ( Figure 6 ) and the corresponding right decoding branch 112R ( Figure 6 Additional left point E sx ' and the right point E of the right word line WL_dx dx Electricity consistent.

[0072] Referring again to the control circuit 199, the control circuit 199 drives the nth right word line WL_dx of the normal sub-array 106 of the normal group 107 of the first right memory array 102A_R. <n>If the pre-decoding stage 30 indicates through the signals sLX, sLY and PX that the nth right word line WL_dx is selected <n>, the control circuit 199 will signal Vcomm <n>is set to a high logic value (e.g., equal to 1.8V in the read step and equal to 4.8V in the write step). In this way, the right deselect transistor 126R is disabled and as shown in the reference Figure 2A and Figure 2B As described, the nth right word line WL_dx <n>With the power node V DD Decoupled, discharged to ground through the corresponding left decoding branch 112L and the corresponding right decoding branch 115R.

[0073] In contrast, the nth right word line WL_dx is deselected at the pre-decoding stage 30 through the signals sLX, sLY and PX. <n>In this case, the corresponding control circuit 199 will signal Vcomm <n>is set to a low logic value (e.g., equal to 0V in the read step and equal to 2.4V in the write step). In this way, the right deselect transistor 126R is turned on, and the nth right word line WL_dx <n>Coupled to the power supply node V DD , thus being charged. In this case, as referenced Figure 2A and Figure 2B As described, the right word line WL_dx <n>Decoupled from ground.

[0074] In more detail, both charging (in the case of deselection) and discharging (in the case of selection) involve the entire right word line WL_dx <n>, that is, it involves the nth right word line WL_dx that crosses the first right memory array 102A_R <n>In fact, as previously described, the right local selection stage 110R and the left local selection stage 110L of the first right memory array 102A_R and the right local selection stage 110R and the left local selection stage 110L of the second right memory array 102B_R are all driven in the same manner. Therefore, in the case of selection, the right word line WL_dx <n>Additional left point E sx ' and add the right point E dx ' respectively connected to ground through the corresponding left decoding branch 112L and the corresponding right decoding branch 112R; in addition, in the case of deselection, the additional left point E sx ' and add the right point E dx 'Decoupled from ground. The same considerations apply to the left word line WL_sx.

[0075] Select the right word line WL_dx <n>In the case of a column decoder 4, the column decoder 4 can thus enable parallel reading of the memory cells 3, which are coupled to the right word line WL_dx <n>And belongs to the first right memory array and / or the second right memory array 102B_R. More generally, as described above, since the right local selection stage 110R and the left local selection stage 110L of the first right memory array 102A_R, the right local selection stage 110R and the left local selection stage 110L of the second right memory array 102B_R, the right local selection stage 110R and the left local selection stage 110L of the first left memory array 102A_L, and the right local selection stage 110R and the left local selection stage 110L of the second left memory array 102B_L receive the same signals sLX, sLY, and PX, and the control circuit 199 drives the corresponding left word lines WL_sx and right word lines WL_dx in the same manner, the column decoder 4 can enable parallel reading of the right word lines WL_dx coupled to the right word lines. <n>The first right memory array 102A_R and / or the second right memory array 102B_R of the memory cell 3, and the parallel read coupled to the left word line WL_sx <n>The first left memory array 102A_L and / or the second left memory array 102B_L of the memory cell 3.

[0076] For practical purposes, the nonvolatile memory device 100 may be used in many applications. For example, Figure 8 A portion of an electronic device 570 is shown, which may be, for example: a PDA (personal digital assistant); a portable or fixed computer capable of wireless data transmission; a mobile phone; a digital audio player; a camera or camcorder; or other device capable of processing, storing, transmitting and receiving information.

[0077] In detail, the electronic device 570 includes: a controller 571 (for example, provided with a microprocessor, DSP or microcontroller); an input / output device 572 for inputting and displaying data (for example, provided with a keyboard and a display); a non-volatile memory device 100; a wireless interface 574 for sending and receiving data through a radio frequency wireless communication network, such as an antenna; and a RAM 575. All components of the electronic device 570 are coupled through a bus 576. A battery 577 can be used as a power source in the electronic device 570, and the electronic device 570 can also be provided with a camera or a video camera 578. In addition, the controller 571 can control the non-volatile memory device 100, for example, by cooperating with the control logic CL.

[0078] The advantages provided by the row decoder of the invention are clearly revealed by the preceding description. In particular, the asymmetric decoder of the invention enables the area used to be reduced without compromising the quality of the selection of the word lines. Thus, a particularly advantageous use is found in the case of memory devices with active line consumption, i.e. in the case of word lines which are traversed by a current when selected.

[0079] Finally, it is evident that modifications and variations may be made to what has been described and illustrated herein, without departing from the scope of the present invention as defined in the appended claims.

[0080] For example, the memory cell may be of a different type than that already described. In particular, the access element 3 b may be of a different type than that already described; for example, the access element 3 b may be a MOSFET. On the other hand, for example in the case of a so-called flash-type non-volatile memory device, the access element 3 b may not even be present.

[0081] Furthermore, the memory device 100 may include a different number and / or a different arrangement of memory arrays. Furthermore, the scheme of hierarchical selection of subarrays 106 may differ from that which has been described.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m> < / m> < / j> < / j>

Claims

1. A non-volatile memory device, include: at least one first array of memory cells arranged in rows and coupled to a first word line; as well as a row decoder comprising: a first pull-down stage and a second pull-down stage, the first pull-down stage and the second pull-down stage being arranged on opposite sides of the first array, and for each first word line, the first pull-down stage and the second pull-down stage respectively comprising a corresponding first pull-down switch circuit and a corresponding second pull-down switch circuit, the first pull-down switch circuit and the second pull-down switch circuit being coupled to a first point and a second point of the first word line, respectively; Wherein the first pull-down switch circuit is electrically controllable so as to: When the first word line is selected, coupling the first point to a corresponding first node; and decoupling the first point from the corresponding first node when the first word line is deselected; wherein the second pull-down switch circuit is electrically controllable so as to: When the first word line is selected, coupling the second point to a corresponding second node; and When the first word line is deselected, the second point is decoupled from the corresponding second node; and The row decoder further comprises a pull-up stage, wherein for each first word line, the pull-up stage comprises a corresponding first pull-up switch circuit, wherein the first pull-up switch circuit is electrically controllable so as to: coupling the first point of the first word line to a power supply node when the first word line is deselected; and When the first word line is selected, the first point of the first word line is decoupled from the power supply node.

2. The memory device according to claim 1, further comprising: include: a second array of memory cells arranged in rows and coupled to a second word line; wherein the row decoder further comprises a first additional pull-down switch circuit and a second additional pull-down switch circuit, the first additional pull-down switch circuit and the second additional pull-down switch circuit being arranged on opposite sides of the second array, and for each second word line, the first additional pull-down switch circuit and the second additional pull-down switch circuit respectively comprise a corresponding first additional pull-down switch circuit and a corresponding second additional pull-down switch circuit, the first additional pull-down switch circuit and the second additional pull-down switch circuit respectively being coupled to a first point and a second point of the second word line; wherein the first additional pull-down switch circuit is electrically controllable so as to: When the second word line is selected, coupling the first point of the corresponding second word line to the corresponding first additional node; and when the second word line is deselected, decoupling the first point of the corresponding second word line from the corresponding first additional node; wherein the second additional pull-down switch circuit is electrically controllable so as to: When the second word line is selected, coupling the second point of the corresponding second word line to the corresponding second additional node; and When the second word line is deselected, the second point of the corresponding second word line is decoupled from the corresponding second additional node; and Wherein for each second word line, the pull-up stage further comprises a corresponding second pull-up switch circuit, the second pull-up switch circuit being electrically controllable so as to alternatively: coupling the first point of the second word line to the power supply node when the second word line is deselected; and When the second word line is selected, the first point of the second word line is decoupled from the power supply node.

3. The memory device of claim 2, wherein the pull-up stage is inserted between the first array and the second array.

4. The memory device according to claim 3, further comprising: include: an external array of memory cells arranged in rows and coupled to the first word line, wherein the first array is interposed between the pull-up stage and the external array; wherein the row decoder further comprises a first external pull-down switch circuit and a second external pull-down switch circuit, the first external pull-down switch circuit and the second external pull-down switch circuit being arranged on opposite sides of the outer array, and for each first word line, the first external pull-down switch circuit and the second external pull-down switch circuit respectively comprise a corresponding first external pull-down switch circuit and a corresponding second external pull-down switch circuit, the first external pull-down switch circuit and the second external pull-down switch circuit respectively being coupled to a first additional point and a second additional point of the first word line; wherein the first external pull-down switch circuit is electrically controllable so as to: When the first word line is selected, coupling the corresponding first additional point to the corresponding first external node; and when the first word line is deselected, decoupling the corresponding first additional point from the corresponding first external node; and wherein the second external pull-down switch circuit is electrically controllable so as to: When the first word line is selected, coupling the corresponding second additional point to the corresponding second external node; and When the first word line is deselected, the corresponding second additional point is decoupled from the corresponding second external node.

5. The memory device according to claim 2, further comprising: include: a control stage configured to select one of the first word lines and deselect first word lines other than the selected first word line, wherein the control stage is further configured to: controlling the first pull-down switch circuit and the second pull-down switch circuit corresponding to the selected first word line so as to couple the first point and the second point of the selected first word line to the corresponding first node and the corresponding second node, respectively, and controlling the first pull-up switch circuit corresponding to the selected first word line so as to decouple the first point of the selected first word line from the power supply node; and For each deselected first word line, the first pull-down switch circuit and the second pull-down switch circuit corresponding to the deselected first word line are controlled so as to decouple the first point and the second point of the deselected first word line from the corresponding first node and the corresponding second node, respectively, and the first pull-up switch circuit corresponding to the deselected first word line is controlled so as to couple the first point of the deselected first word line to the power supply node.

6. The memory device of claim 5 , wherein the control stage is further configured to select one of the second word lines and deselect second word lines other than the selected second word line, and wherein the control stage is further configured to: controlling the first additional pull-down switch circuit and the second additional pull-down switch circuit corresponding to the selected second word line so as to couple the first point and the second point of the selected second word line to the corresponding first additional node and the corresponding second additional node, respectively, and controlling the second pull-up switch circuit corresponding to the selected second word line so as to decouple the first point of the selected second word line from the power supply node; and For each deselected second word line, the first additional pull-down switch circuit and the second additional pull-down switch circuit corresponding to the deselected second word line are controlled so as to decouple the first point and the second point of the deselected second word line from the corresponding first additional node and the corresponding second additional node, respectively, and the second pull-up switch circuit corresponding to the deselected second word line is controlled so as to couple the first point of the deselected second word line to the power supply node.

7. The memory device according to claim 2, wherein the first array is divided into sub-arrays; wherein the first node corresponding to the first word line of each sub-array is electrically consistent with the corresponding first common node; wherein the second node corresponding to the first word line of each sub-array is electrically consistent with the corresponding second common node; Wherein for each sub-array, the first pull-down switch circuit and the second pull-down switch circuit respectively include a first sub-array selection circuit and a second sub-array selection circuit; wherein the first subarray selection circuit is inserted between the first common node and a node at a reference potential, and the first subarray selection circuit is controllable so as to couple the first common node to the node at the reference potential; and The second sub-array selection circuit is inserted between the second common node and the node at the reference potential, and the second sub-array selection circuit is controllable so as to couple the second common node to the node at the reference potential.

8. The memory device according to claim 7, further comprising: include: a control stage configured to select one of the first word lines and deselect first word lines other than the selected first word line, wherein the control stage is further configured to: controlling the first pull-down switch circuit and the second pull-down switch circuit corresponding to the selected first word line so as to couple the first point and the second point of the selected first word line to the corresponding first node and the corresponding second node, respectively, and controlling the first pull-up switch circuit corresponding to the selected first word line so as to decouple the first point of the selected first word line from the power supply node; and for each deselected first word line, controlling the first pull-down switch circuit and the second pull-down switch circuit corresponding to the deselected first word line so as to decouple the first point and the second point of the deselected first word line from the corresponding first node and the corresponding second node, respectively, and controlling the first pull-up switch circuit corresponding to the deselected first word line so as to couple the first point of the deselected first word line to the power supply node; controlling the first subarray selection circuit and the second subarray selection circuit corresponding to the subarray including the selected first word line so as to couple the corresponding first common node and the corresponding second common node to the node at the reference potential; and The first subarray selection circuit and the second subarray selection circuit corresponding to each subarray except the subarray including the selected first word line are controlled to decouple the corresponding first common node and the corresponding second common node from the node at the reference potential.

9. The memory device of claim 1, wherein each memory cell comprises a corresponding selector and a corresponding phase change element.

10. The memory device of claim 9, wherein the corresponding selector comprises a bipolar transistor.

11. An electronic device, include: Controller; a bus coupled to the controller; as well as a non-volatile memory device, communicatively coupled to the controller via the bus, the non-volatile memory device comprising: at least one first array of memory cells arranged in rows and coupled to a first word line; and a row decoder comprising a first pull-down stage and a second pull-down stage, the first pull-down stage and the second pull-down stage being arranged on opposite sides of the first array, and for each first word line, the first pull-down stage and the second pull-down stage respectively comprising a corresponding first pull-down switch circuit and a corresponding second pull-down switch circuit, the first pull-down switch circuit and the second pull-down switch circuit respectively being coupled to a first point and a second point of the first word line; Wherein the first pull-down switch circuit is electrically controllable so as to: When the first word line is selected, coupling the first point to a corresponding first node; and When the first word line is deselected, decoupling the first point from the corresponding first node; wherein the second pull-down switch circuit is electrically controllable so as to: When the first word line is selected, coupling the second point to a corresponding second node; and When the first word line is deselected, the second point is decoupled from the corresponding second node; and The row decoder further comprises a pull-up stage, wherein for each first word line, the pull-up stage comprises a corresponding first pull-up switch circuit, wherein the first pull-up switch circuit is electrically controllable so as to: coupling the first point of the first word line to a power supply node when the first word line is deselected; and When the first word line is selected, the first point of the first word line is decoupled from the power supply node.

12. The electronic device according to claim 11, wherein the non-volatile memory device further comprises: include: a second array of memory cells arranged in rows and coupled to a second word line; wherein the row decoder further comprises a first additional pull-down switch circuit and a second additional pull-down switch circuit, the first additional pull-down switch circuit and the second additional pull-down switch circuit being arranged on opposite sides of the second array, and for each second word line, the first additional pull-down switch circuit and the second additional pull-down switch circuit respectively comprise a corresponding first additional pull-down switch circuit and a corresponding second additional pull-down switch circuit, the first additional pull-down switch circuit and the second additional pull-down switch circuit respectively being coupled to a first point and a second point of the second word line; wherein the first additional pull-down switch circuit is electrically controllable so as to: When the second word line is selected, coupling the first point of the corresponding second word line to the corresponding first additional node; and when the second word line is deselected, decoupling the first point of the corresponding second word line from the corresponding first additional node; wherein the second additional pull-down switch circuit is electrically controllable so as to: When the second word line is selected, coupling the second point of the corresponding second word line to the corresponding second additional node; and When the second word line is deselected, the second point of the corresponding second word line is decoupled from the corresponding second additional node; and Wherein for each second word line, the pull-up stage further comprises a corresponding second pull-up switch circuit, the second pull-up switch circuit being electrically controllable so as to alternatively: coupling the first point of the second word line to the power supply node when the second word line is deselected; and When the second word line is selected, the first point of the second word line is decoupled from the power supply node.

13. The electronic device of claim 12, wherein the pull-up stage is interposed between the first array and the second array.

14. The electronic device according to claim 13, wherein the non-volatile memory device further comprises: include: an external array of memory cells arranged in rows and coupled to the first word line, wherein the first array is interposed between the pull-up stage and the external array; wherein the row decoder further comprises a first external pull-down switch circuit and a second external pull-down switch circuit, the first external pull-down switch circuit and the second external pull-down switch circuit being arranged on opposite sides of the outer array, and for each first word line, the first external pull-down switch circuit and the second external pull-down switch circuit respectively comprise a corresponding first external pull-down switch circuit and a corresponding second external pull-down switch circuit, the first external pull-down switch circuit and the second external pull-down switch circuit respectively being coupled to a first additional point and a second additional point of the first word line; wherein the first external pull-down switch circuit is electrically controllable so as to: When the first word line is selected, coupling the corresponding first additional point to the corresponding first external node; and when the first word line is deselected, decoupling the corresponding first additional point from the corresponding first external node; and wherein the second external pull-down switch circuit is electrically controllable so as to: When the first word line is selected, coupling the corresponding second additional point to the corresponding second external node; and When the first word line is deselected, the corresponding second additional point is decoupled from the corresponding second external node.

15. The electronic device according to claim 12, wherein the non-volatile memory device further include: a control stage configured to select one of the first word lines and deselect first word lines other than the selected first word line, wherein the control stage is further configured to: controlling the first pull-down switch circuit and the second pull-down switch circuit corresponding to the selected first word line so as to couple the first point and the second point of the selected first word line to the corresponding first node and the corresponding second node, respectively, and controlling the first pull-up switch circuit corresponding to the selected first word line so as to decouple the first point of the selected first word line from the power supply node; and For each deselected first word line, the first pull-down switch circuit and the second pull-down switch circuit corresponding to the deselected first word line are controlled so as to decouple the first point and the second point of the deselected first word line from the corresponding first node and the corresponding second node, respectively, and the first pull-up switch circuit corresponding to the deselected first word line is controlled so as to couple the first point of the deselected first word line to the power supply node.

16. The electronic device according to claim 15, wherein the control stage is further configured to select one of the second word lines and deselect second word lines other than the selected second word line, and wherein the control stage is further configured to: controlling the first additional pull-down switch circuit and the second additional pull-down switch circuit corresponding to the selected second word line so as to couple the first point and the second point of the selected second word line to the corresponding first additional node and the corresponding second additional node, respectively, and controlling the second pull-up switch circuit corresponding to the selected second word line so as to decouple the first point of the selected second word line from the power supply node; and For each deselected second word line, the first additional pull-down switch circuit and the second additional pull-down switch circuit corresponding to the deselected second word line are controlled so as to decouple the first point and the second point of the deselected second word line from the corresponding first additional node and the corresponding second additional node, respectively, and the second pull-up switch circuit corresponding to the deselected second word line is controlled so as to couple the first point of the deselected second word line to the power supply node.

17. A method for selecting a word line of a non-volatile memory device, the non-volatile memory device include: a first array of memory cells arranged in rows and coupled to a first word line; as well as a row decoder comprising a first pull-down stage and a second pull-down stage, the first pull-down stage and the second pull-down stage being arranged on opposite sides of the first array, and for each first word line, the first pull-down stage and the second pull-down stage respectively comprising a corresponding first pull-down switch circuit and a corresponding second pull-down switch circuit, the first pull-down switch circuit and the second pull-down switch circuit respectively being coupled to a first point and a second point of the first word line; The first pull-down switch circuit is electrically controllable so as to: coupling the first point to a corresponding first node; or decoupling the first point from the corresponding first node; The second pull-down switch circuit is electrically controllable so as to: coupling the second point to a corresponding second node; or decoupling the second point from the corresponding second node; and The row decoder further comprises a pull-up stage, which comprises, for each first word line, a corresponding first pull-up switch circuit, the first pull-up switch circuit being electrically controllable so as to: coupling the first point of the first word line to a power supply node; or decoupling the first point of the first word line from the power supply node; The method includes selecting a first word line, the selecting including: controlling the first pull-down switch circuit and the second pull-down switch circuit corresponding to the selected first word line so as to couple the first point and the second point of the selected first word line to the corresponding first node and the corresponding second node, respectively, and controlling the first pull-up switch circuit corresponding to the selected first word line to decouple the first point of the selected first word line from the power supply node; and The method further includes deselecting the first word line, the deselecting comprising: controlling the first pull-down switch circuit and the second pull-down switch circuit corresponding to the deselected first word line so as to decouple the first point and the second point of the selected first word line from the corresponding first node and the corresponding second node, respectively, and The first pull-up switch circuit corresponding to the deselected first word line is controlled to couple the first point of the deselected first word line to the power supply node.

18. The method of claim 17 , wherein the nonvolatile memory device further comprises a second array of memory cells, the second array being arranged in rows and coupled to a second word line; the row decoder further comprises a first additional pull-down switch circuit and a second additional pull-down switch circuit, the first additional pull-down switch circuit and the second additional pull-down switch circuit being arranged on opposite sides of the second array, and for each second word line, the first additional pull-down switch circuit and the second additional pull-down switch circuit respectively comprise a corresponding first additional pull-down switch circuit and a corresponding second additional pull-down switch circuit, the first additional pull-down switch circuit and the second additional pull-down switch circuit being coupled to a first point and a second point of the second word line, respectively; The first additional pull-down switch circuit is electrically controllable so as to: coupling the corresponding first point to the corresponding first additional node; or decoupling the corresponding first point from the corresponding first additional node; The second additional pull-down switch circuit is electrically controllable so as to: coupling the corresponding second point to the corresponding second additional node; or decoupling the corresponding second point from the corresponding second additional node; and For each second word line, the pull-up stage further comprises a corresponding second pull-up switch circuit, the second pull-up switch circuit being electrically controllable so as to: coupling the first point of the second word line to the power supply node; or decoupling the first point of the second word line from the power supply node; The method further includes selecting a second word line, the selecting comprising: controlling the first additional pull-down switch circuit and the second additional pull-down switch circuit corresponding to the selected second word line so as to couple the first point and the second point of the selected second word line to the corresponding first additional node and the corresponding second additional node, respectively, and controlling the second pull-up switch circuit corresponding to the selected second word line to decouple the first point of the selected second word line from the power supply node; and The method further includes deselecting the second word line, the deselecting comprising: controlling the first additional pull-down switch circuit and the second additional pull-down switch circuit corresponding to the deselected second word line so as to decouple the first point and the second point of the deselected second word line from the corresponding first additional node and the corresponding second additional node, respectively, and The second pull-up switch circuit corresponding to the deselected second word line is controlled to couple the first point of the deselected second word line to the power supply node.

19. The method of claim 18, wherein the nonvolatile memory device further comprises an external array of memory cells, the external array of memory cells being arranged in rows and coupled to the first word line, the first array being interposed between the pull-up stage and the external array, the row decoder further comprising a first external pull-down switch circuit and a second external pull-down switch circuit, the first external pull-down switch circuit and the second external pull-down switch circuit being arranged on opposite sides of the external array, and for each first word line, the first external pull-down switch circuit and the second external pull-down switch circuit respectively comprise a corresponding first external pull-down switch circuit and a corresponding second external pull-down switch circuit, the first external pull-down switch circuit and the second external pull-down switch circuit being coupled to a first additional point and a second additional point of the first word line, respectively; The first external pull-down switch circuit is electrically controllable so as to: coupling the corresponding first attachment point to the corresponding first external node; or decoupling the corresponding first attachment point from the corresponding first external node; The second external pull-down switch circuit is electrically controllable so as to: coupling the corresponding second attachment point to the corresponding second external node; or decoupling the corresponding second attachment point from the corresponding second external node; Selecting the first word line further includes: controlling the first external pull-down switch circuit and the second external pull-down switch circuit corresponding to the selected first word line so as to couple the corresponding first additional point and the corresponding second additional point to the corresponding first external node and the corresponding second external node, respectively, and Deselecting the first word line further includes: The first external pull-down switch circuit and the second external pull-down switch circuit corresponding to the selected first word line are controlled to decouple the corresponding first additional point and the corresponding second additional point from the corresponding first external node and the corresponding second external node, respectively.

20. The method according to claim 17, wherein the first array is divided into sub-arrays; the first node corresponding to the first word line of each sub-array is electrically consistent with the corresponding first common node; the second node corresponding to the first word line of each sub-array is electrically consistent with the corresponding second common node; for each sub-array, the first pull-down switch circuit and the second pull-down switch circuit respectively include a first sub-array selection circuit and a second sub-array selection circuit; the first sub-array selection circuit is inserted between the first common node and a node at a reference potential, and the first sub-array selection circuit is controllable so as to couple the first common node to the node at the reference potential; and the second sub-array selection circuit is inserted between the second common node and the node at the reference potential, and the second sub-array selection circuit is controllable so as to couple the second common node to the node at the reference potential; Selecting the first word line further includes: controlling the first subarray selection circuit and the second subarray selection circuit corresponding to the subarray including the selected first word line so as to couple the corresponding first common node and the corresponding second common node to the node at the reference potential; and Deselecting the first word line further includes: The first subarray selection circuit and the second subarray selection circuit corresponding to the subarray including the deselected first word line are controlled to decouple the corresponding first common node and the corresponding second common node from the node at the reference potential.

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