Method and apparatus for operating a unit board

Abstract

The present invention relates to methods and apparatus for operating cell plates. Methods, systems, techniques, and devices for operating one or more ferroelectric memory cells are described. Groups of cells can be operated differently depending on, for example, the relationship between the cell plates of the cell groups, cell pages, and / or cell segments. Cells can be selected in pairs or in larger multiples to accommodate current relationships (e.g., short circuits) between two or more cells within a group, page, and / or segment. When access is performed based on a smaller page size, cells of a larger page size can be selected to accommodate short circuits between plates within the smaller page, the larger page, and / or the memory segment containing the smaller page or the larger page.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application. The parent application is an invention patent application filed on June 5, 2019, with application number 201910486891.9 and the title of invention being “Array Board Short Circuit Repair.”

[0003] Cross Reference

[0004] This patent application claims priority to U.S. patent application No. 16 / 001,784, filed by Lovett et al. on June 6, 2018, entitled “Array Plate Short Repair,” which is a continuation-in-part of U.S. patent application No. 15 / 913,413, filed by Fackenthal et al. on March 6, 2018, entitled “Plate Defect Mitigation Techniques,” which is a continuation-in-part of U.S. patent application No. 15 / 184,795, filed by Fackenthal et al. on June 16, 2016, entitled “Plate Defect Mitigation Techniques,” now U.S. Patent No. 9,941,021, each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0005] The technical field relates to array board short circuit repair. Background Art

[0006] The following relates generally to memory devices, and more particularly, to selection of cell boards and operations related to cell boards.

[0007] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states in the memory device. For example, a binary device has two states, typically represented by a logical "1" or a logical "0." In other systems, more than two states can be stored. To access stored information, an electronic device can read or sense the stored states in the memory device. To store information, an electronic device can write or program the states in the memory device.

[0008] There are various types of memory devices, including random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and others. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., flash memory) can store data for extended periods of time, even in the absence of an external power source. Volatile memory devices (e.g., DRAM) can lose their stored state over time unless they are periodically refreshed by an external power source. Binary memory devices may, for example, include charging or discharging capacitors. Charged capacitors can become discharged over time through leakage current, resulting in the loss of stored information. Certain aspects of volatile memory can provide performance advantages, such as faster read or write speeds, while aspects of non-volatility (e.g., the ability to store data without periodic refreshing) can be advantageous.

[0009] FeRAM can use a similar device architecture as volatile memory but can have nonvolatile properties due to the use of ferroelectric capacitors as storage devices. As a result, FeRAM devices can have improved performance compared to other nonvolatile and volatile memory devices. In some FeRAM designs (and other design types), vertically cut cell boards or other closely spaced cell boards and other components can include one or more non-ideal or undesirable relationships or communications that render the cell boards, other elements, and / or other components unusable and potentially require numerous redundant and expensive memory elements. Summary of the Invention

[0010] In one example, a method includes receiving a memory access command for a memory access operation associated with a first page size of memory cells; identifying a first page of memory cells to be activated for the memory access operation based at least in part on the memory access command, the first page having the first page size; determining whether there is a short associated with at least one memory cell of a second page of memory cells that includes the first page and has a second page size that is larger than the first page size; and activating the second page of memory cells based at least in part on determining the presence of a short associated with the at least one memory cell.

[0011] In one example, an electronic memory device or memory apparatus includes a memory array comprising a first page of memory cells having a first page size and a second page of memory cells comprising the first page and having a second page size. The electronic memory device or memory apparatus further includes a command component configured to receive a memory access command associated with the first page of memory cells in the memory array and, based at least in part on the memory access command, send an address range associated with the first page of memory cells. The electronic memory device or memory apparatus further includes a logic component coupled to the command component and the memory array, the logic component configured to receive an address range associated with the first page of memory cells from the command component and, based at least in part on the address range and in response to determining that a short circuit exists associated with at least one memory cell in the second page of memory cells, activate a signal, wherein the memory array is configured to activate the second page of memory cells based at least in part on the activation of the signal.

[0012] In one example, an electronic memory device or apparatus includes a memory array including a set of layers each including a set of memory cell segments divided into a set of memory cell pages. The electronic memory device or apparatus further includes a command component configured to receive a memory access command associated with a first page size and, based at least in part on the memory access command, send an indication of a segment number associated with a first page in the set of pages, wherein the first page has the first page size and is in a first segment associated with the segment number. The electronic memory device or apparatus further includes a logic component coupled to the command component and the set of layers, the logic component configured to receive the indication of the segment number and, based at least in part on the indication, activate a signal in response to determining that a short circuit exists associated with at least one memory cell in a second segment associated with the segment number, wherein the memory array is configured to activate all memory cells in the first segment based at least in part on the activation of the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Example embodiments of the present invention are described with reference to the following figures.

[0014] Figure 1 An example memory array supporting selection of and operations based on one or more cell planes according to various embodiments of the invention is described.

[0015] Figure 2 Example circuits of a memory cell supporting selection of and operations associated with one or more cell planes according to various embodiments of the invention are described.

[0016] Figure 3 Example hysteresis loops of ferroelectric memory cells are illustrated to support selection of and operations associated with one or more cell plates according to various embodiments of the present invention.

[0017] Figure 4 Examples of memory arrays and other components that support selection of and operations associated with one or more cell planes according to various embodiments of the invention are described.

[0018] Figure 5 Examples of memory arrays and other components that support selection of and operations associated with one or more cell planes according to various embodiments of the invention are described.

[0019] Figure 6 Exemplary memory arrays and component relationships that support selection of and operations associated with one or more cell planes according to various embodiments of the invention are described.

[0020] Figure 7 A memory array supporting selection of and operations associated with one or more cell planes according to various embodiments of the present invention is described.

[0021] Figure 8 Systems including a memory array that supports selection of and operations associated with one or more cell planes according to various embodiments of the invention are described.

[0022] Figure 9 and 10 is a flow chart illustrating a method for selecting one or more cell boards and operations associated with the one or more cell boards according to various embodiments of the present invention.

[0023] Figure 11 An example memory array supporting selection of and operations associated with one or more cell planes according to various embodiments of the invention is described.

[0024] Figure 12 An example memory array supporting selection of and operations associated with one or more cell planes according to various embodiments of the invention is described.

[0025] Figure 13 An example memory array supporting selection of and operations associated with one or more cell planes according to various embodiments of the invention is described.

[0026] Figure 14 is a flow chart illustrating a method for selecting one or more cell boards and operations associated with the one or more cell boards according to various embodiments of the present invention. DETAILED DESCRIPTION

[0027] In memory designs, the risk of unexpected defects increases when long traces or continuous portions of memory elements are printed. These defects can cause operational problems and can render portions of a complete memory array unusable. In some array designs, cell plates and other elements are closely together, and there are risks of unexpected currents and other relationships between cell plates (including but not limited to adjacent cell plates). Based on manufacturing or other actions, a cell plate may have a current relationship with an adjacent cell plate, or a cell plate may have other defects relative to an adjacent cell plate. Such relationships or defects may weaken or inhibit the performance of one or more of the cell plates. Examples of such relationships include short circuits, parasitic fields or signals, and the like.

[0028] Some cell plates may include vertically cut cell plates, among others, which may be common in a smaller number of digital lines (e.g., 4 to 16) and a relatively larger number of word lines (e.g., 512 to 1024). The way the cell plates are formed during manufacturing can affect array performance. In some instances, because the distance between the respective cell plates is relatively narrow (e.g., such as the distance between digital lines and word lines), unexpected current relationships may exist between the cell plates. In some embodiments, a current relationship (e.g., a short circuit) between a group of cell plates may render a group, a segment, or some other memory element inoperable. In some cases, the risk of shorting between cells may cause manufacturers to employ expensive wholesale or local redundancy, or both; and the risk of such defects may promote other relatively complex solutions, including more robust design parameters (e.g., increasing the spacing between plates). These alternatives increase costs and reduce memory design functionality and capabilities.

[0029] As described herein, a memory array can be built and operated to mitigate defect risks. By way of example, based on one or more current relationships between various cell plates (and other elements), two or more plates can be selected together to permit operation and filling of one or more sensing elements, despite the presence of a current relationship (e.g., a short circuit) between the plates that would otherwise render the plates or other elements (e.g., a segment) inoperable. In some embodiments, this selection can be based at least in part on selecting both plates simultaneously. In some embodiments, this selection can be based on selecting both plates simultaneously. In some embodiments, this selection can be based on selecting a pair of plates that include a current relationship. In some embodiments, this selection can be based on selecting a pair of plates that do not themselves include a current relationship but are spatially or otherwise related to plates that do have a current relationship. In some embodiments, for memory access operations associated with a smaller page size, this selection can be based at least in part on selecting all memory cells of a larger page size. In some embodiments, this selection can be based at least in part on selecting all memory cells in a segment having two plates shorted together.

[0030] In some embodiments, the cell plates selected in one or more groups of cell plates (e.g., two, four, or eight cell plate groups) may be selected based on their relative positions to each other or other elements or components. For example, and as further described below, if a cell plate in a group of eight plates is in a zero position (e.g., the first position in the group) and a cell plate in one position (e.g., the second position in the group) has a current relationship (e.g., a short circuit exists between the plates), then the cell plates in this or other groups may be selected together or paired using an "even-odd" relationship corresponding to the position-based zero-one relationship. As another example, if a cell plate in a three position (e.g., the fourth position in the group) has an inverse current relationship (e.g., a predetermined current level exists) with a cell plate in a fourth position (e.g., the fifth position in the group), then the cell plates in this or other groups may be selected together or paired using an "odd-even" relationship corresponding to the position-based three-four relationship.

[0031] In some embodiments, by selecting corresponding pairs of cell plates, corresponding selection components (e.g., transistors) are arranged to connect a first set of cell plates (e.g., plates 0, 2, 4, and 6) to designated sensing components (e.g., sense amplifiers) using corresponding digital lines, and a second set of cell plates (e.g., plates 1, 3, 5, and 7) to designated sensing components (e.g., sense amplifiers) using corresponding digital lines. In this way, when one or more pairs of adjacent plates are selected, designated sensing components corresponding to, for example, eight plates can each be correctly populated with data, despite one or more current relationships between, for example, the plates, elements, or components. As discussed further below, in some embodiments, this selection of plates and corresponding correctly populated sensing components can be based on seven plates from a first group of cell plates (e.g., plates 0-6, plates 1-7) and one plate from a second group of cell plates (e.g., plate 7, plate 0), thereby providing eight correctly populated sensing components. However, other selections can be based on differently sized groups of plates, for example, groups having more or fewer than eight plates.

[0032] In some embodiments, selecting a plate includes selecting one or more memory cells associated with the plate, such as by activating one or more word lines, digit lines, plate lines, sensing components associated with the memory cells, etc. In some embodiments, selecting a plate includes biasing the plate with a select voltage without necessarily activating all other access lines or sensing components of the memory cells associated with the plate.

[0033] Some memory devices may support memory access based on different page sizes; for example, a memory device may be capable of performing memory access based on page sizes (e.g., 256B, 128B, 64B, etc.). A page size may be the minimum number of memory cells that can be simultaneously selected or accessed for a memory access operation. In some cases, a memory device may be configured to perform memory access based on a specific page size; that is, during a memory access operation, the memory device may be configured to simultaneously select or activate multiple memory cells for a memory access operation based on the page size. For example, a memory device may be configured to simultaneously access different numbers (e.g., pages) of memory cells corresponding to different page sizes of 64B, 128B, or 256B.

[0034] In some cases, one or more access lines (e.g., word lines, digit lines, and / or plate lines) of a memory array can be shared among multiple memory cells within a page. Configuring a memory device to use a smaller page size (e.g., 128B, 64B) can reduce the power required for memory access by, for example, reducing the number of access line drivers (e.g., word line drivers, digit line drivers, plate line drivers) and sense amplifiers activated during memory access operations relative to the power required for a larger page size (e.g., 256B). In some cases, accessing a smaller page size includes activating or selecting a subset of the plates in each plate group. For example, if each group has four plates, a 64B page memory access may only activate or select memory cells associated with the first plate in each plate group. A 128B page memory access may only select memory cells associated with two plates in each plate group (e.g., the first and third plates or the second and fourth plates). A 256B page memory access may select all memory cells associated with all four plates in each plate group.

[0035] In some cases, a memory device configured to perform memory accesses based on a smaller page size may instead perform memory accesses based on a larger page size to mitigate undesirable electrical connections. For example, if a plate of a target memory cell to be accessed using the smaller page size is electrically shorted to a plate of a second memory cell not within the same page (which may be, for example, an adjacent plate in a group), the memory device may perform the memory access based on a larger page size that includes both the target memory cell and the second memory cell to avoid potentially corrupting the state of the second memory cell. In some cases, if the memory device determines that a short exists between a first plate included in a first page and a second plate not included in the first page but included in a second, larger page, the memory device may "boost" the memory access from the smaller page size to the larger page size to activate both shorted plates. In some cases, selecting all memory cells in the larger page may include selecting all memory cells in a segment that includes the larger page.

[0036] The embodiments of the present invention described above are further described below in the context of memory arrays and other contexts. Next, specific embodiments of cell boards are described, including, among other things, vertically slicing cell boards and cell boards and related operational options. These and other embodiments of the present invention are further illustrated and described with reference to apparatus diagrams, system diagrams, and flow charts related to operational options for cell boards based, at least in part, on one or more groups, one or more pages, and / or one or more segments.

[0037] In this disclosure, cell board is used synonymously with board, unless one or more specific embodiments indicate otherwise.As described herein, a board can be associated with a single memory cell or a plurality of memory cells.

[0038] Figure 1 An example memory array 100 supporting one or more cell plates and operations associated with the one or more cell plates according to various embodiments of the present invention is described. Memory array 100 may also be referred to as an electronic memory device. Memory array 100 includes memory cells 105 that are programmable to store different states. Each memory cell 105 is programmable to store two states, designated as logic 0 and logic 1. In some embodiments, memory cells 105 are configured to store more than two logical states. Each state may generate a corresponding voltage across memory cell 105 when memory cell 105 is accessed. Memory cell 105 may include a capacitor that stores a charge representing the programmable state; for example, a charged and uncharged capacitor may represent two logical states. DRAM architectures may typically use this design, and the capacitors employed may include dielectric materials with linear electrical polarization properties. In contrast, ferroelectric memory cells may include capacitors using ferroelectrics as the dielectric material. Different charge levels of the ferroelectric capacitor may represent different logical states. Ferroelectric materials have nonlinear polarization properties, and details and advantages of ferroelectric memory cell 105 are discussed below.

[0039] Operations (e.g., reading and writing) can be performed on the memory cells 105 by activating or selecting the appropriate word lines 110 and digit lines 115. Activating or selecting a word line 110 or digit line 115 may include applying a voltage to the corresponding line. In some embodiments, the digit lines 115 may be referred to as bit lines. In some embodiments, the word lines 110 or digit lines 115, or both, may be referred to as access lines. The word lines 110 and digit lines 115 may be made of a conductive material. In some embodiments, the word lines 110 and digit lines 115 are made of a metal (e.g., copper, aluminum, gold, tungsten, etc.). Each row of memory cells 105 is connected to a single word line 110, and each column of memory cells 105 is connected to a single digit line 115.

[0040] By activating a word line 110 and a digit line 115, a single memory cell 105 can be accessed at their intersection. The intersection of a word line 110 and a digit line 115 can be referred to as the address of the memory cell. In some embodiments, each digit line 115 can be connected to one or more sensing elements 125, which in some embodiments can include a sense amplifier corresponding to each digit line 115.

[0041] In some embodiments, memory cells 105 may be organized into sectors, which may be a row of multiple groups of memory cells 105. In some cases, plates in the same position within each group (e.g., the first plate in each group) may be served by a single word line 110, or multiple pairs of plates within a group may be served by a single word line, or all plates in a group or sector may be served by a single word line.

[0042] In some embodiments, one or more read or write operations may be based on one or more single-board meta-selections or derived from one or more cell board selections. For example, the selection of one or more cell boards may indicate a board pair between two cell boards or a board pairing for each group (e.g., a group of two cell boards) within one or more groups, sectors, pages, banks, dies, etc. For example, the selection of one or more cell boards may include the selection of a cell board pair within each group or the selection of all cell boards in a group or sector.

[0043] In some architectures, a cell's logical storage device (e.g., a capacitor) can be electrically isolated from the digit line by a select device. A word line 110 can be connected to and control the select device. For example, the select device can be a transistor, and word line 110 can be connected to the gate of the transistor. Activating word line 110 creates an electrical connection between the capacitor of memory cell 105 and its corresponding digit line 115. The digit line can then be accessed to read from or write to memory cell 105.

[0044] Access to memory cells 105 may be controlled by row decoder 120 and column decoder 130. For example, row decoder 120 may receive a row address from memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, column decoder 130 may receive a column address from memory controller 140 and activate the appropriate digit line 115. Thus, by activating word line 110 and digit line 115, memory cell 105 may be accessed. As discussed herein, in various embodiments, the address or location of one or more cells or cell plates may affect identification, determination, or selection related to a cell plate and other elements or components. In some embodiments, the address or location of a memory cell may affect selection, such as selection based on an absolute address or location or a relative address or location. In some embodiments, the presence of a relationship between the address or location and current of a memory cell may affect selection of a plate pair within or across a cell plate group. In some embodiments, the presence of a relationship between the address, location, or segment of a memory cell and current may affect selection or activation of a page of memory cells or a segment of memory cells.

[0045] After access, memory cell 105 can be read or sensed by sensing component 125. When reading memory cell 105, the stored state can be transmitted across the cell's capacitor and, therefore, produce a corresponding signal on digit line 115. For example, sensing component 125 can compare the signal (e.g., voltage) of the associated digit line 115 with a reference signal (not shown) to determine the stored state of memory cell 105. For example, if digit line 115 has a higher voltage than the reference voltage, sensing component 125 can determine that the stored state in memory cell 105 is a logic 1, and vice versa. Sensing component 125 can include various transistors or amplifiers to detect and amplify the difference in the signal, which can be referred to as latching. The detected logic state of memory cell 105 can then be output as output 135 by column decoder 130.

[0046] Memory cells 105 can be set, written, or initialized to a state by similarly activating the associated word lines 110 and digit lines 115. As discussed above, activating a word line 110 electrically connects the memory cells 105 of the corresponding row to their respective digit lines 115. By controlling the associated digit lines 115 when word lines 110 are activated, memory cells 115 can be written—that is, a logic value can be stored in the memory cells 105. Column decoder 130 can accept data to be written to memory cells 105, such as input 135. In the case of ferroelectric capacitors, memory cells 105 are written by applying a voltage across the ferroelectric capacitors. This process is discussed in more detail below.

[0047] In some memory architectures, accessing a memory cell 105 can degrade or damage the stored logic state, and a rewrite or refresh operation can be performed to return the original logic state to the memory cell 105. In DRAM, for example, capacitors can partially or completely discharge during sensing operations and other times, thereby destroying the stored logic state. Therefore, the logic state can be rewritten after the sensing operation. In addition, activating a single word line 110 can cause one or more memory cells in a row to discharge; therefore, one or more memory cells 105 in a row may need to be rewritten.

[0048] Some memory architectures, including DRAM, can lose their stored state over time unless they are periodically refreshed by an external power source. For example, a charged capacitor can become discharged over time through leakage current, resulting in the loss of stored information. The refresh rate of these so-called volatile memory devices can be relatively high (e.g., more than a dozen refresh operations per second for DRAM), which can result in significant power consumption. As memory arrays become larger and larger, especially for mobile devices that rely on limited power sources (e.g., batteries), the increased power consumption can inhibit the deployment or operation of the memory array (e.g., power supply, heat generation, material limitations, etc.). As discussed below, ferroelectric memory cells can have beneficial properties that can result in improved performance relative to other memory architectures. For example, because ferroelectric memory cells tend to be less susceptible to stored charge degradation, a memory array 100 employing ferroelectric memory cells 105 may require fewer or no refresh operations and may therefore require less power to operate.

[0049] Memory controller 140 can control the operation (read, write, rewrite, refresh, etc.) of memory cells 105 through various components (e.g., row decoder 120, column decoder 130, and sense component 125). Memory controller 140 can generate row and column address signals in order to activate the desired word lines 110 and digit lines 115. Memory controller 140 can also generate and control various voltage potentials used during operation of memory array 100. In general, the amplitude, shape, or duration of the applied voltages discussed herein can be adjusted or varied and can be different for the various operations discussed in operating memory array 100. Furthermore, one, multiple, or all memory cells 105 within memory array 100 can be accessed simultaneously; for example, multiple or all cells of memory array 100 can be accessed simultaneously during a reset operation in which all memory cells 105 or a group of memory cells 105 are set to a single logic state. For example, a page of memory cells 105 in the memory array 100 may be accessed simultaneously based on a page size specified in a memory access command or based on the memory array's page size configuration. In this case, the memory controller 140 may generate a series of addresses to access the page of memory cells.

[0050] In some embodiments, a memory device may include multiple levels or layers of memory cells 105, which may include multiple stacked memory arrays 100, such as in a cross-point memory architecture. In some cases, each layer may have its own row decoder 120, sensing element 125, column decoder 130, and / or input / output 135. In some cases, a single memory controller 140 may control multiple layers by generating row or column address signals for memory cells in different layers.

[0051] In some embodiments, the memory controller 140 may be associated with or electronically communicate with the first and second cell boards. A first digit line may electronically communicate with the first cell board and a first sensing component (e.g., a sense amplifier) ​​via a first selection component (e.g., a transistor). A second digit line may also electronically communicate with the second cell board and a second sensing component (e.g., a sense amplifier) ​​via a second selection component (e.g., a transistor). Based at least in part on this electronic communication, the controller may be operable to initiate or perform one or more operations associated with selecting one or more cell board pairs. In some embodiments, the memory controller 140 may be operable to determine a current relationship associated with one or more cell boards. Based at least in part on this determination or identification, the memory controller 140 may initiate (e.g., send an instruction or signal to another element or component or control another element or component to operate) and operate to select the first and second cell boards using the first or second selection component. In some embodiments, this selection may include electronic communication from the controller to the one or more selection components.

[0052] In some embodiments, memory controller 140 is operable to receive a memory access command for a memory access operation associated with a first page size of memory cells. The first page size may be specified in the memory access command, for example, or may be a configuration option of memory controller 140. The memory controller may identify a first page of memory cells to be activated for the memory access operation based at least in part on the memory access command. The first page may have a first page size, and memory controller 140 may identify the first page by generating row and column address signals to activate one or more word lines 110 and / or digit lines 115 associated with the first page. In some embodiments, memory controller 140 may include or be coupled to a logic component (not shown) operable to determine whether a short circuit exists associated with at least one memory cell of a second page of memory cells comprising the first page and having a second page size greater than the first page size. The short circuit may be, for example, a short circuit between a first plate and a second plate associated with the memory cells of the second page. In some embodiments, the logic component determines whether a short circuit exists by receiving a signal associated with the short circuit, such as a signal from a fuse triggered based on the short circuit. The memory array 100 is operable to activate a second page of memory cells (e.g., including the first page of memory cells) based at least in part on determining that a short circuit exists. In some embodiments, the memory controller 140 can activate the second page of memory cells by generating row and column address signals associated with the second page so as to activate the word lines 110 and digit lines 115 associated with the second page. In some embodiments, the memory array 100 generates row and column address signals associated with the second page based at least in part on received signals; for example, by modifying row and column addresses generated by the memory controller 140 and associated with the first page.

[0053] Figure 2 An example circuit 200 is illustrated that supports selection of one or more cell plates and operations associated with the one or more cell plates according to various embodiments of the present invention. The circuit 200 may include a ferroelectric memory cell 105-a, a word line 110-a, a digit line 115-a, and a sensing element 125-a, which may be referenced to Figure 1 10 and / or other described embodiments of memory cells 105, word lines 110, digit lines 115, and sensing elements 125. Circuit 200 includes a logic storage element, such as capacitor 205, which may include conductive terminals, including plate 210 and cell bottom 215. These terminals may be separated by an insulating ferroelectric material. As described herein, various states may be stored by charging or discharging capacitor 205.

[0054] The stored state of capacitor 205 can be read or sensed by operating the various elements shown in circuit 200. Capacitor 205 can be in electronic communication with digit line 115-a. Capacitor 205 can therefore be isolated from digit line 115-a when select component 220 is deactivated, and capacitor 205 can be connected to digit line 115-a via select component 220 when select component 220 is activated to select ferroelectric memory cell 105-a. In other words, ferroelectric memory cell 105-a can be selected using select component 220 in electronic communication with ferroelectric capacitor 205, where ferroelectric memory cell 105-a includes select component 220 and ferroelectric capacitor 205. In some embodiments, select component 220 can be or include a transistor, and its operation can be controlled by applying a voltage to the transistor gate, where the voltage has a magnitude greater than a threshold magnitude of the transistor. Word line 110 - a may activate selection element 220 ; for example, a voltage applied to word line 110 - a is applied to a transistor gate, thereby connecting capacitor 205 to digit line 115 - a .

[0055] exist Figure 2 In the example depicted in FIG, capacitor 205 is a ferroelectric capacitor. Due to the ferroelectric material between the plates of capacitor 205, and as discussed in more detail below, capacitor 205 may not discharge after being connected to digit line 115-a. Instead, plate 210 may be biased by an external voltage (e.g., via plate line 230), resulting in a change in the stored charge on capacitor 205. The change in stored charge corresponds to and / or depends on the initial logic state of capacitor 205. The voltage applied to capacitor 205 changes the charge of capacitor 205. The change in charge can be compared to a reference value 225 (e.g., a reference voltage) by sensing component 125-a to determine the stored logic state in memory cell 105-a.

[0056] The specific sensing scheme or process can take many forms. In one example, digit line 115-a can have an intrinsic capacitance and can generate a non-zero voltage as capacitor 205 charges or discharges in response to a voltage applied to plate 210. The intrinsic capacitance can depend on physical properties, including, among other things, the size of digit line 115-a. Digit line 115-a can connect many memory cells 105, so digit line 115-a can have a length that produces a non-negligible capacitance (e.g., on the order of pF or fF). The subsequent voltage of digit line 115-a can depend on the initial logic state of capacitor 205, and sensing component 125-a can compare this voltage to a reference voltage, which can include a reference voltage generated by other memory cells 105. For example, a voltage can be applied to plate 210, and the voltage at capacitor bottom 215 can change in response to the stored charge. The voltage at capacitor bottom 215 can be compared to a reference voltage at sensing element 125-a, and the comparison to the reference voltage can indicate a change in charge of capacitor 205 due to the applied voltage, and therefore the logic state stored in memory cell 105-a. Figure 3 and others describe in more detail the relationship between the charge and voltage in capacitor 205 .

[0057] In some cases, plate 210 can be shared among multiple memory cells 105, so that applying a voltage to a single plate 210 or plate line 230 can change the voltage at multiple capacitor bottoms 215. This approach can be useful, for example, for reducing the number of plate lines required to access multiple memory cells 105 simultaneously.

[0058] Other sensing processes may be used. For example, two or more sensing components 125-a may each sense the voltage or other characteristic at two or more digit lines 115-a, each corresponding to one or more plates 210. In some embodiments, when the two or more plates 210 include adjacent plates 210, the plates 210 may be selected together, and the values ​​sensed by each sensing component 125-a (e.g., a sense amplifier) ​​may be accurately read or monitored so that each of the eight sensing components 125-a corresponding to an eight-plate group (or a portion of a two-plate group) is correctly populated with data. In some embodiments, each of the four sensing components 125-a is populated based on one of the four digit lines 115-a corresponding to the first cell plate 210, and each of the four sense amplifiers is populated based on one of the four digit lines corresponding to the second cell plate 210. By using the selection and shifting techniques and methods of the present invention and selecting two cell plates 210 together, eight sensing elements (e.g., sense amplifiers) can be accurately filled regardless of any current relationships associated with or between the two cell plates 210 and / or one or more other defects or adverse conditions associated with the two cell plates 210 or other elements or components. Similarly, by using the page-based selection techniques and methods of the present invention and selecting memory cells of a page size larger than the page size associated with the memory access command, the memory device can accurately fill the associated sensing elements and avoid corrupting data stored in memory cells associated with a plate that has a short circuit with another plate.

[0059] To write to memory cell 105-a, a voltage may be applied across capacitor 205. Various methods may be used. In one example, select component 220 may be activated via word line 110-a to electrically connect capacitor 205 to digit line 115-a. A voltage may be applied across capacitor 205 by controlling the voltage of cell plate 210 using plate line 230 and the voltage of cell bottom 215 using digit line 115-a. To write a logic "0," cell plate 210 may be driven high, i.e., a positive voltage may be applied to plate line 230, and cell bottom 215 may be driven low—e.g., a virtual ground—using digit line 115-a. The reverse process is performed to write a logic "1," i.e., cell plate 210 may be driven low and cell bottom 215 may be driven high. Reading and writing operations on capacitor 205 may take into account the nonlinear properties associated with ferroelectric devices.

[0060] exist Figure 2, a single plate 210 and / or plate line 230 can be associated with a single memory cell 105-a. In other examples, a single plate can be associated with or shared by multiple memory cells, and a voltage applied via plate line 230 can thereby affect multiple memory cells. In some cases, multiple smaller plates 210 can be electrically coupled via a larger shared plate 210 to enable biasing of multiple memory cells via a single plate line 230. As used herein, plate can refer to any such embodiment or combination of embodiments.

[0061] Figure 3 An example hysteresis loop 300 of a ferroelectric memory cell supporting selection of one or more cell plates and operations associated with the one or more cell plates according to various embodiments of the present invention is illustrated. Hysteresis loops 300-a and 300-b illustrate the write and read processes of the example ferroelectric memory cell, respectively. Hysteresis loop 300 depicts the variation of the voltage difference V in the magnetic field stored in the ferroelectric capacitor (e.g., Figure 2 The charge Q on capacitor 205).

[0062] Ferroelectric materials are characterized by spontaneous electric polarization, that is, they maintain a non-zero electric polarization in the absence of an electric field. Example ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconate titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitors described herein may include these or other ferroelectric materials. The electric polarization within a ferroelectric capacitor creates a net charge at the surface of the ferroelectric material and attracts opposite charges through the capacitor terminals. As a result, charge can be stored at the interface between the ferroelectric material and the capacitor terminals. Because the electric polarization can be maintained for extended periods of time, or even indefinitely, in the absence of an applied electric field, charge leakage can be significantly reduced compared to capacitors used in, for example, DRAM arrays. This can reduce the need to perform the refresh operations described above for some architectures.

[0063] The hysteresis loop 300 can be understood from the perspective of a single terminal of a capacitor. By way of example, if the ferroelectric material has a negative polarization, then positive charge can accumulate at the terminal. Similarly, if the ferroelectric material has a positive polarization, then negative charge can accumulate at the terminal. In addition, the voltage in the hysteresis loop 300 represents the voltage difference across the capacitor and is directional. For example, a positive voltage can be applied by applying a positive voltage to the terminal in question and maintaining the second terminal at a reference voltage, which can be ground (e.g., approximately zero volts (0V)). A negative voltage can be applied by maintaining the terminal in question at ground and applying a positive voltage to the second terminal, that is, a positive voltage can be applied to negatively polarize the terminal in question. Similarly, two positive voltages, two negative voltages, or a combination of positive and negative voltages can be applied to the appropriate capacitor terminals to generate the voltage difference shown in the hysteresis loop 300.

[0064] As depicted in hysteresis loop 300-a, the ferroelectric material can maintain positive or negative polarization with zero voltage difference, resulting in two possible charge states: charge state 305 and charge state 310. Figure 3 , charge state 305 represents a logic 0 and charge state 310 represents a logic 1. In some embodiments, the logic values ​​of the respective charge states can be reversed to accommodate other schemes for operating the memory cell.

[0065] A logical 0 or 1 can be written to a memory cell by controlling the electrical polarization of the ferroelectric material and, therefore, the charge on the capacitor terminals (by applying a voltage). For example, applying a net positive voltage 315 across the capacitor causes charge to accumulate until charge state 305-a is reached. After positive voltage 315 is removed, charge state 305-a changes along path 320 until it reaches charge state 305 at zero voltage potential. Similarly, charge state 310 is written by applying a net negative voltage 325 that results in charge state 310-a. After negative voltage 325 is removed, charge state 310-a changes along path 330 until it reaches charge state 310 at zero voltage potential. Charge states 305-a and 310-a can also be referred to as remanent polarization (Pr) values, i.e., the polarization (or charge) remaining after the external bias (e.g., voltage) is removed. The coercive voltage is the voltage at which the charge (or polarization) is zero.

[0066] To read or sense the stored state of a ferroelectric capacitor, a voltage may be applied across the capacitor. In response, the stored charge changes, and the extent of the change, depends on the initial charge state—that is, the extent to which the stored charge of the capacitor changes depends on whether charge state 305-b or 310-b was initially stored. For example, hysteresis loop 300-b illustrates two possible stored charge states, 305-b and 310-b. A net voltage 335 may be applied across the capacitor. Although depicted as a positive voltage, voltage 335 may be negative. In response to voltage 335, charge state 305-b may change along path 340. Similarly, if charge state 310-b was initially stored, charge state 305-b may change along path 345. The final positions of charge state 305-c and charge state 310-c depend on several factors, including the specific sensing operation and circuitry.

[0067] In some embodiments, the charge sensed during a read operation may depend on the intrinsic capacitance of the memory cell's digit line. For example, if a ferroelectric capacitor of a memory cell is electrically connected to the digit line and voltage 335 is applied, the voltage of the digit line may increase due to its intrinsic capacitance. Consequently, the voltage measured at the sensing element may not be equal to voltage 335, but may depend on the voltage of the digit line. Consequently, the position of the final charge states 305-c and 310-c on hysteresis loop 300-b may depend on the capacitance of the digit line and may be determined by load line analysis, i.e., charge states 305-c and 310-c may be defined with respect to the digit line capacitance. Consequently, the voltage of the capacitor (voltage 350 or voltage 355) may be different and may depend on the initial state of the capacitor.

[0068] By comparing the digital line voltage to a reference voltage, the initial state of the capacitor can be determined. For example, the reference voltage can be the average of two quantities (voltage 335 - voltage 350) and (voltage 335 - 355). After comparison, it can be determined whether the sensed digital line voltage is above or below the reference voltage. The value of the ferroelectric cell (i.e., logic 0 or 1) can then be determined based on the comparison.

[0069] As discussed above, reading a DRAM memory cell can degrade or damage the stored logic. However, a ferroelectric memory cell can maintain its initial logic state after a read operation. For example, if charge state 305-b is stored and a read operation is performed, the charge state can return to the initial charge state 305-b after voltage 335 is removed, for example, by changing in the opposite direction along path 340.

[0070] In some cases, applying a voltage to a capacitor plate without selecting the corresponding digit line associated with the plate can result in undesirable device behavior, such as corrupting the state of a memory cell associated with the plate. Thus, in some cases, if two plates are shorted such that one of the plates is accidentally biased or activated, it may be desirable to select the digit line associated with both plates to avoid unwanted device behavior, even if only one of the plates is intended for access operations.

[0071] Figure 4 An example array 400 is illustrated that supports selection of one or more cell plates and operations associated with the one or more cell plates according to various embodiments of the present invention. The array 400 may include ferroelectric memory cells, one or more word lines (not shown for simplicity), digit lines (e.g., 115-a to 115-h, 115-n, 115-x to 115-z, etc.), sensing elements (e.g., 125-a to 125-p), plates (e.g., 210-a to 210-p), and / or selection elements (e.g., 220-a to 220-h), which may be referenced as follows: Figure 1 、2 or other described examples of memory cells 105, word lines 110, digit lines 115, sense elements 125, plates 210, and select elements 220. Array 400 may include logical storage elements such as capacitors (e.g., referring to FIG. Figure 2 The capacitor 205 discussed above may include conductive terminals, including a plate 210 and a cell bottom 215 (also see Figure 2 These terminals may be separated by an insulating ferroelectric material. As described above, various states may be stored by charging or discharging capacitor 205.

[0072] According to various embodiments of the invention, additional elements are contemplated, although each may not be explicitly labeled or shown. For example, in addition to selection component pair 455-a (associated with selection component 220-a and selection component 220-b) and selection component pair 455-d (associated with selection component 220-g and selection component 220-h), array 400 may include additional components or selection component pairs, or both, as well as other features. For example, array 400 may include selection component pair 455-b (associated with selection component 220-c and selection component 220-d) and selection component pair 455-c (associated with selection component 220-e and selection component 220-f). As another example, array 400 may include four digit lines per plate (e.g., plate 210-a), or another number of digit lines that may be distinct and individually identifiable, although only some of the digit lines shown are explicitly labeled (e.g., 115-a through 115-h, 115-n, and 115-x through 115-z, etc.). Such distinct digit lines may enable access to multiple memory cells associated with a single plate 210.

[0073] Array 400 may also include plate pairs 445-a to 445-h associated with two or more instances of plate 210 (e.g., 210-a and 210-b). In some embodiments, plate pairs 445-a to 445-h may fall within Figure 4 4. The array 400 may further include one or more plate groups 450 (e.g., plate groups 450-a and 450-b) shown in FIG. The array 400 may further include selection element pairs 455-a to 455-d associated with two selection elements 220 (e.g., 220-a and 220-b). The array 400 may further include sensing element groups (e.g., 460-a to 460-d) associated with one or more sensing elements 125 (e.g., 125-a to 125-d).

[0074] In some embodiments, array 400 includes eight sensing elements 125 per plate group (e.g., plate group 450-a), wherein each sensing element 125 is in electronic communication with one or more digital lines (e.g., digital lines 115-a, 115-b) associated with the same plate or plates (e.g., plates 210-a, 210-b). In other embodiments, array 400 includes more or fewer than eight sensing elements 125 per plate group (e.g., plate group 450-a, 450-b).

[0075] As previously mentioned, although the discussion of the sensing process herein describes a group having eight plates, other group sizes are possible, such as a group having two or four plates. Figure 4 While the word lines, digit lines, plate lines, sensing components are depicted in FIG, there may be more or fewer word lines, digit lines, plate lines, sensing components (eg, sense amplifiers), etc. associated with the plates in the group.

[0076] In some embodiments, array 400 and associated techniques can be used with vertically cut panels (e.g., panels 210-a, 210-b), which can be used with FeRAM or other RAM designs (e.g., resistive RAM, such as CBRAM). In the case of various panels 210, there is typically a current relationship between two panels or between multiple groups of panels. In some embodiments, this current relationship is based on the fact that two adjacent panels are coupled or otherwise have a path between them that supports unintended communication, inducements, interference, or electron flow. Such a relationship between panels can be referred to as a current relationship, a performance-based relationship, or the like, because there can be current flow or influence on current flow between the two panels. In some embodiments, this current relationship can include, among other things, the presence of an unintended short circuit between the two panels. For example, this unintended short circuit can be the result of a defect introduced during the manufacturing process or caused by post-manufacturing device damage.

[0077] In some embodiments, based on identifying a current relationship between two plates (e.g., plates 210-a and 210-b), two or more plates 210 may be selected. This selection may include grouping the two cell plates into a plate pair (e.g., plate pair 445-a) to facilitate read, write, or other operations despite the current relationship between the two plates. If a short circuit exists between two plates in a section of the memory array, this selection may include selecting all memory cells within the section (and / or biasing the corresponding plates), or may include selecting memory cells of a page size larger than the page size specified by the memory access command.

[0078] As an example of grouping cell plates, plate 210-a (in the "0" position) and plate 210-b (in the "1" position) may have a current relationship that may be understood as an "even-odd" current relationship (based on the "0" and "1" positions of plate 210). In some embodiments, this current relationship may be identified or determined based on one or some other method or technique of biasing the plates. For example, by biasing plate 210-a for a read operation and knowing that biasing plate 210-a will cause plate 210-b to have a current or other value below a threshold, if the current (or other value) of plate 210-b is above the threshold, then it may be determined that a current relationship exists between plate 210-a and plate 210-b. In some embodiments, this identification, determination, or selection may be performed during testing, while in other embodiments, this identification, determination, or selection may be performed on an end product having a capability or one or more structural features that enable selection of cell plates based on a current relationship.

[0079] Returning to the example of grouping cell boards, in some embodiments, based on identifying a short circuit or other current relationship, board pair 445-a can be selected. As an example, this selection of boards 210-a and 210-b can be accompanied by selecting selection component pair 455-a that selects selection components 220-a and 220-b. By selecting boards 210-a and 210-b and selecting components 220-a and 220-b (and corresponding word lines and digit lines (e.g., 115-a to 115-h)), each of sense components 125-a to 125-h can be appropriately filled with data, and sense component groups 460-a and 460-b can be fully filled to allow read, write, or other operations.

[0080] In some embodiments, based on identifying the current relationship between plates 210-a and 210-b within first plate group 450-a (as one example), one or more other plate pairs (e.g., 445-b, 455-c) may be selected. For example, selecting plates 210-g and 210-h may be accompanied by a selection element pair 455-d that selects selection elements 220-g and 220-h. By selecting plates 210-g and 210-h and selection elements 220-g and 220-h (and the corresponding word lines and digit lines), each of the sense elements 125 corresponding to digit lines 115 can be properly filled with data and sense element group 460 can be fully populated to allow for read, write, or other operations.

[0081] In some embodiments, a set of selection components 220 (as well as other components or elements) can be in electronic communication with or associated with a plurality of board groups 450, boards 210, or other sets of memory components. For example, a set of selection components 220 (e.g., selection components 220-a through 220-h) can facilitate or perform selection of one or more boards 210 associated with one or more board groups 450 (e.g., board group 450-a, board group 450-b).

[0082] Additionally or alternatively, one or more other selection components 220 (as well as other components or elements) may be in electronic communication with or associated with multiple board groups 450, boards 210, and / or other groups of memory components. As an example, one set of selection components 220 (e.g., selection components 220-a through 220-h) may facilitate or perform selection of one or more boards associated with one board group 450 (e.g., board group 450-a), and another set of selection components 220 (e.g., selection components 220-i through 220-p) may facilitate or perform selection of one or more boards 210 associated with one board group 450 (e.g., board group 450-b).

[0083] In some embodiments, the array 400 may include plate pairs (e.g., 445-a, 445-b, 445-c, 445-d) that fall within the same plate group 450-a and may be selected based on current relationships between the plates 210 within the plate group 450-a.

[0084] In some embodiments, the array 400 may include plate pairs 445 (e.g., 445-e, 445-f, 445-g, 445-h) that fall within another plate group 450-b and may be selected based on the current relationship between plates within another plate group 450 (e.g., plate group 450-a). This selection may be based on a variety of factors, including selection, determination, identification, or array granularity, as discussed below.

[0085] For example, in some embodiments, elements of array 400 (or some related component or element discussed in other figures, such as memory controller 140) may be configured to select a current source based on the current relationship between plates 210-a and 210-b. Figure 44. Based on determining (via a read or write operation or monitoring the performance of one or more boards) or identifying a current relationship, one or more elements (e.g., fuses) associated with a board group of the plurality of groups may initiate or be associated with the selection of a board pair (e.g., 445-a through 445-h, etc.). In some embodiments, the number of elements or components that facilitate the selection of boards and / or board pairs may be minimal and may be based on anticipated or known design parameters (including, for example, one or more known current relationships between boards).

[0086] For example, in some embodiments, the die may include an element that facilitates selection of plates (e.g., a fuse) to provide desired selection and pairing capabilities associated with various technologies or methods. In such cases, when a fuse is triggered, a plate pair, multiple plate pairs, each plate in a page, each plate in a section, or each plate on the die may be grouped into plate pairs based on one or more identified or determined current relationships (e.g., the position of the shorted plates within a group, page, section, or layer; whether some are even-odd; or whether some are odd-even).

[0087] In some embodiments, based on which fuse is triggered, each board may be selected to be paired in an odd-even (e.g., barrel shift) relationship to mitigate the effects of one or more (identified, determined, and / or unknown) current relationships. This barrel shift relationship and / or selection allows for groupings related to one board from a first board group and one board from a second board group, as well as other examples. Figure 5 and others discuss the barrel shift (or cyclic shift) applied herein in more detail.

[0088] In some embodiments, the selection may be finer and may apply only to boards that are in a current relationship, boards in the same board group, boards in adjacent board groups, and / or boards in some other structure of a larger memory sample (e.g., one or more dies, banks, subsets of one or more banks, half banks, pages, sectors, half sectors, and / or subsets of one or more banks, groups, pages, sectors, etc.). For example, in some embodiments, each sector may include a set of fuses (and / or some other element and / or component) per sector (with hundreds of sectors on a memory chip), which may allow for more defects and / or current relationships across the memory chip, and this may also allow for finer tuning and / or selection by sectors (and / or banks comprising multiple sectors) based on designed granularity. In some embodiments, the granularity selected and the associated fuse set may be based on actually identifying or determining the amount and / or location (e.g., current relationship) of one or more defects. In other embodiments, the selected granularity and associated fuse sets may be predicted, anticipated, and / or calculated based on past yields, design parameters, desired robustness, some combination, and / or other factors and / or parameters to identify or determine the amount and / or location (e.g., current relationships) of one or more defects.

[0089] In some embodiments, based on which fuse is triggered, every board within a larger page size (relative to the page size associated with the memory access command) can be selected, or every board within a segment can be selected. In some embodiments, for a multi-layer memory device, a single fuse associated with a segment can be shared by multiple layers, such that a fuse triggered based on detection of a short circuit in a first segment of a first layer can affect board selection in a first segment of a second layer. In other cases, each layer can have a separate set of fuses, such as one fuse per segment per layer.

[0090] In some embodiments, selecting one or more plate pairs may be performed before and / or during identification and / or determination of one or more current relationships between one or more plate pairs. For example, by detecting various features, qualities, and / or measurements at one or more various granularities (e.g., a segment), one or more elements or components may report, identify, read, and / or determine performance factors and / or characteristics (e.g., timing, current, voltage, resistance, etc.) associated with and / or specific to the one or more granularities. Then, based on the detection associated with the one or more plates, as an example, a second plate and / or other plates and / or plate pairs associated with the one or more plates may be selected. If one or more performance factors (and other detected information) increase, decrease, and / or are modified, a current relationship (and other things) may exist between the one or more plates and the second plate. Additional pairings, selections, and / or shifts may then be derived from the current relationships associated with the one or more plates and the second plate, as well as other related ones.

[0091] Figure 5An example array 500 is illustrated that supports operations associated with selecting one or more cell plates according to various embodiments of the present invention. The array 500 may include ferroelectric memory cells, one or more word lines, digit lines (e.g., 115-a to 115-h, 115-n, 115-x, 115-z, etc.), sensing elements 125 (e.g., 125-a to 125-p), plates 210 (e.g., 210-a to 210-p), and selection elements 220 (e.g., 220-a to 220-h), which may be referenced as 115-a, 115-n, 115-x, 115-z, etc., respectively. Figure 1 、 2 , 4 or other described examples of memory cells 105, word lines 110, digit lines 115, sensing elements 125, plates 210, and selection elements 220. Array 500 may include logical storage elements such as capacitors (e.g., referring to Figure 2 The capacitor 205 discussed above may include conductive terminals, including a plate 210 and a cell bottom 215 (also see Figure 2 These terminals may be separated by an insulating ferroelectric material. As described above, various states may be stored by charging or discharging capacitor 205. Array 500 may include features or functions similar to, the same as, or different from those discussed with respect to array 400. Figure 4 and 6 and other discussions or Figure 4 and 6 and other related features, methods, techniques, and structures.

[0092] According to various embodiments of the invention, additional elements are contemplated, although each may not be explicitly labeled or shown. For example, in addition to selection component pair 455-a (associated with selection component 220-a), selection component pair 455-b (associated with selection component 220-b and selection component 220-c), and selection component pair 455-e (associated with selection component 220-h), array 500 may include additional components. For example, array 500 may include selection component pair 455-c (associated with selection component 220-d and selection component 220-e), selection component pair 455-d (associated with selection component 220-f and selection component 220-g), or both. As another example, array 500 may include four digit lines per plate 210 (e.g., plate 210-a) or another number of digit lines that may be different and individually identifiable, although only some of the digit lines shown are explicitly labeled (e.g., 115-a to 115-h, 115-n, and 115-x to 115-z, etc.).

[0093] The array 500 may also include plate pairs 445-a to 445-i associated with two or more (e.g., 210-b and 210-c) of the plates 210. In some embodiments, the plate pairs 445-a to 445-i may fall within Figure 5 , such as one or more plate groups 450 (e.g., plate groups 450-a and 450-b) shown in FIG. Array 500 may also include selection element pairs 455 (e.g., 455-a to 455-e) associated with two selection elements 220 (e.g., 220-b and 220-c). Array 500 may also include sensing element groups 460-a to 460-d that may be associated with a plurality of sensing elements 125 (e.g., 125-a to 125-d).

[0094] In some embodiments, based on identifying a current relationship between two plates (e.g., plates 210-b and 210-c), two or more plates 210 may be selected. This selection may include grouping the two cell plates into a plate pair (e.g., plate pair 445-b) to facilitate reading, writing, or other operations despite the current relationship between the two plates.

[0095] As an example, plate 210-b (in the "1" position) and plate 210-c (in the "2" position) may have a current relationship that may be understood as an "odd-even" current relationship (based on the "1" and "2" positions of plate 210). In some embodiments, this current relationship may be identified or determined based on one or some other method or technique of biasing the plates. For example, by biasing plate 210-b for a read operation and knowing that biasing plate 210-b will cause plate 210-c to have a current or other value below a threshold, if the current (or other value) of plate 210-c is above the threshold, then it may be determined that a current relationship exists between plates 210-b and 210-c. In some embodiments, this identification, determination, or selection may be performed during testing, while in other embodiments, this identification, determination, or selection may be performed on an end product having capabilities or one or more structural features that enable selection of a cell plate based on a current relationship.

[0096] In some embodiments, based on identifying this or other current relationships, plate pair 445-b can be selected. As an example, this selection of plates 210-b and 210-c can be accompanied by selecting select element pair 455-b, which selects select elements 220-b and 220-c. By selecting plates 210-b and 210-c and select elements 220-b and 220-c (and corresponding word lines and digit lines), each of the corresponding sense elements 125 (e.g., 125-a to 125-h) can be appropriately filled with data, and sense element groups 460-a and 460-b can be fully filled to allow reading, writing, and other operations.

[0097] In some embodiments, based on identifying the current relationship between plates 210-b and 210-c (as an example) within the first plate group 450-a, one or more other plate pairs 445 (e.g., 445-a, 445-d) may be selected. This selection of plates 210-f and 210-g may be accompanied by the selection of selection component pair 455-d that selects selection components 220-f and 220-g. By selecting plates 210-f and 210-g and selection components 220-f and 220-g (and the corresponding word lines and digit lines), each of the sense components 125 corresponding to the digit lines can be appropriately filled with data, and the sense component group can be fully populated to allow reading, writing, and other operations.

[0098] In some embodiments, one or more panels or one or more panel pairs may be selected based on a relationship associated with one or more panels or one or more panel pairs, or both. In some embodiments, this relationship may include a spatial relationship, such as one or more absolute positions, one or more relative positions of one, two, and / or more panels and / or pairs, panel addresses (including absolute or relative panel addresses or both) of one or more panels or related units, some combination thereof, or other things. In some embodiments, this relationship may include a position, such as a position directly or immediately adjacent to or adjacent to one, two, or more panels or pairs, among other things. In some embodiments, panels within a panel group (e.g., panel group 450-a) may be adjacent to and / or adjacent to other panels within the panel group. In other embodiments, panels within different panel groups (e.g., panel 210-h and panel 210-j of panel groups 450-a and 450-b, respectively) may be positioned adjacent to each other.

[0099] In some embodiments, based on identifying the current relationship between plates 210-b and 210-c (as an example) within the first plate group 450-a, one or more other plate pairs (e.g., 445-a, 455-e) may be selected. In some embodiments, a first plate (e.g., plate 210-h) and a second plate (e.g., plate 210-i) may be selected, and the second plate may be associated with the second plate group (e.g., plate group 450-b). In some embodiments, this selection may include barrel shifting, barrel selection, wraparound shifting, wraparound selection, or some combination, among other variations. This selection of plates 210-h and 210-j may be accompanied by selecting a selection component pair 455-e that selects a selection component 220-h and one or more other selection components 220. In some embodiments, the one or more selection components 220 may include a selection component 220 associated with another group (e.g., a first selection component of another selection component group), or the one or more selection components 220 may include a selection component 220-a from a first selection component pair 455 (e.g., a group) that may then be paired with selection component 220-h, or some combination.

[0100] Similarly, in some embodiments, a first board (e.g., board 210-p) and a second board (e.g., board 210-a, another board (not shown)) may be selected, which may be associated with a first board group (e.g., 450-a) and a third board group (e.g., 450-c).

[0101] By selecting the plates in an odd-even plate pair (e.g., 210-f and 210-g) and selecting components 220-f and 220-g (and the corresponding word lines and digit lines), each of the sensing components 125 corresponding to the digit line 115 can be appropriately filled with data, and one or more sensing component groups 460 can be fully filled to allow reading, writing, or other operations.

[0102] For example, if Figure 4 , select components 220 (e.g., 220-a through 220-h), which in some embodiments may each be an example of a transistor capable of being selected, are arranged to connect respective digit lines (e.g., 115-a through 115-h) from respective plates (e.g., 210-a through 210-h) to sense components (e.g., sense components 125-a through 125-h) to facilitate selection of one or more plate pairs. Digit lines from some plates (e.g., plates 210-a, 210-c, 210-e, 210-g) may be connected to or in electronic communication with a first group of sense components (e.g., sense component group 460-a). Digit lines from some plates (e.g., plates 210-b, 210-d, 210-f, 210-h) may be connected to or in electronic communication with a second group of sense components (e.g., sense component group 460-b). In some embodiments, when one or more plate pairs (e.g., 445-a, 445-b, 445-c, 445-d) are selected (regardless of the order of each pair (e.g., odd-even, even-odd, or some other order)), the first and second groups of sensing components will be accurately populated with data. The same principles, actions, and operations also apply to other embodiments, methods, and techniques described in this disclosure.

[0103] According to various embodiments of the invention, a set of selection components (as well as other components or elements) can be in electronic communication with or associated with multiple board groups, boards, or other groups of memory components. For example, a set of selection components (e.g., selection components 220-a through 220-h) can facilitate or perform selection of one or more boards associated with one or more board groups (e.g., board group 450-a, board group 450-b), or some combination of both.

[0104] Additionally, alternatively, one or more other group selection components 220 (as well as other components or elements) may be in electronic communication with or associated with multiple board groups, boards, or other groups of memory components. As an example, one group of selection components 220 (e.g., selection components 220-a through 220-h) may facilitate or perform selection of one or more boards associated with one board group (e.g., board group 450-a), and another group of selection components 220 (e.g., selection components 220-h through 220-p) may facilitate or perform selection of one or more boards associated with one or more other board groups (e.g., board group 450-b).

[0105] In some embodiments, the array 500 may include plate pairs (e.g., 445-b, 445-c, 445-d) that fall within the same plate group 450-a and may be selected based on current relationships between plates within the plate group 450-a and / or one or more other plate groups.

[0106] In some embodiments, array 500 may include plate pairs (e.g., 445-a, 445-e, 445-f, 445-g, 445-h) that fall within one or more other plate groups (e.g., 450-b, 450-c), and selection may be made based on current relationships between plates within the same plate group or one or more other plate groups (e.g., plate groups 450-a and / or 450-b), as well as others. This selection may be based on one or more factors, including granularity of selection and / or related components, array design, the presence of one or more current relationships, one or more plate group designs, one or more elements or components of the array and / or memory cells and / or electronic memory devices, performance relationships, current relationships, electronic communication relationships, state determination and / or identification, some combination, and / or other factors.

[0107] For example, in some embodiments, elements of array 500 (and / or some related components and / or elements discussed in other figures, such as memory controller 140) may be configured to select a current source based on the current relationship between plates 210-b and 210-c. Figure 4 and / or Figure 5 Based at least in part on determining (via read or write operations or monitoring performance of one or more boards, among other methods and techniques) and / or identifying current relationships, one or more elements (e.g., fuses) associated with the one or more groups of boards may initiate selection of a board pair (e.g., 445-a through 445-i, etc.).

[0108] In some embodiments, the selection may be finer and may apply only to plates that are in a current relationship, plates in the same plate group, adjacent plate groups, and / or some other subsection of a larger memory sample.

[0109] In some embodiments, methods and techniques for operating ferroelectric memory cells according to various embodiments of the present invention are described. The methods and techniques may include: identifying a first cell plate included in a first cell plate group; identifying a second cell plate adjacent to the first cell plate and included in the first cell plate group or the second cell plate group; and selecting the first cell plate and the second cell plate based at least in part on a current relationship between the first cell plate and the second cell plate, among other operations. The methods and techniques may include: receiving a memory access command for a memory access operation associated with a first page size of memory cells; identifying a first page of memory cells to be activated for the memory access operation based at least in part on the memory access command, the first page having the first page size; determining whether there is a short circuit associated with at least one memory cell of a second page of memory cells that includes the first page and has a second page size greater than the first page size; and activating the second page of memory cells based at least in part on determining the presence of a short circuit associated with the at least one memory cell.

[0110] In some embodiments, the current relationship may include, among other things, a short circuit between a first cell plate and a second cell plate. In some embodiments, the current relationship may include, among other things, a first current level for the first cell plate and / or a second current level for the second cell plate. In some embodiments, the first current level results from applying a voltage to the first cell plate, and the second current level results from applying a voltage to the second cell plate. In some embodiments, the short circuit associated with the memory cell includes a short circuit between the first plate and the second plate associated with the memory cell.

[0111] In some embodiments, one or more cell boards may be included in one or more groups and may be organized and / or sorted in one or more positions within the one or more groups. In some embodiments, the first cell board and / or the second cell board may be included in the first cell board group. In some embodiments, the first cell board may be included in the first cell board group and / or the second cell board may be included in the second cell board group. In some embodiments, the first cell board may be in the last position in the first cell board group and / or the second cell board may be in the first position in the second cell board group.

[0112] In some embodiments, a sector of a memory array may contain a row of groups, where each group contains multiple plates. In some embodiments, a page of memory cells may include memory cells associated with a subset of the plates within each group in a sector, or may include memory cells associated with all of the plates within each group in a sector.

[0113] In some embodiments, memory cells associated with one or more planes in each group can be accessed based on a page size associated with a memory access command. For example, access based on a smaller page size can include biasing, selecting, or activating all memory cells associated with the first plane in each group in a sector, such that executing a memory access command based on the smaller page size can include biasing, selecting, or activating only the memory cells associated with the first plane in each group. In some cases, a larger page size can include memory cells associated with two or more planes in each group, such as memory cells associated with the first and third planes in each group, or memory cells associated with alternating planes in each group, or memory cells associated with all planes in each group. In this case, executing a memory access command based on the larger page size can include selecting, biasing, or activating all memory cells associated with multiple planes within each group. In some cases, a larger page of memory cells can be an entire sector or multiple entire sectors of a memory array, and selecting or activating the larger page of memory cells can include selecting or activating all memory cells associated with all planes in the sector.

[0114] One executable operation associated with one or more cell boards may include a read operation, including a value-based or logic-based read operation. In some embodiments, methods and techniques for operating memory cells according to various embodiments of the present invention may include reading information from a first cell board and a second cell board based at least in part on reading information from a first sense amplifier in electronic communication with the first cell board and a second sense amplifier in electronic communication with the second cell board. In some embodiments, the methods and techniques may include reading information from a combination of the first cell board and the second cell board based at least in part on the selection.

[0115] In some embodiments, methods and techniques for operating memory cells according to various embodiments of the present invention may include: identifying a third cell plate included in a third cell plate group; identifying a fourth cell plate included in the second cell plate group or the third cell plate group; identifying a third cell plate adjacent to the fourth cell plate; and selecting the third cell plate and the fourth cell plate as a pair based at least in part on a current relationship between the first cell plate and the second cell plate.

[0116] In some embodiments, according to various embodiments of the present invention, one or more cell boards may be included in one or more groups or may be organized and ordered in one or more positions within one or more groups. In some embodiments, the third cell board may be included in the third cell board group, and / or the fourth cell board may be included in the second cell board group. In some embodiments, the third cell board may be in the first position in the third cell board group, and / or the fourth cell board may be in the last position in the second cell board group.

[0117] Figure 6 Example arrays 605-625 are illustrated that each support selection of one or more cell plates and operations associated with the one or more cell plates according to various embodiments of the present invention. Each of the arrays 605-625 can include ferroelectric memory cells, one or more word lines, digit lines, one or more sensing elements, one or more plates (e.g., plates 210-a to 210-p), selection elements, or plate groups (e.g., plate group 450-a, plate group 450-b), which can be referenced as follows: Figure 1 、 2 , 4, 5, or other described memory cells 105, word lines 110, digit lines 115, sense components 125, plates 210, and / or select components 220. Each of arrays 605-625 may include features or functions similar to, the same as, or different from those discussed with respect to arrays 400, 500, or the like. Figures 1 to 5 and other discussions or Figures 1 to 5 and other related features, methods, techniques, and structures.

[0118] In some embodiments, additional elements are contemplated according to various embodiments of the invention, although each may not be explicitly labeled or shown. Figure 6 The plate groups (e.g., 450-a), plates (e.g., 210-a), plate pairs (e.g., 665-a), and current performance relationships (e.g., 665-a) shown in FIG. 1 also contemplate the use of a plurality of plate pairs based on the current performance relationship. Figures 1 to 5 Other elements or components disclosed, described, or contemplated, as well as others. For example, while Figure 6 Not clearly shown Figures 1 to 5 (and others) described or shown in the digit line, word line, selection element, sensing element or other elements, but the present invention (including with respect to Figure 6 Each of the digit lines, word lines, selection components, sensing components, or other elements is contemplated (alone or in combination) in the embodiments shown and described.

[0119] Example arrays 605-625 illustrate various current relationships that can exist between cell plates of the array, including short circuits.

[0120] As shown in example array 605, plates 210-a through 210-h are organized as part of plate group 450-a, and plates 210-i through 210-p are organized as part of plate group 450-b. In some embodiments, current relationship 665-a is detected based at least in part on one or more identifications or determinations. Based at least in part on this detection of current relationship 665-a, one or more plate pairs (e.g., plate pair 645-a) are selected by one or more system elements or components. In some embodiments, first plate pair 645-a is identified as corresponding to an even-odd relationship of plates 210-a and 210-b associated with current relationship 665-a. As discussed herein, one or more elements may perform selection of plates 210-a and 210-b based at least in part on the detected current relationship 665-a directly associated with plates 210-a and 210-b.

[0121] In some embodiments, the plate pair 645-a may be individual and may not be selected from other plate pairs in the same plate group (e.g., plate group 450-a) or other plate groups (e.g., plate group 450-b) based at least in part on the current relationship 665-a. This single-pair granularity in identification, determination, or selection may be suitable in certain designs or other embodiments. For example, this single-pair selection reduces power consumption associated with alternative embodiments that may need to read, write, or perform other operations based on multiple, numerous, or every two plates in a segment, column, die, bank, and / or other structure.

[0122] In some embodiments, plate pair 645-a may be individual to a first plate group (e.g., 450-a) and may be associated with or otherwise correspond to plate pair 645-b, as shown in example array 605. In this example, one or more elements or components may select one plate pair in the first group (e.g., plate group 450-a) and one plate pair in one or more other plate groups (e.g., plate group 450-b). In some embodiments, these plate pairs (e.g., 645-a and 645-b) may be selected based on current relationship 665-a and other parameters, factors, or conditions related to array 605 or other system elements or components. In some embodiments, selection of plate pairs 645-a and 645-b may be based on determining current relationship 665-a affecting a first plate in the first group (e.g., plate 210-a of plate group 450-a) and a second plate in the first group (e.g., plate 210-b of plate group 450-a). In some embodiments, based on identifying current relationship 665-a, selection of plate pair 645-b may be performed before, during, or after selection of plate pair 645-a is performed. Thus, indirect selection of plates 210-i and 210-j may be performed based on current relationships between other plates (e.g., plates 210-a and 210-b in array 605). Indirect selection may be performed independently of, in addition to, instead of, or otherwise related to direct selection based on current relationships (e.g., 665-a) between specific plates having current relationships (e.g., plates 210-a and 210-b in array 605).

[0123] As shown in example array 610, plates 210-a through 210-h are organized as part of plate group 450-a, and plates 210-i through 210-p are organized as part of plate group 450-b. In some embodiments, plates 210-a and 210-j may be included in a first page having a smaller page size (e.g., 64B), and plates 210-a, 210-j, 210-b, and 210-j may be included in a second page having a larger page size (e.g., 128B). In some embodiments, groups 450-a and 450-b and corresponding plates 210-a through 210-p may be part of a segment containing multiple other groups (not shown).

[0124] In some embodiments, based on one or more identifications or determinations, current relationship 665-b may be detected (e.g., identified, determined, etc.). Based at least in part on this detection of current relationship 665-b, one or more panel pairs (e.g., panel pair 645-c) may be selected by one or more system elements or components. In some embodiments, first panel pair 645-c is identified as corresponding to an even-odd relationship of panels 210-a and 210-b associated with current relationship 665-b. As discussed herein, one or more components may perform selection of panels 210-c and 210-d based on the detected current relationship 665-b indirectly associated with panels 210-c and 210-d. Additionally, panel pair 645-d may be selected based on the detection of current relationship 665-b, the selection of panel pair 645-c, some combination, and / or other information. In some embodiments, plate pair 645-d may be selected based on the relative position of each plate (e.g., plate 210-k is in the "2" position and plate 210-1 is in "3"), and this may or may not be related to the relative position of one or more other plates (e.g., plate 210-c is in the "2" position and plate 210-d is in "3").

[0125] In some embodiments, as shown in example array 610, plate pair 645-d may correspond to the relative position of plate pair 645-c (which includes plate 210-c and plate 210-d), shown in the "2" and "3" positions of plate group 450-a. In some embodiments, as shown in example array 610, plate pair 645-d may correspond to the relative position of current relationship 665-b (which is based on the relative position of plates 210-a and 210-b) and the ordering of current relationship 665-b, shown in the "0" and "1" positions of plate group 450-a. For example, the ordering of current relationship 665-b (e.g., even-odd) may at least partially influence or otherwise influence the selection of plate pair 645-d (associated with plates 210-k and 210-1).

[0126] In some embodiments, multiple current relationships may exist between plates in one or more plate groups, as shown in example array 615. For example, one or more identifications or determinations may be performed to determine at least one of current relationship 665-c and current relationship 665-d that may each affect two or more plates (e.g., plates 210-a, 210-b, 210-e, 210-f) and other elements or components.

[0127] In some embodiments, based on identifying or determining current relationship 665-c or current relationship 665-d, one or more selections corresponding to plate pair 645-e or 645-f, as well as others, can be made. One or more plate pairs can be selected using a controller, one or more fuses, one or more other elements or components, some combination, and / or other configurations by comparing one or more current relationships, plate order, spatial relationships of relative plate positions (even-odd, odd-even), and / or other factors.

[0128] Alternatively or additionally, a particular pair of plates (e.g., 645-e, 645-f, 645-g) is selected based on identifying or determining (among other operations) one or more current relationships in one or more plate groups. In some embodiments, this selection may be based on identifying or determining some, most, or all current relationships present in one, multiple, or each plate group within a particular die, bank, segment, group, and / or other subset. For example, one or more plate pairs (e.g., 645-e, 645-f, 645-g) may be selected by identifying, comparing, or otherwise determining current relationships 665-c, 665-d, 665-e, 665-f, and 665-g. In some embodiments, this detection may be based on comparing or determining whether each current relationship is an even-odd current relationship or an odd-even current relationship.

[0129] In some embodiments, this detection can be based on comparing or determining whether one or more current relationships are determined to be similar to one or more current relationships without determining whether the one or more current relationships are odd-even, even-odd, whether they affect the first and second boards, whether they affect the second and third boards, and / or some combination. For example, this detection can be based on comparing and / or determining whether current relationship 665-c is similar to current relationship 665-d and / or current relationship 665-e without determining whether each of the current relationships is even, even-odd, whether they affect the first and second boards, whether they affect the second and third boards, whether they affect other boards, and / or some combination.

[0130] In other embodiments, this detection may be performed independently of or dependent upon comparing or determining whether each current relationship is an even-odd current relationship or an odd-even current relationship.

[0131] In some embodiments, a plurality of current relationships exist between the plates in the first plate group, the second plate group, and / or between the first and second plate groups (as well as other variations), as shown in example array 620. For example, one or more identifications or determinations may be performed to determine at least one of current relationships 665-h, 665-i, and 665-j that each affect two or more plates (e.g., plates 210-b and 210-c, 210-h and 210-i, 210-1 and 210-m), as well as other elements or components.

[0132] In some embodiments, based on identifying or determining one or more of the current relationships 665-h, 665-i, and 665-j, one or more selections may be made corresponding to the plate pair 645-h or 645-i, as well as other or some combination thereof. One or more plate pairs may be selected by comparing the spatial relationship of one or more current relationships, plate order, relative plate positions (even-odd, odd-even), and / or other factors. In some embodiments, the selection may be based on one or more current relationships between different plate groups and / or subgroups. For example, as shown in example array 620, one or more current relationships (e.g., current relationships 665-i) exist between a first plate group (e.g., 450-a) and a second plate group (e.g., 450-b), or between the second plate group (e.g., 450-b) and an additional plate group (e.g., a third plate group).

[0133] One or more plate pairs or groups may be selected based at least in part on one or more current relationships between two or more plate groups. In some embodiments, one or more plate pairs may be selected based on determining a first current relationship (e.g., current relationship 665-i). The selected one or more plate pairs may include plates in similar absolute and / or relative positions (e.g., position "7" and position "0"), may have a similar order (e.g., odd-even as in current relationship 665-i), and / or other factors.

[0134] In some embodiments, selecting one or more panel pairs may be based on determining that two or more current relationships (e.g., current relationship 665-i and current relationship 665-j) affect one panel group. By determining that two or more current relationships affect one panel group (e.g., panel group 450-b), one or more selections may be made regarding the affected panel group (e.g., panel group 450-b) and / or one or more other panel groups (including, but not limited to, two or more other panel groups that are adjacent to or adjacent to panel group 450-b and two or more other panel groups that are not adjacent to or adjacent to panel group 450-b but may still be included in the same die vault or segment).

[0135] In some embodiments, multiple current relationships exist between the plates in the first plate group, the second plate group, or between the first and second plate groups (as well as other variations), as shown in example array 625. For example, one or more identifications or determinations may be performed to determine at least one of current relationships 665-k, 665-1, and / or 665-m that each affect two or more plates (e.g., plates 210-b and 210-c, 210-h and 210-i, 210-i and 210-m), as well as other elements or components.

[0136] In some embodiments, based on identifying or determining one or more of the current relationships 665-k, 665-1, and / or 665-m, one or more selections corresponding to the plate pairs 645-j, 645-k, and / or 645-1, as well as others, may be made. One or more plate pairs may be selected by comparing the spatial relationship of one or more current relationships, plate order, relative plate positions (even-odd, odd-even), and / or other factors. In some embodiments, the selection may be based on one or more current relationships between different plate groups. For example, as shown in example array 625, one or more current relationships (e.g., current relationship 665-1) may exist between a first plate group (e.g., 450-a) and a second plate group (e.g., 450-b) and / or between the second plate group (e.g., 450-b) and an additional plate group (e.g., a third plate group).

[0137] One or more plate pairs or groups may be selected based at least in part on one or more current relationships between two or more plate groups. In some embodiments, one or more plate pairs may be selected based on determining a first current relationship (e.g., current relationship 665-1 or 665-k). The selected one or more plate pairs may include pairs of plates in similar absolute or relative positions (e.g., position "7" and position "0" as depicted by plate pair 645-k), may have similar order (e.g., odd-even as in current relationship 665-i or 665-1), and / or other factors.

[0138] In some embodiments, selection of one or more panel pairs may be based on determining that two or more current relationships have a similar order (e.g., odd-even, even-odd) and / or the relative position of at least one panel in the panel pair (e.g., panel pair 645-k). For example, an initial determination may be made regarding the order of some, most, and / or all detected current relationships within a specified group (e.g., a segment, die, bank, group, subset). By determining that at least one of the detected current relationships (e.g., current relationship 665-i and current relationship 665-j) affects a particular panel and / or a particular panel pair (e.g., based on odd-even order, affects the panel in position "7," such as 210-h, etc.), a panel pair including at least one panel from the first panel group and at least one panel from the second panel group (e.g., the first panel and panel 210-a shown by panel pair 645-j, panels 210-h and 210-i shown by panel pair 645-k, etc.) may be selected.

[0139] In some embodiments, the selection may be based on determining whether each current relationship (e.g., 665-k, 665-1, 665-m) includes a specific order (or no specific order), such as even-odd or odd-even (or a more complex order involving additional plates), and whether all plate relationships are similar based on the relative positions of one or more plates directly and / or indirectly affected by at least one current relationship (e.g., position "0" or "4" or "7").

[0140] In some embodiments, selection can be performed based on determining whether a subset of current relationships (e.g., 665-1) includes a particular order (or not), such as even-odd or odd-even (or a more complex order involving additional boards), and without regard to the presence of one or more other current relationships, the order of the boards of the one or more other current relationships, the absolute or relative position of the one or more other current relationships, some combination or other factors. For example, based on determining or identifying current relationship 665-1, selection of boards 210-h and / or 210-i to form board pair 645-k can be performed. Alternatively or additionally, based on the identification or determination regarding board pair 645-k, all other similarly positioned pairs within a segment and / or other granularity (e.g., library, die) can be selected. For example, based on the identification or determination regarding plate pair 645-k, other plate pairs in the same position (eg, positions "7" and "0" in this example) may be paired, resulting in selection of plate pair 645-j or plate pair 645-1 and others.

[0141] Alternatively or additionally, based on the identification or determination regarding board pair 645-k, all other boards within a segment and / or other granularity (e.g., library, die) may be selected in a similar manner. For example, based on the identification or determination regarding board pair 645-k, all other boards may be paired regardless of their position and / or other characteristics, resulting in selection of boards 210-b and 210-c, 210-d and 210-e, 210-f and 210-g, 210-j and 210-k, 210-1 and 210-m, 210-n and 210-o, the first board in board pair 645-j and board 210-a, the second board in board pair 645-1 and board 210-p, and / or others.

[0142] In some embodiments, electronic memory devices according to various embodiments of the present invention are described. The electronic memory device may include a first cell board group, a second cell board group, a first cell board included in the first cell board group, or a second cell board adjacent to the first cell board and included in the first cell board group or the second cell board group. In some embodiments, the first cell board and the second cell board may be in electronic communication.

[0143] In some embodiments, the electronic communication may include, among other things, a short circuit between a first cell board and a second cell board. In some embodiments, the electronic communication is based on proximity of the first cell board to the second cell board. As described in accordance with various embodiments of the present invention, the proximity may include one or more of absolute location, relative location, proximity to another cell board in the same group, proximity to another cell board in at least one other group, some combination thereof, or other variations.

[0144] In some embodiments, an electronic memory device according to various embodiments of the present invention may include a first digit line in electronic communication with a first cell plate and a first sense amplifier via a first transistor. In some embodiments, an electronic memory device according to various embodiments of the present invention may include a second digit line in electronic communication with a second cell plate and a second sense amplifier via a second transistor. In some embodiments, the first transistor and / or the second transistor may be embodiments of a sensing element according to various embodiments of the present invention.

[0145] In some embodiments, according to various embodiments of the present invention, one or more cell boards may be included in one or more groups and may be organized and / or ordered in one or more positions within the one or more groups.

[0146] In some embodiments, the first unit board and the second unit board are each included in a first unit board group. In some embodiments, the first unit board is included in the first unit board group, and the second unit board is included in the second unit board group. In some embodiments, the first unit board is included in one unit board group, and the second unit board is included in another unit board group different from the unit board group of the first unit board. In some embodiments, the first unit board is in the first position in the first unit board group, and the second unit board is in the last position in the second unit board group. In some embodiments, the first unit board is in the last position in the first unit board group, and the second unit board is in the first position in the second unit board group. In some embodiments, the first unit board is not in the first position in the first unit board group, and / or the second unit board is not in the last position in the second unit board group.

[0147] In some embodiments, in addition to employing the methods and techniques described herein to support the selection of cell boards and board pairs and operations associated with cell boards and board pairs, additional methods and techniques involving redundant memory elements or components may be used. For example, certain design parameters may require a level of redundancy that may require full redundant segments (and / or more localized but more expensive redundancy based on groups, etc.). However, the use of board-based selection and the use of one or more board pairs within a board group, segment, library, die, or other organization can greatly reduce the need for redundant segments (and in some embodiments, eliminate the need for redundant segments), thereby reducing the cost of redundant memory segments and avoiding expensive localized redundancy control (e.g., board groups, etc.). The use of the board selection techniques and methods associated herein enables existing memory elements to be more robust and avoids large-scale discarding of groups, segments, libraries, and / or dies based on secondary current performance relationships (which may include shorts between vertically cut boards, among other things).

[0148] For example, where a conventional design may require multiple redundant segments based on one or more of yield constraints, defect density, and / or technology-dependent decisions, the use of board pair and selection techniques associated with one or more board pairs in a board group, a page, a segment, a die, a library, a column, and / or another granularity may actually reduce the required redundancy by making the components more efficient and robust through the use of board selection.

[0149] In some embodiments, associated methods and techniques may include identifying redundancy or robustness factors or requirements, determining how board selection and / or shifting of one or more board pairs will affect the redundancy or robustness factors or requirements, and / or reducing the redundancy or robustness factors or requirements based on the determination. According to various embodiments of the invention, these steps (and others) may be performed before, as part of, or after the board selection step or other steps.

[0150] This hybrid solution (including board selection and reduced redundant memory) can enable memory devices and products to provide additional features and capabilities without the need for a fully redundant and prohibitively expensive fully redundant memory solution. In some designs, employing board selection techniques and methods can reduce the raw redundancy from three redundant sectors to one redundant sector, as just one example. However, in many embodiments, the techniques and methods described throughout this disclosure support selecting, shifting cells, and cell-related operations without the need for raw redundancy or hybrid techniques.

[0151] The example arrays 605 to 625, each supporting the selection of a cell board and operations associated with the cell board, are merely examples of various embodiments according to the present invention. Each of these examples may be modified, adapted, replicated, include additional steps, omit steps, or otherwise adapted at least in part based on the various embodiments and situations described.

[0152] Figure 7 A block diagram 700 is shown of a memory array 100-a that supports selection of and operations associated with one or more cell boards according to various embodiments of the present invention. The memory array 100-a may be referred to as an electronic memory device and may include a memory controller 140-a and memory cells 105-b, which may be referenced as Figure 1 and 2 and other described embodiments of the memory controller 140 and memory unit 105. The memory controller 140-a may include a bias component 710 and a timing component 715, and may be configured as follows: Figures 1 to 3 Memory array 100-a is operated as described in . Memory controller 140-a may be in electronic communication with word lines 110-b, digit lines 115-aa, sense elements 125-q, and / or plates 210-q, which may be reference Figures 1 to 6 11 to 14 and other described embodiments of word lines 110, digit lines 115, sense elements 125, and plate 210 (and other embodiments). Memory array 100-a may also include reference elements 720 or latches 725. The components of memory array 100-a may be in electronic communication with each other and may perform reference operations. Figures 1 to 6 11 to 14 and other described functions. In some embodiments, reference component 720, sense component 125-q, and latch 725 can be components of memory controller 140-a.

[0153] The memory controller 140-a may be configured to activate the word line 110-b, the plate 210-q, or the digit line 115-q by applying voltages to various nodes. For example, the bias component 710 may be configured to apply voltages to operate the memory cell 105-b to read or write to the memory cell 105-b, as described above. In some embodiments, the memory controller 140-a may include a row decoder, a column decoder, or both, as described in reference to FIG. Figure 1 and other descriptions. This can enable the memory controller 140-a to access one or more memory cells 105. The bias component 710 can also provide a voltage potential to the reference component 720 to generate a reference signal for the sensing component 125-q. In addition, the bias component 710 can provide a voltage potential for the operation of the sensing component 125-q.

[0154] In some embodiments, memory controller 140-a can use timing component 715 to perform its operations. For example, timing component 715 can control the timing of various word line selections or plate biases, including the timing of switching and voltage application for performing memory functions discussed herein, such as reading and writing. In some embodiments, timing component 715 can control the operation of bias component 710.

[0155] In some embodiments, the reference component 720 can generate a reference signal for the sensing component 125-q. The reference component 720 can, for example, include a circuit configured to generate a reference signal. In some embodiments, the reference component 720 can be another ferroelectric memory cell 105. In some embodiments, the reference component 720 can be configured to output a voltage having a value between the two sensing voltages, such as a reference voltage. Figure 3 Alternatively, the reference component 720 can be designed to output a virtual ground voltage (ie, approximately 0V).

[0156] In some embodiments, sense component 125-1 can compare a signal from memory cell 105-b (via digit line 115-a) to a reference signal from reference component 720. Once the logic state is determined, the sense component can store the output in latch 725, where it can be used in accordance with the operation of an electronic device using memory array 100-a and other components or elements.

[0157] In some embodiments, the memory controller 140-a may be associated with or in electronic communication with a first cell board and a second cell board, which may each be a variety of boards 210 (see Figures 1 to 6 and other descriptions). The first digit line can be in electronic communication with the first cell plane and the first sensing component (e.g., a sense amplifier) ​​via a first selection component (e.g., a transistor). The second digit line can also be in electronic communication with the second cell plane and the second sensing component (e.g., a sense amplifier) ​​via a second selection component (e.g., a transistor). In some embodiments, memory controller 140-a can be in electronic communication with one or more components of memory array 100-a (and other memory arrays and / or memory devices), including but not limited to the first sensing component and / or the second sensing component.

[0158] Based at least in part on the electronic communications, the controller is operable to initiate and / or perform one or more operations. In some embodiments, the memory controller 140-a is operable to determine or identify a memory device associated with one board 210 (e.g., 210-q) and associated with two different adjacent or neighboring boards (e.g., reference Figures 4 to 6 and 11 to 14 and other described two plates), related to one or more plates in a single plate group, related to two or more plates (at least one of which is included in a plate group, page, segment or layer that is different from the others, some combination and / or other components or elements).

[0159] In some embodiments, such determination may include measuring, reading, writing, calculating, comparing, correlating, verifying, linking, analyzing, estimating, or accessing one or more characteristics, values, measurements, current or voltage levels or relationships, locations, performance relationships, operations, and / or other parameters specific to, related to, or based on one or more boards, digit lines, sensing components, selection components, and / or groups of boards, among other things. In some embodiments, such identification may include detecting, distinguishing, comparing, correlating, correlating, measuring, reading, linking, analyzing, estimating, and / or accessing one or more characteristics, values, measurements, current or voltage levels or relationships, locations, performance relationships, operations, and / or other parameters specific to, related to, or based on one or more boards, digit lines, sensing components, selection components, and / or groups of boards, among other things. As an example, memory controller 140-a may determine and / or identify a current relationship between a first cell board and a second cell board, which may be based at least in part on reading and / or otherwise receiving information from one or more sensing components, each associated with at least one of the first cell board and the second cell board.

[0160] Based at least in part on this determination or identification, the memory controller may initiate (e.g., send an instruction or signal to another element or component or control another element or component to operate) an operation to select the first cell board and the second cell board based at least in part on the spatial relationship. In some embodiments, this selection may include electronic communication from the controller to one or more selection components, which may include communicating with two or more selection components (e.g., including one or more selection component pairs) based at least in part on the determination or identification. In some embodiments, this spatial relationship may be based at least in part on the absolute position or relative position of the one or more cell boards or other elements or components.

[0161] In some embodiments, this spatial relationship can be based at least in part on the position of the first cell plate relative to the second cell plate, including whether the cell plates (and / or others) are adjacent, proximate, in a particular order, in relative positions within a group, and / or otherwise relative to each other (and / or other cell plates and / or elements or components). For example, the selection can include and / or can be based at least in part on a spatial relationship related to the position of the first cell plate in the first cell plate group relative to the second cell plate in the first cell plate group. The selection can include and / or can be based at least in part on the position of the first cell plate in the first cell plate group being in the "7" position (e.g., the last or final position) and the position of the second cell plate in the first cell plate group being in the "0" position (e.g., the first or initial position), in the "4" position (e.g., in a non-endpoint, intermediate position), or in the "6" position (e.g., an adjacent position).

[0162] Additional cell boards may be selected (via the memory controller and / or one or more other elements or components). For example, in some embodiments, a third cell board may be included in the first cell board group, and a fourth cell board may be included in the first cell board group, wherein each of these cell boards may be identified and / or determined to be related to the first cell board and the second cell board and the other elements or components. In some embodiments, the memory controller 140-a is operable to select the third cell board and the fourth cell board based at least in part on a spatial relationship. For example, the third cell board and / or the fourth cell board may be selected based at least in part on a determination that the third cell board is adjacent to at least one of the first cell board and the fourth cell board (and in some embodiments, both the first cell board and the fourth cell board).

[0163] In some embodiments, the selection of the third and fourth cell panels may be based at least in part on the spatial relationship of the third and fourth cell panels themselves. In other embodiments, the selection of the third and fourth cell panels may be based at least in part on the spatial relationship between the first and second cell panels. In other embodiments, the selection of the third and fourth cell panels may be based at least in part on the spatial relationship between at least one of the first and second cell panels and the third and fourth cell panels.

[0164] In some embodiments, memory controller 140-a may initiate or be operable to read information from at least one of the first and second sensing components (and other elements or components) based at least in part on the selection. In some embodiments, this may include memory controller 140-a reading values ​​from first and second sense amplifiers on selected two or more transistors corresponding to and / or otherwise related to the two plates having and / or related to the current relationship, among other factors.

[0165] Figure 8 A diagram showing a system 800 that supports selection of one or more cell boards and operations associated with one or more cell boards according to various embodiments of the present invention. System 800 may include a device 805 that may be or include a printed circuit board that connects or physically supports various components. Device 805 may include a memory array 100-b that may be Figure 1 and Figure 7 Examples of memory arrays 100 are described in and elsewhere. Memory array 100-b may contain a memory controller 140-b and one or more memory cells 105-c, which may be referenced. Figure 1 and 7 and other descriptions of the memory controller 140 and references Figure 1 、 27 and other described embodiments of the memory unit 105. The device 805 may also include a processor 810, a BIOS component 815, one or more peripheral components 820 and / or an input / output control component 825, as well as other components or elements. The components of the device 805 can communicate electronically with each other via a bus 830.

[0166] The processor 810 may be configured to operate the memory array 100-a through the memory controller 140-b. In some embodiments, the processor 810 executes the reference Figure 1 and 7 As well as the functions of the memory controller 140 or 140-a described elsewhere herein. In other embodiments, the memory controller 140-b may be integrated into the processor 810. The processor 810 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these types of components, and the processor 810 may perform the various functions described herein, including performing identification, determination, or selection related to one or more cell boards and / or other components or elements. The processor 810 may, for example, be configured to execute computer-readable instructions stored in the memory array 100-a to cause the device 805 to perform various functions or tasks.

[0167] BIOS component 815 may be a software component that includes a basic input / output system (BIOS) operating as firmware that can initialize and run the various hardware components of system 800. BIOS component 815 may also manage the flow of data between processor 810 and various components (e.g., peripheral components 820, input / output controller components 825, etc.). BIOS component 815 may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0168] The one or more peripheral components 820 can be any input or output device, or an interface for such a device, that is integrated into the device 805. Examples can include a hard disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot.

[0169] The input / output controller component 825 can manage data communications between the processor 810 and the peripheral components 820, the input device 835, or the output device 840. The input / output controller component 825 can also manage peripheral devices that are not integrated into the device 805. In some embodiments, the input / output controller component 825 can represent a physical connection or port to an external peripheral device.

[0170] Input 835 may represent a device or signal external to device 805 that provides input to device 805 or its components. This may include a user interface or interfacing with other devices or between other devices. In some embodiments, input 835 may be a peripheral device that interfaces with device 805 via peripheral component 820 or may be managed by input / output controller component 825.

[0171] Output device 840 may represent a device or signal external to device 805 that is configured to receive output from the device or any of its components. Examples of output device 840 may include a display, an audio speaker, a printing device, another processor or printed circuit board, etc. In some embodiments, output device 840 may be a peripheral device that interfaces with device 805 via peripheral component 820 or may be managed by input / output controller component 825.

[0172] The components of memory controller 140-b, device 805, and memory array 100-b may be composed of circuits designed to implement their functions. This may include various circuit elements configured to implement the functions described herein, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or non-active elements.

[0173] Figure 9 A flow chart illustrating a method 900 of selecting one or more cell boards and operations associated with the one or more cell boards according to various embodiments of the present invention is shown. Figures 4 to 8 The operations of the methods and techniques discussed herein and others may be implemented by the memory array 100, as described with reference to FIG. Figures 1 to 8 Description. For example, Figures 4 to 6 The operations of the methods and techniques and others may be performed by the memory controller 140, as described with reference to Figure 1 、 7 8 and other descriptions. In some embodiments, the memory controller 140 may execute a set of codes to control the functional elements of the memory array 100 to perform the functions described below. Additionally or alternatively, the memory controller 140 may use dedicated hardware to perform embodiments of the functions described below. Additionally or alternatively, the memory controller 140 may initiate one or more signals and / or instructions to enable one or more other components or elements to use dedicated hardware to perform embodiments of the functions described below.

[0174] At block 905, the method may include identifying a first cell board included in a first cell board group, as described with reference to FIG. Figures 1 to 8and other descriptions. In some embodiments, this identification of the first cell board may be based on one or more operational characteristics of the first cell board, another cell board, a combination of the first cell board and the second cell board, and / or one or more other individual cell boards. For example, the operational characteristics may include voltage, current, value, current relationship associated with one or more boards, performance relationship associated with one or more boards, absolute position of one or more boards and / or other components, relative position of one or more boards and / or other components, some combination and / or other characteristics and / or relationships. In some embodiments, the operations of block 905 may be performed by the memory controller 140, as described with reference to Figure 1 、 7 In some embodiments, the operation of block 905 may be initiated by the memory controller 140, as described in reference to FIG. Figure 1 、 7 In other embodiments, the operations of block 905 may be performed by different elements and / or components of the memory array and / or memory device other than the memory controller 140.

[0175] At block 910, the method may include identifying a second cell board that is adjacent to the first cell board and / or included in the first cell board group or the second cell board group, as described with reference to FIG. Figures 1 to 8 and other descriptions. In some embodiments, this identification of the second cell board may be based on one or more operating characteristics of the first cell board, another cell board, a combination of the first cell board and the second cell board, and / or one or more other individual cell boards, as well as other factors. For example, the operating characteristics may include voltage, current, value, current relationship associated with one or more boards, performance relationship associated with one or more boards, absolute position of one or more boards and / or other components, relative position of one or more boards and / or other components, some combination and / or other things. In some embodiments, the operations of block 910 may be performed by the memory controller 140, as described with reference to Figure 1 、 7 In some embodiments, the operation of block 910 may be initiated by the memory controller 140, as described in reference to FIG. Figure 1 、 7 In other embodiments, the operations of block 910 may be performed by different elements and / or components of a memory array and / or memory device, among other things.

[0176] At block 915, the method may include selecting the first cell plate and the second cell plate based on a current relationship between the first cell plate and the second cell plate, as described with reference to FIG. Figures 1 to 8and other descriptions. This selection may be performed by one or more memory elements or components and / or may be performed on one or more memory elements or components and / or may be based on electronic communication with one or more elements or components. In some embodiments, this selection may include selecting one or more selection components (which may include transistors, among other things, in some embodiments). In some embodiments, this selection may include selecting one or more selection component pairs that enable the sensing components corresponding to each digit line to be accurately filled with data depending on each selection component. In some embodiments, the method may further include reading from one or more sensing components associated with the one or more selection components, the board, and / or the digit line based on the selection.

[0177] In some embodiments, one or more selections may be based on one or more triggering events, including but not limited to, fuses being triggered by one or more signals and / or one or more operating parameters associated with one or more elements or components (e.g., cell boards and / or sensing components). In some embodiments, the operations of block 915 may be performed by memory controller 140, as described with reference to FIG. Figure 1 、 7 In some embodiments, the operation of block 915 may be initiated by the memory controller 140, as described in reference to Figure 1 、 7 and 8 and other descriptions. In other embodiments, the operations of block 915 may be performed by different elements and / or components of the memory array and / or memory device, among other things.

[0178] Figure 10 A flow chart illustrating a method 1000 of selecting one or more cell boards and operations associated with the one or more cell boards according to various embodiments of the present invention is shown. Figures 4 to 9 The operations of the methods and techniques discussed herein and others may be implemented by the memory array 100, as described with reference to FIG. Figures 1 to 9 Description. For example, Figures 4 to 6 The operations of the methods and techniques and other related methods may be performed by the memory controller 140, as described in reference to Figure 1 、 7 8 and other descriptions. In some embodiments, the memory controller 140 may execute a set of codes to control the functional elements of the memory array 100 to perform the functions described below. Additionally or alternatively, the memory controller 140 may use dedicated hardware to perform embodiments of the functions described below. Additionally or alternatively, the memory controller 140 may initiate one or more signals and / or instructions to enable one or more other components or elements to use dedicated hardware to perform embodiments of the functions described below.

[0179] At block 1005, the method may include identifying a first cell board included in a first cell board group, as described with reference to FIG. Figures 1 to 9and other descriptions. In some embodiments, this identification of the first cell board may be based on one or more operational characteristics of the first cell board, another cell board, a combination of the first cell board and the second cell board, and / or one or more other individual cell boards. For example, the operational characteristics may include voltage, current, value, current relationship associated with one or more boards, performance relationship associated with one or more boards, absolute position of one or more boards and / or other components, relative position of one or more boards and / or other components, some combination and / or other things. In some embodiments, the operations of block 1005 may be performed by the memory controller 140, as described with reference to Figure 1 、 7 In some embodiments, the operation of block 1005 may be initiated by the memory controller 140, as described in reference to FIG. Figure 1 、 7 In other embodiments, the operations of block 1005 may be performed by different elements and / or components of a memory array and / or memory device, among other things.

[0180] At block 1010, the method may include identifying a second cell panel that is adjacent to the first cell panel and / or included in the first cell panel group or the second cell panel group, as described with reference to FIG. Figures 1 to 8 and other descriptions. In some embodiments, this identification of the second cell board can be based on one or more operational characteristics of the first cell board, another cell board, a combination of the first cell board and the second cell board, and / or one or more other individual cell boards. For example, the operational characteristics can include voltage, current, value, current relationship associated with one or more boards, performance relationship associated with one or more boards, absolute position of one or more boards and / or other components, relative position of one or more boards and / or other components, some combination, and / or other things.

[0181] In some embodiments, identification of a second cell board adjacent to a first cell board may be performed regardless of whether the second cell board is included in a particular board group (e.g., first cell board group, second cell board group). In some embodiments, identification of a second cell board adjacent to a first cell board may be performed based on whether the second cell board is included in the particular board group itself (e.g., first cell board group, second cell board group) and / or based on whether another board (e.g., first cell board) is included in the same board group (regardless of which particular board group it is), a different board group, a related board group, an adjacent board group, some combination, and / or other factors. In some embodiments, the operations of block 1010 may be performed by the memory controller 140, as described with reference to FIG. Figure 1 、 7 In some embodiments, the operation of block 1010 may be initiated by the memory controller 140, as described in reference to FIG. Figure 1 、 7In other embodiments, the operations of block 1010 may be performed by different elements and / or components of a memory array and / or memory device, among other things.

[0182] At block 1015, the method may include identifying or determining that the first cell board is included in a first cell board group and the second cell board is included in a second cell board group, as described with reference to FIG. Figures 1 to 8 and other descriptions. This identification and / or determination can be performed by one or more memory elements or components and / or can be performed on one or more memory elements or components and / or can be based on electronic communication with one or more elements or components. In some embodiments, this identification and / or determination can include identifying or determining the position and / or spatial relationship between the first unit board and the second unit board. This identification or determination of the position and / or spatial relationship can be based on determining or identifying whether the second unit board is located in the same unit board group as the first unit board.

[0183] Additionally or alternatively, this identification or determination of the position and / or spatial relationship may be based in particular on determining whether the second cell panel is adjacent to a first cell panel in the first cell panel group. This identification or determination of the position and / or spatial relationship may be based in particular on determining or identifying whether the first cell panel and the second cell panel are positioned in absolute and / or relative corresponding positions within the first cell panel group and / or the second cell panel group. This identification or determination of the position and / or spatial relationship may be based in particular on determining or identifying whether the first cell panel and the second cell panel are positioned relative to a plate pair associated with and / or comprising a current relationship, the plate pair possibly including the first cell panel and / or the second cell panel.

[0184] In some embodiments, the operation of block 1015 may be performed by the memory controller 140, as described with reference to FIG. Figure 1 、 7 In some embodiments, the operation of block 1015 may be initiated by the memory controller 140, as described in reference to FIG. Figure 1 、 7 In other embodiments, the operations of block 1015 may be performed by different elements and / or components of a memory array and / or memory device, among other things.

[0185] At block 1020, the method may include identifying or determining that the first cell board is in the last position in the first cell board group and the second cell board is in the first position in the second cell board group, as described with reference to FIG. Figures 1 to 8And other descriptions. This identification and / or determination can be performed by one or more memory elements or components and / or can be performed on one or more memory elements or components and / or can be based on electronic communication with one or more elements or components. In some embodiments, this identification and / or determination can include identifying or determining the position of each of the first and second unit boards and / or the spatial relationship between the first and second unit boards. This identification or determination of position and / or spatial relationship can be based on determining or identifying whether the second unit board is adjacent to (and other relationships) the first unit board, but each of these is located in a separate unit board group. This identification or determination can be based on one or more other identifications, determinations, and / or selection steps and other things.

[0186] This identification or determination of positional and / or spatial relationships can be based, in particular, on determining or identifying whether the first and second cell panels are positioned within respective absolute and / or relative positions within the first and / or second cell panel groups. For example, this identification or determination can be based on determining whether the first cell panel is in a first and / or initial position (e.g., position "0") within the first cell panel group. This identification or determination can be based on identification and / or determination relative to the first cell panel and can be based on determining whether the second cell panel is in a first and / or initial position (e.g., position "0"), an intermediate initial position (e.g., positions "1" to "6"), and / or a final and / or ultimate position (e.g., position "7") within the second (or another) cell panel group. This identification or determination of positional and / or spatial relationships can be based, in particular, on determining or identifying whether the first and second cell panels are positioned relative to a plate pair associated with and / or including a current relationship. In some embodiments, this plate pair may or may not include the first cell panel and / or the second cell panel.

[0187] In some embodiments, the operations of block 1020 may be performed by the memory controller 140, as described with reference to FIG. Figure 1 、 7 In some embodiments, the operation of block 1020 may be initiated by the memory controller 140, as described in reference to FIG. Figure 1 、 7 In other embodiments, the operations of block 1020 may be performed by different elements and / or components of a memory array and / or memory device, among other things.

[0188] At block 1025, the method may include selecting a first cell board and a second cell board based on a short circuit between the two cell boards, as described with reference to FIG. Figures 1 to 8and other descriptions. This selection may be performed by one or more memory elements or components and / or may be performed on one or more memory elements or components and / or may be based on electronic communication with one or more elements or components. In some embodiments, this selection may include selecting one or more selection components (which may include transistors, among other things, in some embodiments). In some embodiments, this selection may include selecting one or more selection component pairs that enable the sensing components corresponding to each digit line to be accurately filled with data depending on each selection component. In some embodiments, the method may further include reading from one or more sensing components associated with the one or more selection components, the board, and / or the digit line based on the selection.

[0189] In some embodiments, one or more selections may be based on a triggering event, including, but not limited to, a fuse being triggered by one or more signals and / or operating parameters associated with one or more elements or components (e.g., cell boards and / or sensing components). In some embodiments, based on the presence and / or determination of adverse direct electron flow between two cell boards (e.g., a short circuit). In some embodiments, the operations of block 1025 may be performed by memory controller 140, as described with reference to FIG. Figure 1 、 7 In some embodiments, the operation of block 1025 may be initiated by the memory controller 140, as described in reference to FIG. Figure 1 、 7 and 8 and other descriptions. In other embodiments, the operations of block 1025 may be performed by different elements and / or components of the memory array and / or memory device, among other things.

[0190] Other techniques for selecting boards based on short circuit detection are possible, such as reference Figures 11 to 14 describe.

[0191] Figure 11 Shown is a patch array 1100 that may be about Figure 1 1. A portion of the memory array 100 is depicted. The patch array 1100 is organized into a plurality of patches 1105, each of which may contain a plurality of plates (not shown). Each plate within a patch 1105 may be associated with one or more memory cells. In some cases, a patch may be an instance of a plate group (e.g., plate groups 440-a, 440-b) along with the memory cells and drivers associated with the plate group. In some cases, a patch may include distributed driver circuits, such as one or more word line drivers, digit line drivers, and / or plate line drivers that may be coupled to corresponding word lines, digit lines, and / or plate lines associated with the patch, such as with respect to FIG. Figure 12 Describe in more detail.

[0192] In some embodiments, a row of patches 1105 may be referred to as a sector 1110. The exemplary patch array 1100 is organized into 32 sectors 1110, where each sector 1110 includes a row of 18 patches. Other array sizes are possible. In some cases, each patch 1105 may include a memory cell array; for example, a patch may include a 1000x1000 memory cell array, or may be another sized array, depending on the feature size and density of the memory array.

[0193] In some cases, segment 1110 is accessible via one or more word lines, such as word line 110. In some cases, a column of patch array 1100 is accessible via one or more digit lines, such as digit line 115.

[0194] In some cases, a memory array may include multiple layers 1115 of memory cells, with each layer organized into patches 1105 and sectors 1110 .

[0195] In some cases, a memory device may be configured to access patch array 1100 based on a page size. A page size may be the minimum number of memory cells that can be selected for a memory access operation. For example, a memory device may be configured to access patch array 1100 based on a page size of 64B, 128B, 256B, 2KB, etc. In this case, the memory device may select a page of memory cells for a memory access operation based on the page size. In some cases, a page of memory cells may be distributed across multiple patches 1105. For example, if each patch 1105 includes four slabs, performing a memory access operation based on a 64B page size may include selecting memory cells associated with the first slab in each patch in a segment. Performing a memory access operation based on a 128B page size may include selecting memory cells associated with both slabs in each patch in a segment. Executing a memory access operation based on a page size of 256B may include selecting all memory cells associated with all four plates in each patch in a segment; for example, selecting every memory cell of the segment. Executing a memory access operation based on a page size greater than 256B may include selecting some or all memory cells (and therefore some or all plates) in multiple segments.

[0196] Figure 12 A patch array 1200 supporting array plate short circuit repair technology according to an embodiment of the present invention is shown. The patch array 1200 includes an array of six patches 1205, where each patch 1205 includes four plates 1210 (plates 0, 1, 2, and 3). For example, the patch array 1200 can be part of the patch array 1100 or the memory array 100. Each row 1235 of the patches 1205 of the patch array 1200 can be part of a segment, such as Figure 11 Segment 1110 is described.

[0197] Patch array 1200 includes word line drivers 1215, digit line drivers 1220, and sensing components 1225 for selecting or activating plate 1210 and memory cells (not shown) associated with plate 1210. (For simplicity, Figure 12 Not all drivers and / or sense elements 1225 may be present in each patch 1205. In some cases, word line drivers 1215 and digit line drivers 1220 are distributed around the periphery of the patch 1205 to enable finer activation and selection of plates and memory cells, and to provide various other device advantages. In some cases, a sense element 1225 may be activated based on activation of a corresponding digit line driver 1220. In some cases, each sense element 1225 may be shared by two plates 1210 and may include 16 sense amplifiers.

[0198] In some embodiments, each of the four plates 1210 in the patch 1205 can be associated with a separate plate driver (not shown) so that each plate within the patch can be independently biased or activated. In some cases, each of the four plates 1210 in the patch 1205 can be associated with one or more digit lines (not shown) that can be coupled to the digit line driver 1220 of the patch 1205 to enable memory access operations for one or more memory cells associated with the plate 1210, such as with respect to a memory cell. Figures 4 to 5 describe.

[0199] In some embodiments, each of the four plates 1210 in patch 1205 may be associated with one or more word lines (not shown), which may be coupled with a word line driver 1215 of patch 1205 to enable selection of one or more memory cells associated with the plate 1210. In some cases, two or more plates 1210 within patch 1205 may be associated with memory cells that share a common word line.

[0200] In some embodiments, patch array 1200 can activate one or more word line drivers 1215, digit line drivers 1220, and / or plate line drivers (not shown) to select a page of memory cells for memory access operations. For example, if a (smaller) page of memory cells includes only memory cells associated with the first plate (plate 0) in each patch in a sector, activating the page of memory cells can include activating the word line driver, one or more digit line drivers, and plate line drivers associated with plate 0 of each patch 1205, without activating any drivers associated with other plates in each patch. Activating a larger page of memory cells can include activating one or more word line drivers, digit line drivers, plate line drivers associated with, for example, plates 0 and 2 of each patch 1205, and so on.

[0201] In some cases, a first plate 1210 may have an unintended short circuit with a second plate 1210 (e.g., an adjacent plate within the same patch) due to, for example, a manufacturing defect. In patch array 1200, for example, a short circuit 1240-a exists between a first plate 1210-a and a second plate 1210-b in a patch of a first section 1235-a, and a short circuit 1240-b exists between a second plate 1210-c and a third plate 1210-d in a patch of a second section 1235-c. In this case, activating plate 1210-a without activating the memory cells associated with plate 1210-b may result in data corruption (or other undesirable effects) in the memory cells associated with plate 1210-b, and similarly for plates 1210-c and 1210-d.

[0202] In some embodiments, a memory device may receive a memory access command associated with a first page size and identify a first page of a memory array for the memory access command; for example, identifying the first page of the memory array on which a memory access operation is to be performed. In some cases, the first page may not include all plates in each patch in the sector.

[0203] By way of example, the memory device may identify, based on the first page size, a first page of the memory array that includes all memory cells associated with the first plate 1210 (plate 0) of each patch 1205 in the section 1235-a.

[0204] In some embodiments, a memory device may determine whether a short circuit exists associated with at least one memory cell of a second page of memory cells, where the second page is larger than and includes the first page. In this example, the second page may be in the same segment 1235-a as the first page and may include memory cells associated with one or more additional plates in each patch. For example, the second page may include all memory cells associated with plate 0 (e.g., memory cells in the first page) and may also include all memory cells associated with plate 1 of each patch in segment 1235-a. In this case, because a short circuit exists associated with plate 1210-b included in the second page, the memory device may determine that a short circuit exists associated with at least one memory cell in the second page. Based on determining that a short circuit exists associated with at least one memory cell in the second page, the memory device may activate the second page instead of only the first page. That is, the memory device may activate all memory cells associated with both plate 0 and plate 1 in each patch of segment 1235-a instead of only the memory cells associated with plate 0. In this way, the memory device can mitigate the effects of a short circuit between boards 1210 - a and 1210 - b and avoid unwanted device behavior.

[0205] In the above example, the identified short circuit 1240-a is associated with at least one memory cell in the first page; for example, a memory cell associated with plate 1210-a. That is, a short circuit exists between plate 1210-a, which is included in the first page, and plate 1210-b, which is included in the second page but not in the first page. However, in some embodiments, the memory array may activate the second page even if the short circuit does not involve plates or memory cells in the first page. For example, the memory array may determine whether there is a short circuit associated with any memory cell in the sector containing the first page—even if the short circuit does not involve any plates or memory cells in the first page—and if so, the memory array may activate the second (larger) page.

[0206] By way of example, a memory device may determine that a short circuit 1240-b exists between memory cells associated with a first plate 1210-c in a segment 1235-c and memory cells associated with a second plate 1210-d in the same segment 1235-c. Neither plate 1210-c nor plate 1210-d is included in a first page. In this case, the memory device may, based on the determination that a short circuit exists, activate all memory cells associated with all plates 1210 in segment 1235-c, which may be equivalent to activating a larger page of memory cells. Thus, in some cases, if the memory device determines that a short circuit exists anywhere within a segment that includes the first page, the memory device may activate all memory cells in the segment and thereby "boost" memory access operations to a larger (e.g., maximum) page size.

[0207] In some embodiments, the memory array may perform a memory access operation (e.g., a read operation) on all memory cells in the second (larger) page, thereby generating a complete set of data for the second page. In some embodiments, the memory array may transfer the complete set of data to another component, e.g., via an I / O line or the like. In some cases, the memory array may only transfer a portion of the complete set of data; e.g., the data for the first page. The memory array may discard (e.g., refrain from transferring) the data for the remaining cells in the second page.

[0208] In some embodiments, activating the second page may include activating all drivers and access lines associated with all memory cells in the second page. In some cases, activating the second page may include activating all drivers and access lines associated with all memory cells in the first page, but only activating the plate lines and digit lines associated with the remaining cells in the second page. This latter approach can reduce the amount of power associated with memory access operations while still ensuring that memory cells associated with the shorted plate are not damaged during the memory access operation. In this case, the memory access operation may not be performed on all memory cells in the second page; the memory access operation may be performed only on the memory cells in the first page (e.g., only selected aspects of the memory access operation may be performed on all memory cells in the second page).

[0209] In some embodiments, if the memory array determines that there are no short circuits associated with memory cells in the second page, for example, if the second page is in section 1235-b and does not include any shorting plates, the memory array may select only the first page memory cells without selecting the remaining cells in the second page. That is, if the memory array determines that there are no short circuits, the memory array may perform memory access operations based on the first page size as usual.

[0210] In some embodiments, the memory array may be configured to activate a larger page (e.g., a sector) of memory cells in response to identifying a short circuit anywhere within a sector containing a smaller page of memory cells, regardless of whether the short circuit is associated with memory cells in the first page. This may be referred to as sector-level short repair granularity, and in this case, a single fuse or signal may be used to indicate whether a short circuit exists in the entire sector. In other embodiments, the memory array may be configured to activate a larger page (e.g., 128B, 256B) of memory cells based on a finer granularity. For example, the memory array may be configured to activate a larger page of memory cells only if the detected short circuit is associated with a board included in the first page of memory cells. This may be referred to as board-level granularity, and may require additional fuses or signals (e.g., more than one fuse or signal per sector) to provide separate signals indicating short circuits within different page sizes. In other embodiments, the memory array may be configured to activate a larger page of memory cells based on a coarser granularity. For example, a multi-layer memory array may be configured to activate a larger page (e.g., a sector) of memory cells in response to identifying a short circuit anywhere within the same sector of any layer, regardless of whether the short circuit is within the first page or within the same layer as the first page. In this case, a single fuse or signal may be shared among the layers and used to indicate whether a short circuit exists in a particular sector number of any layer.

[0211] Figure 13 An example memory array 1300 is illustrated that supports techniques for array plate short circuit repair according to embodiments of the present invention. Memory array 1300 includes a command component 1305, a logic component 1310, and a patch array 1315. Command component 1305 and / or logic component 1310 may be included in a memory controller, such as memory controller 140. Memory array 1300 may be an example of a memory array configured to detect and repair short circuits at a segment-level granularity; that is, if memory array 1300 determines that a short circuit exists anywhere within a segment containing the first page to be accessed, memory array 1300 may activate all memory cells in the segment and / or operate in a larger page size mode.

[0212] The command component 1305 can be configured to receive a memory access command specifying a memory access operation, such as a read, write, set, or reset operation. The memory access command can be associated with a first page size of memory cells. The command component can be configured to identify a first page in a segment patch array 1315 for the memory access operation based on the first page size and send an address range associated with the first page size of memory cells based on the memory access command. In the exemplary memory array 1300, the patch array 1315 includes 32 sectors, and the command component 1305 can send an address range, such as a sector address and / or sector number, that indicates the segment of the patch array 1315.

[0213] Logic component 1310 may be configured to receive an address range (e.g., a sector address and / or sector number) from the command component. Logic component 1310 may be configured to also receive a fuse signal for each sector that indicates whether there is a short circuit associated with at least one of the memory cells of that sector. For example, if a short circuit exists between two plates in sector 0, fuse signal 0 may be set to a "1" value or otherwise asserted, thereby indicating a short circuit in sector 0. The fuse signal may be received from a physical or logical fuse that is triggered based on the detection of a short circuit in the corresponding sector, such as, for example, a fuse associated with a sector. Figure 4 describe.

[0214] The logic component may activate a repair signal 1320 based on the received address range and the corresponding fuse signal. In some cases, the logic component includes a physical or logical OR tree, e.g. Figure 13 , if any fuse signal is set to a "1" value (or otherwise asserted) and the address in the corresponding segment is received from the command component, the repair signal 1320 is activated; for example, if the command component sends the segment address of the segment that has a short circuit between two plates in the segment. It will be understood by those skilled in the art that other techniques for identifying short circuits and activating repair signals can be used to similar effect. In addition, although Figure 13 The OR tree depicted in FIG can be associated with the segment-level granularity of short circuit detection and repair, but other OR trees (or other types of logic) can be suitable for different levels of granularity. For example, for board-level granularity, the OR tree can include additional fuse signals or repair signals.

[0215] Patch array 1315 can be coupled with logic component 1310 and configured to activate a larger page of memory cells (e.g., a sector) based at least in part on activation of repair signal 1320. In some embodiments, patch array 1315 can be configured to operate in a larger page size mode whenever repair signal 1320 is activated. In some cases, activating the repair signal adjusts an address range associated with a first page of memory cells to an address range associated with a second, larger page of memory cells.

[0216] For a multi-layer memory device, the same fuse signals may be shared between layers, or each layer may have its own set of independent fuse signals. If the same fuse signals are shared between layers, the command component may be configured to send an indication of a sector number associated with a first page for a memory access operation based at least in part on a memory access command, where the first page is in a segment having that sector number of the first layer. The logic component may be configured to receive the indication of the sector number and activate a repair signal if there is a short circuit associated with a memory cell in the same sector number, regardless of whether the memory cell is in the first layer or the second layer. For example, if the first page is in segment (1) of layer 2, and there is a short circuit between two plates in segment (1) of layer 1, the repair signal may be activated, and the memory array may in turn activate the larger page of memory cells in layer 2. This approach may allow larger page size accesses to be performed more frequently at the potential expense of reducing the number of fuses required to indicate a short circuit.

[0217] An electronic memory device according to various embodiments of the present invention is described. The electronic memory device may include: a memory array comprising a first page of memory cells having a first page size and a second page of memory cells comprising the first page and having a second page size; a command component configured to: receive a memory access command associated with the first page size of memory cells in the memory array; and send an address range associated with the first page of memory cells based at least in part on the memory access command; and a logic component coupled to the command component and the memory array, the logic component configured to: receive the address range associated with the first page of memory cells from the command component; and activate a signal based at least in part on the address range and in response to determining that a short circuit exists associated with at least one memory cell in the second page of memory cells, wherein the memory array is configured to activate the second page of memory cells based at least in part on the activation of the signal.

[0218] In some examples, an electronic memory device may include: a first plate associated with the at least one memory cell; and a second plate associated with at least one second memory cell in the second page, wherein the determination that there is a short circuit associated with the at least one memory cell includes determining that the first plate is shorted to the second plate.

[0219] In some examples, activating the second page of memory cells includes activating the first plate and the second plate.

[0220] In some examples, the first board is a first shared board associated with a first plurality of memory cells including the at least one memory cell, and the second board is a second shared board associated with a second plurality of memory cells including the at least second memory cell. In some examples, the logic component comprises an OR tree.

[0221] An electronic memory device according to various embodiments of the present invention is described. The electronic memory device may include: a memory array comprising a plurality of layers of memory cells, each comprising a plurality of sectors divided into a plurality of pages of memory cells; a command component configured to: receive a memory access command associated with a first page size; and based at least in part on the memory access command, send an indication of a sector number associated with a first page of the plurality of pages, wherein the first page has the first page size and is in a first sector associated with the sector number; and a logic component coupled to the command component and the plurality of layers, the logic component configured to: receive the indication of the sector number; and based at least in part on the indication, in response to determining that a short circuit exists associated with at least one memory cell in a second sector associated with the sector number, activate a signal, wherein the memory array is configured to activate all of the memory cells in the first sector based at least in part on the activation of the signal.

[0222] In some examples, the second segment is in a different layer than the first segment. In some examples, the second segment and the first segment are the same segment in the same layer.

[0223] An electronic memory device according to various embodiments of the present invention is described. The electronic memory device may include: a memory array comprising a plurality of layers of memory cells, each comprising a plurality of sectors divided into a plurality of pages of memory cells; a command component configured to: receive a memory access command associated with a first page size; and based at least in part on the memory access command, send an indication of a sector number associated with a first page of the plurality of pages, wherein the first page has the first page size and is in a first sector associated with the sector number; and a logic component coupled to the command component and the plurality of layers, the logic component configured to: receive the indication of the sector number; and based at least in part on the indication, in response to determining that a short circuit exists associated with at least one memory cell in a second sector associated with the sector number, activate a signal, wherein the memory array is configured to activate all of the memory cells in the first sector based at least in part on the activation of the signal.

[0224] Figure 14A flow chart illustrating a method 1400 of selecting one or more cell boards and operations associated with the one or more cell boards according to various embodiments of the present invention is shown. Figures 11 to 13 The operations of the methods and techniques discussed herein and others may be performed by the memory array 100 or by reference to Figures 1 to 13 The patch arrays 1100, 1200, 1315 described are implemented. For example, Figures 11 to 13 The operations of the methods and techniques and other related methods may be performed by the memory controller 140 and / or the command component 1305 and the logic component 1310, as described in reference to Figure 1 、 7 , 8 and 13 and other descriptions. In some embodiments, memory controller 140 may execute a set of codes to control the functional elements of memory array 100 or patch arrays 1100, 1200, 1315 to perform the functions described below. Additionally or alternatively, memory controller 140 may use dedicated hardware to perform embodiments of the functions described below. Additionally or alternatively, memory controller 140 may initiate one or more signals and / or instructions to enable one or more other components or elements to use dedicated hardware to perform embodiments of the functions described below.

[0225] At block 1405, the method may include receiving a memory access command for a memory access operation associated with memory cells of a first page size. In some embodiments, the first page size may be, for example, 64B or 128B. In some embodiments, the first page size may be specified by the memory access command. In some embodiments, the first page size may not be specified by the memory access command, and a memory controller and / or memory array (or other portion of the memory device) may be configured to execute the memory access command based on the first page size.

[0226] In some embodiments, the operations of block 1405 may be performed by the memory controller 140 and / or the command component 1305 and the logic component 1310, as described with reference to FIG. Figure 1 、 7 , 8 and 13 and other descriptions. In some embodiments, the operation of block 1405 may be initiated by the memory controller 140 and / or the command component 1305 and the logic component 1310, as shown in FIG. Figure 1 、 7 , 8 and 13 and other descriptions. In other embodiments, the operations of block 1405 may be performed by different elements and / or components of the memory array and / or memory device, among other things.

[0227] At block 1410, the method may include identifying a first page of memory cells to be activated for a memory access operation based at least in part on a memory access command, the first page having the first page size. In some embodiments, the memory cells of the first page may be identified by the memory controller 140. In some embodiments, the first page may include memory cells associated with one or more plates in each patch in a segment; for example, the first page may include memory cells associated with a first plate for each patch in a segment, or with a first and second plate for each patch in the segment, etc.

[0228] In some embodiments, the operations of block 1410 may be performed by the memory controller 140 and / or the command component 1305 and the logic component 1310, as described with reference to FIG. Figure 1 、 7 , 8 and 13 and other descriptions. In some embodiments, the operation of block 1410 may be initiated by the memory controller 140 and / or the command component 1305 and the logic component 1310, as shown in FIG. Figure 1 、 7 , 8 and 13 and other descriptions. In other embodiments, the operations of block 1410 may be performed by different elements and / or components of a memory array and / or memory device, among other things.

[0229] At box 1415, the method may include determining whether there is a short circuit associated with at least one memory cell of a second page of memory cells that includes the first page and has a second page size that is larger than the first page size. In some embodiments, the second page size may be 128B or 256B, for example. In some cases, determining whether there is a short circuit associated with the at least one memory cell includes: determining whether there is a short circuit between a first plate associated with the at least one memory cell and a second plate associated with a second memory cell. In some cases, the at least one memory cell may be included in the first page, and the second memory cell may be included in the second page but not in the first page. In some examples, determining whether there is a short circuit may include receiving a signal indicating that a short circuit exists, such as receiving a fuse signal from a fuse or receiving a repair signal from a logic component, such as with respect to Figure 13 In some cases, determining whether a short circuit exists can include performing post-manufacturing or run-time testing of the memory array that determines the short circuit exists and optionally triggering a corresponding fuse.

[0230] In some embodiments, the operations of block 1415 may be performed by the memory controller 140 and / or the command component 1305 and the logic component 1310, as described with reference to FIG. Figure 1 、 7, 8 and 13 and other descriptions. In some embodiments, the operation of block 1415 may be initiated by the memory controller 140 and / or the command component 1305 and the logic component 1310, as shown in FIG. Figure 1 、 7 , 8 and 13 and other descriptions. In other embodiments, the operations of block 1415 may be performed by different elements and / or components of the memory array and / or memory device, among other things.

[0231] At block 1420, the method may include activating the second page of memory cells based at least in part on determining that there is a short circuit associated with the at least one memory cell. In some examples, the memory controller and / or the memory array or patch array may activate the second page of memory cells by activating one or more word lines, digit lines, and / or plate lines associated with the second page of memory cells. In some examples, activating the second page of memory cells includes promoting a memory access operation from an access based on a first page size to an access based on a second page size, for example, by adjusting an address range associated with the first page to an address range associated with the second page.

[0232] In some embodiments, the operations of block 1420 may be performed by the memory controller 140 and / or the command component 1305, the logic component 1310, and / or the patch arrays 1100, 1200, 1315, as described with reference to FIG. Figure 1 、 7 , 8 and 11 to 13 and other descriptions. In some embodiments, the operation of block 1420 may be initiated by the memory controller 140, the command component 1305, the logic component 1310 and / or the patch arrays 1100, 1200, 1315, as described in reference to Figure 1 、 7 , 8 and 11 to 13 and other descriptions. In other embodiments, the operations of block 1420 may be performed by different elements and / or components of the memory array, patch array and / or memory device, among other things.

[0233] An apparatus is described for performing method 1400. The apparatus may include: means for receiving a memory access command for a memory access operation associated with a first page size of memory cells; means for identifying a first page of memory cells to be activated for the memory access operation based at least in part on the memory access command, the first page having the first page size; means for determining whether there is a short circuit associated with at least one memory cell of a second page of memory cells that includes the first page and has a second page size larger than the first page size; and means for activating the second page of memory cells based at least in part on determining the presence of a short circuit associated with the at least one memory cell.

[0234] In some examples, the means for determining whether there is a short circuit associated with at least one memory cell may include means for determining whether a first plate associated with the at least one memory cell of the second page is shorted to a second plate associated with at least one second memory cell of the second page.

[0235] In some examples, the at least the second memory cell is included in the first page, and the at least the second memory cell is not included in the first page.

[0236] In some examples, the second page of memory cells includes a third page of memory cells separate from the first page, and the apparatus may include: means for activating a first access line associated with the first page of memory cells and a second access line associated with the third page of memory cells based at least in part on the determination that there is a short circuit associated with the at least one memory cell, wherein the means for activating the second page of memory cells may include means for activating the first access line and the second access line.

[0237] In some examples, the first access line and the second access line are a first plate line and a second plate line, or a first digit line and a second digit line.

[0238] In some examples, the means for activating the second page may include: means for activating a first word line associated with the first page; and means for activating a digit line and a plate line associated with the at least the second memory cell without activating a second word line associated with the at least the second memory cell.

[0239] In some examples, the apparatus may include means for activating a first driver associated with the first access line and a second driver associated with the second access line based at least in part on the determination that a short circuit associated with the at least one memory cell exists. In some examples, the means for activating the second page of memory cells may include means for activating the first driver and the second driver.

[0240] In some examples, the apparatus may include: means for activating a first plurality of sense amplifiers associated with the first page of memory cells and a second plurality of sense amplifiers associated with the third page of memory cells based at least in part on the determination that a short circuit exists associated with the at least one memory cell. In some examples, the first plate is a first shared plate associated with a first plurality of memory cells including the at least one memory cell, and the second plate is a second shared plate associated with a second plurality of memory cells including the at least second memory cell. In some examples, the first plate is a first cell plate associated with the at least one memory cell, and the second plate is a second cell plate associated with the at least second memory cell.

[0241] In some examples, the first plate and the second plate are adjacent plates in a patch that includes a plurality of plates associated with a plurality of memory cells, and the apparatus may include means for activating all of the plurality of memory cells in the patch based at least in part on the determination that there is a short circuit associated with the at least one memory cell.

[0242] In some examples, the first plate and the second plate are in different patches.

[0243] In some examples, the apparatus may include means for performing the memory access operation on the second page of memory cells. In some examples, the means for performing the memory access operation on the second page may include: means for generating a first set of data for the first page and a second set of data for a remaining plurality of cells in the second page; means for transmitting the first set of data; and means for refraining from transmitting the second set of data.

[0244] In some examples, the apparatus can include means for activating the first page of memory cells without activating a remaining plurality of cells in the second page based at least in part on determining that there is no short circuit associated with the at least one memory cell.

[0245] In some examples, the memory access command specifies the first page size.

[0246] In some examples, the means for determining whether a short circuit is present associated with the at least one memory cell may include means for receiving a signal indicative of whether a short circuit is present associated with the at least one memory cell.

[0247] Thus, methods 900, 1000, and 1400, and other methods described throughout the present invention and contemplated by the present invention, may use one or more elements or components to provide selection of one or more unit boards and operations associated with the unit boards. It should be noted that methods 900, 1000, and 1400, and other methods described throughout the present invention and contemplated by the present invention, may provide for the ... operations and steps may be rearranged, omitted, modified, supplemented, or otherwise modified to make other embodiments possible and contemplated. In some embodiments, two or more embodiments from methods 900, 1000, and 1400, and other methods described throughout the present invention and contemplated by the present invention, may be combined.

[0248] The description herein provides embodiments and is not limited to the scope, capabilities, or embodiments set forth in the claims. Changes may be made in the functions and arrangements of the elements discussed without departing from the scope of the invention. Various embodiments may omit, substitute, or add various programs or components as appropriate. Furthermore, features described with respect to some embodiments may be combined in other embodiments.

[0249] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all embodiments that may be implemented or within the scope of the claims. As used herein, the terms "example" and "exemplary" mean "serving as an example, instance, or illustration" and not "preferred" or "superior to other examples." The detailed description includes specific details for the purpose of providing an understanding of the described technology. However, these technologies can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described embodiments.

[0250] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes the similar components. When a first reference label is used in the specification, the description is applicable to any similar component having the same first reference label, regardless of the second reference label.

[0251] The information and signals described herein can be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a signal bus, where the bus may have multiple bit widths.

[0252] As used herein, the term "virtual ground" refers to a node in a circuit that is maintained at a voltage of approximately zero volts (0V) but is not directly connected to ground. Therefore, the voltage of the virtual ground may fluctuate temporarily and return to approximately 0V in a stable state. A virtual ground can be implemented using various electronic circuit elements, such as a voltage divider consisting of an operational amplifier and resistors. Other implementations are also possible.

[0253] The term "electronic communication" refers to a relationship between components that supports the flow of electrons between the components. This may include a direct connection between the components and / or may include intermediate components. Components in electronic communication may actively exchange electrons or signals (e.g., in an energized circuit) or may not actively exchange electrons or signals (e.g., in an unenergized circuit) but may be configured and operated to exchange electrons or signals after the circuit is energized. By way of example, two components that are physically connected via a switch (e.g., a transistor) electronically communicate regardless of the state of the switch (i.e., open or closed).

[0254] As used herein, the term "short" or "short circuit" refers to a direct conductive path established between two conductive elements. In some cases, the conductive path between the two elements may be an unintentional conductive path caused by a manufacturing defect or device damage. For example, two conductive elements (such as two plates or two wires) that are designed to be manufactured in physical proximity to each other may be accidentally shorted together if a manufacturing defect causes an unintentional conductive path to be established between the two elements. A short circuit may allow current to travel along an unintentional path with very low (e.g., negligible) electrical impedance, which may result in damage to one or both of the shorted elements or components electrically connected to one or both of the elements.

[0255] The devices discussed herein, including memory array 100, can be formed on a semiconductor substrate such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or a subregion of the substrate, can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or any other doping method.

[0256] The transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. Similarly, if the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. The transistor may be "switched on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate. The transistor may be "switched off" or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor's gate.

[0257] The various illustrative blocks, components, and modules described in connection with the present invention herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0258] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or codes. Other embodiments and implementations are within the scope of the present invention and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may also be physically located in various locations, including portions distributed so that the functions are implemented at different physical locations. Furthermore, as used herein (including in the claims), the term "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that, for example, a list of at least one of components A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C).

[0259] Computer-readable media includes both non-transitory computer storage media and communication media, including any media that facilitates transfer of a computer program from one location to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage, or any other non-transitory media that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor.

[0260] Moreover, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies (such as infrared, radio, and microwave), then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies (such as infrared, radio, and microwave) are included in the definition of medium. As used herein, disk and optical disc include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs use lasers to reproduce data optically. Combinations of the above are also included within the scope of computer-readable media.

[0261] The description herein is provided to enable any person skilled in the art to make or use the present invention. Various modifications of the present invention will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present invention. Therefore, the present invention is not limited to the embodiments and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for operating a unit board, comprising: receiving a memory access command for a memory access operation based at least in part on a configuration of a first page size for accessing one or more memory cells, the memory access operation being associated with a first page of memory cells having the first page size, wherein the first page of memory cells is within a second page of memory cells having a second page size greater than the first page size; identifying a short circuit between at least one memory cell of the second page of memory cells and a second memory cell of the second page of memory cells, wherein the at least one memory cell and the second memory cell are not included in the first page of memory cells, the first cell plate being included in a first cell plate group including a first plurality of cell plates, and the second page of memory cells including memory cells of a second cell plate being included in a second cell plate group including a second plurality of cell plates; and Based at least in part on identifying the short between the at least one memory cell of the second page of memory cells and the second memory cell of the second page of memory cells, the second page of memory cells having the second page size is activated instead of the first page of memory cells having the first page size indicated by the configuration.

2. The method according to claim 1, further comprising: It is identified that the first cell board is in a last position in the first group of cell boards.

3. The method according to claim 2, further comprising: The second cell board is identified as being in a first position in the second group of cell boards.

4. The method of claim 1, wherein the first plurality of cell plates are adjacent and the second plurality of cell plates are adjacent.

5. The method according to claim 1, further comprising: identifying a third unit board included in the third unit board group; as well as A fourth unit board included in the second unit board group or the third unit board group is identified.

6. The method according to claim 5, further comprising: identifying that the third unit board is adjacent to the fourth unit board; as well as The third and fourth cell boards are selected based at least in part on the short circuit between the first and second cell boards.

7. The method according to claim 5, further comprising: The fourth unit board included in the second unit board group is identified.

8. The method according to claim 5, further comprising: The third unit board is identified as being in a first position in the third group of unit boards.

9. The method according to claim 8, further comprising: It is identified that the fourth unit board is in a last position in the second group of unit boards.

10. A method for operating a unit board, comprising: identifying a configuration of a first page size for accessing one or more memory cells; identifying a first cell plate associated with a first page of memory cells having a first page size, wherein the first cell plate is included in a cell plate group including a plurality of cell plates; identifying a second cell plate associated with a second page of memory cells that includes the first page of memory cells and has a second page size that is larger than the first page size, wherein the second cell plate is included in the cell plate group that includes the plurality of cell plates; determining that a short circuit exists between at least one memory cell of the second page of memory cells and a second memory cell of the second page of memory cells, wherein the at least one memory cell and the second memory cell are not included in the first page of memory cells; and Based at least in part on determining that the short circuit exists, activating a second selection component coupled to the second cell plate and associated with the second page of memory cells, the second page of memory cells including the first page of memory cells regardless of the configuration of the first page size.

11. The method according to claim 10, further comprising: Based at least in part on the short circuit existing between the first cell board and the second cell board, it is identified that a fuse is triggered.

12. The method according to claim 11, further comprising: Based at least in part on the fuse being triggered, a first selection component coupled to the first cell plate and associated with the first page of memory cells and a second selection component coupled to the second cell plate and associated with the second page of memory cells are activated. The method of claim 12 , wherein the first selection component and the second selection component are activated simultaneously.

14. The method of claim 12, wherein activating the first select component coupled to the first cell board and the second select component coupled to the second cell board is based at least in part on determining a spatial relationship between the first cell board and the second cell board.

15. The method of claim 10, further comprising: identifying that the first cell board is in a first position in the group of cell boards; as well as The second cell board is identified as being in a second position in the group of cell boards.

16. The method of claim 10, wherein the first cell plate is coupled to a first access line and the second cell plate is coupled to a second access line.

17. The method of claim 10, further comprising: determining a spatial relationship between the first cell plate associated with the first page of memory cells and the second cell plate associated with the second page of memory cells based at least in part on identifying the first cell plate and identifying the second cell plate; determining, based at least in part on the spatial relationship, that a second short circuit exists between the first cell plate associated with the first page of memory cells and a second cell plate not associated with the first page of memory cells but associated with the second page of memory cells; and Based at least in part on determining that the second short circuit exists, a first selection component coupled to the first cell plate and associated with the first page of memory cells and a second selection component coupled to the second cell plate and associated with the second page of memory cells are activated regardless of the configuration of the first page size.

18. A memory system comprising: a unit panel group including a plurality of unit panels including a first unit panel and a second unit panel; as well as One or more memory controllers coupled to the group of cell boards, wherein the one or more memory controllers are operable to: identifying a configuration of a first page size for accessing one or more memory cells; identifying the first cell plate associated with a first page of memory cells having a first page size, wherein the first cell plate is included in the group of cell plates; identifying the second cell plate associated with a second page of memory cells that includes the first page of memory cells and has a second page size that is larger than the first page size, wherein the second cell plate is included in the group of cell plates; determining that a short circuit exists between at least one memory cell of the second page of memory cells and a second memory cell of the second page of memory cells, wherein the at least one memory cell and the second memory cell are not included in the first page of memory cells; and Based at least in part on determining that the short circuit exists, activating a second selection component coupled to the second cell plate and associated with the second page of memory cells, the second page of memory cells including the first page of memory cells regardless of the configuration of the first page size.

19. The memory system of claim 18, wherein the one or more memory controllers are operative to: Based at least in part on the short circuit existing between the first cell board and the second cell board, it is identified that a fuse is triggered.

20. The memory system of claim 19, wherein the one or more memory controllers are operative to: Based at least in part on the fuse being triggered, a first selection component coupled to the first cell board and a second selection component coupled to the second cell board are activated.

21. The memory system of claim 18, wherein the one or more memory controllers are operative to: identifying that the first cell board is in a first position in the group of cell boards; and The second cell board is identified as being in a second position in the group of cell boards.

22. The memory system of claim 18, wherein the one or more memory controllers are operative to: determining a spatial relationship between the first cell plate associated with the first page of memory cells and the second cell plate associated with the second page of memory cells based at least in part on identifying the first cell plate and identifying the second cell plate; determining, based at least in part on the spatial relationship, that a second short circuit exists between the first cell plate associated with the first page of memory cells and a second cell plate not associated with the first page of memory cells but associated with the second page of memory cells; and Based at least in part on determining that the second short circuit exists, a first selection component coupled to the first cell plate and associated with the first page of memory cells and a second selection component coupled to the second cell plate and associated with the second page of memory cells are activated regardless of the configuration of the first page size.

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