semiconductor devices

Abstract

The present disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor substrate, a first trench electrode and a second trench electrode formed on the semiconductor substrate, a floating layer of a first conductivity type formed around the first trench electrode and the second trench electrode, a floating separation layer of a second conductivity type formed between the first trench electrode and the second trench electrode and in contact with the floating layer of the first conductivity type, and a floating layer control gate disposed on the floating separation layer of the second conductivity type.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2019-207941 filed on November 18, 2019 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present application relates to a semiconductor device and a method for manufacturing the same, and in particular to a semiconductor device having an insulated gate bipolar transistor (IGBT). Background Art

[0004] Trench gate IGBTs are widely used as IGBTs with low on-resistance (i.e., low forward saturation voltage Vce(sat)). In addition, IE type IGBTs utilizing the IE (injection enhancement) effect have been developed to reduce the on-resistance and on-voltage of the trench gate IGBT in the on-state. In the IE type IGBT, active cells and passive cells (also referred to as floating layers) are arranged alternately. By providing a floating layer, when the IGBT is in the on-state, holes are less likely to be discharged from the emitter electrode, and the concentration of carriers (holes) accumulated in the drift layer can be increased.

[0005] Patent Document 1 discloses an IGBT structure in which active and passive cell regions are arranged alternately in the X-axis direction. Within the active cell region, there is an active portion with an emitter region and a passive portion with a body contact portion. This structure reduces the discharge path for charge carriers (holes), improving the switching losses of the IGBT during conduction.

[0006] Patent Document 2 discloses an IGBT in which active and passive cell regions are arranged alternately in the X-axis direction. Furthermore, within the active cell regions, a hybrid cell region with a body contact, an n-type separation region, and a floating region without a body contact are arranged in the Y-axis direction. This structure reduces the discharge path of carriers (holes) and improves the switching loss of the IGBT during conduction.

[0007] [Prior art literature]

[0008] [Patent Document]

[0009] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2013-258190

[0010] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2019-102759 Summary of the Invention

[0011] The technologies described in Patent Documents 1 and 2 achieve enhanced IE effects (i.e., carrier (hole) storage capacity). However, as the amount of carrier accumulation increases, switching losses (Eoff) during turn-off increase. It is necessary to simultaneously achieve both improved IE effects and reduced Eoff.

[0012] Other objects and novel features will become apparent from the description of the specification and the accompanying drawings.

[0013] Means of solving the problem

[0014] According to an embodiment, a semiconductor device includes: a semiconductor substrate; a first trench electrode and a second trench electrode formed in the semiconductor substrate; a floating layer of a first conductive type formed around the first trench electrode and the second trench electrode; a floating separation layer of a second conductive type formed between the first trench electrode and the second trench electrode and in contact with the floating layer of the first conductive type; and a floating layer control gate, which is arranged above the floating separation layer of the second conductive type.

[0015] In the semiconductor device according to the embodiment, in the IGBT, an improved IE effect and a reduced switching loss at turn-off (Eoff) are achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a plan view of a semiconductor chip according to a first embodiment;

[0017] Figure 2A is a plan view of a semiconductor chip according to a first embodiment;

[0018] Figure 2B is a cross-sectional view of a semiconductor chip according to a first embodiment;

[0019] Figure 3 is a cross-sectional view of a semiconductor chip according to a first embodiment;

[0020] Figure 4 is a cross-sectional view of a semiconductor chip according to a first embodiment;

[0021] Figure 5 is a diagram for explaining the operation of the semiconductor chip according to the first embodiment;

[0022] Figure 6 is a diagram for explaining the operation of the semiconductor chip according to the first embodiment;

[0023] Figure 7 is a diagram for explaining the operation of the semiconductor chip according to the first embodiment;

[0024] Figure 8A is a plan view of a semiconductor chip according to a first embodiment;

[0025] Figure 8B is a plan view of a semiconductor chip according to a first embodiment;

[0026] Figure 9 is a graph for explaining the effects of the semiconductor chip according to the first embodiment;

[0027] Figure 10A is a plan view of a semiconductor chip according to a first modified example of the first embodiment;

[0028] Figure 10B is a cross-sectional view of a semiconductor chip according to a first modified example of the first embodiment;

[0029] Figure 11 is a cross-sectional view of a semiconductor chip according to a first modified example of the first embodiment;

[0030] Figure 12 is a cross-sectional view of a semiconductor chip according to a second modified example of the first embodiment;

[0031] Figure 13 is a cross-sectional view of a semiconductor chip according to a third modified example of the first embodiment;

[0032] Figure 14 is a cross-sectional view of a semiconductor chip according to a fourth modified example of the first embodiment;

[0033] Figure 15A is a plan view of a semiconductor chip according to a second embodiment;

[0034] Figure 15B is a cross-sectional view of a semiconductor chip according to a second embodiment;

[0035] Figure 16A is a plan view of a semiconductor chip according to a fifth modified example of the second embodiment;

[0036] Figure 16B is a cross-sectional view of a semiconductor chip according to a fifth modified example of the second embodiment;

[0037] Figure 17A is a plan view of a semiconductor chip according to a sixth modified example of the second embodiment;

[0038] Figure 17B is a cross-sectional view of a semiconductor chip according to a sixth modified example of the second embodiment;

[0039] Figure 18 is a plan view of a semiconductor chip according to a third embodiment;

[0040] Figure 19Ais a plan view of a semiconductor chip according to a fourth embodiment; and

[0041] Figure 19B is a cross-sectional view of a semiconductor chip according to a fourth embodiment. DETAILED DESCRIPTION

[0042] Hereinafter, semiconductor devices according to embodiments will be described in detail with reference to the accompanying drawings. In the specification and drawings, elements of the same or corresponding shapes are denoted by the same reference numerals, and their repeated descriptions are omitted. In the drawings, configurations may be omitted or simplified for ease of description. In addition, at least some embodiments may be arbitrarily combined with each other.

[0043] First embodiment

[0044] Figure 1 is a plan view of a semiconductor chip 100 as a semiconductor device according to the first embodiment.

[0045] exist Figure 1 In the figure, the insulating film is made transparent for easy understanding. Figure 1 As shown, most of the surface of semiconductor chip 100 is covered by emitter electrode 1, and gate electrode 2 is formed on the periphery of emitter electrode 1. In addition, collector electrode 3 is formed on the back surface of semiconductor chip 100. Emitter potential is supplied to emitter electrode 1. Gate potential is supplied to gate electrode 2.

[0046] Figure 2A is a plan view of a main portion of the semiconductor chip 100 according to the first embodiment, Figure 1 By the way, for the sake of clarity, Figure 2A The case where the interlayer insulating film is transparent is shown. Figure 2B It is along Figure 2A Cross-sectional view of line AA'.

[0047] The semiconductor chip 100 according to the first embodiment is a GE-S type (GE type shrink structure) IGBT, which is a type of IE type IGBT. Figure 2A 、 2BAs shown, a semiconductor chip 100 is formed on a semiconductor substrate and includes an emitter electrode 1, a collector electrode 3, a p+-type collector layer 16, an n+-type field stop layer 17, and an n--type drift layer 18. Semiconductor chip 100 also includes a gate potential trench electrode (hereinafter referred to as a gate potential trench, or also referred to as a gate potential trench gate electrode) 10 to which a gate potential is supplied, and an emitter potential trench electrode (hereinafter referred to as an emitter potential trench, or also referred to as an emitter potential trench gate electrode) 11 to which an emitter potential is supplied. A high-concentration n+-type hole blocking layer 19 is formed between gate potential trench 10 and emitter potential trench 11. The region formed by gate potential trench 10, emitter potential trench 11, and hole blocking layer 19 is an active cell region. A p+ (first conductivity type) floating layer 12 (inactive cell region) is formed between the two active cell regions.

[0048] The emitter electrode 1 is coupled to the emitter potential trench 11 via a contact hole. The emitter electrode 1 is coupled to the p+ type body layer 24 through the contact hole and the body contact. Between the gate potential trench 10 and the contact hole of the emitter electrode 1, an n+ type emitter layer 22 and a p+ type base layer 23 are formed. Incidentally, Figure 2A Reference numeral 15 denotes a body contact Si (silicon) groove. Figure 2B Reference numeral 20 denotes a gate insulating film, and reference numeral 21 denotes an interlayer insulating film.

[0049] Next, the floating separation layer and the floating layer control gate (FC-GATE) which are the features of the first embodiment will be described. Figure 2A As shown, the gate potential trench 10 has an L-shape (first shape) having a straight portion extending in the Y-axis direction (first direction) and a curved portion extending in the X-axis direction (second direction), serving as a first trench electrode (first gate potential trench electrode). Furthermore, the gate potential trench 10 has a line-symmetrical shape (second shape) with respect to the first shape about a line parallel to the X-axis, serving as a second trench electrode (second gate potential trench electrode). A floating separation layer 13 is formed in the region sandwiched between the first and second shapes of the gate potential trench 10. Furthermore, an FC-GATE 14 is formed to cover both curved portions of the gate potential trench 10 and the floating separation layer 13.

[0050] Figure 3 is used to explain in more detail. Figure 3 It is along Figure 2A Cross-sectional view of line BB'. Figure 4 It is along Figure 2A1 . A cross-sectional view taken along line CC' of FIG. An n+ type (second conductivity type) floating separation layer 13 is formed between the p+ type floating layer 12 and the p+ type body layer 24. The FC-GATE 14 is formed to cover the floating separation layer 13, a portion of the floating layer 12, and a portion of the body layer 24. The FC-GATE 14 is polycrystalline silicon (Poly-Si) and is formed simultaneously with the gate (Poly-Si) connected to the gate potential trench 10 and is connected to the gate. In order to suppress an increase in the number of manufacturing steps, it is desirable to form the floating separation layer 13 and the hole blocking layer 19 at the same time. Alternatively, in order to adjust the impurity concentration of the floating separation layer 13, the floating separation layer 13 can be formed separately from the hole blocking layer 19.

[0051] Next, the operation of the semiconductor chip 100 according to the first embodiment will be described. Incidentally, since the basic operation of the IGBT except the floating layer 12, the floating separation layer 13 and the FC-GATE 14 is the same as the conventional operation, the basic operation description of the IGBT will be omitted. Therefore, here, reference will be made to Figures 5 to 7 The floating layer 12, the floating separation layer 13, and the FC-GATE 14 are described.

[0052] Figure 5 The figure shows a case where the gate is turned off, that is, a negative voltage (e.g., -15V) is applied to the gate electrode. When a negative voltage is applied to the gate electrode, a negative voltage is also applied to the FC-GATE 14. When a negative voltage is applied to the FC-GATE 14, holes in the floating separation layer 13 are pulled toward the FC-GATE 14 to generate an inversion layer 25 ( Figure 6 ). When the inversion layer 25 is formed, the floating layer 12 and the body layer 24 become conductive, and the carriers (holes) in the floating layer 12 are discharged to the emitter electrode 1 through the body layer 24. As a result, when the gate is turned off, the floating layer 12 is used to continue discharging the carriers (holes), and the following function (carrier discharge suppression function) is disabled: suppressing the path for the carriers (holes) to be discharged to the emitter electrode.

[0053] Next, we will refer to Figure 7 The following describes a case where the gate is on. When the gate is on, a positive voltage (e.g., +15V) is applied to the gate. When a positive voltage is applied to the gate, a positive voltage is also applied to FC-GATE 14. If a positive voltage is applied to FC-GATE 14, inversion layer 25 is not generated. Therefore, the carrier discharge suppression function of floating layer 12 is activated, and the IE effect can be achieved. Furthermore, when a positive voltage is applied to FC-GATE 14, electrons are attracted to the surface of floating separation layer 13. Since floating layer 12 is further separated from emitter electrode 1, the IE effect can be further enhanced.

[0054] So far, the region 4 in Figure 1 has been described. Here, another region of the semiconductor chip 100 will be described.

[0055] Figure 8A is an enlarged view of a region wider than the region 4 in Figure 1 . As shown in Figure 2A and Figure 8A , the semiconductor chip 100 forms an active unit region and a passive unit region (floating layer 12) adjacent to the active unit region, and the active unit region extends in the Y-axis direction. Then, in the first embodiment, as described above, the gate potential trench 10 is bent in the X-axis direction to form the floating separation layer 13 and the FC-GATE 14. If the portion covered by the FC-GATE 14 is called the FC-GATE region, then a plurality of FC-GATE regions are arranged. For example, as shown in Figure 8A , the FC-GATE regions are arranged at an interval of d1 in the Y-axis direction.

[0056] Here, the active unit region and the terminal region will be described. A p+-type unit peripheral junction region and a terminal region are provided outside the active unit region (the peripheral portion of the semiconductor chip 100) to surround the active unit region (both not shown). Since these regions (referred to as end regions) are passive unit regions and there is no hole discharge path, current concentrates in the region adjacent to the terminal region in the active unit region, which may cause component breakdown, etc. Therefore, in the first embodiment, in order to relieve current concentration, the arrangement density of the FC-GATE 14 is increased in the region adjacent to the terminal region in the active unit region.

[0057] Figure 8B is an enlarged view of the region 5 in Figure 1 , where the active unit region is adjacent to the terminal region. As shown in Figure 8B , the FC-GATE regions are arranged at an interval of d2 in the Y-axis direction. Where d2 < d1. That is, the arrangement density of the FC-GATE 14 in the active unit region adjacent to the terminal region of the semiconductor chip 100 > the arrangement density of the FC-GATE 14 in the active unit region at the center of the semiconductor chip 100.

[0058] As described above, in the semiconductor chip 100 according to the first embodiment, the floating separation layer 13 is provided between the floating layer 12 and the body layer 24. In addition, the FC-GATE 14 is provided above the floating layer, so that the function of the floating layer 12 can be controlled. As a result, both an improvement in the IE effect and a reduction in the switching loss (Eoff) during turn-off can be achieved.

[0059] Here, this effect will be illustrated through simulation results. Figure 9 ” shows the collector voltage and collector current when the gate of the IGBT is turned off. “New (V)” shows the collector voltage in the IGBT in the case where the first embodiment is applied. “New (A)” shows the collector current in the IGBT in the case where the first embodiment is applied. “Conventional (V)” shows the collector voltage of a conventional IGBT. “Conventional (A)” shows the collector current of a conventional IGBT. Figure 9 As shown, the rise of "new (V)" is earlier than that of "normal (V)". The fall of "new (A)" is earlier than that of "normal (A)". In other words, it can be understood that the shut-off speed is improved.

[0060] First Modification Example

[0061] Figure 10A is a plan view of a main portion of a semiconductor chip according to a first modified example of the first embodiment, and is Figure 1 Magnified view of area 4. Figure 10B It is along Figure 10A Cross-sectional view of line D-D'.

[0062] The difference from the first embodiment lies in the form of the gate potential trench 10a. Figure 10A As shown, the gate potential trench 10a of the first modified example has a shape having a straight portion extending in the Y-axis direction and a U-shaped curved portion extending in the X-axis direction, referred to as a P-shape (third shape), serving as a first trench electrode (first gate potential trench electrode). The P-shape curves from a first point in the straight portion in the X-axis direction, further curves in the Y-axis direction, further curves in the X-axis direction, and then returns to a second point in the straight portion. Furthermore, the gate potential trench 10a has a line-symmetrical shape (fourth shape) about a line parallel to the X-axis with respect to the first shape, serving as a second trench electrode (second gate potential trench electrode). A floating separation layer 13a is formed in the region sandwiched between the third and fourth shapes of the gate potential trench 10a. Furthermore, an FC-GATE 14a is formed to cover both curved portions of the gate potential trench 10a and the floating separation layer 13a.

[0063] Along Figure 10A The cross-sectional view of E-E' is similar to Figure 3 Cross-sectional view of . Figure 11 It is along Figure 10A10a. A cross-sectional view taken along line F-F' of FIG. An n+ type floating separation layer 13a is formed between the p+ type floating layer 12 and the p+ type body layer 24. An FC-GATE 14a is formed to cover the floating separation layer 13a, a portion of the floating layer 12, and a portion of the body layer 24. The FC-GATE 14a is polycrystalline silicon, formed simultaneously with the Poly-Si of the gate potential trench 10a, and connected to the gate electrode. In order to suppress an increase in the number of manufacturing steps, it is desirable to form the floating separation layer 13a and the hole blocking layer 19 simultaneously. Alternatively, in order to adjust the impurity concentration of the floating separation layer 13a, the floating separation layer 13a can be formed separately from the hole blocking layer 19.

[0064] The operation of the semiconductor chip according to the first modified example is the same as that of the first embodiment, and therefore a description thereof is omitted.

[0065] As described above, according to the semiconductor chip of the first modified example, similarly to the first embodiment, both the improvement of the IE effect and the reduction of the switching loss (Eoff) at the time of turn-off can be achieved.

[0066] In addition, in the semiconductor chip according to the first modified example, compared with the semiconductor chip 100, due to the increase in the number of grooves extending in the X-axis direction, an electric field relaxation effect can be exerted on the grooves. Due to the structure of the IGBT, a high electric field is generated at the bottom of the groove. By increasing the number of grooves, the electric field applied by each groove can be reduced. As a secondary effect, the hole discharge effect can be enhanced. When a high electric field is applied to the bottom of the groove, hot holes are generated. Hot holes can have an adverse effect on the groove and have an adverse effect on gate reliability. When the high electric field on the groove is relaxed, the adverse effect of hot holes can be reduced.

[0067] Second Modification Example

[0068] Figure 12 1 is a cross-sectional view of a main portion of a semiconductor chip according to a second modified example of the first embodiment. The second modified example is based on the first modified example.

[0069] The difference from the first modified example lies in the gate potential trench 10a and the p+ type diffusion layer 26. In the second modified example, the distance between the two gate potential trenches 10a in contact with the floating separation layer 13a is narrowed compared to FIG10 (the mesa width is narrowed). In other words, the distance between the two gate potential trenches 10a in contact with the floating separation layer 13a is narrower than the distance between the gate potential trench 10a in contact with the floating separation layer 13a and the gate potential trench 10a not in contact with the floating separation layer 13a. In other words, the distance between the curved portion of the first gate potential trench electrode and the curved portion of the second gate potential trench electrode is shorter than the distance between the first and second points of the straight portion. The p+ type diffusion layer 26 is formed on the floating separation layer 13a.

[0070] The basic operation of the semiconductor chip according to the second modified example is the same as that of the first modified example, but the voltage applied to the FC-GATE is different. First, the gate-off case will be described. Because the p+-type diffusion layer 26 is formed between the two gate potential trenches 10a, even if a negative voltage (-15V) is not applied to the FC-GATE 14a, the floating layer 12 (p+-type), the floating separation layer (p+-type), and the body layer 24 (p+-type) will remain conductive (normally on). Therefore, even when the gate-off voltage is, for example, 0V, carriers (holes) will be discharged from the floating layer 12 to the emitter electrode 1.

[0071] Next, we will describe the case where the gate is turned on. A p+-type diffusion layer 26 exists between the two gate potential trenches 10a. As the distance between the two gate potential trenches 10a narrows, the diffusion layer 26 is easily depleted. Therefore, by applying a positive voltage (e.g., +15V) to the gate electrode, a depletion layer forms in the diffusion layer 26, and no conduction is established between the floating layer 12 and the bulk layer 24. Consequently, the carrier discharge suppression function of the floating layer 12 is activated.

[0072] As described above, the semiconductor chip according to the second modified example has the following effect, in addition to the effect of the first modified example: when the gate is turned off, a negative voltage is not required. For example, the second modified example is effective for IGBTs that perform gate drive at 0-15V. Although the second modified example has been described based on the first modified example, the second modified example is also applicable to the first embodiment.

[0073] Third Modification Example

[0074] Figure 13 1 is a cross-sectional view of a main portion of a semiconductor chip according to a third modified example of the first embodiment. The third modified example is based on the second modified example.

[0075] The difference from the second modified example is the addition of an n+ type diffusion layer 27. In this third modified example, the n+ type diffusion layer 27 is formed on the p+ type diffusion layer 26. As in the second modified example, when the p+ type diffusion layer 26 is formed, the p concentration at the surface of the diffusion layer 26 tends to increase depending on the process. If the p concentration at the surface of the diffusion layer 26 becomes higher than expected, depletion is less likely to occur. Therefore, in this third modified example, the n+ type diffusion layer 27 is formed on the diffusion layer 26 to eliminate this phenomenon.

[0076] In this third modified example, the same effects as those of the second modified example can be achieved. Furthermore, since n+ type layers (diffusion layer 27 and floating separation layer 13a) are formed above and below p+ type diffusion layer 26, depletion is promoted from above and below when hole current passes through. As a result, the ability to isolate floating layer 12 is improved. Furthermore, as described above, since depletion is more readily achieved than in the second modified example, the distance between the two gate potential trenches 10a can be wider than in the second modified example.

[0077] Fourth Modification Example

[0078] Figure 14 is a cross-sectional view of a main portion of a semiconductor chip according to a fourth modified example of the first embodiment. Figure 14 It is along Figure 2A Cross-sectional view of line BB'.

[0079] The difference from the first embodiment is the floating separation layer 13d. Figure 14 As shown, the floating separation layer 13d of the fourth modified example is formed in the entire region of the lower layer of the body layer 24. Figure 3 ), the discharge of carriers (holes) from the body layer 24 can be further suppressed.

[0080] The semiconductor chip according to the fourth modification example can further improve the IE effect compared to the semiconductor chip of the first embodiment.

[0081] Second embodiment

[0082] Figure 15A is a plan view of a main portion of a semiconductor chip according to a second embodiment, and is Figure 1 Magnified view of area 4 in FIG. Figure 15B It is along Figure 15A Cross-sectional view of line G-G'.

[0083] The difference from the first embodiment lies in the forms of the gate potential trench 210, the emitter potential trench 211, the floating separation layer 213 and the FC-GATE 214. Figure 15AAs shown, the gate potential trench 210 has a shape (fifth shape) having a straight portion extending in the Y-axis direction and a U-shaped curved portion extending in the X-axis direction. The emitter potential trench 211 has a shape (sixth shape) having a straight portion extending in the Y-axis direction and a U-shaped curved portion extending in the X-axis direction, referred to as a P-shape, serving as a first trench electrode (first emitter potential trench electrode). This P-shape bends from a first point in the straight portion in the X-axis direction, further bends in the Y-axis direction, further bends in the X-axis direction, and then returns to a second point in the straight portion. In addition, the emitter potential trench 211 has a line-symmetrical shape (seventh shape) with respect to a line parallel to the X-axis in the sixth shape, serving as a second trench electrode (second emitter potential trench electrode). The fifth shape is provided between the sixth and seventh shapes.

[0084] A floating separation layer 213 is formed in the region sandwiched between the fifth and sixth shapes. A floating separation layer 213 is also formed in the region sandwiched between the fifth and seventh shapes. FC-GATE 214 is formed to cover the curved portion of the gate potential trench 210 and the floating separation layer 213.

[0085] The operation of the semiconductor chip according to the second embodiment is the same as that of the first embodiment, but the discharge path of carriers (holes) is different. In this second embodiment, carriers are discharged in sequence through the floating layer 12, the floating separation layer 213, the body layer 24 formed on the emitter potential trench 211, and the emitter electrode 1.

[0086] As described above, in the semiconductor chip according to the second embodiment, similar to the first embodiment, the following two can be achieved: improvement of the IE effect and reduction of the switching loss (Eoff) at turn-off. In addition, the advantage of the second embodiment is that the gate capacitance can be reduced. For example, in the first modified example, as described above, the gate potential trench 10a has a third shape and a fourth shape. The third shape and the fourth shape are factors that increase the gate capacitance of the gate potential trench 10a. On the other hand, in the second embodiment, only the fifth shape contributes to the gate capacitance. Therefore, compared with the first modified example, the gate capacitance of the second embodiment is reduced. Smaller gate capacitance makes the switching speed of the IGBT faster.

[0087] Fifth Modification Example

[0088] Figure 16A is a plan view of a main portion of a semiconductor chip according to a fifth modified example of the second embodiment, and is Figure 1 Magnified view of area 4 in FIG. Figure 16B It is along Figure 16A H-H' cross-sectional view.

[0089] The difference from the second embodiment lies in the shapes of the gate potential trench 210a, the floating separation layer 213a and the FC-GATE 214a. Figure 16A As shown, the gate potential trench 210a is formed of a straight line portion extending in the Y-axis direction and does not have the U-shaped bend portion of the second embodiment. Similar to the second embodiment, the emitter potential trench 211a forms a first trench electrode (first emitter potential trench electrode) and a second trench electrode (second emitter potential trench electrode) having the sixth and seventh shapes.

[0090] A floating separation layer 213a is formed in a region sandwiched between the sixth shape and the seventh shape of the emitter potential trench 211a. An FC-GATE 214a is formed to cover the floating separation layer 213a.

[0091] The operation of the semiconductor chip according to the fifth modified example is the same as that of the semiconductor chip of the second embodiment. A discharge path for carriers (holes) is formed in the following order: a floating layer 12, a floating separation layer 213a, a body layer 24 formed on the emitter potential trench 211 side, and an emitter electrode 1.

[0092] As described above, the semiconductor chip according to the fifth modification example can achieve the same effects as the semiconductor chip of the second embodiment. In addition, since the gate potential trench 210a has no curved portion in the X-axis direction, the gate emitter electrode capacitance can be reduced and the switching speed of the IGBT can be increased.

[0093] Sixth Modification Example

[0094] Figure 17A is a plan view of a main portion of a semiconductor chip according to a sixth modified example of the second embodiment, and is Figure 1 Magnified view of area 4 in FIG. Figure 17B It is along Figure 17A Cross-sectional view of I-I'.

[0095] The difference from the fifth modification example lies in the forms of the emitter potential trench 211b, the floating separation layer 213b, and the FC-GATE 214b. Figure 17A As shown, the emitter potential trench 211b has a shape having a straight portion extending in the Y-axis direction and a P-shaped curved portion extending in the X-axis direction (eighth shape), serving as a first trench electrode (first emitter potential trench). The P-shaped portion bends from the straight portion in the X-axis direction, further bends in the Y-axis direction from a first point in the curved portion, further bends in the X-axis direction, and then returns to a second point in the curved portion. Furthermore, the emitter potential trench 211b has a line-symmetric shape (ninth shape) with respect to a line parallel to the X-axis, similar to the eighth shape, serving as a second trench electrode (second emitter potential trench electrode).

[0096] The floating separation layer 213b is formed in a region sandwiched between the eighth shape and the ninth shape. The FC-GATE 214b is formed to cover the emitter potential trench 211b and the bent portion of the floating separation layer 214b.

[0097] The operation of the semiconductor chip according to the sixth modification example is the same as that of the semiconductor chip of the second embodiment. Carriers (holes) are discharged through the floating layer 12, the floating separation layer 213b, the body layer 24 formed on the emitter potential trench 211 side, and the emitter electrode 1.

[0098] As described above, the semiconductor chip according to the sixth modified example can achieve the same effects as those of the semiconductor chip of the second embodiment.

[0099] Third embodiment

[0100] Figure 18 3 is a plan view of a semiconductor chip 300 according to the third embodiment. Although the GE-S type IGBT has been described in the first and second embodiments, Figure 18 A GGEE type IGBT is shown.

[0101] like Figure 18 As shown, the semiconductor chip 300 has a gate potential trench 310 extending on the Y axis, an emitter potential trench 311, a floating layer 312 of a first conductivity type, a floating separation layer 313 of a second conductivity type, an FC-GATE 314, and a contact 315 for providing an emitter potential to the emitter potential trench 311.

[0102] The third embodiment is characterized by the floating separation layer 313 and the FC-GATE 314 as described in the first and second embodiments. Here, the floating separation layer 313 and the FC-GATE 314 will be described in detail.

[0103] A floating separation layer 313 is formed in a region sandwiched between the two emitter potential trenches 311. Specifically, the floating separation layer 313 is formed between a first emitter potential trench electrode, which serves as a first trench electrode, and a second emitter potential trench electrode, which serves as a second trench electrode. An FC-GATE 314 is formed to cover the floating separation layer 313. Incidentally, similar to the first and second embodiments, the FC-GATE 314 is connected to the gate electrode to provide a gate potential.

[0104] The operation of the semiconductor chip 300 according to the third embodiment is the same as that of the first and second embodiments, but the discharge path of the carriers (holes) is different. In the third embodiment, the carriers are discharged to the emitter electrode 1 through the floating layer 312, the floating separation layer 313, the body layer (not shown) and the contact 315.

[0105] As described above, in the semiconductor chip 300 according to the third embodiment, even in a GGEE type IGBT, which is a type of IE type IGBT, similar to the first and second embodiments, both the IE effect is improved and the switching loss during turn-off (Eoff) is reduced. Although the present application has been described with respect to the GE-S type and the GGEE type, the present invention is not limited thereto. It is also applicable to other types of IE type IGBTs, such as the EGE type.

[0106] Fourth embodiment

[0107] Figure 19A is a plan view of a main portion of a semiconductor chip according to a fourth embodiment, and is Figure 1 Magnified view of area 4 in FIG. Figure 19B It is along Figure 19A J-J' cross-sectional view.

[0108] In the first to third embodiments, FC-GATE is connected to the gate electrode and controlled by the gate potential. In the fourth embodiment, FC-GATE is independently controlled instead of being controlled by the gate potential. Figure 19A As shown, similar to the second embodiment ( Figure 15A ), the fourth embodiment has emitter potential trenches 411 of sixth and seventh shapes. Specifically, emitter potential trenches 411 have the first emitter potential trench electrode as the first trench electrode and the second emitter potential trench electrode as the second trench electrode. Furthermore, gate potential trenches 410 are formed of linear portions extending in the Y-axis direction. An independent trench 427, separate from gate potential trenches 410, is provided between the sixth and seventh shapes.

[0109] A floating separation layer 413 is formed in a region sandwiched between the sixth shape and the independent trench 427. A floating separation layer 413 is also formed in a region sandwiched between the seventh shape and the independent trench 427. An FC-GATE 414 is formed to cover the independent trench 427 and the floating separation layer 413. The FC-GATE 414 is connected to an FC-GATE terminal provided separately from the gate electrode 2 (not shown) using, for example, Poly-Si.

[0110] The basic operation of the semiconductor chip according to the fourth embodiment is similar to that of the second embodiment, but FC-GATE 414 can be controlled independently rather than by gate potential. For example, for an IGBT in which +15V is applied to the gate when the gate is on and 0V is applied to the gate when the gate is off, +15V can be applied to FC-GATE 414 when the gate is on, and -15V can be applied to FC-GATE 414 when the gate is off. Thus, the same effects as those described in the first and second embodiments can be achieved. Alternatively, for an IGBT in which +15V is applied to the gate when the gate is on and -15V is applied to the gate when the gate is off, +30V can be applied to FC-GATE 414 when the gate is on, and -30V can be applied to FC-GATE 414 when the gate is off. As a result, the controllability of the inversion layer of the floating separation layer 413 is further improved. Alternatively, the gate on / off timing and the FC-GATE on / off timing can be varied. For example, by turning on the FC-GATE 414 (applying a voltage that forms an inversion layer) earlier than the gate off timing, the carrier discharge suppression function takes effect more quickly. Consequently, switching losses during the turn-off (Eoff) period can be further reduced.

[0111] As described above, in the semiconductor chip according to the fourth embodiment, similar to the first embodiment, both the improvement of IE effect and the reduction of switching loss (Eoff) at turn-off can be achieved. In addition, the flexibility of controlling the floating separation layer 413 can be increased.

[0112] It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist thereof.

Claims

1. A semiconductor device comprising: semiconductor substrates; A first trench electrode and a second trench electrode are formed in the semiconductor substrate; A floating layer of a first conductivity type is formed around the first trench electrode and the second trench electrode; a floating separation layer of a second conductivity type, formed between the first trench electrode and the second trench electrode and in contact with the floating layer of the first conductivity type; as well as A floating layer control gate is disposed above the floating separation layer and a portion of the floating layer. The first conductivity type is opposite to the second conductivity type.

2. The semiconductor device according to claim 1, further comprising: a gate electrode supplied with a gate potential; as well as The emitter electrode is supplied with an emitter potential. wherein the first trench electrode and the second trench electrode are a first gate potential trench electrode and a second gate potential trench electrode to which the gate potential is supplied, and wherein the floating separation layer of the second conductivity type is coupled to the emitter electrode via a contact.

3. The semiconductor device according to claim 2, wherein the first gate potential trench electrode has a linear portion and a curved portion, the linear portion extending in a first direction in a plan view, the curved portion extending in a second direction, and The second gate potential trench electrode is line-symmetrical to the first gate potential trench electrode with respect to a line parallel to the second direction.

4. The semiconductor device according to claim 3, The floating separation layer of the second conductivity type is provided between a bent portion of the first gate potential trench electrode and a bent portion of the second gate potential trench electrode.

5. The semiconductor device according to claim 4, The curved portion extending in the second direction has a shape that curves from the linear portion along the second direction and returns to the linear portion.

6. The semiconductor device according to claim 1, further comprising: a gate electrode supplied with a gate potential; as well as The emitter electrode is supplied with an emitter potential. wherein the first trench electrode and the second trench electrode are a first emitter potential trench electrode and a second emitter potential trench electrode to which the emitter potential is supplied, and wherein the floating separation layer of the second conductivity type is coupled to the emitter electrode via a contact.

7. The semiconductor device according to claim 6, wherein the first emitter potential trench electrode has a linear portion and a curved portion, the linear portion extending in a first direction in a plan view, the curved portion extending in a second direction, and The second emitter potential trench electrode is line-symmetrical to the first emitter potential trench electrode with respect to a line parallel to the second direction.

8. The semiconductor device according to claim 7, The floating separation layer of the second conductivity type is provided between a bent portion of the first emitter potential trench electrode and a bent portion of the second emitter potential trench electrode.

9. The semiconductor device according to claim 8, The curved portion extending in the second direction has a shape that curves from the linear portion along the second direction and returns to the linear portion.

10. The semiconductor device according to claim 8, The bent portion extending in the second direction has a shape that further bends along the first direction and returns to the bent portion extending in the second direction.

11. The semiconductor device according to claim 7, further comprising: a gate potential trench electrode to which the gate potential is supplied, wherein the gate potential trench electrode is provided in a region sandwiched between the first emitter potential trench electrode and the second emitter potential trench electrode, and The floating separation layer of the second conductivity type is provided between the bent portion of the first emitter potential trench electrode and the gate potential trench electrode, and between the bent portion of the second emitter potential trench electrode and the gate potential trench electrode.

12. The semiconductor device according to claim 11, wherein the gate potential trench electrode has a linear portion extending in the first direction, and has a shape that bends from the linear portion along the second direction and returns to the linear portion.

13. The semiconductor device according to claim 4, wherein the curved portion extending in the second direction has a shape that curves from a first point of the linear portion along the second direction and returns to a second point of the linear portion, and The distance between the first point and the second point is longer than the distance between the bent portion of the first gate potential trench electrode and the bent portion of the second gate potential trench electrode.

14. The semiconductor device according to claim 13, further comprising: The diffusion layer of the first conductivity type is provided on the floating separation layer of the second conductivity type.

15. The semiconductor device according to claim 14, further comprising: The second conductive type diffusion layer is provided on the first conductive type diffusion layer.

16. The semiconductor device according to claim 2, further comprising: The first conductive type body layer is coupled to the emitter electrode through the contact member, The floating separation layer of the second conductivity type is formed to cover the body layer of the first conductivity type.

17. The semiconductor device according to claim 1, further comprising: an active cell region formed in the semiconductor substrate; as well as a terminal region formed to surround the active cell region, wherein a plurality of regions are arranged in the active cell region, the first trench electrode and the second trench electrode, the floating separation layer of the second conductivity type, and the floating layer control gate are formed in each of the plurality of regions, and The arrangement density of the regions in the central portion of the active cell region is lower than the arrangement density of the regions near the terminal region.

18. The semiconductor device according to claim 2, wherein the floating layer control gate is coupled to the gate electrode.

19. The semiconductor device according to claim 1, The semiconductor device is an IE type IGBT.

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