Display device and display device detection method

Abstract

Provided are a display device and a detection method thereof. The display device includes: a display panel; a first substrate attached to one side of the display panel; and a second substrate attached to one side of the first substrate, wherein the display panel includes a first panel test pad and a second panel test pad, and the first substrate includes: a 1-1 circuit test lead overlapping with and connected to the first panel test pad; a 1-2 circuit test lead overlapping with and connected to the second panel test pad; a 2-1 circuit test lead overlapping with and connected to the second substrate; a 1-1 test lead-out line connected to the 1-1 circuit test lead; a 1-2 test lead-out line connected to the 1-2 circuit test lead; and a first test lead-out line connected to the 2-1 circuit test lead, with the 1-1 test lead-out line and the 1-2 test lead-out line connected to the first test lead-out line.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0149956 filed on November 20, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present invention relates to a display device and a detection method thereof. Background Art

[0003] A display device is a device configured to present information in a visual form. Such a display device includes a substrate divided into a display area and a non-display area. In the display area, a plurality of pixels are provided on the substrate, and in the non-display area, a plurality of pads (also referred to as pads or pads), peripheral circuits, etc. are provided on the substrate. A flexible film (e.g., a chip on film (COF)) on which a drive circuit, etc. is mounted can be bonded to the plurality of pads to transmit a drive signal to the pixels.

[0004] The flexible film may include a plurality of leads bonded to a plurality of pads, and each of the leads may be bonded to a separate pad.

[0005] The contact resistance between the pad and the lead can be measured by measuring the contact resistance between the detection pad located on the same layer as the pad and the detection lead located on the same layer as the lead. In other words, the contact resistance between the detection pad and the detection lead can correspond to the contact resistance between the pad and the lead. Summary of the Invention

[0006] According to an exemplary embodiment of the present invention, a display device may include: a display panel; a first substrate attached to one side of the display panel; and a second substrate attached to one side of the first substrate, wherein the display panel includes a first panel test pad and a second panel test pad, and the first substrate includes: a 1-1 circuit test lead overlapping with the first panel test pad and connected to the first panel test pad; a 1-2 circuit test lead overlapping with the second panel test pad and connected to the second panel test pad; a 2-1 circuit test lead overlapping with the second substrate and connected to the second substrate; a 1-1 test lead connected to the 1-1 circuit test lead; a 1-2 test lead connected to the 1-2 circuit test lead; and a first test lead connected to the 2-1 circuit test lead, and the 1-1 test lead and the 1-2 test lead are connected to the first test lead.

[0007] The second substrate may include: a first main test pad overlapping with and connected to the 2-1 circuit test lead; and a first test point connected to the first main test pad.

[0008] The first panel test pad and the second panel test pad may be electrically connected to each other through a first panel test line, a second panel test line, and a panel common test line connecting the first panel test line and the second panel test line.

[0009] The display panel may further include a third panel test pad and a third panel test line connected to the third panel test pad, and the third panel test line may be connected to the panel common test line.

[0010] The first substrate may further include: a 1-3 circuit test lead overlapping with and connected to the third panel test pad; and a 2-2 circuit test lead overlapping with and connected to the second substrate, and the 1-3 circuit test lead may be connected to the 2-2 circuit test lead.

[0011] The second substrate may further include: a second main test pad overlapping with and connected to the 2-2 circuit test lead; and a second test point connected to the second main test pad.

[0012] The display panel may further include a fourth panel test pad and a fourth panel test line connected to the fourth panel test pad; and the fourth panel test line may be connected to the panel common test line.

[0013] The first substrate may further include: a 1-4 circuit test lead overlapping with and connected to the fourth panel test pad; and a 2-3 circuit test lead and a 2-4 circuit test lead overlapping with and connected to the second substrate, and the 2-3 circuit test lead and the 2-4 circuit test lead may be connected to the 1-4 circuit test lead.

[0014] The second substrate may further include: a third main test pad overlapping with and connected to the 2-3 circuit test lead; and a fourth main test pad overlapping with and connected to the 2-4 circuit test lead, and the third main test pad and the fourth main test pad may be connected to a third test point.

[0015] The first substrate may also include a first test lead physically connected to the 2-1 circuit test lead, a 1-1 test lead physically connected to the 1-1 circuit test lead, and a 1-2 test lead physically connected to the 1-2 circuit test lead; and the 1-1 test lead and the 1-2 test lead may be physically connected to the first test lead.

[0016] The first substrate may further include a second test lead configured to electrically connect the 1-3 circuit test lead and the 2-2 circuit test lead.

[0017] The first substrate may further include: a third test lead connected to the 1-4 circuit test lead; a 3-1 test lead connected to the 2-3 circuit test lead; and a 3-2 test lead connected to the 2-4 circuit test lead; and the 3-1 test lead and the 3-2 test lead may be connected to the third test lead.

[0018] The first substrate also includes a data drive integrated circuit; and all of the first panel test pad, the second panel test pad, the third panel test pad, the fourth panel test pad, the 1-1 circuit test lead, the 1-2 circuit test lead, the 1-3 circuit test lead, the 1-4 circuit test lead, the 2-1 circuit test lead, the 2-2 circuit test lead, the 2-3 circuit test lead, and the 2-4 circuit test lead, as well as the first main test pad, the second main test pad, the third main test pad, and the fourth main test pad are insulated from the data drive integrated circuit.

[0019] The 1-1 test lead can be physically connected to the 1-1 circuit test lead; the 1-2 test lead can be physically connected to the 1-2 circuit test lead; the first test lead can be physically connected to the 2-1 circuit test lead; and the 1-1 test lead and the 1-2 test lead can be physically connected to the first test lead.

[0020] According to an exemplary embodiment of the present invention, a display device may include: a display panel including a data driving integrated circuit; and a first substrate attached to one side of the display panel, wherein the display panel includes a first panel test pad and a second panel test pad, and the first substrate includes: a 1-1 circuit test lead overlapping with and connected to the first panel test pad; a 1-2 circuit test lead overlapping with and connected to the second panel test pad; and a first test point connected to the 1-1 circuit test lead and the 1-2 circuit test lead.

[0021] The display panel may further include a third panel test pad; and the first substrate may further include: a 1-3 circuit test lead overlapping and connected to the third panel test pad; and a second test point connected to the 1-3 circuit test lead.

[0022] The display panel may further include a fourth panel test pad; and the first substrate may further include: a 1-4 circuit test lead overlapping and connected to the fourth panel test pad; and a third test point connected to the 1-4 circuit test lead.

[0023] The first substrate may also include a first test lead, a 1-1 test lead and a 1-2 test lead; the first test lead may be connected to a first test point; the 1-1 test lead may be physically connected to the 1-1 circuit test lead; the 1-2 test lead may be physically connected to the 1-2 circuit test lead; and the 1-1 test lead and the 1-2 test lead may be physically connected to the first test lead.

[0024] According to an exemplary embodiment of the present invention, a detection method for a display device includes: providing a display device, the display device including: a display panel, including a first panel test pad, a second panel test pad, a third panel test pad, and a fourth panel test pad; a first substrate, including a 1-1 circuit test lead, a 1-2 circuit test lead, a 1-3 circuit test lead, a 1-4 circuit test lead, a 2-1 circuit test lead, a 2-2 circuit test lead, a 2-3 circuit test lead, and a 2-4 circuit test lead, wherein the 1-1 circuit test lead to the 1-4 circuit test lead are respectively connected to the first panel test pad to the fourth panel test pad; and a second substrate, including a first main test pad, a second main test pad, a third main test pad, and a fourth main test pad and a first test point, a second test point, and a third test point, the first main test pad to the fourth main test pad are respectively connected to the 2-1 circuit test lead to the 2-4 circuit test lead, the first test point is connected to the first main test pad, and the second test point is connected to the a second main test pad, and a third test point connected to the third main test pad and a fourth main test pad, wherein the 1-1 circuit test lead and the 1-2 circuit test lead are connected in parallel to the 2-1 circuit test lead, the 1-3 circuit test lead is connected to the 2-2 circuit test lead, and the 2-3 circuit test lead and the 2-4 circuit test lead are electrically connected to the 1-4 circuit test lead; contacting the fixture with the first test point and the second test point to obtain a first measurement value; contacting the fixture with the second test point and the third test point to obtain a second measurement value; contacting the fixture with the first test point and the third test point to obtain a third measurement value; and using the first measurement value, the second measurement value, and the third measurement value to determine the contact resistance between the first panel test pad and the 1-1 circuit test lead, the contact resistance between the second panel test pad and the 1-2 circuit test lead, the contact resistance between the third panel test pad and the 1-3 circuit test lead, and the contact resistance between the fourth panel test pad and the 1-4 circuit test lead.

[0025] When obtaining the first measurement value, the resistance of the fixture in contact with the first test point and the second test point is considered; when obtaining the second measurement value, the resistance of the fixture in contact with the second test point and the third test point is considered; and when obtaining the third measurement value, the resistance of the fixture in contact with the first test point and the third test point is considered.

[0026] The resistance value of the display panel can be removed from the steps of determining the contact resistance between the first panel test pad and the 1-1 circuit test lead, the contact resistance between the second panel test pad and the 1-2 circuit test lead, the contact resistance between the third panel test pad and the 1-3 circuit test lead, and the contact resistance between the fourth panel test pad and the 1-4 circuit test lead. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0028] Figure 1 is a plan layout diagram of a display device according to an exemplary embodiment of the present invention;

[0029] Figure 2 yes Figure 1 A planar layout diagram of the display panel;

[0030] Figure 3 yes Figure 1 A planar layout diagram of the first substrate in FIG;

[0031] Figure 4 yes Figure 1 A planar layout diagram of the second substrate in FIG;

[0032] Figure 5 yes Figure 1 A planar layout diagram of the panel pad area, the first substrate, and the second substrate;

[0033] Figure 6 yes Figure 5 A cross-sectional view of the panel pad, the first lead wire, the second lead wire and the circuit pad;

[0034] Figure 7 yes Figure 5 A cross-sectional view of the detection panel pad, the first detection lead wire, the second detection lead wire and the detection circuit pad;

[0035] Figure 8 is a cross-sectional view illustrating a state in which a voltage applied from a resistance measuring device is applied to a detection point through a jig according to an exemplary embodiment of the present invention;

[0036] Figure 9 is a schematic circuit diagram illustrating a case where first to third measurement values are obtained by a resistance measuring device according to an exemplary embodiment of the present invention;

[0037] Figure 10 is a plan layout diagram showing a situation in which a first measurement value is obtained;

[0038] Figure 11is a plan layout diagram showing a situation in which a second measurement value is obtained;

[0039] Figure 12 is a plan layout diagram showing a situation in which a third measurement value is obtained;

[0040] Figure 13 is a plan layout diagram of a display device according to another exemplary embodiment of the present invention;

[0041] Figure 14 yes Figure 13 A planar layout diagram of the display panel;

[0042] Figure 15 yes Figure 13 A planar layout diagram of the first substrate in FIG;

[0043] Figure 16 yes Figure 13 A planar layout diagram of the display panel and the first substrate;

[0044] Figure 17 is a plan layout diagram illustrating a case where a first measurement value is obtained according to an exemplary embodiment of the present invention;

[0045] Figure 18 is a plan layout diagram illustrating a case where a second measurement value is obtained according to an exemplary embodiment of the present invention;

[0046] Figure 19 is a plan layout diagram of a display panel according to another exemplary embodiment of the present invention;

[0047] Figure 20 is a plan layout diagram of a first substrate according to another exemplary embodiment of the present invention;

[0048] Figure 21 is a plan layout diagram of a second substrate according to another exemplary embodiment of the present invention;

[0049] Figure 22 is a plan layout diagram of a display device according to yet another exemplary embodiment of the present invention;

[0050] Figure 23 yes Figure 22 A planar layout diagram of the display panel;

[0051] Figure 24 yes Figure 22 A planar layout diagram of the first substrate in ; and

[0052] Figure 25 yes Figure 22 Layout diagram of the second substrate in FIG. DETAILED DESCRIPTION

[0053] The detailed structural and functional descriptions of the exemplary embodiments of the present invention disclosed herein are for illustrative purposes only. The present invention can be implemented in many different forms and is therefore not limited to the embodiments disclosed herein.

[0054] It will be understood that when an element is referred to as being associated with another element (such as being "coupled" or "connected" to another element), the element can be directly coupled or directly connected to the other element, or intervening elements may be present. Other expressions explaining the relationship between elements (such as "between," "directly between," "adjacent," or "directly adjacent") can be understood in a similar manner.

[0055] The same reference numerals may refer to the same or like parts throughout the specification.

[0056] As used herein, “a,” “an,” “the,” and “at least one of” are intended to include both the singular and the plural, unless the context clearly indicates otherwise.

[0057] Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

[0058] Figure 1 is a plan layout diagram of a display device according to an exemplary embodiment of the present invention.

[0059] The display device 1 is a device configured to display video or still images and can be used as a display screen for portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs). The display device 1 can also be used as a display screen for various other products such as televisions, notebooks, monitors, billboards, and IoT devices.

[0060] Reference Figure 1 , the display device 1 may include a display panel 100 configured to display an image, a first substrate 300 connected to the display panel 100 , and a second substrate 500 connected to the first substrate 300 .

[0061] For example, an organic light-emitting display panel may be applied as the display panel 100. In the following exemplary embodiments of the present invention, although an example in which an organic light-emitting display panel is applied as the display panel 100 is described, the present invention is not limited thereto. For example, various display panels such as a liquid crystal display (LCD) panel, a quantum dot organic light-emitting display (QD-OLED) panel, a quantum dot liquid crystal display (QD-LCD) panel, a quantum nanoluminescent display (QNED) panel, a micro LED panel, etc. may be applied.

[0062] The display panel 100 includes a display area DA including a plurality of pixel areas and a non-display area NDA disposed around the display area DA. The display area DA may have a rectangular shape in which all corners are right angles in plan view, or a rectangular shape in which all corners are rounded in plan view. The display area DA may have short sides and long sides. The short sides of the display area DA may be sides of the display area DA extending in the first direction DR1. The long sides of the display area DA may be sides of the display area DA extending in the second direction DR2. However, the planar shape of the display area DA is not limited to a rectangle and may have various other shapes, such as a circular shape or an elliptical shape. The non-display area NDA may be disposed adjacent to both short sides and both long sides of the display area DA. In this case, the non-display area NDA may surround all sides of the display area DA and constitute the edge of the display area DA. However, the present invention is not limited to this and the non-display area NDA may be disposed adjacent to only the two short sides of the display area DA or only the two long sides of the display area DA. Alternatively, the non-display area NDA may be disposed adjacent to only one short side and one long side of the display area DA.

[0063] The non-display area NDA of the display panel 100 further includes a panel pad area PA. The panel pad area PA may be, for example, disposed around one short side of the display area DA, but is not limited thereto. For example, the panel pad area PA may be disposed around two short sides of the display area DA, or around two short sides and two long sides of the display area DA.

[0064] The first substrate 300 may include a printed base film ( Figure 6 310 in the printing base film) and a driving integrated circuit 350 provided on the printing base film 310. The printing base film 310 may include an insulating flexible material. In some exemplary embodiments of the present invention, the first substrate 300 may be a flexible substrate.

[0065] The first substrate 300 may include a first circuit region, a second circuit region, and a third circuit region. One side of the first circuit region is attached to the panel pad area PA of the display panel 100. The second circuit region is arranged on one side of the first circuit region in the second direction DR2. The third circuit region is arranged on one side of the second circuit region in the second direction DR2, and the second substrate 500 is attached to the third circuit region. In other words, the first circuit region, the second circuit region, and the third circuit region may be sequentially arranged between the panel pad area PA and the second substrate 500. The driver integrated circuit 350 may be provided on one surface of the second circuit region of the first substrate 300. The driver integrated circuit 350 may be, for example, a data driver integrated circuit, and may be implemented as a data driver chip using a chip-on-film (COF) method.

[0066] The second substrate 500 may include a circuit pad region attached to the third circuit region of the first substrate 300. A plurality of circuit pads are provided in the circuit pad region of the second substrate 500 to be connected to lead wires provided in the third circuit region of the first substrate 300. The second substrate 500 may include a printed circuit board (PCB) Figure 6 510 in). The printed circuit board may be a flexible substrate including a flexible material, but is not limited thereto, and may be a rigid substrate including a rigid material.

[0067] The first substrate 300 may be curved in a thickness direction (eg, a rear direction in the case of a top-emission display device). The other side of the first substrate 300 and the second substrate 500 may be positioned on a lower portion of the display panel 100.

[0068] Figure 2 yes Figure 1 The floor plan of the display panel in Figure 3 yes Figure 1 The plan layout diagram of the first substrate, Figure 4 yes Figure 1 The plan layout of the second substrate in Figure 5 yes Figure 1 A planar layout diagram of the panel pad area, the first substrate and the second substrate, Figure 6 yes Figure 5 A cross-sectional view of the panel pad, the first lead wire, the second lead wire and the circuit pad in FIG. Figure 7 yes Figure 5 sectional view of the detection panel pad, the first detection lead-out line, the second detection lead-out line and the detection circuit pad.

[0069] Reference Figure 2, a panel pad P_PAD and a panel test pad (TP_PAD: TP_PAD1, TP_PAD2, TP_PAD3, and TP_PAD4) may be provided in the panel pad area PA. The panel pad P_PAD may be plural in number, and the plurality of panel pads P_PAD may be arranged along a first direction DR1. The plurality of panel pads P_PAD may include, for example, a power pad, a data pad, and a panel dummy pad. The first direction DR1 may be a direction from a first end of the panel pad area PA toward a second end of the panel pad area PA opposite to the first end. The second direction DR2 refers to a direction intersecting the first direction DR1.

[0070] The panel pad P_PAD can be electrically connected to the pixels. The panel pad P_PAD can be physically connected to the pixels of the display area DA via a first signal line L1. The first signal line L1 can be located on a different layer from the panel pad P_PAD, but is not limited thereto. For example, the first signal line L1 can be located on the same layer as the panel pad P_PAD.

[0071] The panel test pads TP_PAD1 to TP_PAD4 may be plural in number, and the plurality of panel test pads TP_PAD1 to TP_PAD4 may be arranged along the first direction DR1 .

[0072] Unlike the panel pad P_PAD, the panel test pads TP_PAD1 to TP_PAD4 are not electrically connected to the first signal line L1 and may not be physically connected to the first signal line L1.

[0073] The display panel 100 may include a first panel test line TP_L1 electrically connected to the first panel test pad TP_PAD1, a second panel test line TP_L2 electrically connected to the second panel test pad TP_PAD2, a third panel test line TP_L3 electrically connected to the third panel test pad TP_PAD3, and a fourth panel test line TP_L4 electrically connected to the fourth panel test pad TP_PAD4.

[0074] The first panel test line TP_L1 may be physically connected to the first panel test pad TP_PAD1, the second panel test line TP_L2 may be physically connected to the second panel test pad TP_PAD2, the third panel test line TP_L3 may be physically connected to the third panel test pad TP_PAD3, and the fourth panel test line TP_L4 may be physically connected to the fourth panel test pad TP_PAD4.

[0075] The panel test lines TP_L1 to TP_L4 may be electrically connected to each other. Figure 2As shown in , the display panel 100 may include a panel common test line TP_L5 physically connected to the panel test lines TP_L1 to TP_L4. The panel common test line TP_L5 may be electrically connected to the panel test pads TP_PAD1 to TP_PAD4 through the panel test lines TP_L1 to TP_L4. The panel common test line TP_L5 may be physically connected to the panel test lines TP_L1 to TP_L4, and therefore may be connected to the panel test pads TP_PAD1 to TP_PAD4. The panel test lines TP_L1 to TP_L4 may, for example, extend along the second direction DR2, and the panel common test line TP_L5 may extend along the first direction DR1, but the directions are not limited thereto. For example, the panel test lines TP_L1 to TP_L4 may extend from their corresponding panel test pads along the second direction DR2 to intersect and connect with the panel common test line TP_L5.

[0076] The panel test pads TP_PAD1 to TP_PAD4 may be dummy electrodes electrically isolated from the pixels of the display area DA.

[0077] Reference Figure 3 The first lead line LE1 and the first test lead line T_LEa may be disposed in the first circuit region of the first substrate 300 , the driving integrated circuit 350 may be disposed in the second circuit region, and the second lead line LE2 and the second test lead line T_LEb may be disposed in the third circuit region.

[0078] The first lead-out line LE1 may be electrically connected to the driving integrated circuit 350 through the second signal line L2 , and the second lead-out line LE2 may be electrically connected to the driving integrated circuit 350 through the third signal line L3 .

[0079] The first test lead T_LEa may be connected to the second test lead T_LEb but may be electrically insulated from the driver integrated circuit 350. The first test lead T_LEa and the second test lead T_LEb may be dummy electrodes that are electrically and physically insulated from the driver integrated circuit 350. In other words, the first test lead T_LEa and the second test lead T_LEb are not connected to the driver integrated circuit 350.

[0080] The first test lead T_LEa can include a 1-1 test lead (also called a circuit test lead) T_LE1, a 1-2 test lead T_LE2, a 1-3 test lead T_LE3, and a 1-4 test lead T_LE4, and the second test lead T_LEb can include a 2-1 test lead T_LE5, a 2-2 test lead T_LE6, a 2-3 test lead T_LE7, and a 2-4 test lead T_LE8.

[0081] The first substrate 300 may include a first test lead T_L1 physically connected to the 2-1 test lead T_LE5, a 1-1 test lead T_L11 physically connected to the 1-1 test lead T_LE1, and a 1-2 test lead T_L12 physically connected to the 1-2 test lead T_LE2. The 1-1 test lead T_L11 and the 1-2 test lead T_L12 may extend along the second direction DR2 and then be connected to the first test lead T_L1. In other words, the 1-1 test lead T_L11 and the 1-2 test lead T_L12 may be connected in parallel.

[0082] The first substrate 300 may include a second test lead line T_L2 configured to physically connect the 2-2 test lead T_LE6 and the 1-3 test lead T_LE3. The second test lead line T_L2 may electrically connect the 2-2 test lead T_LE6 and the 1-3 test lead T_LE3.

[0083] The first substrate 300 may include a third test lead T_L3 physically connected to the 1-4 test lead T_LE4, a 3-1 test lead T_L31 physically connected to the 2-3 test lead T_LE7, and a 3-2 test lead T_L32 physically connected to the 2-4 test lead T_LE8. The 3-1 test lead T_L31 and the 3-2 test lead T_L32 may be physically connected to the third test lead T_L3. The 3-1 test lead T_L31 and the 3-2 test lead T_L32 may be connected in parallel.

[0084] Reference Figure 4 The second substrate 500 may include a main circuit pad M_PAD and a main test pad TM_PAD. The main circuit pad M_PAD may be plural in number, and the plurality of main circuit pads M_PAD may be arranged along the first direction DR1. The main circuit pad M_PAD may be electrically connected to the main circuit unit 550. Since the main circuit pad M_PAD may be physically connected to the fourth signal line L4, and the main circuit unit 550 may be physically connected to the fourth signal line L4, the main circuit unit 550 and the main circuit pad M_PAD may be electrically connected to each other via the fourth signal line L4.

[0085] Unlike the main circuit pad M_PAD, the main test pad TM_PAD may be electrically insulated from the main circuit portion 550. In other words, the main test pad TM_PAD may be a dummy electrode and may not be connected to the main circuit portion 550.

[0086] The number of the main test pads TM_PAD may be plural, and the plural main test pads TM_PAD may include a first main test pad TM_PAD1 , a second main test pad TM_PAD2 , a third main test pad TM_PAD3 , and a fourth main test pad TM_PAD4 .

[0087] The second substrate 500 may include a first main test line TM_L1 physically connected to a first main test pad TM_PAD1, a second main test line TM_L2 physically connected to a second main test pad TM_PAD2, a 3-1 main test line TM_L31 physically connected to a third main test pad TM_PAD3, and a 3-2 main test line TM_L32 physically connected to a fourth main test pad TM_PAD4. Furthermore, the second substrate 500 may include a third main test line TM_L3 physically connected to the 3-1 main test line TM_L31 and the 3-2 main test line TM_L32.

[0088] The second substrate 500 may include a first test point TPO1 physically connected to the first main test line TM_L1, a second test point TPO2 physically connected to the second main test line TM_L2, and a third test point TPO3 physically connected to the third main test line TM_L3, the 3-1 main test line TM_L31, and the 3-2 main test line TM_L32. The test point TPOa may include the first to third test points TPO1 to TPO3.

[0089] Reference Figure 5 , the first circuit area of the first substrate 300 may be attached to the panel pad area PA, and the main circuit pad M_PAD and the main test pad TM_PAD of the second substrate 500 may be attached to the second circuit area.

[0090] For example, the first test lead line T_LEa may be disposed on the panel test pads TP_PAD1 to TP_PAD4 in an overlapping manner to be connected to the panel test pads TP_PAD1 to TP_PAD4. In addition, the first lead line LE1 may be disposed on the panel pad P_PAD in an overlapping manner to be connected to the panel pad P_PAD.

[0091] The second substrate 500 may be disposed in an overlapping manner under the second test lead T_LEb to be connected to the second test lead T_LEb, the main test pad TM_PAD may be disposed in an overlapping manner under the second test lead T_LEb to be connected to the second test lead T_LEb, and the main circuit pad M_PAD may be disposed in an overlapping manner under the second lead line LE2 to be connected to the second lead line LE2.

[0092] like Figure 6As shown in FIG, the first signal line L1 may be connected to the panel pad P_PAD on the base substrate 110 of the display panel 100, and the panel pad P_PAD and the first lead line LE1 may be electrically connected to each other via a first bonding member AM1. The first bonding member AM1 may include an anisotropic conductive film. In an exemplary embodiment of the present invention, the first bonding member AM1 may be omitted, and the first lead line LE1 and the panel pad P_PAD may be ultrasonically bonded.

[0093] The first lead wire LE1 can be electrically connected to the driver integrated circuit 350 via the second signal line L2, and the driver integrated circuit 350 can be electrically connected to the second lead wire LE2 via the third signal line L3. The second lead wire LE2 can be connected to the main circuit pad M_PAD via the second bonding member AM2. The second bonding member AM2 may include an anisotropic conductive film. In some exemplary embodiments of the present invention, the second bonding member AM2 may be omitted, and the second lead wire LE2 and the main circuit pad M_PAD may be ultrasonically bonded.

[0094] Reference Figure 7 The panel test pad TP_PAD and the first test lead T_LEa may be electrically connected through the third bonding member AM3. The third bonding member AM3 may have the same structure as the first bonding member AM1.

[0095] The main test pad TM_PAD and the second test lead T_LEb can be electrically connected through the fourth bonding member AM4. The fourth bonding member AM4 can have the same structure as the second bonding member AM2. The main test pad TM_PAD can be connected to the test points TPO1 to TPO3 respectively.

[0096] In the above-described embodiment, although an example is described in which the leads and wires provided on the printed base film 310 of the first substrate 300 are provided on one layer (e.g., the same layer), in some exemplary embodiments of the present invention, the first substrate 300 may include a conductive layer stacked on the printed base film 310. An insulating layer may be further provided between the conductive layers.

[0097] For example, the 1-1 test lead T_L11 connected to the 1-1 circuit test lead T_LE1 and the 1-2 test lead T_L12 connected to the 1-2 circuit test lead T_LE2 are arranged on a first layer, and the first test lead T_L1 connected to the 2-1 circuit test lead T_LE5 can be arranged on a second layer different from the first layer. In this case, the 1-1 test lead T_L11 and the 1-2 test lead T_L12 can be electrically connected to the first test lead T_L1 through a contact hole passing through the insulating layer.

[0098] In addition to the 1-1 test lead wire T_L11, 1-2 test lead wire T_L12 and first test lead wire T_L1 described above, the 3-1 test lead wire T_L31, 3-2 test lead wire T_L32 and third test lead wire T_L3 can be set on the first layer or the second layer described above, and the connection between them can be an electrical connection through a contact hole.

[0099] In the present embodiment, although an example in which the first substrate 300 has two conductive layers is described, the present invention is not limited thereto, and the first substrate 300 may have three or more conductive layers.

[0100] Figure 8 is a cross-sectional view illustrating a state in which a voltage applied from a resistance measuring device is applied to a detection point through a jig according to an exemplary embodiment of the present invention.

[0101] Reference Figure 8 , may include a resistance measuring device 700 (ART device) and a fixture 600 connected to the resistance measuring device 700. The resistance measuring device 700 may provide a predetermined input voltage to the test points (TPOa: TPO1 to TPO3) through the fixture 600.

[0102] The resistance measuring device 700 can provide an input voltage to one of the test points (TPOa: TPO1 to TPO3) through the fixture 600, and can measure an output voltage from another one of the test points (TPOa: TPO1 to TPO3) through the fixture 600. Figures 9 to 12 To describe the detailed description.

[0103] Figure 9 is a schematic circuit diagram illustrating a case where first to third measurement values are obtained by a resistance measuring device according to an exemplary embodiment of the present invention, Figure 10 is a plan layout diagram showing a situation in which a first measurement value is obtained, Figure 11 is a plan layout diagram showing a situation in which a second measurement value is obtained, Figure 12 is a plan layout diagram showing a situation in which a third measurement value is obtained.

[0104] First, refer to Figure 10, the resistance measuring device 700 can input an input voltage to the first test point TPO1 through the fixture 600, and measure an output voltage through the second test point TPO2. In other words, the input voltage input to the first test point TPO1 through the fixture 600 can be measured as an output voltage by the resistance measuring device 700 through the fixture 600 by passing through the following components: the first main test line TM_L1, the first main test pad TM_PAD1, the 2-1 test lead T_LE5, the first test lead T_L1, the 1-1 test lead T_L11 and the 1-2 test lead T_L12 connected in parallel, and the 1-1 test lead T_LE1 and the 1-2 test lead T_LE2 connected in parallel. T_LE2, the first panel test pad TP_PAD1 and the second panel test pad TP_PAD2 connected in parallel, the first panel test line TP_L1 and the second panel test line TP_L2, the panel common test line TP_L5, the third panel test line TP_L3, the third panel test pad TP_PAD3, the 1-3 test lead T_LE3, the second test lead line T_L2, the 2-2 test lead T_LE6, the second main test pad TM_PAD2, the second main test line TM_L2 and the second test point TPO2. For example, an input voltage can enter the first test point TPO1 and travel along a first path from the first main test pad TM_PAD1 to the first panel test pad TP_PAD1 and the second panel test pad TP_PAD2, and then travel along a second path from the third panel test pad TP_PAD3 to the second main test pad TM_PAD2, thereby being measured as an output voltage at the second test point TPO2.

[0105] When the drop voltage between the output voltage and the input voltage is divided by the predetermined current, a first measurement value as the resistance between the first test point TPO1 and the second test point TPO2 may be obtained.

[0106] Reference Figure 9 , the first measurement value can be derived from the following equation.

[0107] [Equation 1]

[0108] First measurement value = 2R JIG +2R TAB +2R cof +3 / 2R OLB +R panel

[0109] Here, R JIG It may refer to the resistance of the fixture 600. In other words, by taking into account the resistance of the fixture 600 itself, the first measurement value may be a more accurate measurement value of the resistance between the first test point TPO1 and the second test point TPO2.

[0110] Although the clamp 600 in contact with the first test point TPO1 and the clamp 600 in contact with the second test point TPO2 may have different resistances, for ease of description, the resistances of the two clamps 600 will be referred to as R JIG .

[0111] Although the contact resistance between the first main test pad TM_PAD1 and the 2-1 test lead T_LE5 and the contact resistance between the 2-2 test lead T_LE6 and the second main test pad TM_PAD2 may be different from each other according to the constituent materials and properties of the bonding member configured to bond them, for convenience of description, the two contact resistances will be referred to as R TAB .

[0112] In addition, R TAB Each of the contact resistance between the first main test pad TM_PAD1 and the 2-1 test lead T_LE5 and the contact resistance between the 2-2 test lead T_LE6 and the second main test pad TM_PAD2 may be referred to. Although the contact resistance between the first main test pad TM_PAD1 and the 2-1 test lead T_LE5 and the contact resistance between the 2-2 test lead T_LE6 and the second main test pad TM_PAD2 may be different from each other according to the constituent materials and properties of the bonding member configured to bond them, for the convenience of description, the two contact resistances will be referred to as R TAB .

[0113] R cof The resistance of the first substrate 300 may refer to the resistance of the first substrate 300. The resistance of the first substrate 300 may refer to each of the resistance of the printed base film 310, the sum of the resistance of the 1-1 test lead wire T_L11 and the 1-2 test lead wire T_L12 connected in parallel and the resistance of the first test lead wire T_L1, and the sum of the resistance of the printed base film 310 and the resistance of the second test lead wire T_L2. Although the resistance of the printed base film 310, the sum of the resistance of the 1-1 test lead wire T_L11 and the 1-2 test lead wire T_L12 connected in parallel and the resistance of the first test lead wire T_L1, and the sum of the resistance of the printed base film 310 and the resistance of the second test lead wire T_L2 may be different, for the sake of convenience of description, the sum of the two resistances will be referred to as R cof .

[0114] R OLB It may refer to each of the sum of the contact resistance between the 1-1 test lead T_LE1 and the first panel test pad TP_PAD1, the contact resistance between the 1-2 test lead T_LE2 and the second panel test pad TP_PAD2, and the contact resistance between the 1-3 test lead T_LE3 and the third panel test pad TP_PAD3.

[0115] As R OLBAlthough the sum of the contact resistance between the 1-1 test lead T_LE1 and the first panel test pad TP_PAD1, the contact resistance between the 1-2 test lead T_LE2 and the second panel test pad TP_PAD2, and the contact resistance between the 1-3 test lead T_LE3 and the third panel test pad TP_PAD3 may be different, for the convenience of description, the three contact resistances will be referred to as R OLB .

[0116] R panel It may refer to the sum of the resistance of the base substrate 110 and the resistance of the first panel test line TP_L1, the second panel test line TP_L2, the third panel test line TP_L3, and the panel common test line TP_L5. The resistances of the first panel test line TP_L1, the second panel test line TP_L2, the third panel test line TP_L3, and the panel common test line TP_L5 may be measured separately, but the resistance of the base substrate 110 may not be accurately measured. Therefore, as described above, when R is removed by calculation between the first measurement value to the third measurement value, panel When the factor is OLB The exact value of .

[0117] Reference Figure 11, the resistance measuring device 700 can input the input voltage to the second test point TPO2 through the fixture 600, and measure the output voltage through the third test point TPO3. In other words, the input voltage input to the second test point TPO2 through the fixture 600 can be measured as the output voltage by the resistance measuring device 700 through the fixture 600 by passing through the following elements: the second main test line TM_L2, the second main test pad TM_PAD2, the 2-2 test lead T_LE6, the second test lead T_L2, the 1-3 test lead T_LE3, the third panel test pad TP_PAD3, the third panel test line TP_L3, the panel common test line TP_L5, and the fourth panel test line TP _L4, fourth panel test pad TP_PAD4, 1-4 test lead T_LE4, third test lead T_L3, 3-1 test lead T_L31 and 3-2 test lead T_L32 connected in parallel, 2-3 test lead T_LE7 and 2-4 test lead T_LE8 connected in parallel, third main test pad TM_PAD3 and fourth main test pad TM_PAD4 connected in parallel, 3-1 main test line TM_L31 and 3-2 main test line TM_L32 connected in parallel, and third main test line TM_L3. For example, an input voltage may enter the second test point TPO2 and travel along a first path from the second main test pad TM_PAD2 to the third panel test pad TP_PAD3, and then travel along a second path from the fourth panel test pad TP_PAD4 to the third main test pad TM_PAD3 and the fourth main test pad TM_PAD4, thereby being measured as an output voltage at the third test point TPO3.

[0118] When the drop voltage between the output voltage and the input voltage is divided by the predetermined current, a second measurement value may be obtained as the resistance between the second test point TPO2 and the third test point TPO3.

[0119] Reference Figure 9 , the second measurement value can be derived from the following equation.

[0120] [Equation 2]

[0121] Second measurement value = 2R JIG +3 / 2R TAB +2R cof +2R OLB +R panel

[0122] Reference Figure 12, the resistance measuring device 700 can input the input voltage to the first test point TPO1 through the fixture 600, and measure the output voltage through the third test point TPO3. In other words, the input voltage input to the first test point TPO1 through the fixture 600 can be measured as the output voltage by the resistance measuring device 700 through the fixture 600 by passing through the following elements: the first main test line TM_L1, the first main test pad TM_PAD1, the 2-1 test lead T_LE5, the first test lead T_L1, the 1-1 test lead T_L11 and the 1-2 test lead T_L12 connected in parallel, the 1-1 test lead T_LE1 and the 1-2 test lead T_LE2 connected in parallel, the first panel test pad TP_PAD1 and the second panel test pad TP_PAD2 connected in parallel, the first panel test line TP_L 1 and second panel test lines TP_L2, panel common test line TP_L5, fourth panel test line TP_L4, fourth panel test pad TP_PAD4, 1-4 test lead T_LE4, third test lead line T_L3, 3-1 test lead line T_L31 and 3-2 test lead line T_L32 connected in parallel, 2-3 test lead line T_LE7 and 2-4 test lead T_LE8 connected in parallel, third main test pad TM_PAD3 and fourth main test pad TM_PAD4 connected in parallel, 3-1 main test line TM_L31 and 3-2 main test line TM_L32 connected in parallel, third main test line TM_L3 and third test point TPO3. For example, the input voltage may enter the first test point TPO1 and travel along a first path from the first main test pad TM_PAD1 to the first panel test pad TP_PAD1 and the second panel test pad TP_PAD2, and then travel along a second path from the fourth panel test pad TP_PAD4 to the third main test pad TM_PAD3 and the fourth main test pad TM_PAD4, thereby being measured as the output voltage at the third test point TPO3.

[0123] When the drop voltage between the output voltage and the input voltage is divided by the predetermined current, a third measurement value may be obtained as the resistance between the first test point TPO1 and the third test point TPO3 .

[0124] Reference Figure 9 , the third measurement value can be derived from the following equation.

[0125] [Equation 3]

[0126] The third measurement value = 2R JIG +3 / 2R TAB +2R cof +3 / 2R OLB +R panel

[0127] Furthermore, R can be derived from the following equation OLB .

[0128] [Equation 4]

[0129] R OLB =(second measurement value - third measurement value) × 2

[0130] According to Equation 4, when the third measurement value is subtracted from the second measurement value, due to the removal of R panel factor, so we can get R OLB .

[0131] According to the above example, when deriving the first measurement value, although only the case where the input voltage is applied to the first test point TPO1 and the output voltage is measured from the second test point TPO2 is described, the present invention is not limited thereto, and the input voltage may be applied to the second test point TPO2 and the output voltage may be measured from the first test point TPO1.

[0132] Similarly, when obtaining the second measurement value, although only the case of applying the input voltage to the second test point TPO2 and measuring the output voltage from the third test point TPO3 is described, the present invention is not limited to this, and the input voltage may be applied to the third test point TPO3 and the output voltage may be measured from the second test point TPO2.

[0133] Similarly, when obtaining the third measurement value, although only the case of applying the input voltage to the first test point TPO1 and measuring the output voltage from the third test point TPO3 is described, the present invention is not limited to this, and the input voltage may be applied to the third test point TPO3 and the output voltage may be measured from the first test point TPO1.

[0134] As mentioned above, it may not be possible to accurately measure R panel The resistance of the base substrate 110 itself is increased. When the pixels of the display panel 100 are driven and the display panel 100 is degraded, the resistance of the display panel 100 itself increases in proportion to the degradation. When the resistance of the display panel 100 itself increases, the resistance of the base substrate 110 itself increases. panel Factors included in R OLB In the case of OLB According to the calculated R OLB The contact resistance between the panel pad P_PAD and the first lead line LE1 is calculated using the value of R OLBWhen the value is too low, the contact resistance between the panel pad P_PAD and the first lead line LE1 becomes inaccurate. Therefore, the data value (for example, the voltage value that should be applied from the driver integrated circuit 350 to the panel pad P_PAD and the first lead line LE1) may be inaccurately determined, and when a voltage value having a large error compared to a normal reference value is applied, a pixel defect may be caused.

[0135] However, if Figures 2 to 5 As shown in FIG, in the display device 1 according to the present embodiment, since the lines of the dummy electrodes including the display panel 100, the first substrate 300 and the second substrate 500 are designed, R panel Factors not included in R OLB and thus the exact R can be calculated OLB value.

[0136] Therefore, it is possible to prevent pixel defects that may be caused when determining a data value (eg, a voltage value that should be applied from the driving integrated circuit 350 to the panel pad P_PAD and the first lead line LE1).

[0137] Figure 13 is a plan layout diagram of a display device according to another exemplary embodiment of the present invention, Figure 14 yes Figure 13 The floor plan of the display panel in Figure 15 yes Figure 13 The plan layout diagram of the first substrate, Figure 16 yes Figure 13 A planar layout diagram of the display panel and the first substrate, Figure 17 is a plan layout diagram illustrating a case where a first measurement value is obtained according to an exemplary embodiment of the present invention, Figure 18 is a plan layout diagram illustrating a case where a second measurement value is obtained according to an exemplary embodiment of the present invention.

[0138] Reference Figures 13 to 18 The display device 2 according to this embodiment is different from the display device 1 in that the driver integrated circuit 150 is provided on the display panel 100_1 .

[0139] For example, since the driver integrated circuit 150 is different from the Figure 1 The driving integrated circuit 350 shown in FIG. 1 is substantially the same, and thus repeated description will be omitted.

[0140] The first substrate 300_1 may be attached to the panel pad area PA (see FIG. Figure 14 ).

[0141] Reference Figure 14, the panel pad P_PAD and the driving integrated circuit 150 may be connected to each other through the first signal line L1_1 .

[0142] Since the above reference Figure 2 The panel test pads TP_PAD1 to TP_PAD4 and the panel test lines TP_L1 to TP_L5 are described, and thus repeated descriptions will be omitted.

[0143] Reference Figure 15 , the first substrate 300_1 may include a main circuit portion 550. Since the main circuit portion 550 is connected to Figure 1 The main circuit portion 550 of the second substrate 500 is substantially the same, and thus repeated description will be omitted.

[0144] The main circuit portion 550 and the first lead line LE1 may be electrically connected to each other through the second signal line L2_1 .

[0145] The 1-1 test lead T_LE1 may be connected to the 1-1 main test line TM_L11_1, and the 1-2 test lead T_LE2 may be connected to the 1-2 main test line TM_L12_1. The 1-1 main test line TM_L11_1 and the 1-2 main test line TM_L12_1 may be connected in parallel to the first main test line TM_L1_1.

[0146] The second main test line TM_L2_1 may be connected to the 1-3 test lead T_LE3 , and the third main test line TM_L3_1 may be connected to the 1-4 test lead T_LE4 .

[0147] The first main test line TM_L1_1 may be connected to the first test point TPO1_1 , the second main test line TM_L2_1 may be connected to the second test point TPO2_1 , and the third main test line TM_L3_1 may be connected to the third test point TPO3_1 .

[0148] First, refer to Figure 17 , resistance measuring device (see Figure 17 700 in FIG) can input the input voltage to the first test point TPO1_1 through the fixture 600, and measure the output voltage through the second test point TPO2_1. In other words, through the fixture (see Figure 17The input voltage input to the first test point TPO1_1) can be measured as an output voltage by the resistance measuring device 700 through the fixture 600 by passing through the following elements, wherein the elements passed through are the first main test line TM_L1_1, the 1-1 main test line TM_L11_1 and the 1-2 main test line TM_L12_1 connected in parallel, the 1-1 test lead T_LE1 and the 1-2 test lead T_LE2 connected in parallel, the first panel test pad TP_PAD1 and the second panel test pad TP_PAD2 connected in parallel, the first panel test line TP_L1 and the second panel test line TP_L2, the panel common test line TP_L5, the third panel test line TP_L3, the third panel test pad TP_PAD3, the 1-3 test lead T_LE3, the second main test line TM_L2_1 and the second test point TPO2_1.

[0149] When the drop voltage between the output voltage and the input voltage is divided by the predetermined current, a fourth measurement value may be obtained as the resistance between the first test point TPO1_1 and the second test point TPO2_1 .

[0150] Reference Figure 18 The resistance measuring device 700 can input an input voltage to the second test point TPO2_1 through the fixture 600 and measure an output voltage through the third test point TPO3_1. In other words, the input voltage input to the second test point TPO2_1 through the fixture 600 can be measured as an output voltage by the resistance measuring device 700 through the fixture 600 by passing through the following elements: the second main test line TM_L2_1, the 1-3 test lead T_LE3, the third panel test pad TP_PAD3, the third panel test line TP_L3, the panel common test line TP_L5, the fourth panel test line TP_L4, the fourth panel test pad TP_PAD4, the 1-4 test lead T_LE4, the third main test line TM_L3_1, and the third test point TPO3_1.

[0151] When the drop voltage between the output voltage and the input voltage is divided by the predetermined current, a fifth measurement value may be obtained as the resistance between the second test point TPO2_1 and the third test point TPO3_1 .

[0152] The fourth measurement value can be derived from the following equation.

[0153] [Equation 5]

[0154] Fourth measurement value = 2R JIG +2R cof +3 / 2R OLB +R panel

[0155] The fifth measurement value can be derived from the following equation.

[0156] [Equation 6]

[0157] Fifth measurement value = 2R JIG +2R cof +2R OLB +R panel

[0158] Furthermore, R can be derived from the following equation OLB .

[0159] [Equation 7]

[0160] R OLB =(fifth measurement value - fourth measurement value)×2

[0161] According to Equation 7, when the fourth measurement value is subtracted from the fifth measurement value, due to the removal of R panel factor, so we can get R OLB .

[0162] However, in the display device 2 according to the present embodiment, since Figures 14 to 16 As shown in FIG, the lines including the dummy electrodes of the display panel 100_1 and the first substrate 300_1 are designed, so R panel Factors not included in R OLB and thus the exact R can be calculated OLB value.

[0163] Therefore, it is possible to prevent pixel defects that may be caused when determining a data value (eg, a voltage value that should be applied from the first substrate 300_1 to the panel pad P_PAD and the first lead line LE1).

[0164] Figure 19 is a plan layout diagram of a display panel according to another exemplary embodiment of the present invention, Figure 20 is a plan layout diagram of a first substrate according to another exemplary embodiment of the present invention, Figure 21 is a plan layout diagram of a second substrate according to still another exemplary embodiment of the present invention.

[0165] Reference Figures 19 to 21The display device according to this embodiment is different from the display devices according to other embodiments in that it also includes a power panel pad PP_PAD arranged in the panel pad area PA and connected to the display area DA through the first signal line L1, and the first substrate includes power lead lines LEP1 and LEP2 adjacent to the first lead line LE1 and the second lead line LE2, and a first power signal line LP1 configured to connect the power lead lines LEP1 and LEP2, and the second substrate also includes a power main circuit pad M_PPAD adjacent to the power main test pad TMP_PAD, a power driving unit 570, and a second power signal line LP2 configured to electrically connect the power driving unit 570 and the power main circuit pad M_PPAD.

[0166] For example, the display device according to this embodiment may include a Figures 2 to 4 The power panel test pads TPP_PAD1 to TPP_PAD4 that perform the same functions as the panel test pads TP_PAD1 to TP_PAD4 of the display panel 100 shown in FIG, and the power panel test lines TPP_L1 to TPP_L5 that perform the same functions as the panel test lines TP_L1 to TP_L5 may include power test leads TP_LEa that respectively perform the same functions as the test leads T_LEa and T_LEb and the test lead lines T_L1 to T_L3, T_L11, T_L12, T_L31, and T_L32 of the first substrate 300 described above. and TP_LEb and power test lead lines TP_L1 to TP_L3, TP_L11, TP_L12, TP_L31 and TP_L32, and may include a power main test pad TMP_PAD, power main test lines TMP_L1, TMP_L2, TMP_L3, TMP_L31 and TMP_L32 and a power test point TPPOa that respectively perform the same functions as the main test pad TM_PAD, main test lines TM_L1, TM_L2, TM_L3, TM_L31 and TM_L32 and test point TPOa of the above-mentioned second substrate 500.

[0167] Figure 22 is a plan layout diagram of a display device according to yet another exemplary embodiment of the present invention, Figure 23 yes Figure 22 The floor plan of the display panel in Figure 24 yes Figure 22 The plan layout diagram of the first substrate, Figure 25 yes Figure 22 Layout diagram of the second substrate in FIG.

[0168] Reference Figures 22 to 25The display device according to the embodiment is different from the display devices according to other embodiments in that the scan driving part SGP is further provided in the non-display area NDA of the display panel 100 and is electrically connected to the scan panel pad PG_PAD through the scan signal line LG, the first substrate 300 includes scan lead lines TG_LE1 and TG_LE2 and a first scan signal line LG1 configured to connect the scan lead lines TG_LE1 and TG_LE2, and the second substrate 500 further includes a scan main circuit pad M_GPAD electrically connected to the main circuit part 550 through a fourth signal line L4.

[0169] In the display device according to the present embodiment, since the lines of dummy electrodes including the display panel 100, the first substrate 300, and the second substrate 500 are designed, it is possible to prevent pixel defects that may be caused when determining a signal (a signal that should be applied from the second substrate 500 to the first scan lead-out line TG_LE1 and the scan panel pad PG_PAD) and a scan control signal value (a scan control signal value that controls the scan signal).

[0170] For example, the display device according to this embodiment may include a Figures 2 to 4 The scanning panel test pads TPG_PAD1 to TPG_PAD4 that perform the same functions as the panel test pads TP_PAD1 to TP_PAD4 of the display panel 100 shown in FIG, and the scanning panel test lines TPG_L1 to TPG_L5 that perform the same functions as the panel test lines TP_L1 to TP_L5 may include scanning test leads TG_LEa that respectively perform the same functions as the test leads T_LEa and T_LEb and the test lead lines T_L1 to T_L3, T_L11, T_L12, T_L31, and T_L32 of the first substrate 300 described above. and TG_LEb and scan test lead lines TG_L1 to TG_L3, TG_L11, TG_L12, TG_L31 and TG_L32, and may include a scan main test pad TMG_PAD, scan main test lines TMG_L1, TMG_L2, TMG_L3, TMG_L31 and TMG_L32 and a scan test point TPGOa, which respectively perform the same functions as the main test pad TM_PAD, main test lines TM_L1, TM_L2, TM_L3, TM_L31 and TM_L32 and test point TPOa of the above-mentioned second substrate 500.

[0171] In the above-described exemplary embodiments of the present invention, in the display device and the inspection method thereof, the contact resistance between the pad and the lead can be accurately measured.

[0172] Although exemplary embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims

1. A display device, comprising: Display panel; a first substrate attached to one side of the display panel; as well as a second substrate attached to one side of the first substrate, The display panel includes a first panel test pad, a second panel test pad, a third panel test pad, and a fourth panel test pad connected to a panel common test line. The first substrate includes: a 1-1 circuit test lead, overlapping with the first panel test pad and connected to the first panel test pad; a 1-2 circuit test lead, overlapping with the second panel test pad and connected to the second panel test pad; a 1-3 circuit test lead, overlapping with the third panel test pad and connected to the third panel test pad; a 1-4 circuit test lead, overlapping with the fourth panel test pad and connected to the fourth panel test pad; a 2-1 circuit test lead, a 2-2 circuit test lead, a 2-3 circuit test lead and a 2-4 circuit test lead, overlapping with the second substrate and connected to the second substrate; a 1-1 test lead connected to the 1-1 circuit test lead; a 1-2 test lead connected to the 1-2 circuit test lead; and a first test lead connected to the 2-1 circuit test lead, and The 1-1 test lead and the 1-2 test lead are connected to the first test lead, the 1-3 circuit test lead is connected to the 2-2 circuit test lead, and the 1-4 circuit test lead is connected to the 2-3 circuit test lead and the 2-4 circuit test lead, Wherein, the second substrate includes: a first main test pad, overlapping with the 2-1 circuit test lead and connected to the 2-1 circuit test lead; a second main test pad, overlapping with the 2-2 circuit test lead and connected to the 2-2 circuit test lead; a third main test pad, overlapping with the 2-3 circuit test lead and connected to the 2-3 circuit test lead; a fourth main test pad, overlapping with the 2-4 circuit test lead and connected to the 2-4 circuit test lead; a first test point, connected to the first main test pad; a second test point, connected to the second main test pad; and a third test point, connected to the third main test pad and the fourth main test pad.

2. The display device according to claim 1, wherein The first panel test pad and the second panel test pad are electrically connected to each other through a first panel test line, a second panel test line, and the panel common test line, the first panel test line is connected to the first panel test pad, the second panel test line is connected to the second panel test pad, and the panel common test line connects the first panel test line and the second panel test line.

3. The display device according to claim 2, wherein: The display panel further includes a third panel test line connected to the third panel test pad, and The third panel test line is connected to the panel common test line.

4. The display device according to claim 3, wherein: The display panel further includes a fourth panel test line connected to the fourth panel test pad; and The fourth panel test line is connected to the panel common test line.

5. The display device according to claim 4, wherein The first substrate further includes a second test lead configured to electrically connect the 1-3 circuit test lead and the 2-2 circuit test lead.

6. The display device according to claim 5, wherein: The first substrate further includes: a third test lead connected to the 1-4 circuit test lead; a 3-1 test lead connected to the 2-3 circuit test lead; and a 3-2 test lead connected to the 2-4 circuit test lead; and The 3-1 test lead and the 3-2 test lead are connected to the third test lead.

7. The display device according to claim 1, wherein: The first substrate further includes a data driver integrated circuit; and All of the first panel test pad, the second panel test pad, the third panel test pad, the fourth panel test pad, the 1-1 circuit test lead, the 1-2 circuit test lead, the 1-3 circuit test lead, the 1-4 circuit test lead, the 2-1 circuit test lead, the 2-2 circuit test lead, the 2-3 circuit test lead, and the 2-4 circuit test lead, as well as the first main test pad, the second main test pad, the third main test pad, and the fourth main test pad are insulated from the data drive integrated circuit.

8. The display device according to claim 1, wherein: The 1-1 test lead is physically connected to the 1-1 circuit test lead; The 1-2 test lead is physically connected to the 1-2 circuit test lead; The first test lead is physically connected to the 2-1 circuit test lead; and the 1-1 test lead and the 1-2 test lead are physically connected to the first test lead.

9. A display device, comprising: a display panel including a data driver integrated circuit; as well as a first substrate attached to one side of the display panel, Wherein, the display panel includes a first panel test pad, a second panel test pad, a third panel test pad and a fourth panel test pad, The first substrate includes: a 1-1 circuit test lead, overlapping with and connected to the first panel test pad; a 1-2 circuit test lead, overlapping with and connected to the second panel test pad; a 1-3 circuit test lead, overlapping with and connected to the third panel test pad; a 1-4 circuit test lead, overlapping with and connected to the fourth panel test pad; a first test point, connected to the 1-1 circuit test lead and the 1-2 circuit test lead; a second test point, connected to the 1-3 circuit test lead; and a third test point, connected to the 1-4 circuit test lead.

10. The display device according to claim 9, wherein: The first substrate further includes a first test lead, a 1-1 test lead, and a 1-2 test lead; The first test lead is connected to the first test point; The 1-1 test lead is physically connected to the 1-1 circuit test lead; The 1-2 test lead is physically connected to the 1-2 circuit test lead; and The 1-1 test lead and the 1-2 test lead are physically connected to the first test lead.

11. A method for detecting a display device, the method comprising: A display device is provided, the display device comprising: a display panel, comprising a first panel test pad, a second panel test pad, a third panel test pad, and a fourth panel test pad; a first substrate, comprising a 1-1 circuit test lead, a 1-2 circuit test lead, a 1-3 circuit test lead, a 1-4 circuit test lead, a 2-1 circuit test lead, a 2-2 circuit test lead, a 2-3 circuit test lead, and a 2-4 circuit test lead, wherein the 1-1 circuit test lead to the 1-4 circuit test lead are respectively connected to the first panel test pad to the fourth panel test pad; and a second substrate, comprising a first main test pad, a second main test pad, a third main test pad, a fourth main test pad, and a first test point , a second test point and a third test point, the first main test pad to the fourth main test pad are respectively connected to the 2-1 circuit test lead to the 2-4 circuit test lead, the first test point is connected to the first main test pad, the second test point is connected to the second main test pad, and the third test point is connected to the third main test pad and the fourth main test pad, wherein the 1-1 circuit test lead and the 1-2 circuit test lead are connected in parallel to the 2-1 circuit test lead, the 1-3 circuit test lead is connected to the 2-2 circuit test lead, and the 2-3 circuit test lead and the 2-4 circuit test lead are electrically connected to the 1-4 circuit test lead; contacting a fixture with the first test point and the second test point to obtain a first measurement value; contacting the fixture with the second test point and the third test point to obtain a second measurement; contacting the fixture with the first test point and the third test point to obtain a third measurement; and The first measurement value, the second measurement value, and the third measurement value are used to determine the contact resistance between the first panel test pad and the 1-1 circuit test lead, the contact resistance between the second panel test pad and the 1-2 circuit test lead, the contact resistance between the third panel test pad and the 1-3 circuit test lead, and the contact resistance between the fourth panel test pad and the 1-4 circuit test lead.

12. The detection method according to claim 11, wherein: taking into account the resistance of the fixture in contact with the first test point and the second test point when obtaining the first measurement; taking into account the resistance of the fixture in contact with the second test point and the third test point when obtaining the second measurement; and The resistance of the fixture in contact with the first and third test points is taken into account when obtaining the third measurement value.

13. The detection method according to claim 11, wherein The resistance value of the display panel is removed from the steps of determining the contact resistance between the first panel test pad and the 1-1 circuit test lead, the contact resistance between the second panel test pad and the 1-2 circuit test lead, the contact resistance between the third panel test pad and the 1-3 circuit test lead, and the contact resistance between the fourth panel test pad and the 1-4 circuit test lead.

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