Pixel, associated image sensor and method

Abstract

A pixel includes a semiconductor substrate, a photodiode region, a floating diffusion region, and a dielectric layer. The substrate has a top surface that forms a trench, the trench is lined by the dielectric layer, and has a trench depth relative to a planar region of the top surface. The photodiode region is in the substrate and includes a bottom photodiode portion under the trench and a top photodiode portion adjacent the trench, the top photodiode portion abutting the bottom photodiode portion and extending toward the planar region to a photodiode depth that is less than the trench depth. The floating diffusion region is adjacent the trench and has a junction depth that is less than the trench depth. A top region of the dielectric layer is between the planar region and the junction depth. A bottom region of the dielectric layer is between the photodiode depth and the trench depth and is thicker than the top region.

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of image sensor technology, and in particular to a pixel, an associated image sensor and a method of manufacturing the same. BACKGROUND

[0002] Camera modules in commercial products such as standalone digital cameras, mobile devices, automotive components, and medical devices include image sensors and their pixel arrays. A pixel array includes a plurality of pixels. The pixel density of a pixel array is the number of pixels per unit area on the image sensor. In operation, a lens of a camera module forms an image of an object in its field of view on the image sensor. The object can be observed as a plurality of infinitesimally small illuminating point sources - "impulses" - incident on the camera. The lens images each of the plurality of impulses as a respective one of a plurality of point spread functions - "impulse responses" - at the plane of the pixel array. The resolution of an image captured by the image sensor depends in part on the size of the pixels compared to the size of the impulse responses. Thus, one method of increasing the maximum achievable resolution of a camera is to increase the pixel density by reducing the pixel size. The motivation to reduce the pixel size has led to the development of pixels with vertical transfer gates.

[0003] Each of the plurality of pixels includes a photodiode region, a floating diffusion region, and a transfer gate. The transfer gate controls the flow of current from the photodiode region to the floating diffusion region, and can include a field effect transistor. The potential of the photodiode region exceeds the potential of the floating diffusion region. Light reaching the photodiode region generates photoelectrons. Turning on the transfer gate forms a conductive channel that allows the accumulated photoelectrons to transfer or flow from the photodiode region to the floating diffusion region. When the transfer gate is pulsed to an off state, the potential barrier is higher than the potential barrier of the photodiode region, thus preventing the flow of photoelectrons to the floating diffusion region.

[0004] In one common pixel architecture, the photodiode and floating diffusion regions are laterally displaced within the pixel in a lateral direction parallel to the plane of the pixel array, with the transfer gate therebetween. This plane is oriented horizontally with respect to a vertical direction perpendicular thereto, the vertical direction defining the direction of normal incidence to the pixel array. This horizontal orientation limits how much the pixel density can be reduced. Thus, one method of increasing the pixel density is to orient the photodiode, transfer gate, and floating diffusion in a direction having a vertical component. Such a transfer gate is an example of a vertical transfer gate. SUMMARY

[0005] Problems with pixels having vertical transfer gates include electron transport delay and electron backscattering. Embodiments disclosed herein ameliorate these problems.

[0006] In a first aspect, a pixel includes a semiconductor substrate, a photodiode region, a floating diffusion region, and a dielectric layer. The semiconductor substrate has a substrate top surface that forms a trench extending into the semiconductor substrate. The trench has a trench depth relative to a planar region of the substrate top surface surrounding the trench. The photodiode region is in the semiconductor substrate and includes a bottom photodiode portion under the trench and a top photodiode portion adjacent the trench. The top photodiode portion is (a) adjacent the trench, (b) contiguous with the bottom photodiode portion, (c) implanted at a photodiode depth that is less than the trench depth relative to the planar region, and (d) extends toward and is contiguous with the bottom photodiode region. The floating diffusion region is in the semiconductor substrate, adjacent the trench, and extends away from the planar region to a junction depth that is less than the trench depth. The dielectric layer lines the trench. A top region of the dielectric layer is between the planar region and the junction depth and has a top thickness. A bottom region of the dielectric layer is between the photodiode depth and the trench depth and has a bottom thickness that exceeds the top thickness.

[0007] In a second aspect, a pixel includes a semiconductor substrate, a photodiode region in the semiconductor substrate, a floating diffusion region in the semiconductor substrate, a dielectric layer lining a trench, and a gate electrode material filling the trench. The semiconductor substrate has a substrate top surface that forms the trench, the trench extending into the semiconductor substrate and having a trench depth relative to a planar region of the substrate top surface surrounding the trench. The photodiode region includes (i) a bottom photodiode portion under the trench and (ii) a top photodiode portion adjacent the trench, the top photodiode portion beginning at a photodiode depth that is less than the trench depth, extending toward and being contiguous with the bottom photodiode portion. The photodiode depth is relative to the planar region. The floating diffusion region is in the semiconductor substrate, adjacent the trench, and extends away from the planar region to a junction depth that is less than the trench depth. The dielectric layer has a top region formed between the planar region and the junction depth, and a bottom region formed between the photodiode depth and the trench depth. The semiconductor substrate, the gate electrode material, and the bottom region of the dielectric layer therebetween form a first capacitor having a first capacitance. The semiconductor substrate, the gate electrode material, and the top region of the dielectric layer therebetween form a second capacitor having a second capacitance that exceeds the first capacitance.

[0008] In a third aspect, a pixel fabrication method includes lining a surface of a trench with a first dielectric layer. The trench extends into a top surface of a semiconductor substrate and has a trench depth relative to a planar region surrounding the top surface of the trench. The semiconductor substrate includes a photodiode region adjacent to the trench. The photodiode region is formed at a photodiode depth and extends away from the planar region. The photodiode depth is less than the trench depth relative to the planar region. The method also includes covering a bottom region of the first dielectric layer with an organic layer. The bottom region extends from the trench depth to an etch depth that does not exceed the photodiode depth. The method also includes etching a top region of the first dielectric layer at a depth between the top surface and the etch depth, and depositing a second dielectric layer on the surface of the trench at a depth between the planar region and the trench depth. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A camera imaging a scene.

[0010] Figure 2 is a cross-sectional schematic of a semiconductor substrate that is Figure 1 a semiconductor substrate of a camera of

[0011] Figure 3 is a cross-sectional schematic of a pixel that is Figure 2 a pixel of a semiconductor substrate of

[0012] Figure 4 is a schematic of a potential relative to depth within a pixel illustrating Figure 3 a technical benefit of an embodiment of the pixel of

[0013] Figure 5 is a cross-sectional schematic of a coated substrate in an embodiment that is Figure 3 a semiconductor substrate of

[0014] Figure 6 is a cross-sectional schematic of a coated substrate of Figure 5 in an embodiment, where an organic layer partially fills a trench thereof.

[0015] Figure 7 is a cross-sectional schematic of a coated substrate of Figure 6 in an embodiment after etching.

[0016] Figure 8 is a cross-sectional schematic of a substrate of Figure 7 in an embodiment after depositing a layer thereon.

[0017] Figure 9 is a cross-sectional schematic of a substrate of Figure 7 in an embodiment after depositing a layer thereon.

[0018] Figure 10 is a flowchart illustrating a method for manufacturing a transfer gate in an embodiment. DETAILED DESCRIPTION

[0019] Throughout this specification, the use of “one example” or “an example” means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the application. Thus, appearances of the phrases “in one example” or “in one embodiment” in various places in the specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more examples.

[0020] For ease of description, spatially relative terms such as “below”, “beneath”, “bottom”, “...under”, “above”, “top”, and the like, can be used herein for describing an element’s or feature’s relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as “below” or “beneath” or “...under” other elements or features would then be oriented “above” the other elements or features. The terms “below” and “under” can encompass both orientations “above” and “below”. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers or one or more intervening layers can also be present.

[0021] Throughout this specification, several technical terms are used. Such terms are to take the ordinary meaning as they are commonly used in the field from which they originate. It should be noted that in this document, element names and symbols can be used interchangeably (e.g., Si vs. silicon); however, both have the same meaning.

[0022] Figure 1 A camera 190 imaging a scene is depicted. The camera 190 includes an image sensor 100 that includes a semiconductor substrate 110. Constituent elements of the semiconductor substrate 110 can include silicon and germanium. The semiconductor substrate 110 includes a pixel array 112A. The image sensor 100 can be part of a chip-scale package or a flip-chip package.

[0023] Figure 2 is a cross-sectional schematic view of a semiconductor substrate 210 that is an example of the semiconductor substrate 110 and includes at least one of silicon and germanium. Figure 2The cross-section shown is parallel to a plane formed by orthogonal directions 298X and 298Z, hereinafter referred to as the x-z plane, each of which is orthogonal to direction 298Y. Here, the x-y plane is formed by orthogonal directions 298X and 298Y, and a plane parallel to the x-y plane is referred to as the lateral plane. Unless otherwise stated, the height of an object herein refers to the extent of the object in direction 298Z or the direction opposite 180° thereto. Here, reference to an axis x, y, or z or a related direction ±x, ±y, or ±z refers to direction 298X, 298Y, and 298Z, respectively. Additionally, here, the horizontal plane is parallel to the x-y plane, the width refers to the extent of an object in the y-direction, and the vertical refers to the z-direction.

[0024] Semiconductor substrate 210 has a bottom substrate surface 211 and a top substrate surface 219, each of which can be perpendicular to direction 298Z. Here, top substrate surface 219 can be referred to as a front side surface of semiconductor substrate 210. Here, top substrate surface 219 can be referred to as a non-illuminated surface of semiconductor substrate 210, and bottom substrate surface 211 opposite to top substrate surface 219 can be referred to as an illuminated surface of semiconductor substrate 210. Semiconductor substrate 210 includes a plurality of pixels 212 forming a pixel array 212A, which is an example of pixel array 112A. The plurality of pixels 212 are arranged in a plurality of rows and columns in directions 298X and 298Y, respectively. Pixel array 212A has a pixel pitch 213 in direction 298X. In embodiments, in direction 298Y, pixel array 212A has a pitch P y In embodiments, pixel pitch 213 is less than 1.1 pm, for example, pixel pitch 213 can be equal to 0.9 pm.

[0025] Each pixel 212 includes a respective photodiode 240, a respective vertical transfer gate 250, and a respective floating diffusion region 260. Photodiode 240 of each pixel 212 is configured to generate and accumulate charge in response to incident light, for example, incident light entering from bottom substrate surface 211 of semiconductor substrate 210 (e.g., the backside of semiconductor substrate 210) during an integration period of the image sensor. The electrical connection of photodiode 240 to floating diffusion region 260 depends on the voltage applied to vertical transfer gate 250. Depending on the voltage applied to vertical transfer gate 250, the accumulated charge in photodiode 240 can be selectively transferred to floating diffusion region 260.

[0026] Figure 3 is a cross-sectional schematic view of pixel 300, which is an example of pixel 212. Pixel 300 is formed in semiconductor substrate 310, which isFigure 2 semiconductor substrate 210. The pixel 300 includes a trench 320, a double capacitance dielectric layer 330 lining the trench 320, a photodiode region 340, a floating diffusion region 360. In embodiments, the semiconductor substrate 310 is p-doped, the photodiode region 340 is n-doped, and the floating diffusion region 360 is n + doped. In embodiments, the floating diffusion region 360 has a doping concentration of 10 19 charge carriers per cubic centimeter and a doping concentration of 10 19 5 x 1010 20 charge carriers per cubic centimeter.

[0027] The semiconductor substrate 310 has a surface 319 that forms the trench 320. The surface 319 includes a planar region 318 that surrounds the trench 320. The trench 320 extends into the semiconductor substrate 310 to a trench depth 323 relative to the planar region 318. In embodiments, the trench depth 323 is between 0.1 and 0.9 microns. The trench 320 has a width 321 that can be between 50 nanometers and 0.3 microns in at least one of the 298X and 298Y directions. In embodiments, the trench 320 has a non-uniform width between the planar region 318 and its bottom. Thus, the width 321 can be the width of the trench 320 at a depth equal to half of the trench depth 323. The semiconductor substrate 310 has a bottom substrate surface 311 that is an example of the bottom substrate surface 211. Figure 2

[0028] The photodiode region 340 is an example of the photodiode region 240 and includes a bottom photodiode portion 341 below the trench 320 and a top photodiode portion 345 adjacent to the trench 320. The top photodiode portion 345 is formed relative to the planar region 318 at a photodiode depth 343 that is less than the trench depth 323 and extends toward the bottom surface 311 to a horizontal plane 306. The bottom photodiode portion 341 abuts the top photodiode portion 345 at the horizontal plane 306 and extends from the planar region 318 toward the bottom surface 311. The horizontal plane 306 is perpendicular to the direction 298Z. Figure 2

[0029] ​​The bottom of the trench 320 is formed deeper into the semiconductor substrate 310 relative to the planar region 318 than the top photodiode portion 345, such that a portion of the trench 320 overlaps the top photodiode portion 345. The bottom photodiode portion 341 is separated from the surface 319 by a distance 342 in the x-y plane. The top photodiode portion 345 is separated from the surface 319 by a distance 343 in the vertical direction (e.g., along the direction 298Z). The top photodiode portion 345 is separated from the surface 319 by a distance 346 in the horizontal direction.

[0030] In embodiments, each of the distances 342 and 346 is between 30 nanometers and 300 nanometers. The floating diffusion region 360 is formed in the semiconductor substrate 310 adjacent to the trench 320 and extends away from the planar region 318 to a junction depth 363 that is less than the trench depth 323.

[0031] The dual capacitance dielectric layer 330 lines the trench 320, has a top dielectric surface 339, and has a thin region 331 and a thick region 335 defined by a range of distances from the planar region 318 that are parallel to the direction 298Z. In embodiments, the dual capacitance dielectric layer 330 has a relative permittivity that is greater than or equal to that of silicon dioxide, which enables the layer 330 to have sufficient capacitance to attract electrons to the floating diffusion region 360 during a charge transfer operation.

[0032] In addition to the horizontal plane 306, Figure 3 five horizontal planes 301-305 are also represented, each of which is perpendicular to the direction 298Z. The plane 301 corresponds to the top surface of the dual capacitance dielectric layer 330 above the planar region 318. The plane 302 includes the planar region 318. The planes 302 and 303 are vertically separated by the junction depth 363. The planes 302 and 304 are vertically separated by the photodiode depth 343. The planes 302 and 305 are vertically separated by the trench depth 323. The planes 305 and 306 are separated by the distance 342. The distance 346 described above can be in a plane between the planes 304 and 305.

[0033] The thin region 331 is between the plane 301 and a horizontal plane 332 that is between or co-planar with the plane 304. The thick region 335 is between the plane 305 and a horizontal plane 336 that is between the planes 305 and 332. In embodiments, the horizontal plane 336 is co-planar with the plane 304, and the horizontal plane 332 is between the planes 302 and 304. In embodiments, the horizontal plane 332 is co-planar with the plane 304, and the horizontal plane 336 is between the planes 304 and 305. In embodiments, both of the horizontal planes 332 and 336 are co-planar with the plane 304 within manufacturing tolerances.

[0034] Thin region 331 and thick region 335 have respective thicknesses 333 and 337, where, in embodiments, thickness 337 exceeds thickness 333. Because thin layers often lack uniform thickness, values of layer thicknesses disclosed herein can represent an average thickness of the layer, such as an average thickness of the layer. In embodiments, thickness 333 is between 2 nanometers and 10 nanometers. In embodiments, thickness 333 is 7.5 nanometers. In embodiments, thickness 337 exceeds thickness 333 by at least a factor of two. In embodiments, the factor is between two and five.

[0035] In embodiments, thick region 335 includes multiple material layers. Figure 3 An inner dielectric surface 338 is represented. Thick region 335 can include a first layer between surface 319 and inner dielectric surface 338, and a second layer between inner dielectric surface 338 and a top dielectric surface 339. In embodiments, the first and second layers are formed of the same material, such as silicon dioxide. In other embodiments, the first and second layers are formed of different materials. For example, the first layer can be formed of a dielectric material having a dielectric constant greater than 3.9 (referred to as a high-k material) or a relative dielectric constant greater than or equal to the relative dielectric constant of silicon dioxide, such as aluminum oxide (AI2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), or combinations thereof, and the second layer can be formed of silicon dioxide. In embodiments, thin region 331 and thick region 335 have respective dielectric constants 5) , 331 and 335 , respective thicknesses t 331 and t 335 , and respective area-normalized capacitances K 331 / t 331 and K 335 / t 335 , and where K 331 / t 331 exceeds K 335 / t 335 . Area-normalized capacitance K 335 / t 335 may be a normalized series capacitance, for example, when thick region 335 includes multiple material layers formed of different materials, and is a sum of reciprocals of dielectric constants of the multiple material layers.

[0036] In embodiments, pixel 300 includes a gate electrode material 325 that fills trench 320. Trench 320, double-capacitance dielectric layer 330, and gate electrode material 325 form a vertical transfer gate electrically connected to photodiode region 340 via thick region 335 and a top photodiode portion 345. Double-capacitance dielectric layer 330 and gate electrode material 325 act as a transfer gate for pixel 300, which is Figure 2is an example of a vertical transfer gate 250. The gate electrode material 325 comprises a suitable conductive material, such as polysilicon or metal.

[0037] As will be appreciated by those skilled in the art, the vertical transfer gate 250 can be modeled as a parallel plate capacitor with a capacitance C = (ke0A) / t, where k = e / e0, where A represents the capacitor area or the area of the corresponding portion of the vertical transfer gate 250, e0is the permittivity of free space, i.e., 8.854 x 1012 12 F / m, k represents the permittivity (relative permittivity) of the dual-capacitance dielectric layer 330, and t represents the thickness of the parallel plate capacitor, i.e., the thickness of the dual-capacitance dielectric layer 330 for the corresponding capacitor area. The area A is, for example, the area of the patch having the thin region 331 or the thick region 335 with a surface normal that is perpendicular to the surface 319.

[0038] In other words, the capacitance of the vertical transfer gate 250 is related to the thickness and material composition of the dual-capacitance dielectric layer 330. The thickness of the thin region 331 and the thick region 335 and the material composition of the thin region 331 and the thick region 335 are configured such that the capacitance associated with the thin region 331 is always greater than the capacitance associated with the thick region 335 to (i) facilitate charge transfer (e.g., photoelectron transfer) from the top photodiode region 345 to the floating diffusion region 360 during a charge transfer operation and (ii) reduce image lag. The capacitance associated with the thin region 331 is the capacitance of a capacitor formed by the semiconductor substrate 310, the gate electrode material 325, and the thin region 331 in between. The semiconductor substrate 310 and the gate electrode material 325 serve as capacitor electrodes, while the thin region 331 serves as a capacitor dielectric. The capacitance associated with the thick region 335 is the capacitance of a capacitor formed by the semiconductor substrate 310, the gate electrode material 325, and the thick region 335 in between. The semiconductor substrate 310 and the gate electrode material 325 serve as capacitor electrodes, while the thick region 335 serves as a capacitor dielectric.

[0039] Figure 4 is a plot 400 of potential versus vertical position z that illustrates the technical benefit of the embodiment of the pixel 300. In this embodiment, the boundary of the thin region 331 and the thick region 335 corresponds to the photodiode depth 343 of the photodiode region 340. As described with respect to the planes 302, 304, and 332, in this embodiment, both of the horizontal planes 332 and 336 are co-planar with the plane 304 within manufacturing tolerances. The plot 400 represents the potential V Figure 5 of the charge carriers at the respective planes 303-306 represented in 303 - V 306.

[0040] Light incident on the photodiode region 340 excites charge carriers therein into the conduction band of the doped semiconductor of the photodiode region 340; the charge carriers are at a potential V 306 The potential difference Δφ = (V 305 -V 303 ) between the bottom of the trench 320 (plane 305) and the floating diffusion region 360 (plane 303) creates an electric field that causes current flow between the photodiode region 340 and the floating diffusion region 360.

[0041] The dual capacitance dielectric layer 330 includes a thick region 335 and a thin region 331, which results in a two-step voltage drop between the photodiode region 340 and the floating diffusion region 360, as shown by curve 400. When the dual capacitance dielectric layer 330 has a uniform thickness, the potential between planes 303 and 305 would be constant. Disadvantages of such a pixel include electron transport delay and electron backscattering. The dual capacitance dielectric layer 330 reduces each of these problems when the ratio of thickness 337 to thickness 333 is between two and five. When this ratio exceeds five, or thickness 333 is too small, this results in current leakage, or thickness 337 is too large such that the capacitance of layer 330 is reduced; this decreases charge transfer efficiency.

[0042] Figures 5-8 An intermediate substrate obtained during an exemplary process of fabricating the pixel 300 is shown. Figure 5 is a cross-sectional schematic view of a coated substrate 510, which is the semiconductor substrate 310 with a dielectric layer 530 deposited on the surface 319 and lining the trench 320. In embodiments, the dielectric layer 530 can be formed of silicon dioxide (Si02) or a high-k material, such as aluminum oxide (AI2O3), hafnium oxide (Hf02), tantalum oxide (Ta205), zirconium dioxide (Zr02). The dielectric layer 530 can be deposited into the trench 320 by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or other suitable deposition method.

[0043] Figure 6 is a cross-sectional schematic view of a coated substrate 610, which is the coated substrate 510 with an organic layer 626 added in the trench 320, such that a portion of the dielectric layer 530, referred to as layer portion 532, is between the surface 319 and the organic layer 626. Layer portion 531 represents the remaining portion of the dielectric layer 530 that is not covered by the organic layer 626. The organic layer 626 has a top surface 627 at an etch depth 628 relative to the surface 319. In embodiments, the etch depth 628 is equal to the distance between planes 302 and 336 of the semiconductor substrate 310. Layer portion 532 has a surface 538, which is Figure 3 the surface 319.Figure 3 An example of the inner dielectric surface 338 of the coated substrate 810. The organic layer 626 can be a self-planarizing organic material that includes carbon, hydrogen, oxygen, and optionally at least one of nitrogen, fluorine, and silicon, and forms a planarized horizontal surface at the top surface. The organic layer 626 can be formed of an organic polymer.

[0044] Figure 7 is a cross-sectional schematic of the etched substrate 710, which is the coated substrate 610 after etching the layer portion 531. The etched substrate 710 includes the layer portion 532 between the organic layer 626 and the surface 319.

[0045] Figure 8 is a cross-sectional schematic of the coated substrate 810, which is the etched substrate 710 after removing the organic layer 626 and subsequently depositing a dielectric layer 830 on the etched substrate 710. The combination of the dielectric layer 830 and the layer portion 532 is an example of the dual capacitance dielectric layer 330, where the thickness of the dual capacitance dielectric layer 330 is configured to modulate the capacitance of different portions of a vertical transfer gate (e.g., the vertical transfer gate 250) to facilitate charge transfer.

[0046] Figure 9 is a cross-sectional schematic of the coated substrate 910, which in embodiments is produced by removing the organic layer 626 from the etched substrate 710 and depositing a dielectric layer 930 on the etched substrate 710. The dielectric layer 930 and the layer portion 532 differ by at least one of their respective dielectric constants and respective thicknesses. The combination of the dielectric layer 930 and the layer portion 532 is an example of the dual capacitance dielectric layer 330, where the thickness and dielectric constant of the dual capacitance dielectric layer 330 are configured to modulate the capacitance of different portions of a vertical transfer gate (e.g., the vertical transfer gate 250) to facilitate charge transfer. In embodiments, the layer portion 532 and the dielectric layer 930 have respective dielectric constants 532 and 930 respective thicknesses t 532 and t 930 and respective area-normalized capacitances K 532 / t 532 and K 930 / t 930 where K 930 / t 930 exceeds K 532 / t 532 .

[0047] Figure 10is a flowchart illustrating a method 1000 for fabricating a transfer gate. The method 1000 includes steps 1010, 1020, 1030, and 1050. In embodiments, the method 1000 also includes at least one of steps 1040 and 1060.

[0048] Step 1010 includes lining a surface of a trench with a first dielectric layer. The trench extends into a top surface (e.g., a front side surface) of a semiconductor substrate and has a trench depth relative to a planar region of the top surface surrounding the trench. The semiconductor substrate includes a photodiode region adjacent to the trench, the photodiode region being implanted by ion implantation onto the top surface of the semiconductor substrate and formed in the semiconductor substrate at a photodiode depth relative to the planar region. The photodiode depth is less than the trench depth relative to the planar region. In an example of step 1010, a dielectric layer 530 is deposited on the surface 319 of the semiconductor substrate 310 such that the dielectric layer 530 lines the surface 319, which results in Figure 5 a coated substrate 510.

[0049] Step 1020 includes covering a bottom region of the first dielectric layer with an organic layer, the bottom region extending from the trench depth to an etch depth that does not exceed the photodiode depth relative to the planar region. That is, a distance between the planar region and the etch depth is less than a distance between the planar region and the depth of the top surface of the top photodiode portion. For example, a depth of a top surface of the organic layer 626 relative to the planar region is less than a depth of the top portion of the photodiode region 340. In an example of step 1020, the organic layer 626 is deposited in the trench 320 of the coated substrate 510 such that the organic layer 626 covers the layer portion 532, which results in Figure 6 a coated substrate 610.

[0050] Step 1030 includes etching a top region of the first dielectric layer (e.g., high-k material or silicon dioxide) at a depth between the top surface and the etch depth. In an example of step 1030, the layer portion 531 is etched to result in Figure 7 an etched substrate 710. Step 1040 includes removing the organic layer after etching the top region. In an example of step 1040, the organic layer 626 is removed from the etched substrate 710 by dry etching, wet etching, or a combination of dry and wet etching processes.

[0051] Step 1050 includes depositing a second dielectric layer, such as silicon dioxide, on the surface of the trench at a depth between the planar region and the trench depth. In embodiments, the second dielectric layer can be deposited conformally to sidewall surfaces of the trench. In a first example of step 1050, a dielectric layer 830 is deposited on the surface 319 and the surface 538 to result in Figure 8coated substrate 810. In a second example of step 1050, a dielectric layer 930 is deposited on the surface 319 and the surface 538 to produce a coated substrate 910. Figure 9 coated substrate 810. In a second example of step 1050, a dielectric layer 930 is deposited on the surface 319 and the surface 538 to produce a coated substrate 910.

[0052] Step 1060 includes filling the trench with a gate electrode material. In an example of step 1060, the trench 320 of the coated substrate is filled with the gate electrode material 325 to produce a pixel 300.

[0053] Combinations of features

[0054] The above features, as well as the features claimed below, can be combined in various ways without departing from the scope of the invention. The following enumerated examples illustrate some possible non-limiting combinations:

[0055] (A1) A pixel comprising a semiconductor substrate, a photodiode region, a floating diffusion region, and a dielectric layer. The semiconductor substrate has a substrate top surface that forms a trench extending into the semiconductor substrate. The trench has a trench depth relative to a planar region of the substrate top surface surrounding the trench. The photodiode region is in the semiconductor substrate and comprises (i) a bottom photodiode portion under the trench, (ii) a top photodiode portion adjacent to the trench, the top photodiode portion beginning at a photodiode depth less than the trench depth, extending toward and abutting the bottom photodiode region, the photodiode depth being relative to the planar region. The floating diffusion region is in the semiconductor substrate, adjacent to the trench, and extends away from the planar region to a junction depth less than the trench depth. The dielectric layer lines the trench. A top region of the dielectric layer is between the planar region and the junction depth and has a top thickness. A bottom region of the dielectric layer is between the photodiode depth and the trench depth and has a bottom thickness that exceeds the top thickness.

[0056] (A2) In any of the pixels (A1), the dielectric layer can have a relative permittivity greater than or equal to that of silicon dioxide.

[0057] (A3) In any of the pixels (A1) and (A2), the bottom region can comprise a plurality of material layers.

[0058] (A4) In any of the pixels (A3), the bottom region can comprise a first dielectric layer and a second dielectric layer, wherein the first dielectric layer and the second dielectric layer are formed of different respective dielectric materials.

[0059] (A5) In any of the pixels (A3), the bottom region can comprise a first dielectric layer and a second dielectric layer, wherein the first dielectric layer and the second dielectric layer are formed of the same dielectric material.

[0060] (A6) In any of pixels (Al) - (A5), the bottom thickness can exceed the top thickness by at least two times.

[0061] (A7) In any of pixels (A6), the bottom thickness can exceed the top thickness by between two and five times.

[0062] (A8) In any of pixels (Al) - (A7), the top thickness can be between two nanometers and ten nanometers.

[0063] (A9) In any of pixels (Al) - (A8), the trench depth can be between 0.1 microns and 0.9 microns.

[0064] (A10) In any of pixels (Al) - (A9), the trench can have a width between 0.05 microns and 0.3 microns in a plane parallel to the planar region.

[0065] (A11) In any of pixels (Al) - (A10), the semiconductor substrate can be p-doped, the photodiode region can be n-doped, and the floating diffusion region can be n + doped.

[0066] (A12) Any of pixels (Al) - (A11) can further include a gate electrode material filling the trench. The trench, the dielectric layer, and the gate electrode material form a vertical transfer gate electrically connected to the photodiode region via the bottom region and the top photodiode portion.

[0067] (A13) In any of pixels (A12), the gate electrode material can include at least one of polysilicon and metal.

[0068] (A14) An image sensor includes a plurality of any of pixels (Al) - (A13). For each of the plurality of pixels, the semiconductor substrate is part of a same semiconductor substrate of the image sensor.

[0069] (B1) A pixel includes a semiconductor substrate, a photodiode region in the semiconductor substrate, a floating diffusion region in the semiconductor substrate, a dielectric layer lining a trench, and a gate electrode material filling the trench. The semiconductor substrate has a substrate top surface forming the trench, the trench extending into the semiconductor substrate and having a trench depth relative to a planar region of the substrate top surface surrounding the trench. The photodiode region includes (i) a bottom photodiode portion under the trench and (ii) a top photodiode portion adjacent the trench, the top photodiode portion beginning at a photodiode depth less than the trench depth, extending toward and abutting the bottom photodiode region. The photodiode depth is relative to the planar region. The floating diffusion region is in the semiconductor substrate, adjacent the trench, and extends away from the planar region to a junction depth less than the trench depth. The dielectric layer has a top region formed between the planar region and the junction depth, and a bottom region formed between the photodiode depth and the trench depth.

[0070] (B2) In any of the pixels (B1), the semiconductor substrate, the gate electrode material, and the bottom region therebetween form a first capacitor having a first capacitance, and the semiconductor substrate, the gate electrode material, and the top region therebetween form a second capacitor having a second capacitance exceeding the first capacitance.

[0071] (B3) In any of the pixels (B1), the bottom region can be formed of a first dielectric having a first dielectric constant, and the top region can be formed of a second dielectric having a second dielectric constant exceeding the first dielectric constant.

[0072] (B4) In any of the pixels (B1), (B2), and (B3), the bottom region can include a plurality of material layers.

[0073] (C1) A transfer gate fabrication method includes lining a surface of a trench with a first dielectric layer. The trench extends into a top surface of a semiconductor substrate and has a trench depth relative to a planar region of the top surface surrounding the trench. The semiconductor substrate includes a photodiode region adjacent the trench and extending toward the planar region to a photodiode depth relative to the planar region less than the trench depth. The method further includes covering a bottom region of the first dielectric layer with an organic layer. The bottom region extends from the trench depth to an etch depth not exceeding the photodiode depth. The method further includes etching a top region of the first dielectric layer at a depth between the top surface and the etch depth, and depositing a second dielectric layer on the surface of the trench at a depth between the planar region and the trench depth. In the bottom region, the first dielectric layer and a portion of the second dielectric layer adjacent thereto have an effective dielectric constant K b and a thickness d b . In the top region, the second dielectric layer has a dielectric constant K t and a thickness dt . business κ t / d t can exceed business κ b / d b .

[0074] (C2) The method (C1) can include removing the organic layer after etching the top region.

[0075] (C3) Either of the methods (C1) and (C2) can include filling the trench with a gate electrode material.

[0076] Changes can be made to the above-described methods and systems without departing from the scope of the application. Accordingly, it is intended to be covered by the following claims and their equivalents. It should be noted that the above-described embodiments are merely meant to be illustrative and not limiting. In this document, the terms "example" and "exemplary" mean "an instance of something," and not "the best of its kind." The phrase "in an example" is equivalent to the phrase "in a particular example," and does not mean that all examples are the same. The accompanying claims are intended to cover all general and specific features of the methods and systems described herein, and all statements of the scope of the methods and systems, which, as language, can be said to fall under the fair meaning of the claims.

Claims

1. A pixel, comprising: a semiconductor substrate having a substrate top surface forming a trench, the trench extending into the semiconductor substrate and having a trench depth relative to a planar region of the substrate top surface surrounding the trench; a photodiode region in the semiconductor substrate and including (i) a bottom photodiode portion, having a first conductivity type, under the trench, and (ii) a top photodiode portion, having the first conductivity type, adjacent the trench, the top photodiode portion beginning at a photodiode depth less than the trench depth, extending toward and abutting the bottom photodiode portion, the photodiode depth being relative to the planar region; and a floating diffusion region in the semiconductor substrate, adjacent the trench, and extending away from the planar region to a junction depth less than the trench depth; and a dielectric layer lining the trench, a top region of the dielectric layer between the planar region and the junction depth having a top thickness, a bottom region of the dielectric layer between the photodiode depth and the trench depth having a bottom thickness that exceeds the top thickness; the bottom region includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer does not cover the planar region, directly contacts the trench bottom inner wall and lower sidewall; the second dielectric layer lines the trench, continuously spans between the planar region and the first dielectric layer to cover at least part of the planar region, at least part of the top region of the dielectric layer, and the first dielectric layer.

2. The pixel of claim 1, the dielectric layer having a relative dielectric constant greater than or equal to that of silicon dioxide.

3. The pixel of claim 1, wherein the first dielectric layer and the second dielectric layer are formed of the same dielectric material. In the bottom region, a portion of the first dielectric layer and the second dielectric layer adjacent thereto have an effective dielectric constant and a thickness In the top region, the second dielectric layer has a dielectric constant and a thickness wherein more than .

4. The pixel of claim 1, wherein the first dielectric layer and the second dielectric layer are formed of different respective dielectric materials.

5. The pixel of claim 1, the bottom thickness exceeding the top thickness by at least a factor of two.

6. The pixel of claim 5, the bottom thickness exceeding the top thickness by a factor of between two and five.

7. The pixel of claim 1, the top thickness being between 2 nanometers and 10 nanometers.

8. The pixel of claim 1, the trench depth being between 0.1 microns and 0.9 microns.

9. The pixel of claim 1, the trench having a width in a plane parallel to the planar region of between 0.05 microns and 0.3 microns.

11. The pixel of claim 1, further comprising a gate electrode material filling the trench; the trench, the dielectric layer, and the gate electrode material forming a vertical transfer gate electrically connected to the photodiode region via the bottom region and the top photodiode portion.

12. The pixel of claim 11, the gate electrode material including at least one of polysilicon and a metal.

10. The pixel of claim 1, said semiconductor substrate being doped, said photodiode region being doped, and said floating diffusion region being doped. ​ ​ 13. An image sensor comprising a plurality of pixels as claimed in claim 1, for each of the plurality of pixels, the semiconductor substrate being part of a same semiconductor substrate of the image sensor.

14. A pixel comprising: a semiconductor substrate having a substrate top surface forming a trench, the trench extending into the semiconductor substrate and having a trench depth relative to a planar region of the substrate top surface surrounding the trench; a photodiode region in the semiconductor substrate and comprising (i) a bottom photodiode portion, having a first conductivity type, under the trench, and (ii) a top photodiode portion, having the first conductivity type, adjacent the trench, the top photodiode portion beginning at a photodiode depth less than the trench depth, extending toward and abutting the bottom photodiode portion, the photodiode depth being relative to the planar region; and a floating diffusion region in the semiconductor substrate, adjacent the trench, and extending away from the planar region to a junction depth less than the trench depth; and a dielectric layer lining the trench, the dielectric layer having a top region formed between the planar region and the junction depth, and a bottom region formed between the photodiode depth and the trench depth; the bottom region comprising a first dielectric layer and a second dielectric layer, wherein the first dielectric layer does not cover the planar region, directly contacting the trench bottom inner wall and lower sidewall; the second dielectric layer lining the trench, continuously spanning between the planar region and the first dielectric layer to cover at least part of the planar region, at least part of the dielectric layer top region, and the first dielectric layer; a gate electrode material filling the trench; wherein the semiconductor substrate, the gate electrode material, and the bottom region therebetween form a first capacitor having a first capacitance; wherein the semiconductor substrate, the gate electrode material, and the top region therebetween form a second capacitor having a second capacitance exceeding the first capacitance; 15. The pixel of claim 14, the bottom region being formed of a first dielectric having a first dielectric constant, the top region being formed of a second dielectric having a second dielectric constant exceeding the first dielectric constant.

16. A transfer gate fabrication method comprising: In the bottom region, a portion of the first dielectric layer and the second dielectric layer adjacent thereto have an effective dielectric constant and a thickness In the top region, the second dielectric layer has a dielectric constant and a thickness wherein exceeds . lining a surface of a trench with a first dielectric layer, the trench extending into a top surface of a semiconductor substrate and having a trench depth relative to a planar region of the top surface surrounding the trench, the semiconductor substrate comprising a photodiode region adjacent the trench and formed at a photodiode depth and extending away from the planar region, wherein the photodiode depth is less than the trench depth relative to the planar region; ​ ​ covering a bottom region of the first dielectric layer with an organic layer, the bottom region extending from the trench depth to an etch depth no more than the photodiode depth relative to the planar region; etching a top region of the first dielectric layer at a depth between the top surface and the etch depth such that the first dielectric layer does not cover the planar region and is in direct contact with the trench bottom inner wall and lower sidewall; and depositing a second dielectric layer on a surface of the trench at a depth between the planar region and the trench depth such that the second dielectric layer covers at least a portion of the planar region, at least a portion of the dielectric layer top region, and covers the first dielectric layer; In the bottom region, a portion of the first dielectric layer and the second dielectric layer adjacent thereto have an effective dielectric constant and a thickness In the top region, the second dielectric layer has a dielectric constant and a thickness wherein more than .

17. The method of claim 16, further comprising removing the organic layer after etching the top region.

18. The method of claim 16, further comprising filling the trench with a gate electrode material.

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