Image sensor using a boost capacitor and a negative bias voltage

Abstract

An image sensor includes a photodiode that generates electric charges in response to light, a transfer transistor connected to the photodiode and a floating diffusion, a reset transistor connected between the floating diffusion and a power node, a boost capacitor connected to the floating diffusion and adjusting a capacity of the floating diffusion in response to a boost control signal, and a bias circuit having a first current circuit and a second current circuit for supplying different bias currents to an output node to which a voltage signal corresponding to electric charges accumulated in the floating diffusion is output. After the transfer transistor is turned off, the boost control signal is lowered from a high level to a low level, and the reset transistor is switched from an on state to an off state when the bias currents of the first current circuit and the second current circuit are simultaneously supplied to the output node.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0089435, filed on July 24, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] An exemplary embodiment of the present invention relates to an image sensor using a boost capacitor and a negative bias voltage. Background Technology

[0004] An image sensor is a semiconductor-based sensor that receives light to generate electrical signals. It may include a pixel array with multiple pixels, logic circuitry for driving the pixel array and generating an image, etc. The multiple pixels may include photodiodes and pixel circuitry; the photodiodes generate electrical charges in response to external light, and the pixel circuitry converts the charges generated by the photodiodes into electrical signals. Besides cameras used to capture photos or videos, image sensors are widely used in smartphones, tablet PCs, laptops, televisions, vehicles, and more. Recently, as image sensors have become increasingly smaller, various methods have been proposed to increase power efficiency. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, an image sensor includes: a photodiode configured to generate charge in response to light; a transfer transistor connected to the photodiode and a floating diffuser in response to a transmission control signal; a reset transistor connected between the floating diffuser and a power node; a boost capacitor connected to the floating diffuser and configured to adjust the capacitance of the floating diffuser in response to a boost control signal; and a bias circuit having a first current circuit and a second current circuit, the first current circuit and the second current circuit being configured to supply different bias currents to an output node that outputs a voltage signal corresponding to the charge accumulated in the floating diffuser. After the transfer transistor is turned off, the boost control signal drops from a high level to a low level, and during a first time period during which the first bias current of the first current circuit and the second bias current of the second current circuit are simultaneously supplied to the output node, the reset transistor switches from an on state to an off state.

[0006] According to an exemplary embodiment of the present inventive concept, an image sensor includes a photodiode configured to generate a charge in response to light, a transfer transistor connecting the photodiode and a floating diffusion in response to a transfer control signal, a reset transistor connected between the floating diffusion and a power node, and a booster capacitor connected to the floating diffusion and configured to adjust a capacity of the floating diffusion in response to a booster control signal. The booster control signal increases from a low level to a high level before the transfer transistor is turned on, and decreases from the high level to the low level after the transfer transistor is turned off.

[0007] According to an exemplary embodiment of the present inventive concept, an image sensor includes a first semiconductor chip including a photodiode configured to generate a charge in response to light, a reset transistor connected between a floating diffusion and a power node, a transfer transistor configured to transfer the charge generated by the photodiode to the floating diffusion, a bias voltage supply terminal configured to supply a bias voltage to the photodiode and the floating diffusion, and an output node configured to output a voltage signal corresponding to the charge accumulated in the floating diffusion, and a second semiconductor chip connected to the output node through a metal pad and including a first current circuit configured to output a first bias current. The bias voltage is a negative voltage with respect to a ground voltage of the second semiconductor chip. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and other aspects and features of the present inventive concept will become clearer from the following detailed description of exemplary embodiments thereof, taken in conjunction with the accompanying drawings.

[0009] Figure 1 FIG. 1 is a view schematically illustrating an image processing apparatus including an image sensor according to an exemplary embodiment of the present inventive concept.

[0010] Figure 2 and Figure 3 FIG. 2 is a view schematically illustrating an image sensor according to an exemplary embodiment of the present inventive concept.

[0011] Figure 4 FIG. 3 is a view for illustrating an operation of an image sensor according to an exemplary embodiment of the present inventive concept.

[0012] Figure 5 FIG. 4 is a view for illustrating an operation of an image sensor according to an exemplary embodiment of the present inventive concept.

[0013] Figure 6 FIG. 5 is a view for illustrating an operation of an image sensor according to an exemplary embodiment of the present inventive concept.

[0014] Figure 7 FIG. 6 is a view illustrating an image sensor according to an exemplary embodiment of the present inventive concept.Figure 6 a timing chart showing the operation of the image sensor of

[0015] Figure 8A and Figure 8B is a diagram showing the change of potential barriers of elements constituting a unit pixel in the image sensor of Figure 6

[0016] Figure 9 is a timing chart showing the operation of the image sensor according to the example embodiment of the present inventive concept.

[0017] Figure 10 is a view for showing the operation of the image sensor according to the example embodiment of the present inventive concept.

[0018] Figure 11 is a timing chart showing the operation of the image sensor during the horizontal scanning time of one cycle according to the example embodiment of the present inventive concept.

[0019] Figure 12 is a view for showing the operation of the image sensor according to the example embodiment of the present inventive concept.

[0020] Figure 13 is a timing chart showing the operation of the image sensor of Figure 12

[0021] Figure 14A and Figure 14B is a diagram showing the change of potential barriers of elements constituting a unit pixel in the image sensor of Figure 12

[0022] Figure 15 is a view for showing the operation of the image sensor according to the example embodiment of the present inventive concept.

[0023] Figure 16 is a timing chart showing the operation of the image sensor of Figure 15

[0024] Figure 17A and Figure 17B is a diagram showing the change of potential barriers of elements constituting a unit pixel in the image sensor of Figure 15

[0025] Figure 18 is a view for showing the operation of the image sensor according to the example embodiment of the present inventive concept.

[0026] Figure 19 ​​​​​is a timing diagram for illustrating an operation of an image sensor according to an exemplary embodiment of the present inventive concept.

[0027] Figure 20 is a block diagram schematically illustrating an electronic device including an image sensor according to an exemplary embodiment of the present inventive concept. DETAILED DESCRIPTION

[0028] Exemplary embodiments of the present inventive concept relate to an image sensor that can reduce a power supply voltage applied to a pixel and can shorten a settling time for stabilizing a voltage of a column line connected to the pixel.

[0029] Hereinafter, exemplary embodiments of the present inventive concept will be described with reference to the accompanying drawings. Like reference numerals can refer to like elements throughout the application.

[0030] Figure 1 is a view schematically illustrating an image processing apparatus including an image sensor according to an exemplary embodiment of the present inventive concept.

[0031] Reference Figure 1 An image processing apparatus 1 according to exemplary embodiments of the present inventive concept can include an image sensor 10 and an image processor 20. The image sensor 10 can include a pixel array 11, a row driver 12, a switching circuit 13, a bias circuit 14, a readout circuit 15, a timing controller 16, etc. The row driver 12, the switching circuit 13, the bias circuit 14, the readout circuit 15, and the timing controller 16 can be circuits for generating image data used to control the pixel array 11, and can be included in a control logic.

[0032] The image sensor 10 can operate according to a control command received from the image processor 20, and can convert light transmitted from an object 30 into an electrical signal and output the converted signal to the image processor 20. The pixel array 11 included in the image sensor 10 can include a plurality of pixels PX, which can each include a photoelectric device, such as a photodiode (PD), that receives light to generate an electric charge. In exemplary embodiments of the present inventive concept, each of the plurality of pixels PX can include two or more photoelectric devices. Two or more photoelectric devices can be included in each of the plurality of pixels PX for the purpose of generating a pixel signal corresponding to light of various colors or providing an auto focus function.

[0033] Meanwhile, each of the plurality of pixels PX can include a pixel circuit for generating a pixel signal from the electric charge generated by the photodiode. In an exemplary embodiment of the present inventive concept, the pixel circuit can include a transfer transistor, a drive transistor, a selection transistor, a reset transistor, etc. The pixel circuit can obtain the pixel signal by detecting a reset voltage and a pixel voltage from each of the plurality of pixels PX and by calculating a difference between the reset voltage and the pixel voltage. The pixel voltage can be a voltage reflecting the electric charge generated in the photodiode included in each of the plurality of pixels PX. In an exemplary embodiment of the present inventive concept, two or more pixels PX adjacent to each other can constitute one pixel group, and the two or more pixels PX included in the pixel group can share at least a part of the transfer transistor, the drive transistor, the selection transistor, and the reset transistor with each other.

[0034] The row driver 12 can drive the pixel array 11 in units of rows. For example, the row driver 12 can generate a transfer control signal for controlling a transfer transistor of the pixel circuit, a reset control signal for controlling a reset transistor, a selection control signal for controlling a selection transistor, etc.

[0035] The readout circuit 15 can include a correlated double sampler (CDS), an analog-to-digital converter (ADC), etc. The correlated double sampler can be connected to the pixels PX included in the row selected by the row selection signal provided by the row driver 12 through the column line, and can perform correlated double sampling to detect a reset voltage and a pixel voltage. The analog-to-digital converter can convert the reset voltage and the pixel voltage detected by the correlated double sampler into a digital signal and output the digital signal.

[0036] The bias circuit 14 can input a predetermined bias current to the column line connected to the pixels PX while the readout circuit 15 detects the reset voltage and the pixel voltage from the pixels PX. The bias circuit 14 can include a plurality of current circuits corresponding to the column lines. The switch circuit 13 can set a connection path of the plurality of current circuits and the column lines.

[0037] The operations of the row driver 12, the switch circuit 13, the bias circuit 14, and the readout circuit 15 can be determined by the timing controller 16, and the timing controller 16 can operate by a control command transmitted by the image processor 20. The image processor 20 can process the image data output by the readout circuit 15 and output the image data to a display device or the like, or store the image data in a storage device such as a memory or the like. Alternatively, when the image processing apparatus 1 is installed on an autonomous vehicle, the image processor 20 can process the image data and transmit the image data to a main controller for controlling the autonomous vehicle.

[0038] Figure 2 and Figure 3is a view schematically illustrating an image sensor according to an exemplary embodiment of the present inventive concept.

[0039] First, referring to Figure 2 An image sensor 2 according to an exemplary embodiment of the present inventive concept can include a first layer 40, a second layer 50 disposed below the first layer 40, and a third layer 60 disposed below the second layer 50, etc. The first layer 40, the second layer 50, and the third layer 60 can be stacked with each other, for example, in a direction perpendicular to surfaces thereof. In an exemplary embodiment of the present inventive concept, the first layer 40 and the second layer 50 can be stacked with each other at a wafer level, and the third layer 60 can be attached to a lower portion of the second layer 50 at a chip level. The first layer 40 to the third layer 60 can be disposed in one semiconductor package.

[0040] The first layer 40 can include a sensing area SA in which a plurality of pixels PX are disposed, and a first pad area PA1 disposed around the sensing area SA. The first pad area PA1 can include a plurality of upper pads PAD, and the plurality of upper pads PAD can be connected to pads and control logic LC disposed in a second pad area PA2 of the second layer 50 through vias, etc.

[0041] Each of the plurality of pixels PX can include a photodiode that receives light to generate a charge, a pixel circuit that processes the charge generated by the photodiode, etc. The pixel circuit can include a plurality of transistors for outputting a voltage corresponding to the charge generated by the photodiode.

[0042] The second layer 50 can include a plurality of devices that provide control logic LC. The plurality of devices included in the control logic LC can provide a circuit for driving the pixel circuit disposed in the first layer 40, such as a row driver, a column driver, a timing controller, etc. The plurality of devices included in the control logic LC can be connected to the pixel circuit through the first pad area PA1 and the second pad area PA2. The control logic LC can generate a pixel signal by obtaining a reset voltage and a pixel voltage from the plurality of pixels PX.

[0043] In an exemplary embodiment of the present inventive concept, at least one of the plurality of pixels PX can include a plurality of photodiodes disposed at the same stage. Pixel signals generated according to charges of each of the plurality of photodiodes can have a phase difference from each other, and the control logic LC can provide an auto focus function based on the phase difference of the pixel signals generated according to the plurality of photodiodes included in one pixel PX.

[0044] A third layer 60 disposed below the second layer 50 can include a memory chip MC, a dummy chip DC, and an encapsulation layer EN for encapsulating the memory chip MC and the dummy chip DC. The memory chip MC can be a dynamic random access memory (DRAM) or a static random access memory (SRAM), and the dummy chip DC can not have a function of actually storing data. The memory chip MC can be electrically connected to at least a part of devices included in the control logic LC of the second layer 50 through a bump, and can store information to provide an auto focus function. In an exemplary embodiment of the inventive concept, the bump can be a micro bump.

[0045] Next, referring to Figure 3 , an image sensor 3 according to an exemplary embodiment of the inventive concept can include a first layer 70 and a second layer 80. The first layer 70 can include a sensing area SA provided with a plurality of pixels PX, a control logic LC provided with devices for driving the plurality of pixels PX, and a first pad area PA1 provided at a periphery of the sensing area SA and the control logic LC. The first pad area PA1 can include a plurality of upper pads PAD, and the plurality of upper pads PAD can be connected to a memory chip MC provided in the second layer 80 through a via or the like. The second layer 80 can include the memory chip MC, a dummy chip DC, and an encapsulation layer EN for encapsulating the memory chip MC and the dummy chip DC.

[0046] Figure 4 is a view for illustrating an operation of an image sensor according to an exemplary embodiment of the inventive concept. Referring to Figure 4 , the image sensor 100 can include a pixel array 110, a row driver 120, a switch circuit 130, a bias circuit 140, and a readout circuit 150, etc. The bias circuit 140 can include a first bias circuit 141 outputting a first bias current and a second bias circuit 142 outputting a second bias current. The switch circuit 130 can connect each of a plurality of column lines connected to a plurality of pixels in the pixel array 110 to the first bias circuit 141 or the second bias circuit 142.

[0047] Figure 5 is a view for illustrating an operation of an image sensor according to an exemplary embodiment of the inventive concept. Referring to Figure 5 , a pixel array PA of an image sensor according to an exemplary embodiment of the inventive concept can include a plurality of pixels PX. The plurality of pixels PX can be connected to a plurality of row lines ROW (ROW1 to ROW m ) and a plurality of column lines COL (COL1 to COL n). The image sensor can drive a plurality of pixels PX in units of a plurality of row lines ROW. For example, a time required for driving a selection driving line in a row line ROW and reading a reset voltage and a pixel voltage from a pixel PX connected to the selection driving line can be defined as one horizontal period. The image sensor can operate in a rolling shutter method of sequentially driving a plurality of row lines ROW.

[0048] Meanwhile, a frame time period FT of the image sensor can be defined as a time required for reading a reset voltage and a pixel voltage from all pixels PX included in the pixel array PA. For example, the frame time period FT can be greater than or equal to a product of the number of row lines ROW and the horizontal period. The shorter the frame time period FT of the image sensor, the greater the number of image frames the image sensor can generate during the same time period.

[0049] Power consumption of the image sensor can be defined as a product of a power supply voltage applied to the pixel PX and a current flowing in the pixel PX. A low-power image sensor can be implemented by reducing the power supply voltage applied to the pixel PX or by reducing the current in the pixel PX.

[0050] According to an exemplary embodiment of the present inventive concept, the bias circuit 140 can output a second bias current to the column line COL at least for a time in one horizontal period in which a first bias current is input to the column line COL connected to the pixel PX. By using the first bias current and the second bias current, a stabilization time for stabilizing a voltage of the column line COL can be shortened. Accordingly, performance of the image sensor 100 can be improved without significantly increasing an amount of current flowing in the pixel PX.

[0051] According to an exemplary embodiment of the present inventive concept, a booster capacitor can be used to increase a capacitance of a floating diffusion to reduce a power supply voltage applied to the pixel PX. According to an exemplary embodiment of the present inventive concept, a power supply voltage applied to the pixel PX can be reduced by supplying a negative bias voltage to the photodiode and the floating diffusion. Accordingly, a low-power image sensor can be implemented.

[0052] Figure 6 is a view for illustrating an operation of an image sensor according to an exemplary embodiment of the present inventive concept. Referring to Figure 6 The pixel included in the image sensor 200 can include a photodiode PD generating a charge in response to light, a pixel circuit processing the charge generated by the photodiode PD and outputting an electrical signal, etc. For example, the pixel circuit can include a floating diffusion FD, a booster capacitor C2, a reset transistor RX, a driving transistor DX, a selection transistor SX, a transfer transistor TX, etc.

[0053] The reset voltage and the pixel voltage of the pixel can be output to the column line COL through the output node ND2. The image sensor 200 can include a first switch SW1 and a first current circuit CS1. The first switch SW1 can connect the first current circuit CS1 to the column line COL. The first switch SW1 can control the first current circuit CS1 to supply a first bias current Ib1 to the column line COL while performing a readout operation on the pixel.

[0054] The reset transistor RX can be connected between a power supply node ND1 that supplies a power supply voltage VDD and a floating diffusion FD, and can be controlled by a reset control signal RG. For example, when the reset transistor RX is turned on, the voltage of the floating diffusion FD can be reset to the power supply voltage VDD. When the voltage of the floating diffusion FD is reset, the selection transistor SX can be turned on by the selection control signal SEL, so that the reset voltage can be output to the column line COL through the output node ND2.

[0055] In an exemplary embodiment of the inventive concept, the photodiode PD can generate electrons or holes as a primary charge carrier in response to light. When the transfer transistor TX is turned on in response to a transfer control signal TG after the reset voltage is output to the column line COL, the charge generated by the photodiode PD can move to the floating diffusion FD. The drive transistor DX can function as a source follower amplifier for amplifying the voltage of the floating diffusion FD. The current Ipix can flow through the drive transistor DX. When the selection transistor SX is turned on by the selection control signal SEL, the pixel voltage corresponding to the charge generated by the photodiode PD can be output to the column line COL through the output node ND2.

[0056] Since the floating diffusion FD accumulates the charge corresponding to the reset voltage or the charge corresponding to the pixel voltage, the floating diffusion FD can be modeled as a capacitor C1 unique to the floating diffusion FD. A boost capacitor C2 can be connected between the floating diffusion FD and a control node ND3. The control node ND3 can output a boost control signal FDB to the boost capacitor C2. The boost control signal FDB can control the capacitance of the floating diffusion FD. According to the boost control signal FDB, the capacitance of the floating diffusion FD can correspond to the sum of the capacitance of the capacitor C1 and the capacitance of the boost capacitor C2, but is not limited thereto.

[0057] Each of the reset voltage and the pixel voltage can be detected by a sampling circuit connected to the column line COL. The sampling circuit can include a plurality of samplers having first input terminals and second input terminals, and the samplers can receive the ramp voltage through the first input terminals. The samplers can compare the ramp voltage input to the first input terminals with the reset voltage or the pixel voltage input to the second input terminals. An analog-to-digital converter (ADC) can be connected to output terminals of the samplers, and the analog-to-digital converter can output reset data corresponding to a comparison result of the ramp voltage and the reset voltage and pixel data corresponding to a comparison result of the ramp voltage and the pixel voltage. Control logic can generate image data by using a pixel signal corresponding to a difference between the reset data and the pixel data.

[0058] In an exemplary embodiment of the inventive concept, a power voltage VDD applied to a pixel can be reduced by increasing a capacitance of a floating diffusion FD using a booster capacitor C2.

[0059] Figure 7 is a timing chart illustrating an operation of an image sensor according to an exemplary embodiment of the inventive concept, Figure 6 Figure 8A and Figure 8B is a graph illustrating a change in a potential barrier of an element constituting a unit pixel in an image sensor according to an exemplary embodiment of the inventive concept. Figure 6

[0060] Figure 8A illustrates potential levels when a booster control signal is at a low level, and Figure 8B illustrates potential levels when the booster control signal is at a high level. In Figure 8A and Figure 8B , a potential (e.g., a voltage level) in a vertical direction illustrates a negative potential upward and a positive potential downward.

[0061] Referring to Figure 7 and Figure 8A , at t1, a selection control signal SEL can have a high level, and a reset control signal RG can have a low level. Figure 8A illustrates potential levels at t1. A potential Vim of the image sensor can be a sum of a potential Vpd of the photodiode and a potential VFD of the floating diffusion. PD FD

[0062] To increase the potential Vim of the image sensor, the potential Vpd of the photodiode can be increased. PD PD PD ​​​​The voltage difference between the ground voltage 0V and the first power supply voltage VDD1 can be increased. However, when the voltage difference between the ground voltage 0V and the first power supply voltage VDD1 is increased, the power consumption of the image sensor can also increase.

[0063] Referring to Figure 7 and Figure 8A , the boost control signal FDB can transition from a low level to a high level at t2. The boost control signal FDB can maintain the high level for a time period from t2 to t6. After the boost control signal FDB transitions from the low level to the high level, the transfer control signal TG can transition from the low level to the high level at t3. When the transfer control signal TG transitions from the low level to the high level, the transfer transistor TX is turned on.

[0064] At t4, the boost control signal FDB can have the high level and the transfer control signal TG can have the high level. Figure 8B The potential level at t4 is shown. When the boost control signal FDB is maintained at the high level, the capacitance of the floating diffusion FD can increase, and the potential of the floating diffusion FD can be higher than the potential of the non-floating diffusion FD. Figure 8A The potential of the non-floating diffusion FD when the boost control signal FDB is at the low level is V FD In contrast, the potential of the floating diffusion FD when the boost control signal FDB is at the high level is V FD ' can increase in the negative direction. In other words, the absolute value of the potential of the floating diffusion FD can increase. Thus, the potential Vim of the image sensor can be achieved equally even when the second power supply voltage VDD2 lower than the first power supply voltage VDD1 is applied.

[0065] When the transfer transistor TX is turned on, the charge generated in the photodiode PD when exposed to light can move to the floating diffusion FD. After the charge generated in the photodiode PD moves to the floating diffusion FD, the transfer transistor TX can be turned off at t5. After the transfer transistor TX is turned off, the boost control signal FDB can transition from the high level to the low level at t6.

[0066] By using the boost capacitor C2, the image sensor 200 according to the exemplary embodiment of the inventive concept can increase the capacitance of the floating diffusion FD for a time from t2 to t6. Thus, when the transfer transistor TX is turned on and the charge of the photodiode PD moves to the floating diffusion FD, the capacitance of the floating diffusion FD can increase, and the power supply voltage VDD applied to the pixel to achieve the same potential Vim in the image sensor can be reduced. Thus, the power consumption of the image sensor can be reduced.

[0067] Figure 9 is a timing diagram illustrating the operation of the image sensor according to the exemplary embodiment of the inventive concept. With reference to Figure 7Different from Figure 9 In the embodiment, when the transfer control signal TG transitions from the low level to the high level at t3, the boost control signal FDB can transition from the low level to the high level at t4. When the boost control signal FDB transitions from the low level to the high level after the transfer transistor TX is turned on, the electric charges in the photodiode PD region can be retained without being transferred to the floating diffusion FD region. The remaining electric charges can be used as an error factor of the image sensor 200, such as a leakage, etc.

[0068] Figure 10 is a view for illustrating an operation of an image sensor according to an exemplary embodiment of the inventive concept. As with Figure 6 Different from the image sensor 200 of Figure 10 The image sensor 300 can further include a second switch SW2 and a second current circuit CS2. The second switch SW2 can connect the second current circuit CS2 to the column line COL.

[0069] The first current circuit CS1 can supply a first bias current Ib1 to the column line COL, and the second current circuit CS2 can supply a second bias current Ib2 to the column line COL. The first bias current Ib1 and the second bias current Ib2 can have different magnitudes, but are not limited thereto, and the first bias current Ib1 and the second bias current Ib2 can have the same magnitude as each other.

[0070] According to an exemplary embodiment of the inventive concept, the second switch SW2 can control the second current circuit CS2 so that the second bias current Ib2 is supplied to the column line COL only when necessary. For example, the second bias current Ib2 can be supplied to the column line COL for at least a period of time in which the first bias current Ib1 is supplied to the column line COL.

[0071] During the readout operation of the image sensor 300, since the second bias current Ib2 is supplied to the column line COL only at a desired time, the settling time can be shortened without significantly increasing the amount of current Ipix flowing through the driving transistor DX. Accordingly, the operation speed of the image sensor 300 can be increased with low power.

[0072] Figure 11 is a timing chart illustrating an operation of an image sensor during a horizontal scan time of one period according to an exemplary embodiment of the inventive concept. Reference is made together to Figure 10 and Figure 11 The reset control signal RG can transition from the low level to the high level at t1. When the reset control signal RG transitions from the low level to the high level, the reset transistor RX can be turned on. When the reset transistor RX is turned on, the voltage of the floating diffusion FD can be reset to the power supply voltage VDD.

[0073] When the voltage of the floating diffusion FD is reset to the power supply voltage VDD, the selection control signal SEL can transition from low to high at t2. When the selection control signal SEL transitions from low to high, the select transistor SX can turn on. When the select transistor SX turns on, the reset voltage can be output to the column line COL through the output node ND2.

[0074] The selection control signal SEL can maintain high during the period from t2 to t11. When the selection control signal SEL is maintained at high, the select transistor SX can maintain the on state. The first bias current Ib1 of the first current circuit CS1 can be supplied to the column line COL while the select transistor SX is maintained in the on state.

[0075] The second bias current Ib2 of the second current circuit CS2 can be supplied to the column line COL from t3 to t5. When the second bias current Ib2 of the second current circuit CS2 is supplied to the output node ND2 from t3 to t5, the reset control signal RG can transition from high to low at t4. When the reset control signal RG transitions from high to low, the reset transistor RX can turn off.

[0076] When the reset transistor RX turns off, a reset settling time can be required to stabilize the reset voltage of the column line COL connected to the pixel. The reset settling time D3 when the second bias current Ib2 is supplied to the column line COL can be shorter than the reset settling time D1 when the second bias current Ib2 is not supplied to the column line COL.

[0077] Accordingly, when the reset control signal RG falls from high to low while the second bias current Ib2 of the second current circuit CS2 is supplied to the column line COL, the reset settling time can be shortened. After the reset voltage has stabilized, the reset voltage can be sampled during the reset sampling time.

[0078] At t6, the boost control signal FDB can transition from low to high. The boost control signal FDB can maintain high during the period from t6 to t10. After the boost control signal FDB transitions from low to high, the transfer control signal TG can transition from low to high at t7. When the transfer control signal TG transitions from low to high, the transfer transistor TX can turn on. When the transfer transistor TX turns on, the charge generated when the photodiode PD is exposed to light can move to the floating diffusion FD.

[0079] The second bias current Ib2 of the second current circuit CS2 can be supplied to the column line COL from t8 to t11. When the second bias current Ib2 of the second current circuit CS2 is supplied to the column line COL, the transfer control signal TG can transition from a high level to a low level at t9. When the transfer control signal TG transitions from the high level to the low level, the transfer transistor TX can be turned off. After the transfer transistor TX is turned off, the boost control signal FDB can transition from the high level to the low level at t10.

[0080] When the transfer transistor TX is turned off, a pixel settling time can be required to stabilize a pixel voltage of the column line connected to the pixel. The pixel settling time D4 when the second bias current Ib2 is supplied to the column line COL can be shorter than the pixel settling time D2 when the second bias current Ib2 is not supplied to the column line COL.

[0081] Accordingly, when the transfer control signal TG transitions from the high level to the low level when the second bias current Ib2 of the second current circuit CS2 is supplied to the column line COL, the pixel settling time can be shortened. After the pixel voltage is stabilized, the pixel voltage can be sampled during a pixel sampling time.

[0082] According to an exemplary embodiment of the inventive concept, the total readout time can include a reset settling time, a reset sampling time, a pixel settling time, and a pixel sampling time. The image sensor 300 according to an exemplary embodiment of the inventive concept can shorten the reset settling time and the pixel settling time by supplying the second bias current Ib2 only at a necessary time. Accordingly, the total readout time can be shortened without significantly increasing the amount of current Ipix flowing through the drive transistor DX.

[0083] Figure 12 is a view for illustrating an operation of an image sensor according to an exemplary embodiment of the inventive concept. Referring to Figure 12 In the image sensor 400, a sensing region in which a plurality of pixels PX are disposed can be disposed in the first semiconductor chip CHIP1, and a control logic region for driving the plurality of pixels PX can be disposed in the second semiconductor chip CHIP2.

[0084] Each of the plurality of pixels PX can include a photodiode PD that receives light to generate a charge, a pixel circuit that processes the charge generated by the photodiode PD, and the like. The pixel circuit can include a plurality of transistors RX, TX, DX, and SX for outputting a voltage corresponding to the charge generated by the photodiode PD. A reset transistor RX can reset a voltage of a floating diffusion FD to a power supply voltage VDD in response to a reset control signal RG. A transfer transistor TX can transfer the charge generated by the photodiode PD to the floating diffusion in response to a transfer control signal TG. A source follower (driver) transistor DX can generate a voltage signal corresponding to the charge accumulated in the floating diffusion FD, and a selection transistor SX can transfer the voltage signal to an output node ND2 in response to a selection control signal SEL.

[0085] The plurality of devices included in the control logic LC can provide a circuit for driving the pixel circuit provided in the first semiconductor chip CHIP1, such as a row driver, a bias circuit, a readout circuit, and the like.

[0086] The second semiconductor chip CHIP2 can be connected to the output node ND2 included in the first semiconductor chip CHIP1 through a metal pad. According to an exemplary embodiment of the inventive concept, the first semiconductor chip CHIP1 can be included in a first layer, and the second semiconductor chip CHIP2 can be included in a second layer. The first layer and the second layer can be stacked with each other.

[0087] The first semiconductor chip CHIP1 can include a first power (supply) node ND1 for supplying a power supply voltage VDD and a second power node ND4 for supplying a bias voltage Vsub. The second power node ND4 can supply the bias voltage Vsub to the photodiode PD and the floating diffusion FD included in the first semiconductor chip CHIP1. The bias voltage Vsub can be a negative voltage with respect to a ground voltage of the second semiconductor chip CHIP2.

[0088] Since the image sensor 400 according to an exemplary embodiment of the inventive concept can supply the bias voltage Vsub corresponding to a negative voltage to the first semiconductor chip CHIP1, the image sensor 400 can implement the potential Vim even when the size of the power supply voltage VDD is reduced. Thus, a low-power image sensor can be implemented.

[0089] Figure 13 is a timing diagram illustrating an operation of an image sensor according to an exemplary embodiment of the inventive concept. Figure 12 Figure 14A is a timing diagram illustrating an operation of an image sensor according to an exemplary embodiment of the inventive concept. Figure 14B Figure 12 ​​a change in potential of an element constituting a unit pixel in an image sensor.

[0090] Figure 14A The potential levels when the boost control signal is at a low level are shown, and Figure 14B The potential levels when the boost control signal is at a high level are shown. In Figure 14A and Figure 14B In the vertical direction, the potential (e.g., voltage level) shows a negative potential toward the top and a positive potential toward the bottom.

[0091] Referring to Figure 13 and Figure 14A At time (a), the selection control signal SEL can have a high level, the reset control signal RG can have a low level, and the transfer control signal TG can have a low level. Figure 14A The potential levels at time (a) in Figure 13 are shown. The potential Vim of the image sensor 400 can be the sum of the potential V PD of the photodiode and the potential V FD of the floating diffusion. Since the bias voltage Vsub is a voltage smaller than the ground voltage 0 V (e.g., -0.7 V), the potential Vim of the image sensor 400 can increase compared to when the bias voltage Vsub is the ground voltage 0 V.

[0092] Referring to Figure 13 and Figure 14B At time (b) in Figure 13 , the selection control signal SEL can have a high level, the reset control signal RG can have a low level, and the transfer control signal TG can have a high level. Figure 14B The potential levels at time (b) in Figure 13 are shown. Since the transfer control signal TG has a high level, the gate potential of the transfer transistor TX decreases. When the gate potential of the transfer transistor TX decreases, the charge in the photodiode PD can be transferred to the floating diffusion FD.

[0093] The image sensor 400 according to the exemplary embodiment of the present inventive concept can supply a negative bias voltage Vsub smaller than the ground voltage 0 V to the photodiode PD and the floating diffusion FD included in the first semiconductor chip CHIP1. When the bias voltage Vsub is a negative bias voltage, the potential Vim of the image sensor 400 can increase compared to when the bias voltage Vsub is the ground voltage 0 V. Therefore, since the potential Vim of the image sensor can be achieved even if the size of the power supply voltage VDD' is reduced, a low-power image sensor can be achieved.

[0094] In addition, a sensing region provided with a plurality of pixels PX is provided in the first semiconductor chip CHIP1, and a control logic region for driving the plurality of pixels PX is provided in the second semiconductor chip CHIP2. Therefore, a substrate of the sensing region and a substrate of the control logic region can be separated. Since a negative bias voltage can be supplied only to the substrate of the sensing region, and a ground voltage can be supplied to the substrate of the control logic region, it is possible to prevent elements included in the control logic region from being affected by the negative bias voltage supplied to the substrate of the sensing region.

[0095] Figure 15 is a view for illustrating an operation of an image sensor according to an exemplary embodiment of the present inventive concept. As Figure 12 the image sensor 400 of Figure 15 the image sensor 500, the first semiconductor chip CHIP1 can further include a boost capacitor C2. The boost capacitor C2 can be connected between the floating diffusion FD and the control node ND3. A boost control signal FDB can control a capacitance of the floating diffusion FD. The capacity of the floating diffusion FD can be adjusted in response to the boost control signal FDB.

[0096] In an exemplary embodiment of the present inventive concept, a power supply voltage VDD applied to a pixel can be reduced by increasing a capacitance of a floating diffusion FD using a boost capacitor C2. According to an exemplary embodiment of the present inventive concept, a negative bias voltage Vsub can be supplied to a photodiode PD and the floating diffusion FD to reduce the power supply voltage VDD applied to the pixel. Therefore, a low-power image sensor can be implemented.

[0097] Figure 16 is a timing diagram for illustrating an operation of an image sensor according to an exemplary embodiment of the present inventive concept, Figure 15 Figure 17A and Figure 17B is a graph illustrating a change in a potential barrier of elements constituting a unit pixel in the image sensor of Figure 15

[0098] Figure 17A illustrates a potential level when a boost control signal is at a low level, and Figure 17B illustrates a potential level when the boost control signal is at a high level. In Figure 17A and Figure 17B , a potential (e.g., a voltage level) in a vertical direction illustrates a negative potential toward a top and a positive potential toward a bottom.

[0099] Referring to Figure 16 and Figure 17A together, Figure 16 ​​During time (a), the selection control signal SEL can be high, the reset control signal RG can be low, and the transmission control signal TG can be low. Additionally, the boost control signal FDB can be low. Figure 17A It shows Figure 16 The potential level at time (a) in the image sensor. The potential Vim of the image sensor can be the potential V of the photodiode. PD and the potential V of the floating diffuser FD The sum of these two values. Since the bias voltage Vsub is a voltage less than the ground voltage 0V (e.g., -0.7V), the potential Vim of the image sensor can increase compared to when the bias voltage Vsub is the ground voltage 0V.

[0100] Let's refer to each other. Figure 16 and Figure 17B ,exist Figure 16 During time (b), the selection control signal SEL can be high, the reset control signal RG can be low, and the transmission control signal TG can be high. Additionally, the boost control signal FDB can be high. Figure 17B It shows Figure 16 The potential level at time (b) in the diagram. When the boost control signal FDB is maintained at a high level, the capacitance of the floating diffuser FD can increase, and this is related to the ground potential level V of the floating diffuser FD when the boost control signal FDB is at a low level. FD In comparison, the baseline potential level V of the floating diffuser FD FD It can increase in the negative direction. In other words, the absolute value of the ground potential level of the floating diffuser FD can increase. Therefore, even when a second power supply voltage VDD2 lower than the first power supply voltage VDD1 is applied, the potential Vim of the image sensor can be achieved in the same way.

[0101] Furthermore, since the transmission control signal TG is at a high level, the gate potential of the transfer transistor TX decreases. When the gate potential of the transfer transistor TX decreases, the charge in the photodiode PD can be transferred to the floating diffuser FD.

[0102] Figure 18 This is a view used to illustrate the operation of an image sensor according to an exemplary embodiment of the concept according to the present invention. Figure 15 The image sensor 500 is different, in Figure 18 In the image sensor 600, the second semiconductor chip CHIP2 may further include a second switch SW2 and a second current circuit CS2. The first switch SW1 can connect the first current circuit CS1 to the column line COL, and the second switch SW2 can connect the second current circuit CS2 to the column line COL.

[0103] The first current circuit CS1 can supply the first bias current Ib1 to the column line COL, and the second current circuit CS2 can supply the second bias current Ib2 to the column line COL. The first bias current Ib1 and the second bias current Ib2 can have different magnitudes from each other, but are not limited thereto.

[0104] The second switch SW2 can control the second current circuit CS2 so that the second bias current Ib2 is supplied to the column line COL only at a required time. For example, the second bias current Ib2 can be supplied to the column line COL for at least a period of time in which the first bias current Ib1 is supplied to the column line COL.

[0105] In the readout operation of the image sensor 600, the second bias current Ib2 is supplied to the column line COL only at a required time, so that the settling time can be reduced without significantly increasing the amount of current Ipix flowing through the drive transistor DX. Accordingly, the operation speed of the image sensor 600 can be increased with low power.

[0106] Figure 19 is a timing chart for illustrating an operation of an image sensor according to an exemplary embodiment of the inventive concept. Referring to Figure 18 and Figure 19 The reset control signal RG can be transitioned from a low level to a high level at t1. When the reset control signal RG is transitioned from the low level to the high level, the reset transistor RX can be turned on. When the reset transistor RX is turned on, the voltage of the floating diffusion FD can be reset to the power supply voltage VDD.

[0107] Since the image sensor 600 is applied with the bias voltage Vsub (e.g., -0.7 V) that is less than the ground voltage 0 V, the power supply voltage VDD' applied to the image sensor 600 can be reduced while maintaining the potential Vim of the image sensor 600. Accordingly, the power consumption of the image sensor 600 can be reduced.

[0108] When the voltage of the floating diffusion FD is reset to the power supply voltage VDD', the selection control signal SEL can be transitioned from a low level to a high level at t2. When the selection control signal SEL is transitioned from the low level to the high level, the selection transistor SX can be turned on. When the selection transistor SX is turned on, the reset voltage can be output to the column line COL through the output node ND2.

[0109] The selection control signal SEL can maintain the high level for a period from t2 to t11. When the selection control signal SEL is maintained at the high level, the selection transistor SX can be maintained in the on state. The first bias current Ib1 of the first current circuit CS1 can be supplied to the column line COL while the selection transistor SX is maintained in the on state.

[0110] The second bias current Ib2 of the second current circuit CS2 can be supplied to the column line COL from t3 to t5. The reset control signal RG can transition from a high level to a low level at t4 when the second bias current Ib2 of the second current circuit CS2 is supplied to the output node ND2 from t3 to t5. The reset transistor RX can be turned off when the reset control signal RG transitions from the high level to the low level.

[0111] A reset settling time can be required to stabilize the reset voltage of the column line COL connected to the pixel when the reset transistor RX is turned off. The reset settling time D3 when the second bias current Ib2 is supplied to the column line COL can be shorter than the reset settling time Dl when the second bias current Ib2 is not supplied to the column line COL.

[0112] Therefore, the reset settling time can be shortened when the reset control signal RG transitions from the high level to the low level when the second bias current Ib2 of the second current circuit CS2 is supplied to the column line COL. The reset voltage can be sampled during a reset sampling time after the reset voltage has been stabilized.

[0113] The boost control signal FDB can transition from a low level to a high level at t6. The boost control signal FDB can be maintained at the high level for a period from t6 to tlO. The transfer control signal TG can transition from a low level to a high level at t7 after the boost control signal FDB transitions from the low level to the high level. The transfer transistor TX can be turned on when the transfer control signal TG transitions from the low level to the high level. The charge generated when the photodiode PD is exposed to light can move to the floating diffusion FD when the transfer transistor TX is turned on.

[0114] The base potential level of the floating diffusion FD can be maintained higher than the base potential level of the floating diffusion FD when the boost control signal FDB is at the low level when the boost control signal FDB is maintained at the high level. In other words, the capacitance of the floating diffusion FD can be increased. Therefore, the potential Vim of the image sensor can be realized equally even when the second power supply voltage VDD2 lower than the first power supply voltage VDDl is applied.

[0115] The second bias current Ib2 of the second current circuit CS2 can be supplied to the column line COL from t8 to tl l. The transfer control signal TG can transition from a high level to a low level at t9 when the second bias current Ib2 of the second current circuit CS2 is supplied to the column line COL. The transfer transistor TX can be turned off when the transfer control signal TG transitions from the high level to the low level. The boost control signal FDB can transition from a high level to a low level at tlO after the transfer transistor TX is turned off.

[0116] When the transfer transistor TX is turned off, a pixel settling time can be required to stabilize the pixel voltage of the column line COL connected to the pixel. The pixel settling time D4 when the second bias current Ib2 is supplied to the column line COL can be shorter than the pixel settling time D2 when the second bias current Ib2 is not supplied to the column line COL.

[0117] Therefore, when the transfer control signal TG falls from a high level to a low level when the second bias current Ib2 of the second current circuit CS2 is supplied to the column line COL, the pixel settling time can be shortened. After the pixel voltage is stabilized, the pixel voltage can be sampled during a pixel sampling time.

[0118] The image sensor 600 according to the exemplary embodiment of the inventive concept can shorten the reset settling time and the pixel settling time by supplying the second bias current Ib2 only at a required time. Therefore, the total readout time can be shortened without significantly increasing the amount of current Ipix flowing through the driving transistor DX.

[0119] Figure 20 FIG. 1 is a block diagram schematically illustrating an electronic device including an image sensor according to an exemplary embodiment of the inventive concept.

[0120] The computer device 1000 according to the exemplary embodiment of the inventive concept can include an image sensor 1010, a display 1020, a memory 1030, a processor 1040, a port 1050, etc. In addition, the computer device 1000 can further include a wired / wireless communication device, a power supply device, etc. Among the illustrated components, the port 1050 can be an element for communicating with a video card, a sound card, a memory card, a USB card, etc. The computer device 1000 can be a smart phone, a tablet personal computer (PC), a smart wearable device, etc. in addition to a general desktop computer or a laptop computer. Figure 15

[0121] The processor 1040 can perform a specific operation, command, task, etc. The processor 1040 can be a central processing unit (CPU), a micro processing unit (MCU), a system on chip (SoC), etc., and can communicate with the image sensor 1010, the display 1020, and the memory 1030, and other devices connected to the port 1050 via a bus 1060.

[0122] ​The memory 1030 can be a storage medium that stores data, multimedia data, etc. for the operation of the computer device 1000. The memory 1030 can include volatile memory such as random access memory (RAM) or non-volatile memory such as flash memory. In addition, the memory 1030 can include at least one of a solid state drive (SSD), a hard disk drive (HDD), or an optical disk drive (ODD) as a storage device.

[0123] The image sensor 1010 can be mounted on a package substrate and connected to the processor 1040 through the bus 1060 or other communication means. The image sensor 1010 can be implemented in the computer device 1000 according to an exemplary embodiment of the present inventive concept as described with reference to Figures 1 to 19

[0124] As described above, in the image sensor according to an exemplary embodiment of the present inventive concept, the power supply voltage applied to the pixel can be reduced by using the booster capacitor and the negative bias voltage. In addition, the second bias current can be output to the column line during at least a time period in which the first bias current is input to the column line connected to the pixel in one horizontal period. The second bias current can shorten a settling time for stabilizing the voltage of the column line, thereby improving the performance of the image sensor without significantly increasing the amount of current flowing in the pixel. Accordingly, the performance of the image sensor at low power can be improved.

[0125] While the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that modifications in form and details can be made therein without departing from the spirit and scope of the inventive concept as set forth in the appended claims.​

Claims

1. An image sensor comprising: a photodiode connected to a second power node and configured to generate electric charges in response to light, wherein the second power node is configured to supply a second power supply voltage; a transfer transistor connecting the photodiode and a floating diffusion in response to a transfer control signal; a reset transistor connected between the floating diffusion and a first power node, wherein the first power node is configured to supply a first power supply voltage higher than the second power supply voltage; a boost capacitor directly connected to the floating diffusion and a control node and configured to adjust a capacitance of the floating diffusion in response to a boost control signal, wherein the boost control signal is input at the control node; a bias circuit having a first current circuit and a second current circuit configured to supply different bias currents to an output node, wherein a voltage signal corresponding to electric charges accumulated in the floating diffusion is output to the output node, wherein the control node is different from the second power node, wherein the boost control signal decreases from a high level to a low level after the transfer transistor is turned off, and the reset transistor is switched from an on state to an off state during a first time when the first bias current of the first current circuit and the second bias current of the second current circuit are simultaneously provided to the output node, and wherein the second power supply voltage includes a ground voltage or a negative bias voltage less than the ground voltage. the transfer transistor is switched from an on state to an off state during a second time when the second bias current of the second current circuit is provided to the output node, and 2. The image sensor of claim 1, wherein, the second time is different from the first time. the boost control signal decreases from a high level to a low level during the second time when the second bias current of the second current circuit is provided to the output node.

3. The image sensor of claim 2, wherein, the boost control signal increases from a low level to a high level before the transfer transistor is turned on.

4. The image sensor of claim 1, wherein, the boost control signal increases from a low level to a high level after the transfer transistor is turned on.

5. The image sensor of claim 1, wherein, 6. The image sensor of claim 1, further comprising a selection transistor connected between the output node and the floating diffusion and configured to output the voltage signal corresponding to electric charges accumulated in the floating diffusion to the output node, the first bias current of the first current circuit is provided when the selection transistor is maintained in an off state. wherein the boost control signal increases from a low level to a high level after the reset transistor is turned off.

7. The image sensor of claim 1, wherein, the reset transistor is turned on after the boost control signal decreases from a high level to a low level.

8. The image sensor of claim 7, wherein, the image sensor includes a first semiconductor chip and a second semiconductor chip, the first semiconductor chip includes the output node, the second semiconductor chip is connected to the output node through a metal pad, 9. The image sensor of claim 1, wherein, the first semiconductor chip includes the photodiode, the floating diffusion, the transfer transistor, the reset transistor, and the boost capacitor, and the second semiconductor chip includes the bias circuit. The second semiconductor chip includes the bias circuit.

10. An image sensor comprising: a photodiode connected to a second power node and configured to generate a charge in response to light, wherein the second power node is configured to supply a second supply voltage; a transfer transistor connecting the photodiode and a floating diffusion in response to a transfer control signal; a reset transistor connected between the floating diffusion and a first power node, wherein the first power node is configured to supply a first supply voltage higher than the second supply voltage; and a boost capacitor directly connected to the floating diffusion and a control node and configured to adjust a capacity of the floating diffusion in response to a boost control signal, wherein the boost control signal is input at the control node, wherein the control node is different from the second power node, wherein the boost control signal increases from a low level to a high level before the transfer transistor turns on, and decreases from the high level to the low level after the transfer transistor turns off, and wherein the second supply voltage includes a ground voltage or a negative bias voltage less than the ground voltage.

11. The image sensor of claim 10, wherein, a first bias current and a second bias current having different magnitudes from each other are input to an output node for one period of a horizontal scan time, and the output node outputs a voltage signal corresponding to a charge accumulated in the floating diffusion.

12. The image sensor of claim 11, wherein, the second bias current is input to the output node at least for a portion of a time when the first bias current is input to the output node.

13. The image sensor of claim 12, wherein, the output node receives only the first bias current for a portion of the horizontal scan time.

14. An image sensor comprising: a first semiconductor chip including: a photodiode connected to a second power node and configured to generate a charge in response to light, the second power node configured to supply a second supply voltage to the photodiode and a floating diffusion; a reset transistor connected between the floating diffusion and a first power node, the first power node configured to supply a first supply voltage; a transfer transistor configured to transfer the charge generated by the photodiode to the floating diffusion; and an output node configured to output a voltage signal corresponding to a charge accumulated in the floating diffusion; and a second semiconductor chip connected to the output node through a metal pad and including a first current circuit configured to output a first bias current and a second current circuit configured to output a second bias current, wherein the first supply voltage is higher than the second supply voltage, and the second supply voltage includes a ground voltage or a negative bias voltage less than the ground voltage, wherein the reset transistor switches from an on state to an off state during a first time when the first bias current of the first current circuit and the second bias current of the second current circuit are simultaneously supplied to the output node, and wherein the transfer transistor is configured to transfer the charge generated by the photodiode to the floating diffusion in response to a transfer control signal. wherein during a second time different from the first time when the first bias current of the first current circuit and the second bias current of the second current circuit are simultaneously provided to the output node, the transfer transistor switches from an on state to an off state.

15. The image sensor of claim 14, wherein, The first semiconductor chip further includes a boost capacitor connected to the floating diffusion and configured to adjust a capacitance of the floating diffusion in response to a boost control signal.

16. The image sensor of claim 15, wherein, The boost control signal decreases from a high level to a low level after the transfer transistor is turned off.

17. The image sensor of claim 16, wherein, The boost control signal increases from a low level to a high level before the transfer transistor is turned on.

18. The image sensor of claim 16, wherein, The boost control signal increases from a low level to a high level after the transfer transistor is turned on.

19. The image sensor of claim 14, wherein, The first semiconductor chip further includes: a source follower transistor configured to generate the voltage signal corresponding to a charge accumulated in the floating diffusion; and a select transistor configured to transfer the voltage signal to the output node in response to a select control signal.

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