Chip packaging structure and manufacturing method thereof

Abstract

The present invention provides a chip packaging structure, including a chip, a packaging colloid, a first dielectric layer, a first redistribution wiring layer, a second redistribution wiring layer and a second dielectric layer. The packaging colloid encapsulates the chip. The packaging colloid has a plurality of conductive connectors. The first dielectric layer is arranged on the active surface of the chip and part of the packaging colloid. The first redistribution wiring layer is arranged on the surface of the packaging colloid relative to the first dielectric layer. The second redistribution wiring layer is arranged on the first dielectric layer. The second dielectric layer is arranged on the second redistribution wiring layer and part of the first dielectric layer. Some conductive connectors are located on the back side of the chip, and the back side is electrically connected to the first redistribution wiring layer through some conductive connectors, and the conductive part is electrically connected to the second redistribution wiring layer, the conductive connector and the first redistribution wiring layer. A method for manufacturing a chip packaging structure is also provided.

Description

Technical Field

[0001] The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a chip packaging structure and a manufacturing method thereof. Background Art

[0002] As the demand for electronic products moves towards high functionality, high-speed signal transmission, and high-density circuit components, the design of signal transmission paths in chip packaging is becoming increasingly important. Therefore, how to transmit signals between the back side and the active side of the chip and improve signal transmission capabilities has become one of the current problems that need to be solved urgently. Summary of the invention

[0003] The present invention provides a chip packaging structure and a manufacturing method thereof, which can transmit signals between the back side and the active side of the chip and improve the signal transmission capability.

[0004] The chip packaging structure of the present invention includes a first chip, a packaging colloid, a first dielectric layer, a first redistribution wiring layer, a second redistribution wiring layer and a second dielectric layer. The first chip has a first active surface, a back surface relative to the first active surface and a plurality of conductive parts located on the first active surface. The packaging colloid encapsulates the first chip. The packaging colloid has a plurality of conductive connectors. The first dielectric layer is configured on the first active surface of the first chip and a portion of the packaging colloid. The first redistribution wiring layer is configured on the surface of the packaging colloid relative to the first dielectric layer. The second redistribution wiring layer is configured on the first dielectric layer. The second dielectric layer is configured on the second redistribution wiring layer and a portion of the first dielectric layer. Some of the conductive connectors are located on the back surface of the first chip, the back surface is electrically connected to the first redistribution wiring layer through some of the conductive connectors, and the conductive parts are electrically connected to the second redistribution wiring layer, the conductive connectors and the first redistribution wiring layer.

[0005] Based on the above, in the chip packaging structure, since some conductive connectors are located on the back side, the back side is electrically connected to the redistribution wiring layer through some conductive connectors, and the conductive part is electrically connected to the redistribution wiring layer, the conductive connectors and the redistribution wiring layer, so that the signal can be transmitted between the back side and the active surface of the chip and the signal transmission capability can be improved through the redistribution wiring layer and the fine line pitch of the redistribution wiring layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1A to 1L FIG. 4 is a partial cross-sectional schematic diagram of a partial manufacturing method of a chip packaging structure according to an embodiment of the present invention.

[0007] Description of Figure Numbers:

[0008] 10, 20: Adhesive layer

[0009] 100: Chip packaging structure

[0010] 110, 160: Carrier board

[0011] 120, 174: Dielectric layer

[0012] 1201: Dielectric material layer

[0013] 130, 180, 190: Chip

[0014] 130a, 180a, 190a: Active surface

[0015] 130b: Back

[0016] 131: Insulation layer

[0017] 132: Conductive pad

[0018] 134: Conductive bump

[0019] 136: Conductive part

[0020] 136s: Sidewall

[0021] 140: Encapsulation colloid

[0022] 140a: Surface

[0023] 142, 1421, 1422: Conductive connectors

[0024] 150, 172: Re-routing circuit layer

[0025] 192: Substrate

[0026] O1, O2, O3: Open DETAILED DESCRIPTION

[0027] The directional terms used herein (eg, up, down, right, left, front, back, top, bottom) are used only with reference to the drawings shown and are not intended to imply an absolute orientation.

[0028] Unless expressly stated otherwise, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.

[0029] The present invention is more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or size of the layers or regions in the accompanying drawings may be exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

[0030] Figures 1A to 1L FIG. 1 is a partial cross-sectional diagram of a partial manufacturing method of a chip packaging structure according to an embodiment of the present invention. Figure 1AFirst, a carrier 110 is provided. The carrier 110 may be a carrier made of glass, plastic or other suitable materials, as long as the aforementioned materials can carry the package structure formed thereon in the subsequent process. Here, the carrier 110 may be a first carrier. Next, a dielectric material layer 1201 is formed on the carrier 110.

[0031] In one embodiment, the adhesive layer 10 may be disposed between the carrier 110 and the dielectric material layer 1201 , wherein the adhesive layer 10 may be a thin film having adhesive properties on both the upper and lower surfaces to enhance the bonding force between the carrier 110 and the dielectric material layer 1201 and to enhance the peelability of subsequent structures removed from the carrier 110 .

[0032] Please refer to Figure 1B , a photolithography or laser drilling process is performed on the dielectric material layer 1201 to form a dielectric layer 120 having a plurality of openings O1, wherein the plurality of openings O1 can expose the adhesive layer 10 below. Here, the openings O1 can be first openings; and the dielectric layer 120 can be a first dielectric layer.

[0033] Please also refer to Figure 1A and Figure 1B In one embodiment, the dielectric material layer 1201 may include a photosensitive material, such as polyimide (PI), benzocyclobutene (BCB), silica gel or polybenzoxazole (PBO), so the dielectric material layer 1201 may be directly subjected to a lithography and etching process to reduce the complexity of the process, but the present invention is not limited thereto, and the dielectric layer 120 may also be other suitable dielectric materials.

[0034] Please refer to Figure 1C , a chip 130 is disposed on the dielectric layer 120, wherein the chip 130 has an active surface 130a, a back surface 130b opposite to the active surface 130a, and a plurality of conductive pads 132 located on the active surface 130a and partially exposed by the insulating layer 131. The conductive pads 132, the dielectric layer 120, and the adhesive layer 10 can form a cavity, but the present invention is not limited thereto. The conductive pads 132 can include aluminum pads, copper pads, or other suitable metal pads (e.g., nickel and gold). Here, the chip 130 can be a first chip; and the active surface 130a can be a first active surface.

[0035] Please refer to Figure 1D, forming an encapsulation 140 to encapsulate the chip 130. The encapsulation 140 may cover the back surface 130b of the chip 130, so as to facilitate the subsequent formation of a conductive connection that can be electrically connected to the back surface 130b. In this embodiment, the dielectric layer 120 is disposed on the active surface 130a of the chip 130 and a portion of the encapsulation 140.

[0036] In one embodiment, the material of the encapsulant 140 can be substantially the same as the material of the dielectric layer 120 , thereby improving the adhesion between the dielectric layer 120 and the encapsulant 140 , reducing the stress generated by shrinkage between the dielectric layer 120 and the encapsulant 140 , and further reducing the probability of delamination between the dielectric layer 120 and the encapsulant 140 .

[0037] Please refer to Figure 1E , the encapsulation 140 is subjected to a lithography or laser drilling process to form a plurality of openings O2 and a plurality of openings O3, wherein the openings O2 penetrate the encapsulation 140 and the dielectric layer 120 to expose the adhesive layer 10 below, and the openings O3 expose a portion of the back surface 130b of the chip 130. The openings O2 may be formed on both sides of the chip 130, in other words, the openings O2 may surround the chip 130. Here, the openings O2 may be the second opening; and the openings O3 may be the third opening.

[0038] In one embodiment, the encapsulation colloid 140 may include a photosensitive material, so the encapsulation colloid 140 may be directly subjected to a lithography and etching process to reduce the complexity of the process, but the present invention is not limited thereto, and the material of the encapsulation colloid 140 may be determined according to actual design requirements.

[0039] Please refer to Figure 1F , fill the opening O2 and the opening O3 with conductive material to form a plurality of conductive connectors 142. For example, the conductive connector 142 may include a conductive connector 1421 and a conductive connector 1422, wherein the opening O2 is filled with conductive material to form the conductive connector 1421, and the opening O3 is filled with conductive material to form the conductive connector 1422. In one embodiment, the conductive material may cover the top surface of the encapsulation 140, and then the conductive material may be planarized until the top surface of the encapsulation 140 is exposed, so that the top surface of the formed conductive connector 1421 and the top surface of the conductive connector 1422 are substantially coplanar. The aforementioned planarization process may be, for example, etching, grinding, etc., but the present invention is not limited thereto.

[0040] In this embodiment, part of the conductive connection member 142 is located on the back surface 130b, while another part of the conductive connection member 142 surrounds the chip 130. For example, the conductive connection member 1422 is located on the back surface 130a, while the conductive connection member 1421 surrounds the chip 130. Since the conductive connection member 1422 is located on the back surface 130a, the back surface 130b of the chip 130 can be electrically connected to other circuit layers, conductive elements or chips to be connected through the conductive connection member 1422, so that the signal of the back surface 130b of the chip 130 can be transmitted through the conductive connection member 1422.

[0041] Please refer to Figure 1G A redistribution wiring layer 150 is formed on a surface 140a of the encapsulation colloid 140 opposite to the dielectric layer 120, wherein the back side 130b of the chip 130 can be electrically connected to the conductive connector 1421 through the conductive connector 1422 and the redistribution wiring layer 150, so that the redistribution wiring layer 150 can electrically connect the conductive connector 1421 and the conductive connector 1422 to each other. Here, the redistribution wiring layer 150 can be a first redistribution wiring layer.

[0042] Please refer to Figure 1H , the carrier 110 and the adhesive layer 10 are separated and removed from the chip 130 and the dielectric layer 120 to expose a portion of the conductive connector 142, the conductive pad 132 and the dielectric layer 120. The exposed surfaces of the conductive connector 142 and the dielectric layer 120 can be substantially coplanar, so that other circuit layers can be formed on the flat surface later.

[0043] Please refer to Fig. 1I After removing the carrier 110 and the adhesive layer 10, Figure 1H The structure shown is flipped upside down. Next, a carrier 160 is disposed on the redistribution circuit layer 150. The carrier 160 may be a second carrier. In one embodiment, an adhesive layer 20 may be disposed between the carrier 160 and the redistribution circuit layer 150. The adhesive layer 20 may be similar to the adhesive layer 10 and will not be described in detail herein.

[0044] Please refer to Figure 1J, a redistribution wiring layer 172 is formed on the dielectric layer 120, and a dielectric layer 174 is formed on the redistribution wiring layer 172 and a portion of the dielectric layer 120. For example, the redistribution wiring layer 172 can be formed first, and then the dielectric layer 174 is formed to cover the redistribution wiring layer 172. In this embodiment, while forming the redistribution wiring layer 172, a plurality of conductive bumps 134 can be formed on the cavity formed by the dielectric layer 120 and the adhesive layer 10 and the conductive pads 132 of the chip 130, wherein the conductive pads 132 and the conductive bumps 134 constitute a plurality of conductive portions 136 on the active surface 130a of the chip 130. In one embodiment, the dielectric layer 120 at least covers a portion of the side walls 136s of the plurality of conductive portions 136. In one embodiment, the material of the conductive bumps 134 may include copper, tin, gold, nickel, solder, or a combination thereof. However, the present invention is not limited thereto, and the order of forming the redistribution wiring layer 172 and the dielectric layer 174 may be determined according to actual design requirements. Here, the redistribution wiring layer 172 may be a second redistribution wiring layer; and the dielectric layer 174 may be a second dielectric layer. In one embodiment, the redistribution wiring layer 172 and the conductive bumps 134 may be formed simultaneously using an electroplating process, which may further simplify the process of the chip packaging structure 100, but the present invention is not limited thereto.

[0045] In this embodiment, since part of the conductive connector 142 is located on the back side 130b, the back side 130b is electrically connected to the redistribution wiring layer 150 through part of the conductive connector 142, and the conductive portion 136 is electrically connected to the redistribution wiring layer 172, the conductive connector 142 and the redistribution wiring layer 150, so that the signal can be transmitted between the back side 130a and the active surface 130a of the chip 130 and the signal transmission capability can be improved through the fine line pitch of the redistribution wiring layer 172 and the redistribution wiring layer 150.

[0046] The dielectric layer 174 may have a plurality of openings to expose the redistribution wiring layer 172, so as to facilitate the chip 130 to be further electrically connected to other chips. In one embodiment, the dielectric layer 174 may include a photosensitive material, so that the dielectric layer 174 may be directly subjected to a lithography and etching process to reduce the complexity of the process, but the present invention is not limited thereto, and the material of the dielectric layer 174 may be determined according to actual process requirements.

[0047] In one embodiment, the material of the dielectric layer 174 may be substantially the same as the material of the dielectric layer 120, thereby improving the adhesion between the dielectric layer 120 and the dielectric layer 174, reducing the stress between the dielectric layer 120 and the dielectric layer 174 due to shrinkage, and further reducing the probability of delamination between the dielectric layer 120 and the dielectric layer 174 and disconnection of the redistribution wiring layer 172. In another embodiment, the material of the dielectric layer 174 may be substantially the same as the material of the dielectric layer 120 and the material of the encapsulation colloid 140, thereby further reducing the probability of delamination between the chip 130 and the encapsulation colloid 140 and the redistribution wiring layer 172 and disconnection of the redistribution wiring layer 172, thereby improving the reliability of the chip packaging structure 100.

[0048] Please also refer to Figure 1K and Figure 1L After forming the redistribution circuit layer 172, the carrier 160 and the adhesive layer 20 are separated and removed from the redistribution circuit layer 150. Then, the chip 180 is configured on the redistribution circuit layer 172 by flip chip bonding, and at least one chip 190 ( Figure 1L Schematically showing two chips 190) on the redistribution wiring layer 150. Here, the chip 180 may be the second chip; and the chip 190 may be the third chip.

[0049] In the present embodiment, the chip 180 has an active surface 180a facing the redistribution wiring layer 172, and the chip 180 is electrically connected to the chip 130 through the redistribution wiring layer 172; and each of the at least one chip 190 has an active surface 190a facing the redistribution wiring layer 150, and the chip 130 and the chip 180 are electrically connected to the at least one chip 190 through the redistribution wiring layer 172, the conductive connection 142 and the redistribution wiring layer 150. Here, the active surface 180a can be the second active surface; and the active surface 190a can be the third active surface.

[0050] Please continue to refer to Figure 1L In this embodiment, a substrate 192 may also be included, wherein at least one chip 190 may be disposed between the redistribution wiring layer 150 and the substrate 192. After the above process, the chip package structure 100 of this embodiment can be substantially completed. It should be noted that the present invention does not limit the types of the chip 130, the chip 180 and the chip 190, which may be determined according to actual design requirements.

[0051] In summary, in the chip packaging structure, since part of the conductive connectors are located on the back side, the back side is electrically connected to the redistribution wiring layer through part of the conductive connectors, and the conductive part is electrically connected to the redistribution wiring layer, the conductive connectors and the redistribution wiring layer, so that the signal can be transmitted between the back side and the active side of the chip and the signal transmission capability is improved through the redistribution wiring layer and the fine line pitch of the redistribution wiring layer. In addition, the material of the first dielectric layer, the material of the second dielectric layer and the material of the packaging colloid are substantially the same, so the adhesion between the first dielectric layer, the second dielectric layer and the packaging colloid can be improved, and the stress caused by shrinkage between the first dielectric layer, the second dielectric layer and the packaging colloid can be reduced, thereby reducing the probability of delamination between the first dielectric layer, the second dielectric layer and the packaging colloid and disconnection of the redistribution wiring layer, so as to improve the reliability of the chip packaging structure.

Claims

1. A chip packaging structure, comprising: A first chip having a first active surface, a back surface opposite to the first active surface, and a plurality of conductive parts located on the first active surface; A packaging colloid encapsulating the first chip, wherein the packaging colloid has a plurality of conductive connecting members; A first dielectric layer is disposed on the first active surface of the first chip and a portion of the packaging colloid; A first redistribution wiring layer is disposed on a surface of the packaging colloid opposite to the first dielectric layer; A second redistribution wiring layer is disposed on the first dielectric layer; as well as A second dielectric layer is disposed on the second redistribution wiring layer and a portion of the first dielectric layer. Part of the multiple conductive connectors are located on the back side, and another part of the multiple conductive connectors penetrate the packaging colloid and the first dielectric layer and surround the first chip. The back side is electrically connected to the first redistribution wiring layer through the part of the multiple conductive connectors, and the multiple conductive parts are electrically connected to the second redistribution wiring layer, the multiple conductive connectors and the first redistribution wiring layer. 2 . The chip package structure according to claim 1 , wherein a material of the first dielectric layer is substantially the same as a material of the second dielectric layer. 3 . The chip packaging structure according to claim 1 , wherein a material of the first dielectric layer, a material of the second dielectric layer, and a material of the encapsulant are substantially the same. The chip packaging structure according to claim 1 , wherein the first dielectric layer at least covers a portion of sidewalls of the plurality of conductive parts.

5. The chip packaging structure according to claim 1 further includes a second chip, which is configured on the second redistribution wiring layer, wherein the second chip has a second active surface facing the second redistribution wiring layer, and the second chip is electrically connected to the first chip through the second redistribution wiring layer.

6. The chip packaging structure according to claim 5 further includes at least one third chip, which is configured on the first redistribution wiring layer, wherein each of the at least one third chip has a third active surface facing the first redistribution wiring layer, and the first chip and the second chip are electrically connected to the at least one third chip through the second redistribution wiring layer, the multiple conductive connectors and the first redistribution wiring layer. 7 . The chip packaging structure according to claim 1 , wherein the first dielectric layer, the second dielectric layer and the packaging colloid comprise photosensitive materials.

8. A method for manufacturing a chip packaging structure, comprising: providing a first carrier board; forming a first dielectric layer on the first carrier; Disposing a first chip on the first dielectric layer, wherein the first chip has a first active surface, a back surface opposite to the first active surface, and a plurality of conductive portions located on the first active surface; forming a packaging colloid to encapsulate the first chip; A plurality of conductive connecting members are formed in the packaging colloid, wherein the step of forming the plurality of conductive connecting members comprises: Performing a photolithography or laser drilling process on the encapsulant to form a plurality of second openings and a plurality of third openings, wherein the plurality of second openings penetrate the encapsulant and the first dielectric layer, and the plurality of third openings expose a portion of the back surface; and Filling the plurality of second openings and the plurality of third openings with conductive material; forming a first redistribution wiring layer on a surface of the packaging colloid opposite to the first dielectric layer; removing the first carrier board; forming a second redistribution wiring layer on the first dielectric layer; and forming a second dielectric layer on the second redistribution wiring layer and a portion of the first dielectric layer; Some of the multiple conductive connectors are located on the back side, the back side is electrically connected to the first redistribution wiring layer through some of the multiple conductive connectors, and the multiple conductive parts are electrically connected to the second redistribution wiring layer, the multiple conductive connectors and the first redistribution wiring layer.

9. The method for manufacturing a chip packaging structure according to claim 8, wherein the step of forming the first dielectric layer comprises: forming a dielectric material layer on the first carrier; as well as The dielectric material layer is subjected to a lithography etching or laser drilling process to form a plurality of first openings.

10. The method for manufacturing a chip packaging structure according to claim 8, further comprising: Disposing a second chip on the second redistribution wiring layer by flip chip bonding; as well as At least one third chip is configured on the first redistribution wiring layer by flip chip bonding. 11 . The method for manufacturing a chip packaging structure according to claim 8 , further comprising forming a second carrier on the first redistribution wiring layer after removing the first carrier. 12 . The method for manufacturing a chip packaging structure according to claim 11 , further comprising removing the second carrier after forming the second redistribution wiring layer.

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