Semiconductor device with deep trench isolation and trench capacitor

Abstract

The present invention discloses a semiconductor device (100) having an isolation structure (120) and a trench capacitor (130), wherein the isolation structure (120) and the trench capacitor (130) are each formed by etching corresponding first and second trenches (121, 131) of different widths and different depths using a single resist mask, and have a dielectric liner (121, 131) formed on the trench sidewalls and polysilicon (126, 136) filling the trenches (121, 131) and deeply doped regions (122, 132) surrounding the trenches (121, 131), and a conductive feature (160, 162) including a metallization structure (154, 156) connecting the polysilicon (126) of the isolation structure trench (121) to the deeply doped region (122) to form the isolation structure (120).

Description

Technical Field

[0001] The present description relates to semiconductor devices having isolation structures and capacitors. Background Art

[0002] Isolation structures are used in integrated circuits to electrically isolate active areas of one or more transistors or other circuit components, allowing for the use of different power supply domains (e.g., high- and low-voltage circuits) on a single IC. One form of isolation structure is deep trench isolation. Deep trenches are also used to form trench capacitors in integrated circuits. Some semiconductor device manufacturing processes fabricate trench isolation and trench capacitors separately, requiring separate masking and other process steps and increasing cost and process complexity. Summary of the Invention

[0003] The present disclosure introduces concepts that will be further illustrated and described below without limiting the scope of the claimed subject matter. The described aspects include a semiconductor device and a method for manufacturing the same. An example semiconductor device includes an isolation structure and a trench capacitor formed by etching corresponding first and second trenches using a single resist mask. In one example, the trench includes a dielectric liner formed on the trench sidewalls and filled with polysilicon. A deeply doped region extends around the trench. In one example, the trench and the deeply doped region extend from a semiconductor surface layer to a buried layer of the semiconductor structure. A conductive feature of a metallization structure connects the polysilicon of the isolation trench to the deeply doped region to form an isolation structure. A second conductive feature of the metallization structure is connected to the polysilicon of the capacitor trench to form a first capacitor plate, and another conductive feature of the metallization structure is connected to the deeply doped region around the capacitor trench to form a second capacitor plate. In one example, the isolation trench width is different from the capacitor trench width. In one example, the isolation and capacitor trenches have different depths. In one example, the trench includes a multi-layer dielectric liner, such as an oxide, a nitride, and an oxide (ONO) sublayer. In one example, the capacitor includes a plurality of trenches surrounded by the second deeply doped region and each including corresponding dielectric sidewall liners and polysilicon fillers. In a specific example, the trench polysilicon is doped. One example further includes shallow implanted regions in the semiconductor surface layer extending along the sides of the isolation trench within the deeply doped region.

[0004] A method for fabricating an isolation structure in a semiconductor device is described. An example method includes forming a trench in a semiconductor structure; forming a deeply doped region surrounding the trench; forming a dielectric on sidewalls of the trench; filling the trench with polysilicon; and forming a metallization structure connecting the polysilicon to the deeply doped region to form conductive features of the isolation structure. In one example, the dielectric is formed as a multilayer dielectric liner by depositing a first oxide layer on the sidewalls of the trench, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer. In one example, the method further includes forming shallow implanted regions along the sides of the trench within the deeply doped region.

[0005] A method for fabricating a semiconductor device includes forming a resist layer having a first opening and a second opening on a top surface of a semiconductor structure; etching through the first opening to form a first trench and etching through the second opening to form a second trench; and implanting dopants through the first opening to form a first deeply doped region surrounding the first trench and implanting dopants through the second opening to form a second deeply doped region surrounding the second trench. The method further includes depositing a first dielectric liner through the first opening and through the second opening; and depositing polysilicon through the first and second openings to fill the trenches. The method further includes forming a first conductive feature of a metallization structure connecting the first polysilicon to the first deeply doped region to form an isolation structure; forming a second conductive feature of the metallization structure connected to the second polysilicon to form a first capacitor plate; and forming another conductive feature of the metallization structure connected to the second deeply doped region to form a second capacitor plate. In one example, the resist layer formation includes patterning the first opening with a first width; and patterning the second opening with a smaller second width. In this example, the first trench has a greater depth than the second trench. In one example, the dielectric liner is formed as a multi-layer structure by performing a deposition process through the mask opening to deposit a first oxide layer on the sidewalls of the trench, deposit a nitride layer on the first oxide layer, and deposit a second oxide layer on the nitride layer (or grow an oxide on the nitride to form an oxynitride). In one example, the method further includes forming a shallow implanted region along the side of the trench within the deep doped region before the ONO deposition. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a partial cross-sectional side view of an integrated circuit semiconductor device including a deep trench isolation structure and a trench capacitor.

[0007] Figure 2 yes Figure 1A top view of a portion of a semiconductor device.

[0008] Figure 3 is a flow chart showing a method for fabricating a semiconductor device and for fabricating an isolation structure in a semiconductor device.

[0009] Figures 4 to 18 yes Figure 1 and 2 The integrated circuit is based on Figure 3 Partial cross-sectional side views of various manufacturing stages of the method. DETAILED DESCRIPTION

[0010] In the drawings, like reference numerals refer to all like elements, and features are not necessarily drawn to scale. In the following description and claims, the terms "including / includes," "having / has / with," or variations thereof are inclusive (similar to the term "comprising") and mean "including, but not limited to..." . Furthermore, the terms "couple" / couples" are intended to include indirect or direct electrical or mechanical connections, or a combination thereof. For example, if a first device is coupled to or with a second device, the connection may be through a direct electrical connection or through an indirect electrical connection via one or more intermediary devices and connections. The various features of the examples may be used in conjunction with a variety of different semiconductor devices, including, but not limited to, integrated circuits having multiple electronic components and single-component semiconductor devices (e.g., single transistor products, single diode products, etc.).

[0011] Example devices and fabrication methods provide process integration for both trench isolation and high-density trench capacitors fabricated using a shared resist mask to save fabrication time and cost. In some examples, trenches are etched, deeply doped regions surrounding the trenches are implanted, and the trenches are lined and filled using a thick photoresist and a hard mask patterned with openings for the capacitor trenches and wider openings for the isolation structure trenches. The described examples provide a metallization layout structure to provide connected polysilicon and deeply doped regions for the first and second capacitor plates of the capacitor trench structures and the isolation trench structures. The described examples facilitate the use of self-aligned deeply doped region implants on the deep trench sidewalls to form deep trench isolation features and high-density trench capacitors with a single mask and reduced isolation (e.g., deep n-region) spacing.

[0012] Figure 1 and 2 An example integrated circuit semiconductor device 100 is shown including two metal oxide semiconductor (MOS) transistors 101. Some examples may also include a stand-alone discrete transistor semiconductor device having a single transistor. Figure 1The transistor 101 in FIG. 1 has a single gate, source, and drain finger structure. In other embodiments, the transistor can be constructed using multiple finger structures surrounding a central finger, such as a source-centered configuration, a drain-centered configuration, etc. The deep trench isolation and trench capacitor concepts described can be implemented in combination with any type or form of transistor, such as a MOS transistor, a bipolar transistor, etc. In addition, the various aspects described can be used in combination with a drain-extended MOS transistor (not shown). The examples described include doped regions of various semiconductor structures that can be characterized as p-doped and / or n-doped regions or portions, and include regions having a particular type of majority carrier dopant, such as an n-type dopant or a p-type dopant.

[0013] Transistor 101 is fabricated on and / or in a semiconductor substrate 102. In one example, semiconductor substrate 102 is a silicon wafer, a silicon-on-insulator (SOI) substrate, or other semiconductor structure. In one example, substrate 102 is a p-doped silicon substrate or wafer having a first (e.g., top) side 103 (wherein each buried layer 104, 106 is formed) and a second (e.g., bottom) side 105. In another possible implementation, substrate 102 includes one or more epitaxial silicon layers (not shown) formed on a top surface, wherein one or more of buried layers 104, 106 are formed in an epitaxial layer of the substrate. In the illustrated example, substrate 102, buried layers 104 and 106, and an upper semiconductor surface layer (e.g., body region 108) comprise a semiconductor structure. The example semiconductor structure includes a first doped layer 106 comprising a p-type majority carrier dopant. In one embodiment, the p-type layer comprises a portion implanted with boron to form a p-type buried layer (PBL) along with an upper or top side 107. A semiconductor surface layer 108 extends over (e.g., directly over) the p-type buried layer 106 and comprises the upper side 103 of the semiconductor structure. An example layer 104 (e.g., an n-type buried layer or NBL) comprises an n-type majority carrier dopant. The NBL 104 extends from beneath the PBL 106 toward the second side 105 along a vertical Z-direction. In one example, a first epitaxial silicon layer is formed on the upper surface of the silicon wafer substrate 102, and the entire first epitaxial layer or a portion thereof is implanted with an n-type dopant (e.g., phosphorus) to form the NBL 104. In this example, a second epitaxial silicon layer is formed over the first epitaxial layer, and the entire second epitaxial layer or a portion thereof is implanted with a p-type dopant (e.g., boron) to form, along with the upper side 107, the p-type buried layer 106. In one example, the PBL region 106 is formed through the first epitaxial surface using ion implantation. The example surface layer 108 has a p-type majority carrier dopant and extends downward from the first side 103 along the Z-direction.

[0014] Transistor 101 is formed on or in a semiconductor surface layer 108 within an active region 110 of semiconductor structures 102, 104, 106, 108. The example semiconductor surface layer 108 includes a p-type majority carrier dopant. The illustrated device 100 includes an outer oxide isolation structure 118 surrounding transistor 101 along a first (e.g., top) side 103 in semiconductor surface layer 108. In one example, oxide structure 118 is a shallow trench isolation (STI) structure disposed laterally outside transistor 101. In the illustrated example, STI structure 118 defines an end of active region 110 of semiconductor substrate 102 in which transistor 101 is formed.

[0015] The illustrated device 100 includes a trench-based isolation structure 120, referred to as a deep trench isolation structure. Figure 1 A deep trench isolation structure 120 is formed adjacent to the STI structure 118 and laterally surrounds or encircles the transistor 101 and the active region 110 of the semiconductor structure. The isolation structure 120 includes a first trench 121 extending downward from the first side 103 through the semiconductor structures 102, 104, 106, 108 to the buried layer 104. The isolation structure 120 also includes a first deeply doped region 122 having an n-type majority carrier dopant (e.g., phosphorus). The first deeply doped region 122 surrounds the first trench 121 and extends from the semiconductor surface layer 108 to the buried layer 104.

[0016] The isolation structure 120 further includes a first dielectric liner extending from the semiconductor surface layer 108 to the buried layer 104 along the sidewalls of the first trench 121. Any single or multi-layer dielectric liner can be used. In one example, the first dielectric liner includes a first oxide layer 123, a nitride layer 124, and a second oxide layer 125. The first oxide layer 123 (e.g., silicon dioxide or SiO2) extends from the semiconductor surface layer 108 to the buried layer 104 along the sidewalls of the first trench 121. The nitride layer 124 (e.g., silicon nitride or silicon oxynitride) extends from the semiconductor surface layer 108 to the buried layer 104 along the first oxide layer 123. The second oxide layer 125 (e.g., silicon dioxide or SiO2) extends from the semiconductor surface layer 108 to the buried layer 104 along the nitride layer 124.

[0017] The isolation structure 120 further includes a first polysilicon 126 extending inside the first dielectric liners 123, 124, 125. The first polysilicon 126 fills the first trench 121 to the top side 103 of the semiconductor surface layer 108. In one example, the first polysilicon 126 includes a p-type majority carrier dopant (e.g., boron). Figure 1 and 2 In the example of FIG, the deep trench isolation structure 120 is formed as a ring structure laterally surrounding the transistor 101. Figure 11 , the first trench 121 has a first depth 127 and a first width 128. The semiconductor device 100 also includes a shallow implanted region 129 having an n-type majority carrier dopant (e.g., a shallow n-well implanted with phosphorus). The shallow implanted region 129 extends along the sides of the first trench 121 within the first deeply doped region 122 in the semiconductor surface layer 108. In one example, the shallow implant is also used to form lower n-type source / drain features (not shown) for transistors in the device 100.

[0018] The illustrated device 100 also includes one or more trench-based capacitors. In one example, the trench capacitor 130 can be constructed using a single trench. Figure 1 and 2 In the example of , the capacitor 130 includes a plurality of second trenches 131 extending individually through the semiconductor structures 102 , 104 , 106 , 108 to the buried layer 104 . Each of the second trenches 131 is surrounded by a second deeply doped region 132 . Figure 1 Three trenches 131 are shown extending from the first side 103 through the semiconductor structure to the buried layer 104. The second trench 131 has a second depth 137 and a second width 138. Figure 1 and 2 In the device of FIG. 1 , the first width 128 of the first (isolation) trench 121 is greater than the second (capacitor trench) width 138. The first width 128 of the first trench 121 is greater than the second width 138 of the capacitor trench 131. In one example, the first width 128 of the first trench 121 is about 1.5 μm, e.g., from 1.35 μm to 1.65 μm, and the second width 138 of the capacitor trench 131 is about 1.2 μm, e.g., from 1.05 μm to 1.35 μm.

[0019] The example capacitor 130 further includes a second dielectric liner (e.g., layers 133, 134, and 135) in each of the trenches 131. The second dielectric liner extends from the semiconductor surface layer 108 to the buried layer 104 along the sidewalls of the second trenches 131. The example second dielectric liner is a multilayer structure having a third oxide layer 133 extending from the semiconductor surface layer 108 to the buried layer 104 along the sidewalls of the second trenches 131. The example second dielectric liner also includes a second nitride layer 134 extending from the semiconductor surface layer 108 to the buried layer 104 along the third oxide layer 133 and a fourth oxide layer 135 extending from the semiconductor surface layer 108 to the buried layer 104 along the second nitride layer 134.

[0020] Capacitor 130 also includes a second deeply doped region 132 implanted with an n-type majority carrier dopant (e.g., phosphorus). Second deeply doped region 132 surrounds second trench 131 and extends from semiconductor surface layer 108 to buried layer 104. Additionally, capacitor 130 includes a second polysilicon 136 implanted with a p-type majority carrier dopant (e.g., boron). Second polysilicon 136 extends within second dielectric liners 133, 134, 135 and fills second trench 131 to top side 103 of semiconductor surface layer 108. Capacitor 130 also includes a shallowly implanted region 129 implanted with a majority carrier dopant of the second conductivity type. Shallowly implanted region 129 extends in semiconductor surface layer 108 between second trenches 131 within second deeply doped region 132.

[0021] Semiconductor device 100 includes a metallization structure extending over semiconductor surface layer 108. The metallization structure includes conductive features connecting first polysilicon 126 to first deeply doped region 122 of trench-based isolation structure 120, second conductive features connected to second polysilicon 136 to form a first capacitor plate, and further conductive features connected to second deeply doped region 132 to form a second capacitor plate of capacitor 130. The metallization structure includes a first dielectric structure layer 154 formed over the semiconductor structure and a multi-level upper metallization structure 156. In one example, first dielectric structure layer 154 is a pre-metal dielectric (PMD) layer disposed over transistor 101 and the upper surface of the semiconductor structure. In one example, first dielectric structure layer 154 includes silicon dioxide (SiO2) deposited over transistor 101, semiconductor surface layer 108, and STI structure 118. Metallization structures 154 and 156 cover transistor 101 and provide internal and / or external electrical interconnects to the transistor's source, drain, and gate terminals.

[0022] The PMD layer 154 includes a contact structure 160 (e.g., tungsten) that provides direct electrical connection to one or more features of the transistor 101, such as direct contact or connection through a silicide layer (not shown) such as CoSi2. The PMD material layer 154 is formed on the illustrated structure, with the contact structure 160 formed therein to provide electrical interconnect access to one or more additional upper metallization layers 158 and 164-168. In one example, the silicide is formed on the top surfaces of the source, drain, and gate electrode structures of the transistor 101 and on top of the polysilicon features 126, 136 and to the deeply doped regions 122, 132. The contacts 160 of the PMD layer 154 are connected to the polysilicon features 126, 136 and the deeply doped regions 122, 132 of the isolation structure 120 and the capacitor 130.

[0023] The upper metallization structure 156 includes one or more layers. In the illustrated example, the upper metallization structure 156 includes a first metallization layer 158 formed on the PMD layer 154 and a second metallization layer 158 formed on the PMD layer 154. Figure 1 Additional metallization layers 164, 165, 166, 167, and 168 on the previous layers shown in FIG. Figure 1 and 2 The device 100 in FIG. 1 is shown as a wafer 170 prior to singulation and packaging, but the illustrated structure represents the described features after separation into dies for packaging. Although the example die 170 is an integrated circuit having multiple components such as transistor 101, other independent discrete semiconductor device implementations may include a single transistor or other electronic component with isolation structure 120 and at least one capacitor 130.

[0024] The upper metallization structure 156 is a six-layer structure with a first layer 158 (referred to herein as an interlayer or inter-level dielectric (ILD) layer). Different numbers of layers may be used in different implementations. In one example, the first ILD layer 158 and the other ILD layers of the upper metallization structure 156 are formed from silicon dioxide (SiO2) or other suitable dielectric materials. In a particular implementation, the individual layers of the multi-layer upper metallization structure 156 are formed in two stages, including an inter-metal dielectric (IMD, not shown) sublayer having conductive metal wiring features or lines 162 (e.g., aluminum, copper, etc.) and an ILD sublayer overlying the IMD sublayer having conductive contacts or plugs 163 (e.g., tungsten vias). The individual IMD and ILD sublayers may be formed from any one or more suitable dielectric materials, such as SiO2-based dielectric materials. The first layer 158 and subsequent layers in the upper metallization structure 156 include conductive metal interconnect structures 162, referred to as lines, formed on the top surface of the underlying layers. In this example, the first layer 158 and subsequent ILD layers also include conductive vias 163 , such as tungsten or aluminum, that provide electrical connection from the metallization features 162 of the individual layers to overlying metallization layers.

[0025] Figure 1 The example of ILD layer 158 includes a second layer 164 disposed on the first layer 158. The ILD layer 158 includes a conductive interconnect structure 162 and a via 163. In various implementations, the structures 162, 163 can be the same metal or different metals. The individual layers can be constructed using any suitable metallization manufacturing process, such as a single or dual damascene process. The illustrated structure includes additional metallization levels with corresponding dielectric layers 165, 166, and 167 and an uppermost or top metallization layer 168. In this example, the individual layers 165-168 include a conductive interconnect structure 162 and associated vias or contact plugs 163.

[0026] The semiconductor structure, electronic components (e.g., transistor 101), capacitor 130, first dielectric structure layer 154, and upper metallization structure 156 together form a wafer or die 170 with an upper side or upper surface 171. Upper side 171 of metallization structure 156 forms the upper side of wafer or die 170. Top metallization layer 168 includes conductive features 169, such as uppermost aluminum vias. Conductive features 169 include a side or surface at upper side 171 of wafer or die 170 at the top of uppermost metallization layer 168. Any number of conductive features 169 may be provided. One or more of conductive features 169 may be electrically coupled to an electronic component, such as one of transistors 101.

[0027] In one example, the upper ILD dielectric layer 168 is covered by one or more passivation layers 173 (eg, a protective overcoat (PO) and / or a passivation layer), such as silicon nitride (SiN), silicon oxynitride (SiO x N y ) or silicon dioxide (SiO2). In one example, the one or more passivation layers 173 include one or more openings that expose a portion of the conductive features 169 to allow the features 169 to be electrically connected to corresponding contact structures 174. The contact structures 174 extend outwardly from the upper side 171 of the metallization structure 156 (e.g., along the Figure 1 1. In one example, the individual contact structures 174 include a conductive seed layer, such as copper, extending outward from the upper side 171 of the metallization structure 156. In one example, the contact structures 174 include titanium (Ti) or titanium tungsten (TiW).

[0028] The metallization structures 154, 156 include first conductive features 160, 162 of the metallization structures 154, 156 that connect the first polysilicon 126 to the first deeply doped region 122. This provides an isolation trench structure 120 that electrically isolates the active region 110 of the semiconductor structure from the capacitor 130 and other areas of the wafer or die 170. Additionally, the metallization structures include second conductive features 160, 162 that are connected to the second polysilicon 136 to form a first capacitor plate and further conductive features 160, 162 that are connected to the second deeply doped region 132 to form a second capacitor plate. The metallization structures 154, 156 allow for additional conductive connections (not shown) that connect the first and second capacitor plates to other circuitry within the wafer or die 170 and / or provide external connections for one or both of the first and second capacitor plates.

[0029] Figure 2 A top view of a portion of device 100 is shown. In the illustrated example, isolation structure 120 extends around the lateral periphery of active area 110 and also extends around three sides of the capacitor region. In this example, the capacitor region includes a plurality of capacitor trenches 131, three of which are shown in FIG. Figure 1 In one example, the capacitor trench width 138 is about 1.2 μm, and the spacing distance between adjacent capacitor structures is about 0.6 μm. In one example, the shallow n-well implant (e.g. Figure 1 In area 129, Figure 2 In one example, NBL 104 extends into the capacitor region by about 0.1 μm and encloses the capacitor region by about 0.65 μm. Figure 1 In another example (not shown), the capacitor region is enclosed by NBL 104. In one example, the silicide blocking layer (not shown) extends beyond the capacitor region by approximately 0.25 μm and into the capacitor region by approximately 0.255 μm.

[0030] Also refer to Figures 3 to 18 , Figure 3 A method 300 is shown for fabricating an electronic device, such as an integrated circuit or a stand-alone device. The illustrated method 300 also includes a process or method for fabricating an isolation structure in a semiconductor device. Figures 4 to 18 Showing various manufacturing stages according to method 300 Figure 1 and 2 The method 300 begins at 302, where an n-type implant is performed to form an n-doped region, such as Figure 1 The NBL region 104 in the.

[0031] In one example, a first epitaxial silicon layer is formed on the upper surface of a silicon wafer substrate 102, and the entire first epitaxial layer or a portion thereof is implanted with an n-type dopant (e.g., Sb, etc.) at 302 to form the NBL 104. In one example, the entire first epitaxial layer or a portion thereof is implanted with a p-type dopant (e.g., boron, etc.) at 303 to form a p-type buried layer 106 along with the upper side 107. In one example, the PBL region 106 is formed through the last silicon surface (e.g., the top of the second epitaxial layer) using ion implantation, having a depth set by using a high implant energy. In one example, another epitaxial silicon deposition process is performed at 304, which deposits a second epitaxial silicon layer on the first epitaxial layer. At 306, the semiconductor surface layer 108 (e.g., labeled p-body) is implanted with a p-type majority carrier dopant (e.g., boron) and extends along the Z-direction from the first side 103 downward to the upper side 107 of the PBL 106.

[0032] The method 300 also includes depositing an etch stop layer at 306 . Figure 4An example is described in which a deposition process 402 is performed to deposit a nitride or oxynitride or oxide layer 400 on the first side 103 of the semiconductor structure. In one example, the layer 400 operates as an etch stop layer for subsequent planarization, such as chemical mechanical polishing (CMP). In one example, the etch stop layer 400 comprises a nitride or oxynitride or oxide layer formed to about (e.g. 100 to ) and a nitride is formed on the pad oxide to a thickness of about 0.2 μm.

[0033] The method 300 further includes depositing and patterning a thick resist layer at 308 to have an opening for the isolation structure and a second opening for the trench capacitor. Figure 5 An example is shown in which process 503 is performed. Process 503 deposits and patterns a resist mask 500 on the hard mask layer 400 on the first surface 103 of the semiconductor structure. In one example, process 503 includes forming the resist layer 500 and patterning a first opening 501 with a first width 128 and a second opening 502 with a second width 138, wherein the first width 128 is greater than the second width 138. A trench 121 (e.g., corresponding to the desired isolation structure) is formed over the desired isolation structure 120. Figure 1 ) is patterned with a first opening 501 having a width 128 of the desired width. A first opening 501 is patterned with a width 128 of the desired width corresponding to the desired capacitor trench 131 ( Figure 1 ). In one example, the width 128 of the first resist opening 501 is about 1.5 μm, and the width 138 of the second resist opening 502 is about 1.2 μm.

[0034] The method 300 continues at 310 where deep trench etching is performed through the nitride 400 and silicon of the semiconductor surface layer 108 , the PBL 106 , and through at least a portion of the NBL 104 to form trenches 121 and 131 using the patterned resist 500 as an etch mask. Figure 6 An example is shown in which an etching process 600 etches a first trench 121 extending through the semiconductor surface layer 108 into the buried layer 104 through the resist opening 501. The etching process 600 simultaneously etches through the second opening 502 to form a trench 131 extending into the NBL 104. In the illustrated example, a first trench width 128 generally corresponds to the size of the first opening 501, and a second trench width 138 generally corresponds to the size of the second opening 502. The wider first opening 501 causes the first trench 121 to extend to a first depth 127 (e.g., approximately 6.8 μm, e.g., 6.2 μm to 7.2 μm), which is greater than the second depth 137 of the second trench 131.

[0035] Continuing at 312 and 314 , the method 300 further includes one or more deep trench implants for forming a first deeply doped region 122 surrounding the first trench 121 and a second deeply doped region 132 surrounding the second trench 131 . Figure 7 and 8 An example is shown in which a first implantation process 700 is performed using the remaining resist mask 500 to simultaneously implant n-type dopants (e.g., phosphorus) through the openings 501 and 502 to form a first deeply doped region 122 and a second deeply doped region 132, respectively. The first deeply doped region 122 surrounds the first trench 121 and extends from the semiconductor surface layer 108 to the buried layer 104. The second deeply doped region 132 surrounds the second trench 131 and extends from the semiconductor surface layer 108 to the buried layer 104.

[0036] In one example, the first implant process at 312 is a sloped deep N trench sidewall implant. Figure 7 An example is shown in which a tilted implantation process 700 implants phosphorus or other n-type dopants through the resist openings 501 and 502 to form a 9x10 4 cm -3 A dose of 200 keV and a plant energy of 200 keV are implanted into the sidewalls of the trenches 121 and 131 to form a first deeply doped region 122 and a second deeply doped region 132 rotated four times at a twist angle of 45 degrees relative to the layout direction (for example, the direction of the transistor source, drain and gate fingers) at an implantation angle of 16 degrees.

[0037] At 314 , a second implant is performed to implant the bottoms of regions 122 and 132 . Figure 8 An example is shown in which implantation of phosphorus or other n-type dopants is performed through the resist openings 501 and 502 to form a 9x10 4 cm -3 The implantation process 800 with a dose of 50 keV and an implantation angle of 0 degrees can further implant silicon below the bottom of the trenches 121 and 131.

[0038] In one example, Figure 3 The annealing process is performed at 316, which oxidizes the silicon on the sidewalls of the trenches and forms a dummy or sacrificial oxide layer on the sidewalls of the trenches 121 and 131, for example, to In one example, a wet clean process is then used at 316 to strip the sacrificial oxide with a 50% overetch to remove approximately 100% of the sacrificial oxide from the sidewalls of trenches 121 and 131. In one example, the overetch at 316 removes the deposited sacrificial oxide and the original silicon that may have been damaged during the implantation at 312 and / or 314.

[0039] The example method 300 continues at 318, 320, and 322 with a deposition process to form a dielectric liner on the sidewalls of the trenches 121 and 131. The dielectric liner deposition process deposits a dielectric material through the first opening 501 and the second opening 502 of the remaining resist mask 500. Any suitable dielectric that forms the capacitor dielectric in the finished trench capacitor 130 can be used. The dielectric liner can be a single layer or a multilayer structure. Figures 9 to 11 A multi-step deposition to form an oxide-nitride-oxide (ONO) dielectric liner in each of trenches 121 and 131 is illustrated.

[0040] exist Figure 3 In step 318 , a first oxide deposition is performed to form a first oxide layer on the sidewalls of the trenches 121 and 131 . Figure 9 An example is shown in which the oxidation annealing process 900 for depositing silicon dioxide 123 (e.g., SiO2) on the sidewalls of the first trench 121 and depositing silicon dioxide 133 and the sidewalls of the second trench 131 is performed at 850° C. In one example, the process 900 (850° C.) results in thermal oxidation of the trench sidewall silicon to form a silicon oxide layer of approximately Thickness (e.g. arrive )'s first oxide layers 123 and 133.

[0041] At 320 , a second deposition process (eg, nitride deposition) is performed to deposit a nitride layer on the first oxide layer along the sidewalls of the trenches 121 and 131 . Figure 10 An example is shown in which a deposition process 1000 (e.g., a deposition temperature of 650° C.) deposits a nitride material 124 (e.g., silicon nitride, silicon oxynitride) onto the first oxide layer 123 in the first trench 121 through the first and second openings of the resist layer 500 and deposits a nitride material 134 onto the first oxide layer 133 along the sidewalls in the second trench 131 through the first and second openings of the resist layer 500. In one example, the process 1000 forms a nitride layer 133 up to about 100° C. Thickness (e.g. from arrive ) nitride material layers 124 and 134.

[0042] At 322 , a third deposition process (eg, oxide deposition) is performed to deposit a second oxide layer on the nitride layer along the sidewalls of the trenches 121 and 131 . Figure 11An example is shown in which a wet oxidation process 1100 grows a second oxide layer, such as an oxynitride 125, on the nitride layer 124 in the first trench 121 through the first opening. In this example, the deposition process 1100 deposits a second oxide layer 135 onto the nitride layer 134 in the second trench 131 through the second opening of the resist layer 500. In one example, the process 1100 forms a second oxide layer 135 up to about 100 mm. Thickness (e.g. arrive )'s second oxide material layers 125 and 135.

[0043] The example method 300 continues at 324 and 326 where polysilicon is deposited to fill the trenches 121 and 131 . Figure 12 An example is shown in which a first polysilicon deposition process 1200 (e.g., Figure 3 324 in the resist layer 500) deposits a first polysilicon 126 through the first opening of the resist layer 500 to fill the first trench 121. The first polysilicon deposition process 1200 also deposits a second polysilicon 136 through the second opening of the resist layer 500 to fill the second trench 131. In one example, the initial deposition process 1200 deposits p-doped polysilicon 126, 136 having a p-type majority carrier dopant (e.g., boron) to a depth of 100 nm. thickness.

[0044] At 326 , a second polysilicon deposition is performed by depositing polysilicon 126 to fill trench 121 and depositing polysilicon 136 to fill second trench 131 . Figure 13 An example is shown where the second polysilicon deposition process 1300 deposits doped polysilicon to fill trenches 121 and 131, for example, to approximately In one example, the target polysilicon deposition thickness is about (For example arrive ) to fill the trenches 121 and 131. Figure 12 and 13 , in one example, an initial polysilicon deposition process 1200 and a trench fill deposition process 1300 form polysilicon 126 , 136 on both sides of the device 100 , including deposition along the bottom side 105 of the semiconductor structure.

[0045] exist Figure 3 Continuing with steps 328 to 332, method 300 further includes a backside polysilicon removal or stripping step at 328. In one example, a wet etch process (not shown) is performed to strip excess polysilicon from the bottom side 105 of the semiconductor structure. At 330, the top side of the wafer is planarized. Figure 14An example is shown in which a chemical mechanical polishing (CMP) process 1400 removes the remaining polysilicon above the top side 103 of the wafer and planarizes the top side of the wafer. The CMP process 1400 stops on the nitride hard mask layer 400, as shown in FIG. Figure 14 At 332, a wet etching process is performed to strip the remaining nitride hard mask layer. Figure 15 An example is shown in which a wet etching process 1500 is performed to remove the remaining nitride layer from the top side 103 of the wafer.

[0046] The method 300 also includes shallow trench isolation (STI) processing at 334 . Figure 16 An example is shown in which an STI fabrication process 1600 is performed in which trenches are etched and filled with an oxide material 118. In one example, the STI process includes growing a pad oxide, depositing a nitride layer (not shown) using low-pressure chemical vapor deposition (LPCVD), patterning and etching trenches in the silicon of the surface layer 108 and the liner and silicon of trenches 121 and 131, growing a liner oxide in the STI trenches to repair the silicon and round off the corners, and then plasma-enhanced CVD (PECVD) depositing TEOS oxide. The process further includes another chemical mechanical polishing of the trench oxide using nitride as an etch stop and then removing the nitride etch stop layer.

[0047] At 336 , a transistor fabrication process is performed including fabricating transistor 101 . Figure 17 A simplified example is shown in which a transistor fabrication process 1700 is performed to produce the transistor structure 101. In one example, the transistor fabrication at 336 includes performing an implantation process to implant n-type majority carriers into the semiconductor surface layer 108 to form shallow implanted regions 129 extending along the sides of the first trench 121 within the deeply doped region 122. In one example, the same implantation process is used to form lowercase Np-type source / drain regions that are features of the transistor 101 or other components (not shown) of the wafer 170.

[0048] exist Figure 3 At 338, method 300 continues with metallization to form one or more dielectric layers along with conductive metal features to provide interconnections for transistors and / or other components of wafer 170. The metallization process at 338 includes forming conductive features to provide capacitor plates of trench capacitor 130 and features interconnecting trench-based isolation structure 120. Figure 18A portion of a metallization process 1800 is illustrated that forms first conductive features 160, 162 that extend over the semiconductor surface layer 108 and connect the first polysilicon 126 to the first deeply doped region 122 to form the trench-based isolation structure 120. The metallization process 1800 also forms second conductive features 160, 162 that connect to the second polysilicon 136 to form the first capacitor plate, and further conductive features 160, 162 that connect to the metallization structures 154, 156 of the second deeply doped region 132 to form the second capacitor plate.

[0049] Figure 3 The process 300 further includes die singulation at 340 of one or more product dies from the wafer 170. The processing at 340 also includes packaging to provide one or more finished semiconductor devices, such as individual components and / or integrated circuits.

[0050] Method 300 provides an integrated process for simultaneously manufacturing both the trench isolation structure 120 and the high-density trench capacitor 130 using a shared resist mask 500. Example embodiments also use a thick resist mask 500 to facilitate processing of both trench types. Using a thick shared mask and similar trench structure architecture for both the isolation structure 120 and the trench capacitor 130 provides economical processing steps and costs. In addition, some examples promote density advantages compared to using non-trench isolation structures with deep well implants. In this regard, deep implanted isolation features extending into the semiconductor structure to the buried layer (e.g., implanted and diffused to extend into the deep n-well in the NBL 104) involve significant lateral diffusion, thereby extending the lateral extent of the isolation features. Some examples do not require a separate deep implant mask and also promote reduced resistance in the deep doped region by using a trench pillar type isolation layout. In addition to the manufacturing cost and time advantages of simultaneously constructing the isolation structure 120 and the trench capacitor 130, some examples also use self-aligned deep doped region implantation on the deep trench sidewalls to provide lateral area control of the isolation feature 120 to reduce the isolation-to-isolation spacing. These features provide significant advantages, particularly when combined with simple modifications to the metallization structure, by shortening the bottom and top plates (e.g., of the deep doped region 122 and the p-type polysilicon structure 126) to form the isolation structure 120. The described embodiments may be modified within the scope of the claims, and other embodiments are possible.

Claims

1. A semiconductor device comprising: a semiconductor surface layer having a first conductivity type; a buried layer having a second conductivity type, the buried layer being disposed on the semiconductor substrate and below the semiconductor surface layer; a metallization structure extending over the semiconductor surface layer; and An isolation structure comprising: a first trench extending from a top side of the semiconductor surface layer through the buried layer and into the semiconductor substrate, a first dielectric liner extending along sidewalls of the first trench, first polysilicon having the first conductivity type, the first polysilicon extending inside the first dielectric liner and filling the first trench to the top side of the semiconductor surface layer, a first doped region having the second conductivity type, the first doped region surrounding a contour of the first trench and extending linearly from the top side of the semiconductor surface layer through the buried layer, and A first conductive feature of the metallization structure connects the first polysilicon to the first doped region.

2. The semiconductor device according to claim 1, further comprising: A capacitor comprising: a second trench extending from the semiconductor surface layer to the buried layer, a second dielectric liner extending along sidewalls of the second trench, a second polysilicon having the first conductivity type, the second polysilicon extending inside the second dielectric liner and filling the second trench to a top side of the semiconductor surface layer, a second doped region having the second conductivity type, the second doped region laterally surrounding the second trench and extending from the semiconductor surface layer to the buried layer, a second conductive feature of the metallization structure connected to the second polysilicon, the second conductive feature corresponding to the first plate of the capacitor, and A third conductive feature of the metallization structure is connected to the second doped region, the third conductive feature corresponding to the second plate of the capacitor. 3 . The semiconductor device of claim 2 , wherein the first trench has a first depth, wherein the second trench has a second depth, and wherein the first depth is greater than the second depth. 4 . The semiconductor device of claim 3 , wherein the first trench has a first width, wherein the second trench has a second width, and wherein the first width is greater than the second width. 5 . The semiconductor device of claim 2 , wherein the first trench has a first width, wherein the second trench has a second width, and wherein the first width is greater than the second width.

6. The semiconductor device according to claim 2, The first dielectric liner comprises: a first oxide layer extending along the sidewalls of the first trench to, a nitride layer extending over the first oxide layer, and a second oxide layer extending over the nitride layer; and The second dielectric liner comprises: a third oxide layer extending along the sidewalls of the second trench, a second nitride layer extending over the third oxide layer, and A fourth oxide layer extends on the second nitride layer.

7. The semiconductor device according to claim 1 , further comprising a capacitor, the capacitor comprising: a plurality of second trenches extending from the semiconductor surface layer to the buried layer, each of the second trenches being surrounded by a second doped region and comprising: a second dielectric liner along the sidewalls of the second trench, and A second polysilicon having the first conductivity type extends inside the second dielectric liner and fills the second trench to the top side of the semiconductor surface layer. 8 . The semiconductor device of claim 7 , wherein the capacitor further comprises an implanted region having the second conductivity type and extending in the semiconductor surface layer between the plurality of second trenches in the second doped region.

9. The semiconductor device of claim 1 , wherein the first dielectric liner comprises: a first oxide layer extending along the sidewalls of the first trench; a nitride layer extending over the first oxide layer; and A second oxide layer extends over the nitride layer. 10 . The semiconductor device of claim 1 , further comprising an implanted region having the second conductivity type and extending in the semiconductor surface layer along a side of the first trench in the first doped region.

11. A method for manufacturing an isolation structure in a semiconductor device, comprising: forming a trench extending from a top side of a semiconductor surface layer having a first conductivity type through a buried layer and into a semiconductor substrate, the buried layer having a second conductivity type, the buried layer being disposed on the semiconductor substrate and below the semiconductor surface layer; performing an implantation process of implanting a dopant of the second conductivity type into the trench to form a doped region surrounding the outline of the trench and extending linearly from the top side of the semiconductor surface layer through the buried layer; performing a deposition process of depositing a dielectric liner on the sidewalls of the trench; performing a deposition process of depositing polysilicon to fill the trench; and Conductive features of a metallization structure extending over the semiconductor surface layer are formed to connect the polysilicon to the doped regions.

12. The method of claim 11 , wherein performing the deposition process of depositing the dielectric liner comprises: performing a first deposition process of depositing a first oxide layer on the sidewalls of the trench; performing a second deposition process of depositing a nitride layer on the first oxide layer; and A third deposition process of depositing a second oxide layer on the nitride layer is performed.

13. The method according to claim 12, further comprising: An implantation process is performed to implant dopants of the second conductivity type into the semiconductor surface layer to form implantation regions extending along sides of the trenches within the doped regions.

14. The method according to claim 11, further comprising: An implantation process is performed to implant dopants of the second conductivity type into the semiconductor surface layer to form implantation regions extending along sides of the trenches within the doped regions.

15. A method of manufacturing a semiconductor device, comprising: forming a resist layer over a top surface of a semiconductor surface layer having a first conductivity type, the semiconductor surface layer being located over a buried layer having a second conductivity type, the buried layer being disposed on a semiconductor substrate, wherein the resist layer comprises a first opening and a second opening; performing an etching process of etching through the first opening to form a first trench extending from a top side of the semiconductor surface layer through the buried layer and into the semiconductor substrate, and etching through the second opening to form a second trench extending through the semiconductor surface layer to the buried layer; performing an implantation process of implanting a dopant of the second conductivity type through the first opening to form a first doped region surrounding the contour of the first trench and linearly extending from the top side of the semiconductor surface layer through the buried layer, and implanting the dopant of the second conductivity type through the second opening to form a second doped region laterally surrounding the second trench and extending from the semiconductor surface layer to the buried layer; performing a deposition process of depositing a dielectric liner on the sidewalls of the first trench and the sidewalls of the second trench; performing another deposition process of depositing polysilicon filling the first trench and the second trench; and forming a first conductive feature of a metallization structure extending above the semiconductor surface layer, the first conductive feature connecting the polysilicon of the first trench to the first doped region to form an isolation structure; forming a second conductive feature of the metallization structure, the second conductive feature connected to the polysilicon of the second trench to form a first plate of a capacitor; and A third conductive feature of the metallization structure is formed connected to the second doped region to form a second plate of the capacitor.

16. The method of claim 15, wherein performing the deposition process of depositing the dielectric liner comprises: performing a first deposition process of depositing a first oxide layer on the sidewalls of the first and second trenches; performing a second deposition process of depositing a nitride layer on the first oxide layer; and A third deposition process of depositing a second oxide layer on the nitride layer is performed. 17 . The method of claim 15 , wherein forming the resist layer comprises patterning the first opening with a first width and patterning the second opening with a second width, and wherein the first width is greater than the second width.

18. The method of claim 17, wherein the first trench has a first depth, wherein the second trench has a second depth, and wherein the first depth is greater than the second depth.

19. The method of claim 15, wherein the first trench has a first depth, wherein the second trench has a second depth, and wherein the first depth is greater than the second depth.

20. The method of claim 15, further comprising: An implantation process is performed to implant dopants of the second conductivity type into the semiconductor surface layer to form implantation regions extending along sides of the first trench within the first doped region.

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