Display device

Abstract

The present disclosure relates to a display device. An embodiment of the display device includes: a display panel, including multiple pixels, multiple gate lines connected to the multiple pixels, and multiple data lines; a gate driving unit, applying gate signals to the multiple gate lines; a data driving unit, applying data signals to the multiple data lines; and a voltage supply unit, generating a gate-on voltage that gradually changes within a frame and a kick-back voltage that gradually changes within a frame and transmitting them to the gate driving unit, wherein among the multiple gate lines, a gate-on voltage that gradually increases as the gate line with the shortest distance to the gate signal is closer to the gate line with the farthest distance to the gate signal is applied, and a kick-back voltage that gradually decreases as the gate line with the shortest distance to the gate signal is closer to the gate line with the farthest distance to the gate signal is applied, and the change in the gate-on voltage within a frame is proportional to the change in the kick-back voltage within a frame.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] Display devices are devices that display images, and include liquid crystal displays (LCDs) and organic light emitting diode displays (OLEDs). These devices are used in a variety of electronic devices, including mobile phones, navigation systems, digital cameras, e-books, portable game consoles, and various terminals.

[0003] A display device includes a display panel having a plurality of pixels, a plurality of gate lines connected to the plurality of pixels, and a plurality of data lines. Each pixel can be connected to the gate lines and the data lines via a switching element. A predetermined gate signal can be applied to the plurality of gate lines. When the gate signal changes from a gate-off voltage to a gate-on voltage, the switching element is turned on in response to the validity of the gate signal, thereby charging the pixel according to the data signal applied to the data line. Subsequently, when the gate signal changes from a gate-on voltage to a gate-off voltage, the switching element is turned off in response to the de-activation of the gate signal, thereby preventing the pixel from being charged.

[0004] When the gate-off voltage is applied, the data voltage value charged to the pixel drops due to parasitic capacitance, potentially preventing the desired image from being displayed. To address this issue, a kickback circuit can be used. This circuit gradually drops to a kickback voltage higher than the gate-off voltage before applying the gate-off voltage, and then applies the gate-off voltage, thereby minimizing the change in the data voltage value.

[0005] When applying gate signals to a display panel, there's a problem where the gate-on voltage decreases as the distance over which the gate signal is applied increases. As a result, switching elements in some rows might not be turned on, or pixels might not be properly charged. To improve this, gradually increasing the gate-on voltage within a frame can be considered.

[0006] However, if the gate-on voltage is gradually increased and applied within a frame, the effectiveness of the kick-back circuit is relatively reduced. Specifically, the gate-off voltage may be applied before the gate signal has dropped to the desired kick-back voltage, potentially causing the data voltage charged to the pixel to drop. Summary of the Invention

[0007] Various embodiments are provided to provide a display device that can reduce variations in data voltage values charged to pixels.

[0008] A display device according to one embodiment includes: a display panel including a plurality of pixels, a plurality of gate lines connected to the plurality of pixels, and a plurality of data lines; a gate driving unit applying gate signals to the plurality of gate lines; a data driving unit applying data signals to the plurality of data lines; and a voltage supply unit generating a gate-on voltage that gradually changes within a frame and a kick-back voltage that gradually changes within a frame and transmitting the voltages to the gate driving unit, wherein the gate-on voltage is applied gradually higher as the gate line with the shortest distance to the gate signal is closer to the gate line with the farthest distance to the gate signal among the plurality of gate lines, and the kick-back voltage is applied gradually lower as the gate line with the shortest distance to the gate signal is closer to the gate line with the farthest distance to the gate signal among the plurality of gate lines, and the amount of change in the gate-on voltage within a frame is proportional to the amount of change in the kick-back voltage within a frame.

[0009] The amount of change in the gate-on voltage may be constant within one frame, and the ratio of the amount of change in the kick-back voltage within one frame to the amount of change in the gate-on voltage within one frame may be adjusted.

[0010] The amount of change in the kick-back voltage within one frame may be constant, and the ratio of the amount of change in the gate-on voltage within one frame to the amount of change in the kick-back voltage within one frame may be adjusted.

[0011] It may be that the multiple gate lines include a first gate line to an nth gate line, and the closer the first gate line is to the nth gate line, the longer the distance for applying the gate signal gradually becomes, and the gate signal is applied to the first gate line to the nth gate line in sequence, and the gate turn-on voltage is applied gradually increasing within one frame, and the kick-back voltage is applied gradually decreasing within one frame.

[0012] It may be that the multiple gate lines include a first gate line to an nth gate line, and the closer from the first gate line to the nth gate line, the longer the distance for applying the gate signal gradually becomes, and the gate signal is applied to the nth gate line to the first gate line in sequence, and the gate turn-on voltage is applied gradually decreasing within one frame, and the kick-back voltage is applied gradually increasing within one frame.

[0013] It may be that, for each gate line, the kick-back time for applying the kick-back voltage is the same.

[0014] It may be that a kick-back time for applying the kick-back voltage is different in at least one gate line among the plurality of gate lines.

[0015] The plurality of gate lines may include a first gate line to an n-th gate line, and the kick-back time may gradually increase or decrease as the first gate line approaches the n-th gate line.

[0016] It may be possible to adjust the amount of change in the kick-back time.

[0017] It may be that the plurality of gate lines include a first gate line to an nth gate line, the kick-back time is maintained constant for the first gate line to the pth gate line, and the kick-back time is gradually increased or decreased as the pth gate line approaches the nth gate line.

[0018] It may be possible to adjust the variation of the kick-back time and the p-value.

[0019] It may be that the multiple gate lines include a first gate line to an nth gate line, the kick-back time is maintained constant for the first gate line to the pth gate line, and the kick-back time is gradually increased or decreased as the pth gate line approaches the qth gate line.

[0020] It may be possible to adjust the variation of the kick-back time, the p value, and the q value.

[0021] A display device involved in one embodiment includes: a display panel, including multiple pixels, multiple gate lines and multiple data lines connected to the multiple pixels; a gate driving unit, applying gate signals to the multiple gate lines; a data driving unit, applying data signals to the multiple data lines; and a voltage supply unit, generating a gate on-voltage that gradually changes within a frame and a kick-back voltage that gradually changes within a frame and transmitting them to the gate driving unit, wherein among the multiple gate lines, the gate on-voltage that gradually increases as the gate line with the shortest distance to which the gate signal is applied approaches the gate line with the farthest distance to which the gate signal is applied, and the kick-back time for applying the kick-back voltage is different for at least one gate line among the multiple gate lines.

[0022] The same kick-back voltage may be applied to the plurality of gate lines.

[0023] The plurality of gate lines may include a first gate line to an n-th gate line, and the kick-back time may gradually increase or decrease as the first gate line approaches the n-th gate line.

[0024] It may be possible to adjust the amount of change in the kick-back time.

[0025] A display device involved in one embodiment includes: a display panel, including multiple pixels, multiple gate lines and multiple data lines connected to the multiple pixels; a gate driving unit, applying gate signals to the multiple gate lines; a data driving unit, applying data signals to the multiple data lines; and a voltage supply unit, generating a gate-on voltage that changes within a frame and a kick-back voltage that changes within a frame and transmitting them to the gate driving unit, dividing the multiple gate lines into multiple intervals, and being able to set the gate-on voltage applied to the gate lines respectively located at the starting position of the first interval of the multiple intervals, the boundary position between the multiple intervals, and the end position of the last interval of the multiple intervals, and dividing the multiple gate lines into multiple intervals, and being able to set the kick-back voltage applied to the gate lines respectively located at the starting position of the first interval of the multiple intervals, the boundary position between the multiple intervals, and the end position of the last interval of the multiple intervals.

[0026] It may be that, within each of the plurality of intervals, the gate-on voltage has a gradually changing value.

[0027] It may be that, within each of the plurality of intervals, the kick-back voltage has a gradually changing value.

[0028] According to various embodiments, a gate-on voltage, a kick-back voltage, etc. are adjusted based on the position of a gate line, so that variations in data voltage values charged to pixels can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a diagram schematically showing a display device according to an embodiment.

[0030] Figure 2 This is a block diagram showing a voltage supply unit of a display device according to an embodiment.

[0031] Figure 3 This is a timing diagram showing gate signals generated by a display device according to one embodiment.

[0032] Figure 4 This is a diagram showing gate output voltages output to some gate lines of a display device according to one embodiment.

[0033] Figure 5 This is a timing diagram showing gate signals generated by a display device according to one embodiment.

[0034] Figure 6 It is a diagram schematically showing a display device according to an embodiment.

[0035] Figure 7 This is a timing diagram showing gate signals generated by a display device according to one embodiment.

[0036] Figure 8 This is a diagram showing gate output voltages output to some gate lines of a display device according to one embodiment.

[0037] Figure 9 This is a diagram showing gate output voltages output to some gate lines of a display device according to one embodiment.

[0038] Figure 10 This is a diagram showing gate output voltages output to some gate lines of a display device according to one embodiment.

[0039] Figure 11 This is a diagram showing gate output voltages output to some gate lines of a display device according to one embodiment.

[0040] Figure 12 1 is a timing diagram showing gate signals generated by a display device according to an embodiment.

[0041] (Explanation of Symbols)

[0042] 100 : display panel; 200 : gate driving unit; 300 : data driving unit; 400 : signal control unit; 500 : voltage supply unit; 510 : receiving unit; 530 : voltage generating unit; 550 : output unit. DETAILED DESCRIPTION

[0043] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be implemented in various forms and is not limited to the embodiments described herein.

[0044] In order to clearly describe the present invention, parts not related to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification.

[0045] In addition, the sizes and thicknesses of various components are arbitrarily shown in the figures for ease of explanation, and the present invention is not necessarily limited to the figures. In the figures, the thicknesses of various layers and regions are exaggerated to clearly illustrate them. Furthermore, in the figures, the thicknesses of some layers and regions are exaggerated for ease of explanation.

[0046] Furthermore, when a portion of a layer, film, region, or the like is located on or above another portion, this includes not only the case where it is directly located on the other portion, but also the case where there is another portion therebetween. Conversely, when a portion is directly located on another portion, this means that there is no other portion therebetween. Furthermore, "located on or above a portion serving as a reference" means being above or below the portion serving as the reference, and does not necessarily mean being above or above in the direction opposite to gravity.

[0047] Furthermore, throughout the specification, when a certain part includes a certain component, this does not exclude other components unless otherwise stated, but rather means that the part may further include other components.

[0048] In addition, throughout the specification, “in plan view” refers to a case where a target portion is viewed from above, and “in cross section” refers to a case where a cross section of the target portion is viewed from the side.

[0049] First, refer to Figure 1 , briefly describing a display device involved in one embodiment.

[0050] Figure 1 It is a diagram schematically showing a display device according to an embodiment.

[0051] like Figure 1 As shown, a display device involved in one embodiment includes: a display panel 100, including a plurality of pixels PX, a plurality of gate lines GL1-GLn and a plurality of data lines DL1-DLm connected to the plurality of pixels PX; a gate driving unit 200, applying gate signals to the gate lines GL1-GLn; and a data driving unit 300, applying data signals to the data lines DL1-DLm.

[0052] Multiple pixels PX can be arranged in rows and columns. However, this configuration of the pixels PX is only an example and can be modified in various ways. Multiple pixels PX can be connected to gate lines GL1-GLn and data lines DL1-DLm through switching elements such as thin film transistors.

[0053] The plurality of gate lines GL1-GLn may be formed to extend long along the row direction. The plurality of gate lines GL1-GLn may include a first gate line GL1, a second gate line GL2, a third gate line GL3, and an n-th gate line GLn, arranged sequentially from the upper edge of the display panel 100. Each pixel PX in the first row may be connected to the first gate line GL1, and each pixel PX in the second row may be connected to the second gate line GL2. Each pixel PX in the third row may be connected to the third gate line GL3, and each pixel PX in the n-th row may be connected to the n-th gate line GLn.

[0054] The plurality of data lines DL1-DLm may be formed in a form extending long along the column direction. The plurality of data lines DL1-DLm may include a first data line DL1, a second data line DL2, to an mth data line DLm sequentially arranged from the left edge of the display panel 100. Each pixel PX located in the first column may be connected to the first data line DL1, each pixel PX located in the second column may be connected to the second data line DL2, and each pixel PX located in the mth column may be connected to the mth data line DLm.

[0055] The display panel 100 may be formed of various display panels, such as an organic light-emitting display panel, a liquid crystal display panel, an electrophoretic display panel, an electrowetting display panel, etc. Furthermore, the display panel 100 may also be formed of new-generation display panels, such as a micro-light-emitting diode (Micro LED) display panel, a quantum dot light-emitting diode (QLED) display panel, or a quantum dot organic light-emitting diode (QD-OLED) display panel.

[0056] The gate driver 200 is connected to a plurality of gate lines GL1-GLn. The gate driver 200 can sequentially apply gate signals to the plurality of gate lines GL1-GLn. For example, the gate signal can be applied first to the first gate line GL1, then to the second gate line GL2, and finally to the nth gate line GLn at the end of a frame. However, this is merely an example, and the gate signal can also be applied first to the nth gate line GLn, and finally to the first gate line GL1 at the end of a frame.

[0057] The gate signal may include a gate-on voltage VGH, a kick-back voltage VKB, and a gate-off voltage VGL. The kick-back voltage VKB may have a value between the gate-on voltage VGH and the gate-off voltage VGL. When the gate-on voltage VGH is applied to the gate lines GL1-GLn, the gate output voltage of the gate lines GL1-GLn may rise while the pixels PX connected to the corresponding gate lines GL1-GLn are charged to a predetermined data voltage value. Subsequently, when the kick-back voltage VKB is applied to the gate lines GL1-GLn, the gate output voltage of the gate lines GL1-GLn may drop. Subsequently, when the gate-off voltage VGL is applied to the gate lines GL1-GLn, the gate output voltage of the gate lines GL1-GLn further drops while the switching elements connected to the corresponding gate lines GL1-GLn are disconnected.

[0058] The gate driver 200 may be located at one side edge of the display panel 100. For example, the gate driver 200 may be directly formed on the substrate of the display panel 100 using an ASG (Amorphous Silicon Gate) method or an OSG (Oxide Silicon Gate) method. However, this is merely an example, and the gate driver 200 may also be located at both side edges of the display panel 100. In addition, the gate driver 200 may be mounted on a flexible printed circuit board (FPCB) using a chip on film (COF) method, and may be electrically connected to the display panel 100 via the FPCB.

[0059] The display device according to an embodiment may further include a voltage supply unit 500. The voltage supply unit 500 generates a gate-on voltage VGH, a kick-back voltage VKB, and a gate-off voltage VGL and transmits them to the gate driving unit 200. In an embodiment, the gate-on voltage VGH and the kick-back voltage VKB may have different values depending on the position of the gate lines GL1-GLn. Figures 2 to 4 The magnitudes of the gate-on voltage VGH and the kick-back voltage VKB will be described again later.

[0060] The data driver 300 can be connected to the plurality of data lines DL1-DLm. The data driver 300 can apply data signals to the plurality of data lines DL1-DLm. The data driver 300 can be mounted on a flexible printed circuit board (FPCB) in a chip-on-film (COF) manner and electrically connected to the display panel 100 via the FPCB.

[0061] The display device according to one embodiment may further include a signal control unit 400. The signal control unit 400 may receive image signals and control signals for controlling the display of the image signals (e.g., vertical synchronization signals, horizontal synchronization signals, main clock signals, and data strobe signals) from the outside. Based on these control signals, the signal control unit 400 may apply data signals and data control signals to the data driving unit 300 to process the image signals into data signals that meet the operating conditions of the display panel 100, and may also apply gate control signals to the gate driving unit 200. The data control signals may be formed by a horizontal synchronization start signal, a clock signal, a line latch signal, etc., and the gate control signals may be formed by a gate start signal, a gate clock signal, and an output strobe signal, etc.

[0062] Further reference below Figures 2 to 4 , further illustrating a display device involved in an embodiment.

[0063] Figure 2 is a block diagram showing a voltage supply unit of a display device according to an embodiment. Figure 3 is a timing diagram showing gate signals generated by a display device according to an embodiment. Figure 4 This is a diagram showing gate output voltages output to some gate lines of a display device according to one embodiment.

[0064] like Figure 2As shown, the voltage supply unit 500 of the display device involved in one embodiment may include: a receiving unit 510 that receives input signals from the outside; a voltage generating unit 530 that generates a gate-on voltage VGH, a kick-back voltage VKB and a gate-off voltage VGL; and an output unit 550 that transmits the generated voltages to the gate driving unit 200.

[0065] like Figure 3 As shown, if the gate start signal STV is applied, a frame begins and enters the active period (ActivePeriod). A gate-on voltage VGH can be applied to each gate line GL1-GLn. The gate-on voltage VGH can be formed by a gradually changing value within a frame. In this case, among the multiple gate lines GL1-GLn, a gradually increasing gate-on voltage VGH can be applied, starting from the gate line GL1-GLn with the shortest distance to which the gate signal is applied and moving closer to the gate line GL1-GLn with the farthest distance to which the gate signal is applied.

[0066] For example, the first gate line GL1 may have the shortest distance to which a gate signal is applied, and the n-th gate line GLn may have the longest distance to which a gate signal is applied. In this case, the gate-on voltage VGH applied to the first gate line GL1 may have the lowest value, and the gate-on voltage VGH applied to the second gate line GL2 may have a higher value than the gate-on voltage VGH applied to the first gate line GL1. Furthermore, the gate-on voltage VGH applied to the third gate line GL3 may have a higher value than the gate-on voltage VGH applied to the second gate line GL2. Furthermore, the gate-on voltage VGH applied to the n-th gate line GLn may have the highest value.

[0067] For example, a gate signal may be applied to the first gate line GL1 first, then to the second gate line GL2, and finally to the nth gate line GLn at the end of a frame. In this case, the output unit 550 of the voltage supply unit 500 first outputs the lowest gate-on voltage VGH and sequentially outputs progressively higher gate-on voltages VGH. The output unit 550 of the voltage supply unit 500 may output the highest gate-on voltage VGH last.

[0068] The gate-on voltage VGH applied to each gate line GL1-GLn can be a predetermined value. Therefore, the change in gate-on voltage VGH, ΔVh, can be constant within a frame. Within a frame, the change in gate-on voltage VGH, ΔVh, refers to the difference between the gate-on voltage VGH applied to the first gate line GL1 and the gate-on voltage VGH applied to the nth gate line GLn. For example, the change in gate-on voltage VGH, ΔVh, can be approximately 5V.

[0069] Furthermore, a kick-back voltage VKB may be applied to each gate line GL1-GLn. The kick-back voltage VKB may be formed to have a gradually changing value within a frame. In this case, a gradually decreasing kick-back voltage VKB may be applied as the gate line GL1-GLn with the shortest gate signal applied thereto approaches the gate line GL1-GLn with the longest gate signal applied thereto.

[0070] For example, the first gate line GL1 may have the shortest distance to which a gate signal is applied, and the n-th gate line GLn may have the longest distance to which a gate signal is applied. In this case, the kick-back voltage VKB applied to the first gate line GL1 may have the highest value, and the kick-back voltage VKB applied to the second gate line GL2 may have a lower value than the kick-back voltage VKB applied to the first gate line GL1. In addition, the kick-back voltage VKB applied to the third gate line GL3 may have a lower value than the kick-back voltage VKB applied to the second gate line GL2. In addition, the kick-back voltage VKB applied to the n-th gate line GLn may have the lowest value.

[0071] For example, a gate signal may be applied to the first gate line GL1 first, then to the second gate line GL2, and finally to the nth gate line GLn at the end of a frame. In this case, the output unit 550 of the voltage supply unit 500 may first output the highest kick-back voltage VKB and then sequentially output the kick-back voltages VKB that gradually decrease. The output unit 550 of the voltage supply unit 500 may finally output the lowest kick-back voltage VKB.

[0072] The kick-back voltage VKB applied to each gate line GL1-GLn can be adjusted. Therefore, the change in the kick-back voltage VKB, ΔVk, can be adjusted within a frame. The change in the kick-back voltage VKB, ΔVk, within a frame refers to the difference between the kick-back voltage VKB applied to the first gate line GL1 and the kick-back voltage VKB applied to the nth gate line GLn. The change in the gate-on voltage VGH, ΔVh, within a frame can be proportional to the change in the kick-back voltage VKB, ΔVk, within a frame. The change in the kick-back voltage VKB, ΔVk, within a frame can be determined according to Equation 1.

[0073]

Mathematical formula 1

[0074] ΔVk=αΔVh

[0075] That is, the change ΔVk of the kick-back voltage VKB within a frame can be α times the change ΔVh of the gate-on voltage VGH within a frame. In this case, α can be a value greater than 0 and less than 2. The ratio α of the change ΔVk of the kick-back voltage VKB within a frame to the change ΔVh of the gate-on voltage VGH within a frame can be adjusted. The receiving unit 510 of the voltage supply unit 500 can externally receive an input of the ratio α of the change ΔVk of the kick-back voltage VKB within a frame to the change ΔVh of the gate-on voltage VGH within a frame. Based on this ratio, the kick-back voltage VKB applied to each gate line GL1-GLn can be calculated and generated.

[0076] For example, the change ΔVh in the gate-on voltage VGH can be approximately 5V. In this case, the change ΔVk in the kick-back voltage VKB can be approximately 5V. Furthermore, the change ΔVk in the kick-back voltage VKB can be modified based on the α value input to the receiving unit 510 of the voltage supply unit 500. For example, the change ΔVk in the kick-back voltage VKB can be approximately 4V or approximately 6V. In other words, the change ΔVk in the kick-back voltage VKB can be adjusted by appropriately inputting the α value as needed.

[0077] like Figure 4 As shown, gate signals may be applied sequentially to the gate lines GL1 -GLn. Figure 4 It represents the gate output voltage output to a portion of the gate lines GL1 -GLn (eg, the first gate line GL1 , the second gate line GL2 , and the third gate line GL3 ).

[0078] The lowest gate-on voltage VGH can be applied to the first gate line GL1, where the gate signal is applied at the shortest distance, while progressively higher gate-on voltages VGH can be applied to the second and third gate lines GL2 and GL3. As the distance from the first gate line GL1 to the nth gate line GLn increases, a voltage drop occurs. In a display device according to one embodiment, progressively higher gate-on voltages VGH are applied as the distance from the first gate line GL1 to the nth gate line GLn approaches. Therefore, even if a voltage drop occurs, the gate output voltages of the gate lines GL1-GLn can maintain a constant value.

[0079] Furthermore, the highest kick-back voltage VKB can be applied to the first gate line GL1, where the gate signal is applied at the shortest distance, while gradually lower kick-back voltages VKB can be applied to the second and third gate lines GL2 and GL3. When a constant kick-back voltage VKB is applied to each gate line GL1-GLn, as indicated by the dashed lines, the gate output voltage of each gate line GL1-GLn does not drop sufficiently. In other words, the effect of the kick-back circuit decreases with increasing distance between gate signals. In a display device according to one embodiment, a gradually lower kick-back voltage VKB is applied from the first gate line GL1 to the nth gate line GLn. As a result, as indicated by the solid lines, the gate output voltage of each gate line GL1-GLn can drop sufficiently. Therefore, even when the gate-off voltage VGL is applied to each gate line GL1-GLn, the drop in the data voltage value charged in the pixel PX can be reduced. In other words, the variation in the data voltage value charged in the pixel PX can be reduced.

[0080] Below, refer to Figure 5 , describing a display device according to an embodiment.

[0081] Figure 5 The embodiment shown relates to a display device having Figures 1 to 4 The display devices of the embodiments shown have many common parts, so the description of the common parts is omitted. In this embodiment, the order of applying gate signals is different from that of the previous embodiment, which is further described below.

[0082] Figure 5 This is a timing diagram showing gate signals generated by a display device according to one embodiment.

[0083] Similar to the aforementioned embodiment, a gate-on voltage VGH can be applied to each gate line GL1-GLn of the display device according to one embodiment. The gate-on voltage VGH can be formed by gradually changing values within a frame. In this case, among the multiple gate lines GL1-GLn, a gate-on voltage VGH that gradually increases as the gate line GL1-GLn with the shortest gate signal application distance approaches the gate line GL1-GLn with the farthest gate signal application distance. For example, the first gate line GL1 can have the shortest gate signal application distance, and the nth gate line GLn can have the farthest gate signal application distance.

[0084] In this embodiment, a gate signal may be applied to the nth gate line GLn first, and a gate signal may be applied to the first gate line GL1 at the end of a frame. In this case, the output unit 550 of the voltage supply unit 500 may output the highest gate-on voltage VGH first, and may sequentially output gradually lower gate-on voltages VGH. The output unit 550 of the voltage supply unit 500 may output the lowest gate-on voltage VGH last.

[0085] Furthermore, a kick-back voltage VKB may be applied to each gate line GL1-GLn. The kick-back voltage VKB may be formed by a gradually changing value within a frame. In this case, a gradually decreasing kick-back voltage VKB may be applied as the gate line GL1-GLn with the shortest gate signal applied thereto approaches the gate line GL1-GLn with the farthest gate signal applied thereto. For example, the first gate line GL1 may have the shortest gate signal applied thereto, and the nth gate line GLn may have the farthest gate signal applied thereto.

[0086] In this embodiment, a gate signal may be applied first to the nth gate line GLn, and a gate signal may be applied to the first gate line GL1 at the end of a frame. In this case, the output unit 550 of the voltage supply unit 500 may first output the lowest kick-back voltage VKB and then sequentially output progressively higher kick-back voltages VKB. The output unit 550 of the voltage supply unit 500 may finally output the highest kick-back voltage VKB.

[0087] Below, refer to Figure 6 A display device according to an embodiment will be described.

[0088] Figure 6 The embodiment shown relates to a display device having Figures 1 to 4 The display devices of the embodiments shown have many common parts, so the description of the common parts is omitted. In this embodiment, the difference from the previous embodiment is that the distance for applying the gate signal is the farthest from the first gate line, which is further described below.

[0089] Figure 6 It is a diagram schematically showing a display device according to an embodiment.

[0090] Similar to the aforementioned embodiment, a gate-on voltage VGH can be applied to each gate line GL1-GLn of the display device according to one embodiment. The gate-on voltage VGH can be formed to have a gradually changing value within a frame. In this case, the gate-on voltage VGH can be applied to the gate lines GL1-GLn, gradually increasing as the gate line GL1-GLn with the shortest gate signal applied thereto approaches the gate line GL1-GLn with the farthest gate signal applied thereto.

[0091] In this embodiment, the first gate line GL1 may be the farthest from which a gate signal is applied, and the nth gate line GLn may be the closest to which a gate signal is applied. In this case, the gate-on voltage VGH applied to the first gate line GL1 may have the highest value, and the gate-on voltage VGH applied to the second gate line GL2 may have a lower value than the gate-on voltage VGH applied to the first gate line GL1. Furthermore, the gate-on voltage VGH applied to the third gate line GL3 may have a lower value than the gate-on voltage VGH applied to the second gate line GL2. Furthermore, the gate-on voltage VGH applied to the nth gate line GLn may have the lowest value.

[0092] For example, a gate signal may be applied to the first gate line GL1 first, then to the second gate line GL2, and finally to the nth gate line GLn at the end of a frame. In this case, the highest gate-on voltage VGH may be output first, and gradually lower gate-on voltages VGH may be output in sequence. Finally, the lowest gate-on voltage VGH may be output.

[0093] However, this is merely an example, and the order in which gate signals are applied can be changed. For example, a gate signal can be applied first to the nth gate line GLn, and then to the first gate line GL1 at the end of a frame. In this case, the lowest gate-on voltage VGH can be output first, followed by successively higher gate-on voltages VGH. Finally, the highest gate-on voltage VGH can be output.

[0094] Furthermore, a kick-back voltage VKB may be applied to each gate line GL1-GLn. The kick-back voltage VKB may be formed to have a gradually changing value within a frame. In this case, a gradually decreasing kick-back voltage VKB may be applied as the gate line GL1-GLn with the shortest gate signal applied thereto approaches the gate line GL1-GLn with the longest gate signal applied thereto.

[0095] In this embodiment, the first gate line GL1 may be the farthest from which the gate signal is applied, and the n-th gate line GLn may be the closest from which the gate signal is applied. At this time, the kick-back voltage VKB applied to the first gate line GL1 may have the lowest value, and the kick-back voltage VKB applied to the n-th gate line GLn may have the highest value.

[0096] For example, a gate signal may be applied to the first gate line GL1 first, then to the second gate line GL2, and finally to the nth gate line GLn at the end of a frame. In this case, the lowest kick-back voltage VKB may be output first, and gradually higher kick-back voltages VKB may be output in sequence. The highest kick-back voltage VKB may be output last.

[0097] However, this is merely an example, and the order in which gate signals are applied may be changed. For example, a gate signal may be applied first to the nth gate line GLn, and then applied to the first gate line GL1 at the end of a frame. In this case, the highest kick-back voltage VKB may be output first, and then successively lower kick-back voltages VKB may be output. The lowest kick-back voltage VKB may be output last.

[0098] Below, refer to Figure 7 A display device according to an embodiment will be described.

[0099] Figure 7 The embodiment shown relates to a display device having Figures 1 to 4 The display devices involved in the illustrated embodiments have many common parts, so descriptions of the common parts are omitted. In this embodiment, the difference from the previous embodiment is that the change amount of the gate on-voltage can be adjusted within a frame, which is further described below.

[0100] Figure 7 1 is a timing diagram showing gate signals generated by a display device according to an embodiment.

[0101] Similar to the aforementioned embodiment, a gate-on voltage VGH can be applied to each gate line GL1-GLn of the display device according to one embodiment. The gate-on voltage VGH can be formed to have a gradually changing value within a frame. In this case, the gate-on voltage VGH can be applied to the gate lines GL1-GLn, gradually increasing as the gate line GL1-GLn with the shortest gate signal applied thereto approaches the gate line GL1-GLn with the farthest gate signal applied thereto.

[0102] Furthermore, a kick-back voltage VKB may be applied to each gate line GL1-GLn. The kick-back voltage VKB may be formed to have a gradually changing value within a frame. In this case, a gradually decreasing kick-back voltage VKB may be applied as the gate line GL1-GLn with the shortest gate signal applied thereto approaches the gate line GL1-GLn with the longest gate signal applied thereto.

[0103] In this embodiment, the kick-back voltage VKB applied to each gate line GL1-GLn can be formed by a fixed value. Therefore, the change ΔVk of the kick-back voltage VKB can be constant within a frame. The change ΔVk of the kick-back voltage VKB within a frame refers to the difference between the kick-back voltage VKB applied to the first gate line GL1 and the kick-back voltage VKB applied to the nth gate line GLn.

[0104] Furthermore, the gate-on voltage VGH applied to each gate line GL1-GLn can be adjusted. Therefore, the change in gate-on voltage VGH, ΔVh, can be adjusted within a frame. Within a frame, the change in gate-on voltage VGH, ΔVh, refers to the difference between the gate-on voltage VGH applied to the first gate line GL1 and the gate-on voltage VGH applied to the nth gate line GLn. The change in gate-on voltage VGH, ΔVh, within a frame can be proportional to the change in kick-back voltage VKB, ΔVk, within a frame. The change in gate-on voltage VGH, ΔVh, within a frame can be determined by Equation 2.

[0105]

Mathematical formula 2

[0106] ΔVh=βΔVk

[0107] That is, the change ΔVh of the gate-on voltage VGH within a frame can be β times the change ΔVk of the kick-back voltage VKB within a frame. In this case, β can be a value greater than 0 and less than 2. The ratio β of the change ΔVh of the gate-on voltage VGH within a frame relative to the change ΔVk of the kick-back voltage VKB within a frame can be adjusted. The receiving unit 510 of the voltage supply unit 500 can externally receive an input of the ratio β of the change ΔVh of the gate-on voltage VGH within a frame relative to the change ΔVk of the kick-back voltage VKB within a frame. Based on this ratio, the gate-on voltage VGH applied to each gate line GL1-GLn can be calculated and generated.

[0108] In the above description, the case where the change ΔVk of the kick-back voltage VKB within a frame is constant and the change ΔVh of the gate-on voltage VGH within a frame is adjustable is described. However, the present invention is not limited to this. Alternatively, the change ΔVk of the kick-back voltage VKB within a frame and the change ΔVh of the gate-on voltage VGH within a frame can be adjusted separately.

[0109] Below, refer to Figure 8 A display device according to an embodiment is described.

[0110] Figure 8 The embodiment shown relates to a display device having Figures 1 to 4 The display devices involved in the illustrated embodiments have many common parts, so descriptions of the common parts are omitted. In this embodiment, the difference from the previous embodiment is that the kick-back time for applying the kick-back voltage is different for each gate line, which is further described below.

[0111] Figure 8 This is a diagram showing gate output voltages output to some gate lines of a display device according to one embodiment.

[0112] Similar to the aforementioned embodiment, a gate-on voltage VGH can be applied to each gate line GL1-GLn of the display device according to one embodiment. The gate-on voltage VGH can be formed to have a gradually changing value within a frame. In this case, the gate-on voltage VGH can be applied to the gate lines GL1-GLn, gradually increasing as the gate line GL1-GLn with the shortest gate signal applied thereto approaches the gate line GL1-GLn with the farthest gate signal applied thereto.

[0113] Furthermore, a kick-back voltage VKB may be applied to each gate line GL1-GLn. The kick-back voltage VKB may be formed to have a gradually changing value within a frame. In this case, a gradually decreasing kick-back voltage VKB may be applied as the gate line GL1-GLn with the shortest gate signal applied thereto approaches the gate line GL1-GLn with the longest gate signal applied thereto.

[0114] In the aforementioned embodiment, the kick-back voltage VKB may be applied to each gate line GL1-GLn for the same duration. In this embodiment, the kick-back voltage VKB may be applied to each gate line GL1-GLn for a different duration. The kick-back duration for applying the kick-back voltage VKB to each gate line GL1-GLn may be determined by Equation 3.

[0115]

Mathematical formula 3

[0116] t(i)=(1±(i-1)γ)tref

[0117] Wherein, t(i) is the kick-back time of the i-th gate line, and tref is the reference time.

[0118] A kick-back voltage VKB may be applied to the first gate line GL1 within a reference time tref. A kick-back voltage VKB may be applied to the second gate line GL2 for a time ((1+γ)tref) longer than the reference time tref. A kick-back voltage VKB may be applied to the third gate line GL3 for a time ((1+2γ)tref) longer than the second gate line GL2. A kick-back voltage VKB may be applied to the n-th gate line GLn for the longest time ((1+nγ)tref). That is, the closer the first gate line GL1 is to the n-th gate line GLn, the longer the kick-back time may be.

[0119] Conversely, the kick-back voltage VKB may be applied to the second gate line GL2 within a time shorter than the reference time tref ((1-γ)tref). The kick-back voltage VKB may be applied to the third gate line GL3 within a time shorter than the second gate line GL2 ((1-2γ)tref). The kick-back voltage VKB may be applied to the n-th gate line GLn within the shortest time ((1-nγ)tref). The closer the first gate line GL1 is to the n-th gate line GLn, the shorter the kick-back time.

[0120] In Mathematical Formula 3, γ can be a value greater than 0 and less than 1. This γ value is adjustable. The receiving unit 510 of the voltage supply unit 500 can receive an input of the γ value related to the amount of change in the kick-back time from the outside.

[0121] In this embodiment, if the gate output voltage does not drop sufficiently, the kick-back time for applying the kick-back voltage VKB to each gate line GL1-GLn is increased, thereby adjusting the gate output voltage to drop sufficiently. Conversely, if the gate output voltage drops excessively, the kick-back time for applying the kick-back voltage VKB to each gate line GL1-GLn is reduced, thereby adjusting the gate output voltage to drop to a desired level.

[0122] Below, refer to Figure 9 A display device according to an embodiment is described.

[0123] Figure 9 The embodiment shown relates to a display device having Figure 8 The display devices involved in the illustrated embodiments share many common features, and therefore descriptions of the common features are omitted. This embodiment differs from the previous embodiments in that the kick-back time is maintained constant and gradually increased starting from the gate signal applied to the predetermined gate line, as further described below.

[0124] Figure 9 This is a diagram showing gate output voltages output to some gate lines of a display device according to one embodiment.

[0125] Similar to the aforementioned embodiment, a gate-on voltage VGH can be applied to each gate line GL1-GLn of the display device according to one embodiment. The gate-on voltage VGH can be formed to have a gradually changing value within a frame. In this case, the gate-on voltage VGH can be applied to the gate lines GL1-GLn, gradually increasing as the gate line GL1-GLn with the shortest gate signal applied thereto approaches the gate line GL1-GLn with the farthest gate signal applied thereto.

[0126] Furthermore, a kick-back voltage VKB may be applied to each gate line GL1-GLn. The kick-back voltage VKB may be formed to have a gradually changing value within a frame. In this case, a gradually decreasing kick-back voltage VKB may be applied as the gate line GL1-GLn with the shortest gate signal applied thereto approaches the gate line GL1-GLn with the longest gate signal applied thereto.

[0127] In the aforementioned embodiment, the kick-back time may gradually increase as the first gate line GL1 approaches the nth gate line GLn. In this embodiment, the kick-back time may be maintained constant up to the predetermined gate lines GL1-GLn, and then increased thereafter. The kick-back time for applying the kick-back voltage VKB to each gate line GL1-GLn may be determined by Equation 4.

[0128]

Mathematical formula 4

[0129] t(i)=tref,i≤p

[0130] t(i)=(1±(ip)γ)tref,i>p

[0131] Wherein, t(i) is the kick-back time of the i-th gate line, and tref is the reference time.

[0132] The kick-back voltage VKB may be applied to the first gate line GL1 for a reference time tref. The kick-back voltage VKB may be applied to the second and third gate lines GL2 and GL3 for a reference time tref. Similarly, the kick-back voltage VKB may be applied to the p-th gate line GLp for a reference time tref, similar to the first gate line GL1. That is, the kick-back time may be constant from the first gate line GL1 to the p-th gate line GLp.

[0133] The kick-back voltage VKB may be applied to the p+1th gate line GL(p+1) for a longer time ((1+γ)tref) than the pth gate line GLp. The kick-back voltage VKB may be applied to the p+2th gate line (not shown) for a longer time ((1+2γ)tref) than the p+1th gate line GL(p+1). The kick-back voltage VKB may be applied to the nth gate line GLn for the longest time ((1+(np)γ)tref). That is, the kick-back time may gradually increase as the pth gate line GLp approaches the nth gate line GLn.

[0134] Conversely, the kick-back voltage VKB may be applied to the p+1th gate line GL(p+1) for a shorter time ((1-γ)tref) than the pth gate line GLp. The kick-back voltage VKB may be applied to the p+2th gate line for a shorter time ((1-2γ)tref) than the p+1th gate line GL(p+1). The kick-back voltage VKB may be applied to the nth gate line GLn for the shortest time ((1-nγ)tref). That is, the kick-back time may gradually decrease as the pth gate line GLp approaches the nth gate line GLn.

[0135] In Mathematical Formula 4, γ can be a value greater than 0 and less than 1, and p can be a value greater than 2 and less than n. These values of γ and p can be adjusted. The receiving unit 510 of the voltage supply unit 500 can externally receive input of a γ value related to the amount of change in the kick-back time and a p value indicating the number of the gate line at which the change in the kick-back time begins.

[0136] In this embodiment, the gate output voltage is controlled solely by the change in the kick-back voltage VKB from the first gate line to the predetermined gate line. After the predetermined gate line, the kick-back time is varied in conjunction with the change in the kick-back voltage VKB to control the gate output voltage. Specifically, if the gate output voltage does not drop sufficiently, the kick-back time is increased after the predetermined gate line to achieve a sufficient drop in the gate output voltage. Conversely, if the gate output voltage drops excessively, the kick-back time is reduced after the predetermined gate line to achieve a desired drop in the gate output voltage.

[0137] Below, refer to Figure 10 A display device according to an embodiment will be described.

[0138] Figure 10 The embodiment shown relates to a display device having Figure 9 The display devices involved in the illustrated embodiments share many common features, and therefore descriptions of the common features are omitted. This embodiment differs from the previous embodiments in that the kick-back time is maintained constant, the kick-back time is increased starting from a predetermined gate line, and the kick-back time is maintained constant again starting from another predetermined gate line. This is further described below.

[0139] Figure 10 This is a diagram showing gate output voltages output to some gate lines of a display device according to one embodiment.

[0140] Similar to the aforementioned embodiment, a gate-on voltage VGH can be applied to each gate line GL1-GLn of the display device according to one embodiment. The gate-on voltage VGH can be formed to have a gradually changing value within a frame. In this case, the gate-on voltage VGH can be applied to the gate lines GL1-GLn, gradually increasing as the gate line GL1-GLn with the shortest gate signal applied thereto approaches the gate line GL1-GLn with the farthest gate signal applied thereto.

[0141] Furthermore, a kick-back voltage VKB may be applied to each gate line GL1-GLn. The kick-back voltage VKB may be formed to have a gradually changing value within a frame. In this case, a gradually decreasing kick-back voltage VKB may be applied as the gate line GL1-GLn with the shortest gate signal applied thereto approaches the gate line GL1-GLn with the longest gate signal applied thereto.

[0142] In the aforementioned embodiment, the kick-back time may be maintained constant up to a predetermined gate line GL1-GLn, and the kick-back time may be increased from the predetermined gate line GL1-GLn onward. In this embodiment, the kick-back time may be maintained constant up to the predetermined gate line GL1-GLn, and the kick-back time may be increased from the predetermined gate line GL1-GLn to another predetermined gate line GL1-GLn, and the kick-back time may be maintained constant again after the other predetermined gate line GL1-GLn. The kick-back time for applying the kick-back voltage VKB to each gate line GL1-GLn can be determined by Equation 5.

[0143]

Mathematical formula 5

[0144] t(i)=tref,i≤p

[0145] t(i)=(1±(ip)γ)tref, p<i<q

[0146] t(i)=(1±(qp)γ)tref,i≥q

[0147] Wherein, t(i) is the kick-back time of the i-th gate line, and tref is the reference time.

[0148] The kick-back voltage VKB may be applied to the first gate line GL1 for a reference time tref. The kick-back voltage VKB may be applied to the second and third gate lines GL2 and GL3 for a reference time tref. Similarly, the kick-back voltage VKB may be applied to the p-th gate line GLp for a reference time tref, similar to the first gate line GL1. That is, the kick-back time may be constant from the first gate line GL1 to the p-th gate line GLp.

[0149] The kick-back voltage VKB may be applied to the p+1 gate line GL(p+1) for a time longer than the p-th gate line GLp ((1+γ)tref). The kick-back voltage VKB may be applied to the p+2 gate line (not shown) for a time longer than the p+1 gate line GL(p+1) ((1+2γ)tref). The kick-back voltage VKB may be applied to the q-th gate line (not shown) for a time longer than the p+1 gate line GL(p+1) ((1+(qp)γ)tref). That is, the kick-back time may gradually increase from the p-th gate line GLp to the q-th gate line. The kick-back voltage VKB may be applied to the q+1 gate line (not shown) for the same time as the q-th gate line ((1+(qp)γ)tref). The kick-back voltage VKB may be applied to the n-th gate line GLn for the same time as the q-th gate line ((1+(qp)γ)tref). That is, the kick-back time from the qth gate line to the nth gate line GLn may be constant.

[0150] On the contrary, the kick-back voltage VKB may be applied to the p+1 gate line GL(p+1) within a time ((1-γ)tref) shorter than that of the p-th gate line GLp. The kick-back voltage VKB may be applied to the p+2 gate line within a time ((1-2γ)tref) shorter than that of the p+1 gate line GL(p+1). The kick-back voltage VKB may be applied to the q-th gate line within a time ((1-(qp)γ)tref) shorter than that of the p+1 gate line GL(p+1). That is, the closer the p-th gate line GLp is to the q-th gate line, the gradually shorter the kick-back time may be. The kick-back voltage VKB may be applied to the q+1 gate line within the same time ((1-(qp)γ)tref) as that of the q-th gate line. The kick-back voltage VKB may be applied to the n-th gate line GLn within the same time ((1-(qp)γ)tref) as that of the q-th gate line. That is, the kick-back time from the qth gate line to the nth gate line GLn may be constant.

[0151] In Mathematical Formula 5, γ can be a value greater than 0 and less than 1, p can be a value greater than 2 and less than q, and q can be a value greater than p and less than n. These values of γ, p, and q can be adjusted. The receiving unit 510 of the voltage supply unit 500 can externally receive input of a γ value related to the amount of change in the kick-back time, a p value indicating the gate line number at which the change in the kick-back time begins, and a q value indicating the gate line number at which the change in the kick-back time ends.

[0152] In this embodiment, the gate output voltage can be controlled by changing only the kick-back voltage VKB from the first gate line GL1 to the predetermined gate line, and the gate output voltage can be controlled by changing the kick-back time together with the kick-back voltage VKB from the predetermined gate line GL1-GLn to another predetermined gate line GL1-GLn. That is, if the gate output voltage does not drop sufficiently, the kick-back time can be increased from the predetermined gate line GL1-GLn, so that the gate output voltage can be adjusted to drop sufficiently. Conversely, if the gate output voltage drops excessively, the kick-back time can be reduced from the predetermined gate line GL1-GLn, so that the gate output voltage can be adjusted to drop to the desired degree. In addition, the gate output voltage can be controlled by changing the kick-back voltage VKB while maintaining the changing kick-back time from another predetermined gate line GL1-GLn.

[0153] The above-described variations in the kick-back time are merely illustrative, and various modifications are possible. For example, the kick-back time may be increased from the first gate line GL1 to the predetermined gate lines GL1-GLn, and maintained from the predetermined gate lines GL1-GLn to the nth gate line GLn. Furthermore, the kick-back time of at least some of the gate lines GL1-GLn may be varied in various ways.

[0154] Below, refer to Figure 11 A display device according to an embodiment is described.

[0155] Figure 11 The embodiment shown relates to a display device having Figure 8 The display devices of the illustrated embodiments have many common parts, so descriptions of the common parts are omitted. This embodiment differs from the previous embodiment in that the kick-back voltages applied to the multiple gate lines are the same, which will be further described below.

[0156] Figure 11 This is a diagram showing gate output voltages output to some gate lines of a display device according to one embodiment.

[0157] Similar to the aforementioned embodiment, a gate-on voltage VGH can be applied to each gate line GL1-GLn of the display device according to one embodiment. The gate-on voltage VGH can be formed to have a gradually changing value within a frame. In this case, the gate-on voltage VGH can be applied to the gate lines GL1-GLn, gradually increasing as the gate line GL1-GLn with the shortest gate signal applied thereto approaches the gate line GL1-GLn with the farthest gate signal applied thereto.

[0158] Furthermore, a kick-back voltage VKB can be applied to each gate line GL1-GLn of the display device according to one embodiment. The timing of applying the kick-back voltage VKB can be different for each gate line GL1-GLn. For example, the kick-back time can gradually increase or decrease as the first gate line GL1 approaches the nth gate line GLn. This is merely an example, and the kick-back time can be varied in various ways. For some gate lines GL1-GLn, the kick-back time can also be maintained constant. For example, the kick-back time can be maintained constant and gradually increased starting with the gate signal applied to a predetermined gate line GL1-GLn. Alternatively, the kick-back time can be maintained constant and gradually increased starting with a predetermined gate line GL1-GLn, while the kick-back time is maintained again starting with another predetermined gate line GL1-GLn. Furthermore, the kick-back time for at least some gate lines GL1-GLn can be varied in various ways. In this case, the rate of change of the kick-back voltage VKB can be adjusted. Furthermore, the location where the kick-back voltage VKB is changed or the location where the kick-back voltage VKB is maintained can also be adjusted.

[0159] In the aforementioned embodiment, the kick-back voltage VKB may be formed by a gradually changing value within a frame. In this embodiment, the same kick-back voltage VKB may be applied to each gate line GL1-GLn. The kick-back voltage VKB applied to the first gate line GL1 may be the same as the kick-back voltage VKB applied to the second gate line GL2. The kick-back voltage VKB applied to the n-th gate line GLn may be the same as the kick-back voltage VKB applied to the first gate line GL1.

[0160] In this embodiment, if the gate output voltage does not drop sufficiently as shown by the dotted line, the kick-back time for applying the kick-back voltage VKB is changed, thereby adjusting the gate output voltage to drop sufficiently as shown by the solid line. In other words, the gate output voltage can be adjusted to a desired value by changing the kick-back time while maintaining the same kick-back voltage VKB applied to each gate line GL1-GLn.

[0161] Below, refer to Figure 12 A display device according to an embodiment is described.

[0162] Figure 12 The embodiment shown relates to a display device having Figures 1 to 4 The display devices involved in the illustrated embodiments share many common features, so descriptions of these common features are omitted. This embodiment differs from the previous embodiments in that the gate lines are divided into multiple sections, allowing for adjustment of the gate turn-on voltage and kick-back voltage at the boundaries of each section, as further described below.

[0163] Figure 12This is a timing diagram showing gate signals generated by a display device according to one embodiment.

[0164] Similar to the previous embodiment, a gate-on voltage VGH can be applied to each gate line GL1-GLn of the display device according to one embodiment. In this embodiment, the plurality of gate lines GL1-GLn can be divided into a plurality of sections, and the gate-on voltage VGH can be adjusted for each section. For example, the gate lines GL1-GLn can be divided into a first section P1, a second section P2, a third section P3, a fourth section P4, a fifth section P5, a sixth section P6, and a seventh section P7. The gate-on voltage VGH applied to the first gate line GL1, which is the starting point of the first section P1, and the gate-on voltage VGH applied to the gate lines located at the boundary between the first section P1 and the second section P2 can be set. The gate-on voltage VGH within the first section P1 can have a value that gradually changes from the gate-on voltage VGH applied to the first gate line GL1, which is the starting point of the first section P1, to the gate-on voltage VGH applied to the gate lines located at the boundary between the first section P1 and the second section P2. The gate-on voltage VGH applied to the gate line located at the boundary between the second section P2 and the third section P3 can be set. The gate-on voltage VGH within the second section P2 can have a value that gradually changes from the gate-on voltage VGH applied to the gate line located at the boundary between the first section P1 and the second section P2 to the gate-on voltage VGH applied to the gate line located at the boundary between the second section P2 and the third section P3. Similarly, the gate-on voltage VGH applied to the gate line located at the boundary between the third section P3 and the fourth section P4, the boundary between the fourth section P4 and the fifth section P5, the boundary between the fifth section P5 and the sixth section P6, the boundary between the sixth section P6 and the seventh section P7, and the end position of the seventh section P7 can be set. Furthermore, the gate-on voltage VGH within the third section P3, the fourth section P4, the fifth section P5, the sixth section P6, and the seventh section P7 can have a value that gradually changes from the gate-on voltage VGH at the beginning of each section to the gate-on voltage VGH at the end position. In each interval, the gate-on voltage VGH may gradually increase or gradually decrease.

[0165] In addition, a kick-back voltage VKB can be applied to each gate line GL1-GLn. The multiple gate lines GL1-GLn can be divided into multiple intervals, and the kick-back voltage VKB can be adjusted according to each interval. For example, the gate lines (GL1-GLn) can be divided into a first interval P1, a second interval P2, a third interval P3, a fourth interval P4, a fifth interval P5, a sixth interval P6, and a seventh interval P7. The kick-back voltage VKB applied to the first gate line GL1 as the starting position of the first interval P1 and the kick-back voltage VKB applied to the gate line located at the boundary between the first interval P1 and the second interval P2 can be set. The kick-back voltage VKB within the first interval P1 can have a value that gradually changes from the kick-back voltage VKB applied to the first gate line GL1 as the starting position of the first interval P1 to the kick-back voltage VKB applied to the gate line located at the boundary between the first interval P1 and the second interval P2. The kick-back voltage VKB applied to the gate line located at the boundary between the second interval P2 and the third interval P3 can be set. The kick-back voltage VKB within the second interval P2 may have a value that gradually changes from the kick-back voltage VKB applied to the gate line located at the boundary between the first interval P1 and the second interval P2 to the kick-back voltage VKB applied to the gate line located at the boundary between the second interval P2 and the third interval P3. Similarly, the kick-back voltage VKB applied to the gate line located at the boundary position between the third interval P3 and the fourth interval P4, the boundary position between the fourth interval P4 and the fifth interval P5, the boundary position between the fifth interval P5 and the sixth interval P6, the boundary position between the sixth interval P6 and the seventh interval P7, and the end position of the seventh interval P7 may be set. In addition, the kick-back voltage VKB within the third interval P3, the fourth interval P4, the fifth interval P5, the sixth interval P6, and the seventh interval P7 may have a value that gradually changes from the kick-back voltage VKB at the start position of each interval to the kick-back voltage VKB at the end position. Within each interval, the kick-back voltage VKB may gradually increase or decrease.

[0166] The receiving unit 510 of the voltage supply unit 500 can externally receive inputs of the gate-on voltage VGH and the kick-back voltage VKB at the start of the first interval P1, the end of the seventh interval P7, and the boundaries between intervals (P1-P7). The gate-on voltage VGH and the kick-back voltage VKB within each interval (P1-P7) can also be determined based on the input values. As described above, by adjusting the gate-on voltage VGH and the kick-back voltage VKB for each interval, a desired gate voltage output value can be controlled.

[0167] The above description describes a case where the gate lines GL1-GLn are divided into seven sections. However, this is merely an example and various modifications are possible. For example, approximately 2160 gate lines GL1-GLn may be formed, which may be divided into eight sections, so that each section may include 270 gate lines GL1-GLn. The number of gate lines GL1-GLn may be modified in various ways, and the number of sections that divide the gate lines GL1-GLn may also be modified in various ways. Furthermore, each section may include the same number of gate lines GL1-GLn, or a different number of gate lines GL1-GLn.

[0168] The embodiments of the present invention are described in detail above, but the scope of the present invention is not limited thereto. Various modifications and improvements of the basic concepts of the present invention defined in the claims made by those skilled in the art also fall within the scope of the present invention.

Claims

1. A display device comprising: A display panel comprising a plurality of pixels, a plurality of gate lines and a plurality of data lines connected to the plurality of pixels; a gate driving unit for applying a gate signal to the plurality of gate lines; a data driving unit for applying data signals to the plurality of data lines; as well as A voltage supply unit generates a gate-on voltage that gradually changes within one frame and a kick-back voltage that gradually changes within one frame and transmits them to the gate driving unit. Among the plurality of gate lines, the gate-on voltage is applied gradually higher as the gate line from which the gate signal is applied at the shortest distance approaches the gate line from which the gate signal is applied at the farthest distance, Among the plurality of gate lines, the kick-back voltage is applied gradually lower as the gate line with the shortest distance to which the gate signal is applied approaches the gate line with the farthest distance to which the gate signal is applied, The change in the gate on voltage within one frame is proportional to the change in the kick-back voltage within one frame. The ratio of the change amount of the kick-back voltage within a frame to the change amount of the gate-on voltage within a frame can be adjusted, or the ratio of the change amount of the gate-on voltage within a frame to the change amount of the kick-back voltage within a frame can be adjusted, A kick-back time for applying the kick-back voltage is different in at least one gate line among the plurality of gate lines, The plurality of gate lines include a first gate line to an nth gate line, The kick-back time for applying the kick-back voltage to each gate line of the plurality of gate lines is determined by the following formula: t(i)=(1+(i-1)γ)tref or t(i)=(1-(i-1)γ)tref, Wherein, t(i) is the kick-back time of the i-th gate line, i is a positive integer greater than 0 and less than n, tref is the reference time, and γ is an arbitrary number greater than 0 and less than 1.

2. The display device according to claim 1, wherein The change amount of the gate on-voltage is constant within one frame.

3. The display device according to claim 1, wherein The variation of the kick-back voltage is constant within one frame.

4. The display device according to claim 1, wherein The plurality of gate lines include a first gate line to an nth gate line, The closer the first gate line is to the nth gate line, the longer the distance for applying the gate signal becomes. applying the gate signal to the first gate line to the nth gate line in sequence, Applying a gradually increasing gate-on voltage within a frame, The kick-back voltage is applied gradually decreasing within one frame.

5. The display device according to claim 1, wherein The plurality of gate lines include a first gate line to an nth gate line, The closer the first gate line is to the nth gate line, the longer the distance for applying the gate signal becomes. applying the gate signal to the nth gate line to the first gate line in sequence, Applying the gate turn-on voltage which gradually decreases within one frame, The kick-back voltage is applied gradually increasing within one frame. The display device according to claim 1 , wherein: The amount of variation in the kick-back time can be adjusted.

7. The display device according to claim 1, wherein The plurality of gate lines include a first gate line to an nth gate line, Maintaining a constant kick-back time from the first gate line to the p-th gate line, The kick-back time is gradually increased or decreased as the p-th gate line approaches the n-th gate line.

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