Test apparatus and test method

Abstract

A test device and a test method, the test device comprising: a detection interface device configured to accommodate a semiconductor device to be tested; a signal acquisition device configured to acquire at least one pulse signal; a signal providing device configured to provide the semiconductor device to be tested with at least one pulse signal having an adjustable physical characteristic; a state acquisition device configured to acquire a real-time state of the semiconductor device to be tested between two detection interfaces in the detection interface device; a preprocessing device; and a controller configured to adjust the physical characteristic of the at least one pulse signal in response to the real-time state to obtain a relationship between the physical characteristic of the at least one pulse signal and the real-time state. The test device can dynamically perform a super-speed pulse test of the semiconductor device to be tested by adjusting the pulse signal.

Description

Technical Field

[0001] This disclosure relates to a testing system and a testing method. Background Technology

[0002] With the increasing popularity of big data and artificial intelligence applications, storage devices for in-memory computing have become a target of intense research in both industry and academia, striving to develop towards high performance, low cost, low energy consumption, and high speed. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a test apparatus, comprising: a detection interface device configured to accommodate a semiconductor device under test and including a plurality of detection interfaces, the plurality of detection interfaces being respectively used for connection to a plurality of terminals of the semiconductor device under test; a signal providing device configured to provide at least one pulse signal having adjustable physical characteristics to the semiconductor device under test through at least one of the plurality of detection interfaces of the detection interface device; a signal acquisition device configured to acquire at least one pulse signal; a state acquisition device configured to acquire a real-time state of the semiconductor device under test between two detection interfaces in the detection interface device, the real-time state of the semiconductor device under test depending on the physical characteristics of the at least one pulse signal; a preprocessing device configured to perform at least one preprocessing operation on the semiconductor device under test through at least two detection interfaces in the detection interface device; and a controller configured to adjust the physical characteristics of the at least one pulse signal in response to the physical characteristics of the at least one pulse signal and the real-time state, and to provide the adjusted at least one pulse signal to the semiconductor device under test to reacquire the real-time state, thereby obtaining the relationship between the physical characteristics of the at least one pulse signal and the real-time state of the semiconductor device under test.

[0004] At least one embodiment of this disclosure also provides a testing method, the testing method comprising: providing a semiconductor device under test; performing at least one preprocessing operation on the semiconductor device under test using a preprocessing device; providing at least one pulse signal having adjustable physical characteristics to the semiconductor device under test using a signal providing device; acquiring at least one pulse signal using a signal acquisition device; acquiring a real-time state of the semiconductor device under test from the semiconductor device under test using a state acquisition device, the real-time state of the semiconductor device under test depending on the physical characteristics of the at least one pulse signal; and adjusting the physical characteristics of the at least one pulse signal in response to the physical characteristics of the at least one pulse signal and the real-time state, and providing the adjusted at least one pulse signal to the semiconductor device under test to reacquire the real-time state, so as to obtain the relationship between the physical characteristics of the at least one pulse signal and the real-time state of the semiconductor device under test. Attached Figure Description

[0005] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0006] Figure 1 A block diagram of a test apparatus provided in at least one embodiment of the present disclosure is shown;

[0007] Figure 2 A block diagram of another test apparatus provided in at least one embodiment of the present disclosure is shown;

[0008] Figure 3 A block diagram of yet another testing device provided in at least one embodiment of the present disclosure is shown;

[0009] Figure 4 A block diagram of another test apparatus provided in at least one embodiment of the present disclosure is shown;

[0010] Figure 5 A schematic diagram of a semiconductor device under test provided in this disclosure, at least according to a specific embodiment, is shown;

[0011] Figure 6 A block diagram of a test apparatus provided in this disclosure, at least according to a specific embodiment, is shown;

[0012] Figure 7 A flowchart of a testing method provided by at least one embodiment of this disclosure is shown;

[0013] Figure 8 A flowchart of another testing method provided by at least one embodiment of this disclosure is shown;

[0014] Figure 9 A flowchart of yet another testing method provided by at least one embodiment of this disclosure is shown;

[0015] Figure 10 A flowchart of yet another testing method provided by at least one embodiment of this disclosure is shown;

[0016] Figure 11 A flowchart of a testing method for a three-terminal semiconductor provided in at least one embodiment of this disclosure is shown;

[0017] Figure 12 A flowchart of a method for obtaining real-time status provided by at least one embodiment of this disclosure is shown; and

[0018] Figure 13 A flowchart of at least one test method provided in a specific embodiment is shown. Specific Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0020] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “contains,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “coupled,” “connected,” or “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0021] Compared to traditional non-volatile memory, resistive random access memory (IRRAM) offers advantages such as simple physical structure, low operating voltage, multi-bit storage capability, and excellent cyclic erasure and write characteristics, making it one of the best hardware carriers for realizing big data and artificial intelligence. Furthermore, IRRAM features high switching speed; compared to flash memory with microsecond-level erase and write speeds, typical IRRAM arrays can achieve speeds of 10ns to 50ns, facilitating high-speed data access and computation, thereby improving storage efficiency.

[0022] The inventors discovered that the switching speed of resistive random access memory (RRAM) is not limited to the nanosecond range, and that the internal temperature distribution of the device under ultra-narrow pulse excitation differs from that under DC voltage excitation. The internal temperature distribution under ultra-narrow pulse excitation can improve the intrinsic random noise and relaxation effect of the device. However, the switching voltage under ultra-narrow pulse is much higher than the voltage amplitude under DC operation, which may damage the RRAM cell, as RRAM cells are prone to breakdown and damage in the absence of a selector. Therefore, there is an urgent need to propose a test system for RRAM devices with selectors (e.g., 1T1R memory cells) to study the relationship between voltage amplitude and resistance state under ultra-narrow pulse excitation. The ultra-narrow pulse range can be hundreds of nanoseconds, tens of nanoseconds, or even shorter.

[0023] In addition, in traditional semiconductor device testing systems, due to the limitations of low signal source bandwidth and low data transmission bandwidth, it is impossible to generate and transmit high-speed pulse signals of hundreds of picoseconds or even tens of picoseconds, let alone achieve high-speed erasure and writing of data. Therefore, the industry faces the following problems: (1) When erasing and writing data to phase-change memory by changing the pulse width and applying pulse sequences with different pulse widths, wide pulses play a major role while narrow pulses participate less, thus reducing the erasure and writing speed; (2) Resistive switching components without selectors are easily affected by excitation voltage fluctuations and may break down; (3) High-speed erasure and writing systems suitable for array testing are greatly affected by parasitic capacitance and parasitic resistance in the circuit, and the addressing switch matrix and relay group connected in each path inevitably introduce power loss, which may lead to limited bandwidth of the overall circuit. Therefore, it is not suitable for high-speed testing and research of individual devices.

[0024] At least one embodiment of this disclosure provides a test apparatus, including a detection interface device configured to accommodate a semiconductor device under test and including a plurality of detection interfaces, the plurality of detection interfaces being respectively used for connection to a plurality of terminals of the semiconductor device under test; a signal providing device configured to provide at least one pulse signal having adjustable physical characteristics to the semiconductor device under test through at least one of the plurality of detection interfaces of the detection interface device; a signal acquisition device configured to acquire at least one pulse signal; a state acquisition device configured to acquire a real-time state of the semiconductor device under test between two detection interfaces in the detection interface device, the real-time state of the semiconductor device under test depending on the physical characteristics of the at least one pulse signal; a preprocessing device configured to perform at least one preprocessing operation on the semiconductor device under test through at least two detection interfaces in the detection interface device; and a controller configured to adjust the physical characteristics of the at least one pulse signal in response to the physical characteristics of the at least one pulse signal and the real-time state, and to provide the adjusted at least one pulse signal to the semiconductor device under test to reacquire the real-time state, thereby obtaining the relationship between the physical characteristics of the at least one pulse signal and the real-time state of the semiconductor device under test.

[0025] Some embodiments of this disclosure also provide test methods.

[0026] The test equipment provided in the above embodiments of this disclosure can be used to automatically execute ultra-narrow pulse sequence test methods and can automatically adjust the pulse signal to obtain the relationship between the physical characteristics of the pulse signal and the real-time state of the semiconductor device under test. Furthermore, some embodiments of this disclosure provide test equipment that can maintain high-speed erase / write and read speeds by changing the amplitude of the ultra-narrow pulse instead of the pulse width. Additionally, some embodiments of this disclosure provide test equipment that can reduce the influence of parasitic capacitance and resistance in the circuit and reduce power loss in the circuit. This test equipment can generate high-amplitude pulse sequences, suitable for obtaining electrical characterization of memory.

[0027] In addition, in some embodiments of this disclosure, the arrangement of the semiconductor device under test can also protect the semiconductor device from breakdown, thereby reducing the influence of interference current and suppressing leakage current.

[0028] The embodiments and examples of this disclosure will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the same reference numerals in the drawings denote the same components, parts, or elements.

[0029] At least one embodiment of this disclosure provides a testing apparatus capable of performing operations such as forming, writing, erasing, and reading on semiconductor elements, such as resistive switching memories. The resistive switching memory may include non-volatile memories based on the following resistive switching physical mechanisms: nanomechanical memory, molecular resistive switching, electrostatic / electronic memory, electrochemical metallization memory, valence change memory, thermochemical memory, phase transition memory, magnetoresistive memory, ferroelectric tunneling, or other physical mechanisms that induce resistive switching.

[0030] Figure 1 A block diagram of a test apparatus 100 provided in at least one embodiment of the present disclosure is shown.

[0031] For example, in some examples, the test device 100 may include a detection interface device 120, a signal providing device 130, a signal acquisition device 140, a status acquisition device 150, a preprocessing device 160, and a controller 170 for testing the semiconductor device 110 to be tested.

[0032] For example, the detection interface device 120 may be configured to accommodate the semiconductor device under test 110 and include multiple detection interfaces, each for connection to multiple terminals of the semiconductor device under test. For example, in some examples, the detection interface device 120 may provide signal paths through multiple detection interfaces. For example, in some examples, the semiconductor device under test 110 may include at least one resistive switching memory (RSM) and a gate transistor. Optionally, the test semiconductor device 110 may include multiple memory components consisting of at least one RSM and a gate transistor. Preferably, the test semiconductor device 110 may include an RSM and a gate transistor such as a diode or transistor. More preferably, the test semiconductor device 110 may include an RSM and a field-effect transistor, such as... Figure 5 and Figure 6 As shown. The test semiconductor device 110, which includes a resistive random access memory and a field-effect transistor, can be referred to in detail below, and will not be repeated here.

[0033] For example, the signal providing device 130 can be configured to provide at least one pulse signal with adjustable physical characteristics to the semiconductor device under test 110 through at least one of the plurality of detection interfaces of the detection interface device 120. For example, the signal providing device 130 can be a signal generator, particularly a picosecond pulse signal generator. For example, in some examples, the physical characteristics can include pulse width and / or amplitude. For example, in some examples, at least one pulse signal has a pulse width of no more than 100 ps and / or an amplitude of more than 10 V. Hundred-picosecond pulse signals with amplitudes higher than 10 V can be used for the electrical characterization of the semiconductor device under test 110, which is beneficial for exploring the physical mechanism of resistive switching and various types of operating voltages.

[0034] For example, signal acquisition device 140 may be configured to acquire at least one pulse signal from signal providing device 130. For example, in some examples, signal acquisition device 140 may be an oscilloscope or other circuitry or device for acquiring pulse sequences. For example, in some examples, signal acquisition device 140 may also be used to acquire the amplitude of an output pulse signal from at least one of the detection interfaces.

[0035] For example, the state acquisition device 150 can be configured to acquire the real-time state of the semiconductor device under test 110 between two detection interfaces in the detection interface device 120, the real-time state of the semiconductor device under test 110 depending on the physical characteristics of at least one pulse signal. For example, in some examples, the state acquisition device may include a current waveform analyzer, a resistance analyzer, etc. For example, the real-time state of the semiconductor device under test 110 depends on the amplitude of at least one pulse signal. For example, in the case where the semiconductor device under test 110 includes a resistive random access memory (RRAM), the real-time state may refer to other physical or chemical states of the RRAM, such as the resistive state, phase state, magnetic state, valence state, etc. In this paper, the electrical characterization of the real-time state, i.e., real-time resistance, is mainly used as an example.

[0036] For example, the preprocessing device 160 may be configured to perform at least one preprocessing operation on the semiconductor device 110 under test via at least two detection interfaces in the detection interface device 120. For example, in some examples, the preprocessing device 160 may include a semiconductor parameter analyzer. For example, at least one preprocessing operation includes a forming operation on the semiconductor device under test containing resistive random access memory (RRAM), and set, reset, and read operations under DC voltage. For example, a set operation may refer to a write operation or programming operation of the RRAM, such as changing data in the memory from "0" to "1", or changing the resistance value from a high resistance state to a low resistance state. For example, a reset state may refer to an erase operation of the RRAM, such as correspondingly changing data in the memory from "1" to "0", or changing the resistance value from a low resistance state to a high resistance state.

[0037] For example, controller 170 may be configured to adjust the physical characteristics of at least one pulse signal in response to its physical characteristics and real-time state, and to provide the adjusted pulse signal via signal providing device 130 to the semiconductor device under test 110 to reacquire the real-time state, thereby obtaining the relationship between the physical characteristics of the at least one pulse signal and the real-time state. For example, the amplitude of at least one pulse signal may be adjusted in response to its amplitude and real-time state without changing its pulse width. Alternatively or additionally, the pulse width of at least one pulse signal may also be adjusted to obtain the relationship between its pulse width and the real-time state.

[0038] For example, in some examples, the controller can also be configured as any electronic device with computing capabilities, such as a smartphone, laptop computer, tablet computer, desktop computer, web server, etc., to automatically control the signal providing device 130, signal acquisition device 140, status acquisition device 150, and preprocessing device 160, as well as the switching device mentioned later. The embodiments of this disclosure do not limit the specific implementation of the controller. For example, the electronic device may include an FPGA processor, ARM processor, GPA processor, ARM processor, Central Processing Unit (CPU), or Graphics Processing Unit (GPU), Digital Signal Processor (DSP), or other forms of processing units with data processing capabilities and / or instruction execution capabilities, storage units, etc., and may also have an operating system, application programming interfaces (e.g., OpenGL (Open Graphics Library), Metal, etc.) installed on it.

[0039] Figure 2 A block diagram of another test apparatus 200 provided in at least one embodiment of the present disclosure is shown. For example, Figure 2 The semiconductor device under test 110, detection interface device 120, signal providing device 130, signal acquisition device 140, status acquisition device 150, preprocessing device 160, and controller 170 shown are... Figure 1 The corresponding components shown with the same reference numerals are essentially the same and will not be described again here.

[0040] like Figure 2 As shown, the test equipment 200 also includes at least one line L1 to L5 and a switching device 180. The switching device 180 is configured to control the connection or disconnection of at least one line L1 to L5. For example, at least one line L1 to L5 includes one or more of the following lines:

[0041] (1) A first line L1 connecting the signal providing device 130 and the signal acquisition device 140;

[0042] (2) A second line L2 connecting the signal providing device 130 and the detection interface device 120;

[0043] (3) A third line L3 connecting the signal providing device 130, the detection interface device 120 and the signal acquisition device 140;

[0044] (4) A fourth line L4 connecting the signal providing device 130, the detection interface device 120, and the status acquisition device 150; and

[0045] (5) The fifth line L5 is connected between the pretreatment device 160 and the detection interface device 120.

[0046] It should be noted that each line provided in this article can be a transmission line for transmitting various electrical signals, optical signals, magnetic signals, etc., and is an impedance-matched transmission line between the output and input ends, so that high-frequency pulse signals can be efficiently transmitted to the load end without causing the signal to return to the source end.

[0047] Optionally, in some examples, the second line L2 may remain connected without passing through the switching device 180 and without switching. Optionally, in some examples, the first lines L1 to the fifth lines L5 may be individually, partially, or entirely connected or disconnected via the switching device 180. For example, in some examples, the switching device 180 may be implemented as a hardware device including at least one high-speed switch and switching control software program. For example, the high-speed switch mentioned herein refers to a switch for conducting or disconnecting high-speed pulse signals on the order of hundreds of picoseconds, tens of picoseconds, or narrower. For example, in some examples, the switching control software program may use software such as LabVIEW to control the switch box to perform line switching. Optionally, the switching software program may also be implemented using other programming languages ​​such as Python, C++, or C#, or other programming languages ​​that support the communication interface protocol of the high-speed switch used. Compared with traditional manual line switching, the switching device 180 can achieve higher line switching efficiency, reduce the inconvenience and insertion loss caused by manual line switching, and shorten the connection length, thereby reducing line loss. In addition, this implementation method can reduce power loss in the line compared to conventional switch arrays and relay groups.

[0048] Figure 3 A block diagram of another test apparatus 300 provided in at least one embodiment of the present disclosure is shown, the test apparatus being used to test two-terminal semiconductor devices 110 to be tested. Figure 3 The semiconductor device under test 110, detection interface device 120, signal providing device 130, signal acquisition device 140, status acquisition device 150, preprocessing device 160, and controller 170 shown are... Figure 1 The corresponding components shown with the same reference numerals are essentially the same and will not be described again here.

[0049] like Figure 3As shown, the switching device 180 includes a first switch 182 and a second switch 184. Multiple detection interfaces include a first detection interface P1 and a second detection interface P2. For example, in the first line L1, the signal providing device 130 is connected to the signal acquisition device 140 via the first switch 182. In the third line L3, the signal providing device 130 is connected to the first detection interface P1 of the detection interface device 120 via the first switch 182, as indicated by line L3.1, and the second detection interface P2 of the detection interface device 120 is connected to the signal acquisition device 140 via the second switch 184, as indicated by line L3.2. In the fourth line L4, the signal providing device 130 is connected to the first detection interface P1 of the detection interface device 120 via the first switch 182, as indicated by line L4.1, and the second detection interface P2 of the detection interface device 120 is connected to the status acquisition device 150 via the second switch 184, as indicated by line L4.2; and in the fifth line L5, the preprocessing device 160 is connected to the first detection interface P1 of the detection interface device 120 via the first switch 184, as indicated by line L5.1, and the second detection interface P2 of the detection interface device 120 is connected to the preprocessing device 160 via the second switch 184, as indicated by line L5.2.

[0050] For example, in some examples, both the first switch 182 and the second switch 184 can be high-speed switches, such as PIN switches, and the switching control can be performed via a control switch box in the aforementioned switching control software program. The switching control software program can optionally be implemented using other programming languages ​​such as LabVIEW, Python, C++, or C#, or other programming languages ​​that support the communication interface protocol of the high-speed switches used. The first switch 182 and the second switch 184 provided in the embodiments of this disclosure have advantages such as high switching efficiency, low insertion loss, and fast response speed. The arrangement of the first switch 182 and the second switch 184 can further shorten the wiring length and further reduce line losses.

[0051] For example, in some examples, the detection interface device 120 is configured to accommodate the semiconductor device 110 to be tested. Figure 3 As shown, the first terminal T1 of the semiconductor device under test 110 is used to connect to the first detection interface P1 of the detection interface device 120, and the second terminal T2 of the semiconductor device under test 110 is used to connect to the second detection interface P2 of the detection interface device 120.

[0052] Optionally, in some examples, the semiconductor device under test 110 may include a selector such as a diode for controlling current switching and a resistive random access memory (IRRAM), also known as a 1D1R memory cell. For example, the anode of the diode serves as the first terminal T1, and the output terminal of the diode after being connected to the IRRAM serves as the second terminal T2. The technique of having a selector can effectively suppress interference current. For example, in some examples, since the diode only performs unidirectional conduction, the arrangement of the diodes is suitable for erase and write operations of the same polarity. Alternatively, the two-terminal semiconductor device may only have a two-terminal IRRAM, or the two-terminal semiconductor device may include a two-terminal selector and two or more IRRAMs; this disclosure is not limiting in this regard.

[0053] Figure 4 A block diagram of another test apparatus 400 provided in at least one embodiment of the present disclosure is shown, the test apparatus being used to test a three-terminal semiconductor device 410 to be tested. Figure 4 The detection interface device 120, signal providing device 130, signal acquisition device 140, status acquisition device 150, preprocessing device 160, controller 170, and switching device 180 including first switch 182 and second switch 184 shown are... Figure 3 The corresponding components shown with the same reference numerals are essentially the same and will not be described again here.

[0054] like Figure 4 As shown, in order to facilitate the connection of the three-terminal semiconductor device 410, the multiple detection interfaces of the detection interface device 120 also include a third detection interface P3, and the second line L2 is configured to connect the signal providing device 130 to the third detection interface P3 of the detection interface device 120.

[0055] For example, in some examples, the detection interface device 120 is further configured to accommodate a three-terminal semiconductor device 410 to be tested, the three terminals of which include a drain terminal D, a source terminal S, and a gate terminal G. A first detection interface P1, a second detection interface P2, and a third detection interface P3 are respectively connected to the drain terminal D, the source terminal S, and the gate terminal G. Optionally, in some examples, the three-terminal semiconductor device 410 may include a gate transistor, such as a transistor, for controlling current switching, and a resistive random access memory (RRAM), also known as a 1T1R memory cell. For example, in some examples, the transistor may be a bipolar junction transistor (BJT), a field-effect MOSFET, etc. For example, the gate of the transistor serves as the gate terminal G of the three-terminal semiconductor device 410, the output terminal of the transistor connected to the RRAM serves as the drain terminal D of the three-terminal semiconductor device 410, and the source of the transistor serves as the source terminal S of the three-terminal semiconductor device. The transistor-based solution can further suppress interference current. For example, in some examples, since the transistor can conduct current bidirectionally, the transistor arrangement is suitable for erase / write operations of opposite polarities. For example, in some examples, the three-terminal semiconductor device may also include a transistor and two or more resistive random access memories, or a memory array consisting of multiple 1T1R memory cells, but the embodiments of the present invention are not limited thereto.

[0056] Note that the semiconductor device 110 to be tested can be arranged outside the testing interface device 120, such as... Figure 1 and Figure 2 As shown, it can also be arranged inside the detection interface device 120, such as... Figure 3 and Figure 4 As shown, the embodiments of the present invention do not limit this, as long as the multiple terminals of the semiconductor device are respectively connected to the multiple detection interfaces of the detection interface device.

[0057] The second line L2 is configured to connect the signal providing device 130 to the third detection interface P3 of the detection interface device 120. In other words, the signal providing device 130 provides a pulse signal to the gate terminal of the detection interface device 120 through the second line L3 to provide a gate pulse signal to the semiconductor device 110 under test.

[0058] The following is combined with Figure 5 and Figure 6 This document describes in detail a specific embodiment of a semiconductor device under test (i.e., a 1T1R memory cell) and a test apparatus for performing tests on the semiconductor device under test having the structure.

[0059] Figure 5 A schematic diagram of a semiconductor device under test provided in this disclosure, with at least one specific embodiment, is shown. For example... Figure 5As shown, the structure of the resistive random access memory (IRRAM) is a 1T1R memory cell, based on which high-speed testing is performed. As illustrated, the IRRAM consists of a sandwich structure comprising an upper electrode (or first electrode), a resistive switching functional layer, and a lower electrode (or second electrode), connected to the drain of a transistor. The gate voltage of the transistor controls the current flowing through the IRRAM. A semiconductor parameter analyzer can set and reset the IRRAM by applying voltages to the drain and source terminals under DC voltage. The 1T1R memory cell circuit design in the embodiments of this disclosure meets the 50-ohm design rule. A 50-ohm GSG probe on a high-speed probe station is connected to the four terminals of the device, ensuring impedance matching of each line. This prevents pulse signals reaching the load point from being sent back to the source point, thus improving the transmission efficiency of the pulse signal.

[0060] Figure 6 A block diagram of a test apparatus 500 provided in at least a specific embodiment of the present disclosure is shown.

[0061] Figure 6 The description is for testing such as Figure 5 The test equipment 600 for the 1T1R memory cell shown can apply pulse signals with arbitrary controllable pulse width and / or amplitude to three-terminal semiconductor devices. The test equipment 600 consists of a picosecond pulse generator and power amplifier, a high-speed oscilloscope, a current waveform analyzer, a semiconductor parameter analyzer, and a high-speed switch box.

[0062] For example, in some examples, a picosecond pulse generator and a power amplifier coupled to the picosecond pulse generator are included in the signal providing device 130 described above. For example, the power amplifier receives a picosecond pulse signal input from the picosecond pulse generator and is configured to provide at least one gate pulse signal with adjustable amplitude to a third detection interface P3 and at least one drain pulse signal with adjustable amplitude to a first detection interface P1. For example, in some examples, at least one drain pulse signal and / or at least one gate pulse signal have a pulse width of no more than 100 ps and / or an amplitude greater than 10 V. For example, in a specific embodiment, the picosecond pulse generator may be a Keysight M8194A, and the power amplifier may be a high-bandwidth amplifier capable of stably outputting a pulse sequence with a pulse width of 100 ps and an amplitude of 11 V, particularly a pulse sequence with a maximum output of 20 ps. For example, in some examples, the pulse bandwidth of the high-bandwidth amplifier described above may be in the range of 1 kHz to 50 GHz, preferably on the order of 10 GHz. Furthermore, compared to conventional picosecond pulse generators (such as the PSPL 10070A series commonly used in high-speed testing), the aforementioned signal providing device, which combines a picosecond pulse generator with a power amplifier, offers advantages such as a more advanced operating system, diverse programming methods, and shorter picosecond pulse rise times, making it easier to reproduce ideal waveforms (such as rectangular square waves). The ultra-narrow picosecond pulse signal with an amplitude of up to 11V can be used for the electrical characterization of resistive switching components, facilitating the investigation of the physical mechanisms of resistive switching components and the voltage changes during formation, setting, resetting, and readout operations.

[0063] For example, in some examples, a high-speed oscilloscope is included in the signal acquisition device 140 described above. The high-speed oscilloscope acquires the output voltage signal from the second detection interface P2 of the detection interface device 120. For example, in some examples, a current waveform analyzer is included in the status acquisition device 150, and the current waveform analyzer reads the real-time current signal caused by at least one gate pulse signal and / or at least one drain pulse signal with adjustable amplitude from the second detection interface P2 of the detection interface device. Then, based on the output voltage signal acquired by the high-speed oscilloscope and the real-time current signal read by the current waveform analyzer, the real-time resistance of the resistive random access memory (RRAM) is obtained. For example, the amplitude of the output voltage signal is divided by the amplitude of the real-time current signal to obtain the real-time resistance of the RRAM. Alternatively, in some examples, the real-time resistance of the RRAM can also be obtained by other test circuits, which are not limited in this disclosure. For example, in a specific embodiment, a 59GHz bandwidth oscilloscope from Tektronix or other commercially available high-bandwidth oscilloscope is selected as the high-speed oscilloscope to acquire the waveform of the pulse signal and the voltage signal waveform change when resistance changes after connecting the RRAM. In addition, the current waveform analyzer uses a Keysight CX3300 analyzer and a current sensor to read the current changes caused by different pulse signals. The semiconductor parameter analyzer uses a Keysight B1500 or S4200 semiconductor device analyzer to perform various preprocessing operations on the device under test, including setup operations and initial DC voltage setting, resetting, and reading operations.

[0064] For example, the switch matrix includes a double-pole double-throw (2P2T) high-speed switch corresponding to the first switch 182 and a single-pole triple-throw (SP3T) high-speed switch corresponding to the second switch 184. The advantages of the switch matrix are the same as those of the switch device 180 described above, and will not be repeated here.

[0065] like Figure 6 As shown, the circuitry in the switch box is divided into five lines, represented by lines L1 to L5, according to different testing requirements. For example, in some cases, at the start of a high-speed test, the first line L1 is connected, and the waveform of the pulse signal provided by the picosecond pulse generator and amplifier is acquired using a high-speed oscilloscope. For example, in the second line L2, one end of the picosecond pulse generator and amplifier is connected to the gate terminal of the device under test, providing a rapidly changing gate voltage, also known as the gate pulse signal. The second line L2 does not necessarily need to be switched and can bypass the switch box. Figure 6An implementation of the second line L2 without passing through a switch box is shown. The third line includes L3.1 and L3.2. L3.1 refers to inputting at least one drain pulse signal from a picosecond pulse generator and amplifier to the drain terminal of the device under test (DUT) via a high-speed switch 2P2T. L3.2 refers to the electrical signal being acquired by a high-speed oscilloscope from the source terminal of the DUT via a high-speed switch SP3T. The high-speed oscilloscope can observe the response of the DUT to pulse signals of different amplitudes or widths, thereby determining whether a resistance change has occurred in the resistive switching memory. The fourth line includes L4.1 and L4.2, with L4.1 sharing a single transmission line with L3.1. L4.2 refers to the electrical signal being acquired by a current waveform analyzer from the source terminal of the DUT via a high-speed switch SP3T. Note that the current waveform analyzer differs from the high-speed oscilloscope in that the former can directly read the current signal flowing through the DUT. In addition, the fifth line, L5, is a DC test line, including L5.1 and L5.2, which perform necessary pre-processing operations such as forming, setting, resetting, and reading on the device under test under DC voltage conditions. During actual testing, the switching between these five lines L1 to L5 can be controlled by the switch box using LabVIEW software on a computer.

[0066] The following is combined with Figures 7 to 10 This disclosure describes in detail various test methods provided in at least one embodiment, such as using the aforementioned test equipment to perform high-speed testing on semiconductor devices under test, such as resistive random access memory (RRAM). The resistive switching physical mechanism of RRAM can be found in the relevant description above and will not be repeated here.

[0067] Figure 7 A flowchart of a test method 700 provided in at least one embodiment of this disclosure is shown. Figure 7 As shown, the test method 700 includes steps S710 to S760.

[0068] Step S710: Provide the semiconductor device to be tested. For example, the specific structure of the semiconductor device to be tested 110 can be referred to the relevant description above, and will not be repeated here.

[0069] Step S720: Perform at least one preprocessing operation on the semiconductor device under test using a preprocessing device 160. In step S720, the preprocessing device 160 performs at least one preprocessing operation on the semiconductor device under test 110 under DC voltage conditions, such as forming, setting, resetting, and reading operations. For example, refer to the description related to the preprocessing device 160 and at least one preprocessing operation above, which will not be repeated here.

[0070] Step S730: Provide at least one pulse signal with adjustable physical characteristics to the semiconductor device under test using a signal providing device. In step S730, at least one pulse signal with adjustable physical characteristics is provided to the semiconductor device under test 110 using signal providing device 130. For example, refer to the description above relating to signal providing device 130 and the physical characteristics of the at least one pulse signal, which will not be repeated here.

[0071] Step S740: Acquire at least one pulse signal using a signal acquisition device. In step S740, at least one pulse signal is acquired from the semiconductor device under test 110 using signal acquisition device 140. For example, refer to the description related to signal acquisition device 140 above, which will not be repeated here.

[0072] Step S750: The real-time state of the semiconductor device under test (SDT) is acquired from the SDT using a state acquisition device. The real-time state of the SDT depends on the physical characteristics of at least one pulse signal. In step S750, the real-time state of the SDT 110 is acquired from the SDT 110 using a state acquisition device 150. The real-time state of the SDT 110 depends on the physical characteristics of at least one pulse signal. For example, refer to the descriptions related to the state acquisition device 150 and the real-time state above; they will not be repeated here.

[0073] Step S760: In response to the physical characteristics and real-time state of at least one pulse signal, adjust the physical characteristics of at least one pulse signal, and provide the adjusted at least one pulse signal to the semiconductor device under test to reacquire the real-time state, so as to obtain the relationship between the physical characteristics of at least one pulse signal and the real-time state. The configuration of controller 170 can be referred to the relevant description above, and will not be repeated here.

[0074] Figure 8 A flowchart of another test method 800 provided by at least one embodiment of the present disclosure is shown. Figure 8 Steps S810 to S860 and Figure 7 Steps S710 to S760 are essentially the same and will not be repeated here.

[0075] For example, in test method 800, the semiconductor device under test may include at least a first terminal and a second terminal. Figure 8 As shown, test method 800 further includes one or more of steps S872 to S879. A detailed description follows.

[0076] Step S872: Connect the pretreatment device to the first terminal and the second terminal. For example, in some examples, this can be achieved by... Figure 3The first switch 182 and the second switch 184 shown connect the preprocessing device 160 to the first terminal T1 and the second terminal T2 of the semiconductor under test 110, respectively, thereby establishing lines L5.1 and L5.2 to achieve the overall connection of the fifth line L5. After connecting the fifth line, at least one preprocessing operation, namely step S820, is performed on the semiconductor device 110 under test. For example, in some examples, after the preprocessing operation under DC voltage is completed, the connection of the fifth line can be selectively disconnected by the first switch 182 and the second switch 184 according to the actual application requirements. This disclosure does not limit this.

[0077] In step S874, the signal providing device is connected to the first terminal to provide at least one pulse signal. In this step S874, the signal providing device 130 is connected to the first terminal T1 of the semiconductor device under test 110, that is, as... Figure 3 As shown, the shared portion connecting the third and fourth lines, namely L3.1 / L4.1, is used to provide at least one pulse signal to the semiconductor device under test 110, namely step S830.

[0078] Step S876: Connect the signal providing device to the signal acquisition device to detect at least one pulse signal. In this step S876, the signal providing device 130 is connected to the signal acquisition device 140, such as... Figure 3 The first line L1 is shown. Optionally, in some examples, the first line L1 does not pass through any switch, which facilitates real-time observation of the waveform of at least one pulse signal with adjustable physical characteristics within one cycle. Preferably, in some examples, it can also be via... Figure 3 The first switch 182 connects and disconnects the first line L1 to eliminate the influence of parasitic capacitance and parasitic resistance caused by the first line L1 on other high-speed test lines when the first line L1 is not needed.

[0079] Step S878: Connect the signal providing device to the first terminal and connect the second terminal to the status acquisition device. For example, in some examples, this can be achieved through... Figure 3 The first switch 182 connects the signal providing device 130 to the first terminal T1 of the semiconductor device under test 110, and the second terminal T2 is connected to the status acquisition device 150 via the second switch 184, thereby establishing lines L4.1 and L4.2 respectively to achieve the overall connection of the fourth line L4. For example, after connecting the fourth line L4, the signal providing device 130 provides at least one pulse signal with adjustable pulse width and / or amplitude to the first terminal T1 of the semiconductor device under test 110, and the status acquisition device 150 acquires the real-time status from the second terminal T2 of the semiconductor device under test 110, i.e., step S850.

[0080] Step S879: Connect the signal providing device to the first terminal and connect the second terminal to the signal acquisition device to acquire the output signal caused by at least one pulse signal from the second terminal. For example, in some examples, in this step S879, by... Figure 3 The first switch 182 connects the signal providing device 130 to the first terminal T1, and through Figure 3 The second switch 184 connects the second terminal T2 to the signal acquisition device 140, thereby establishing lines L3.1 and L3.2 respectively to achieve the overall connection of the third line L3. For example, in some examples, after connecting the third line L3, the specific implementation method for obtaining the relationship between the amplitude and real-time state of at least one pulse signal will be described below. Figure 10 This will be explained in detail in the text.

[0081] Figure 9 A flowchart of another test method 900 provided in at least one embodiment of the present disclosure is shown.

[0082] Figure 9 Steps S920, S930, S940, and S950 Figure 7 Steps S720, S730, S740, and S750 are essentially the same, and for the sake of brevity, Figure 9 The corresponding text is omitted. Figure 7 Steps S710 and S760.

[0083] For example, in some examples, Figure 9 The test method 900 also includes steps S982, S984, S992, and S994. These are described in detail below.

[0084] Step S982: Obtain the initial state of the semiconductor device under test according to at least one preprocessing operation, wherein the at least one preprocessing operation includes a set operation and / or a reset operation. For example, the initial state of the semiconductor device under test 110 may be the initial resistance value of a resistive switching memory under DC voltage conditions. Furthermore, the set operation and reset operation can be referred to the relevant descriptions above, and will not be repeated here.

[0085] Step S984: Based on the initial state of the semiconductor device under test, preset a first reference state and a second reference state. For example, based on the initial resistance value of the semiconductor device under test, a first reference resistance value and a second reference resistance value can be preset. For example, under DC voltage conditions, the preprocessing device 160 measures the initial resistance value of the semiconductor device under test, the low resistance value corresponding to the low resistance state of the resistive random access memory (RRAM), and the high resistance value corresponding to the high resistance state of the RRAM in a reset operation. For example, the first reference resistance value can be less than the high resistance value and greater than the initial resistance value, while the second reference resistance value can be greater than the low resistance value and less than the initial resistance value. For example, in some examples, the first reference resistance value can be 1.2 times the initial resistance value, and the second reference state can be 0.8 times the initial resistance value. By setting the first reference state and the second reference state, it can be determined whether the real-time state under the pulse signal response of a specified amplitude is in a set operation or a reset operation, so as to further determine whether the amplitude of the pulse signal needs to be adjusted.

[0086] Step S992: Based on at least one pulse signal acquired by the signal acquisition device, preset the initial value, termination value, and step value of at least one pulse signal relative to the physical characteristics. In step S992, for example, the controller 170 can set the initial value, termination value, and step value of the pulse signal relative to the pulse width and / or amplitude based on the waveform profile of the acquired at least one pulse signal. For example, in the case of adjusting the amplitude, the initial value can be the minimum amplitude, and the termination value can be the maximum amplitude, and vice versa. For example, the step value can be a fraction of the difference between the termination value and the initial value, or even a fraction of a hundredth. Note that the step value is a constant positive or negative value, and the smaller the absolute value of the step value, the more real-time states are acquired, thereby achieving higher measurement accuracy. In addition, a similar approach can be used in the case of adjusting the pulse width, which will not be elaborated here. For example, in the case of a two-terminal semiconductor device, at least one pulse signal includes a first pulse signal for a set operation and / or a second pulse signal for a reset operation provided to the first terminal T1 of the semiconductor device under test 100. For example, in the case of a three-terminal semiconductor device, at least one pulse signal is acquired by the signal acquisition device 140 and provided to the drain terminal D by the signal providing device 430, such as... Figure 4 As shown.

[0087] Step S994: ​​Adjust the physical characteristics of at least one pulse signal and provide the adjusted pulse signal to the semiconductor device under test. For example, in step S994, the controller 170 sends an instruction to the signal providing device 130 to adjust the amplitude or pulse width of at least one pulse signal. Upon receiving the adjustment instruction, the signal providing device 130 automatically adjusts the amplitude or pulse width of at least one pulse signal to a specified amplitude or pulse width and provides a pulse signal with the specified amplitude or pulse width to the semiconductor device under test, thereby achieving automatic adjustment of the amplitude or pulse width of the pulse signal.

[0088] Figure 10 A flowchart of another test method 1000 provided in at least one embodiment of the present disclosure is shown. Figure 10 Steps S1092, S1094 and S1050 are the same as Figure 9 Steps S992, S994, and S950 are essentially the same, and Figure 10 Step S1078 and Figure 8 Step S878 is essentially the same. Furthermore, for the sake of brevity, Figure 10 The corresponding text is omitted. Figure 9 Steps S920, S982, S984, S930, and S940. For example, in some examples, Figure 10 Accordingly, omitted Figure 8 Steps S872, S874, and S876.

[0089] For example, in some examples, Figure 10 Step S1092 describes the preset pulse signal in detail. Additionally, Figure 9 Some examples of step S960 also include steps S1061a, S1061b, S1062a, S1062b, S1063a, S1063b and S1164. These are described in detail below.

[0090] For example, step S1092: Based on at least one acquired pulse signal, preset the initial amplitude Vset-ini of the first pulse signal, the initial amplitude Vreset-ini of the second pulse signal, the termination amplitude Vset-stop of the first pulse signal, the termination amplitude Vreset-stop of the second pulse signal, and the step amplitude Vstep.

[0091] Step 1061a: Determine whether the real-time state meets the first reference state. For example, determine whether the real-time resistance value is greater than the first reference resistance value, and whether the high-resistance state of the resistive variable memory has been reached.

[0092] If the real-time state meets the first reference state, step S1079 is executed: the signal providing device is connected to the first terminal, and the second terminal is connected to the signal acquisition device, i.e., L3 is connected. The specific implementation of connecting L3 is as described above and will not be repeated here.

[0093] Step 1062a: Further determine whether the amplitude of the current first pulse signal has reached the termination amplitude of the first pulse signal. For example, whether the amplitude Vset of the current first pulse signal is greater than or equal to the termination amplitude Vset-stop of the first pulse signal.

[0094] If the amplitude of the current first pulse signal has not reached the termination amplitude of the first pulse signal, step 1063a is executed: the step amplitude is added to the amplitude of the current first pulse signal to obtain the amplitude of the next first pulse signal. For example, the step amplitude Vstep is added to the amplitude Vset of the current first pulse signal to obtain the amplitude Vset' of the next first pulse signal, which is expressed as Vset' = Vset + Vstep.

[0095] Step 1061b: Determine whether the real-time state meets the second reference state. For example, determine whether the real-time resistance value is greater than the second reference resistance value, and whether the low-resistance state of the resistive variable memory has been reached.

[0096] If the real-time state meets the second reference state, execute step S1079: connect the signal providing device to the first terminal and connect the second terminal to the signal acquisition device, i.e. connect L3.

[0097] Step 1062b: Determine whether the amplitude of the current second pulse signal has reached the termination amplitude of the second pulse signal. For example, whether the amplitude Vreset of the current first pulse signal is greater than or equal to the termination amplitude Vreset-stop of the first pulse signal.

[0098] If the amplitude of the current second pulse signal has not reached the termination amplitude of the second pulse signal, step 1063b is executed: the step amplitude is added to the amplitude of the current second pulse signal to obtain the amplitude of the next second pulse signal. For example, the step amplitude Vstep is added to the amplitude Vreset of the current second pulse signal to obtain the amplitude Vreset' of the next second pulse signal, which is expressed as Vreset' = Vreset + Vstep.

[0099] Next, the controller 150 sends the amplitude of the next first pulse signal and / or the amplitude of the next second pulse signal as an amplitude adjustment request to the signal generator 130 to re-execute step S1144, that is, to adjust the amplitude of the first pulse signal and the second pulse signal, and to provide the adjusted first pulse signal and the second pulse signal to the semiconductor device under test 110, so as to reacquire the real-time state and make a judgment again until the reacquired real-time state no longer satisfies both the first reference state and the second reference state. Then, the controller obtains the data of the amplitude of the pulse signal and the real-time resistance in the set and reset states, and obtains the relationship between the amplitude of the pulse signal and the real-time resistance, that is, step S1064.

[0100] Figure 11 A flowchart of a measurement method 1100 for a three-terminal semiconductor device provided in at least one embodiment of the present disclosure is shown.

[0101] For example, in some examples, the semiconductor device under test can refer to a three-terminal semiconductor device, and further includes a third terminal, wherein the first terminal is the drain terminal, the second terminal is the source terminal, and the third terminal is the gate terminal. For example, a three-terminal semiconductor device can be as follows: Figure 4 Semiconductor devices under test and Figure 5 The structure of the 1T1R memory cell is shown in the diagram. Please refer to the relevant description above; it will not be repeated here.

[0102] Figure 11 Steps S1194, S1178, S1150, S1161a-b, S1162a-b, S1163a-b, and S1164 are sequentially connected with... Figure 10 Steps S1094, S1078, S1050, S1061a-b, S1062a-b, S1063a-b, and S1064 are essentially the same and will not be described again here.

[0103] Additionally, for the sake of brevity, with Figure 10 Similarly, Figure 11 The same is omitted in the middle. Figure 9 Steps S920, S982, S984, S930, and S940, and optionally omitted. Figure 8 Steps S872, S874, and S876.

[0104] For example, in the case where a three-terminal semiconductor device also includes a third terminal, Figure 11 The test method 1100 steps S1192 and S1179 are the same as Figure 10There are slight differences between steps S1092 and S1079. In step S1192, when at least one pulse signal is preset, the at least one pulse signal includes, in addition to the first pulse signal and the second pulse signal, a third pulse signal for setting operation and / or a fourth pulse signal for resetting operation provided to the gate terminal of the semiconductor device under test. That is, the initial amplitude Vg-set-ini of the third pulse signal, the termination amplitude Vg-set-stop of the third pulse signal, the initial amplitude Vg-reset-ini of the fourth pulse signal, and the termination amplitude Vg-reset-stop of the fourth pulse signal.

[0105] In step S1179, when the signal providing device is connected to the first terminal, i.e., the drain terminal, it is also connected to the gate terminal to provide at least one pulse signal. For example, when the second line L2 and the third line L3 are connected, the signal providing device 130 provides a first pulse signal and a second pulse signal to the drain terminal D, and provides a third pulse signal and a fourth pulse signal to the gate terminal G.

[0106] For example, test method 1100 also includes the following operations.

[0107] If the amplitude Vset of the current first pulse signal reaches the termination amplitude Vset-stop of the first pulse signal, further determine step S1165a: whether the amplitude Vg-set of the current third pulse signal reaches the termination amplitude Vg-set-stop of the third pulse signal.

[0108] If the amplitude Vg-set of the current third pulse signal has not reached the termination amplitude Vg-set-stop of the third pulse signal, execute step S1166a: add the step amplitude Vstep to the amplitude Vg-set of the current third pulse signal to obtain the amplitude Vg-set' of the next third pulse signal, and set the amplitude Vset' of the next first pulse signal to the initial amplitude Vset-ini of the first pulse signal, as follows. Figure 11 In this context, it is represented as Vg-set' = Vg-set + Vstep, Vset' = Vset-ini.

[0109] Additionally or alternatively, if the amplitude Vreset of the current second pulse signal reaches the termination amplitude Vreset-stop of the second pulse signal, further determine step S1165b: whether the amplitude Vg-reset of the current fourth pulse signal reaches the termination amplitude Vg-reset-stop of the fourth pulse signal;

[0110] If the amplitude Vg-reset of the current fourth pulse signal has not reached the termination amplitude Vg-reset-stop of the fourth pulse signal, a step amplitude Vstep is added to the current amplitude Vg-reset of the fourth pulse signal to obtain the amplitude Vg-reset' of the next fourth pulse signal, and the amplitude Vreset' of the next second pulse signal is set as the initial amplitude Vreset-ini of the second pulse signal, as follows. Figure 11 In this context, it is represented as Vg-reset'=Vg-reset+Vstep, Vreset'=Vreset-ini.

[0111] Next, the amplitudes of the next first pulse signal Vset', the next second pulse signal Vreset', the next third pulse signal Vg-set', and the next fourth pulse signal Vg-reset' are sent to the signal generator 130 to re-execute step S1194 and the subsequent steps of obtaining the real-time state S1150 and the specific judgment steps, until the re-obtained real-time state no longer satisfies both the first reference state and the second reference state. Then, the amplitudes of the pulse signals and the real-time resistance under the obtained set and reset states are used to obtain the relationship between the amplitudes of the pulse signals and the real-time resistance, i.e., step S1064.

[0112] Figure 12 A flowchart of a method S1250 for obtaining real-time status provided in at least one embodiment of the present disclosure is shown. Figure 7 Some examples of the real-time state acquisition step S750 correspond to the real-time state method S1250, specifically including Figure 12 Steps S1252, S1254, and S1256. The specific description of the real-time state method S1250 is as follows.

[0113] Step S1252: The current analyzer in the status acquisition device reads the current signal flowing through the semiconductor device under test (SDT). For example, using a current analyzer, the current signal flowing through the SDT 110 can be read. By using a current analyzer instead of directly capturing the real-time state of the SDT, the current characterization of the resistive switching memory can be automatically and in real-time captured at high speeds, thereby improving the accuracy of real-time measurements.

[0114] Step S1254: Acquire the output voltage signal from the semiconductor device under test using a high-speed oscilloscope. For example, a high-speed oscilloscope can be used to acquire the amplitude of the output voltage signal from the semiconductor device under test 110. The high-speed oscilloscope can capture the amplitude of the output voltage signal in real time.

[0115] Step S1256: Obtain the real-time resistance of the semiconductor device under test based on the current signal and the output voltage signal. For example, the controller 170 can calculate the real-time resistance of the semiconductor device under test by dividing the amplitude of the output voltage signal by the current signal, and store the pulse width and amplitude of the pulse signal that causes the real-time resistance, as well as the data of the real-time resistance, in the memory of the controller.

[0116] The features and advantages of the equipment and steps involved in the above steps can be found in the relevant descriptions above, and will not be repeated here.

[0117] Figure 13 A flowchart of at least one test method 1300 provided in a specific embodiment is shown. This test method 1300 is based on… Figure 5 The structure of the 1T1R three-terminal semiconductor device and Figure 6 The testing was conducted using 600 testing devices.

[0118] like Figure 13 As shown, after startup, the first switch 2P2T and the second switch SP3T in the switch box are controlled via LABVIEW software to connect to the fifth line L5, providing preprocessing operations to the source and drain terminals of the three-terminal semiconductor device. The three-terminal semiconductor device is initialized using a semiconductor parameter analyzer, completing the forming operation. Based on the resistance range of the three-terminal semiconductor device under DC voltage, four target resistance values ​​R0, R1, R2, and R3 are set. For example, R0 can correspond to the initial resistance value under DC current conditions, R1 can correspond to the resistance value in the reset state, R2 can correspond to the resistance value in the set state, and R3 can correspond to the resistance value under read / write or forming operations. The four target resistance values ​​can also be represented by other resistance values, and this disclosure does not limit this.

[0119] The first switch in the switch box is connected to the first line L1 via LabVIEW software to acquire the pulse signal provided by the high-speed pulse generator using a high-speed oscilloscope. The pulse shape of the pulse signal within one pulse cycle is then observed using the high-speed oscilloscope. Based on the acquired pulse shape, the initial amplitude of the pulse signal is set, including the initial amplitude Vg-set0 of the third pulse signal input to the gate for the set operation, the initial amplitude Vg-reset0 of the fourth pulse signal input to the reset operation, the initial amplitude Vset0 of the first pulse signal input to the drain for the set operation, the initial amplitude Vreset0 of the second pulse signal input to the drain for the reset operation, and the step amplitude Vstep. For example, the maximum amplitude of the pulse signal can also be set using the controller, including the maximum amplitude Vg-set-max of the third pulse signal input to the gate for the set operation, the maximum amplitude Vg-reset-max of the fourth pulse signal input to the reset operation, the maximum amplitude Vset-max of the first pulse signal input to the drain for the set operation, and the maximum amplitude Vreset-max of the second pulse signal input to the drain for the reset operation. The amplitude of the pulse signal is adjusted stepwise from the initial amplitude using a high-speed pulse generator, and the amplitude of the pulse signal is written into the semiconductor device.

[0120] The first and second switches in the switch box are controlled using LabVIEW software to connect to the fourth line L4. A current waveform analyzer is then used to read the current signal flowing through the semiconductor device, and the real-time resistance R is calculated based on the current signal and the acquired voltage signal. Finally, the relationship between the real-time resistance R and the target resistance is determined.

[0121] The first decision is made regarding whether the real-time resistance R is greater than 1.2 times R0.

[0122] If the first decision result is yes, then the second line L2 and the third line L3 are connected to provide pulse signals to the gate end and the source end respectively using a high-speed pulse generator, and further perform the first judgment on whether the amplitude Vset of the current first pulse is equal to the maximum amplitude Vset-max of the first pulse.

[0123] If the first judgment result is negative, the amplitude Vset of the current first pulse is increased by the step amplitude Vstep to calculate the adjusted amplitude Vset of the first pulse.

[0124] If the first judgment is yes, then a second judgment is made on whether the amplitude Vg-set of the current third pulse is equal to the maximum amplitude Vg-set-max of the third pulse. If the second judgment is yes, then the amplitude Vg-set of the current third pulse is increased by a step amplitude Vstep to calculate the adjusted amplitude Vg-set of the third pulse, and the adjusted amplitude Vset of the first pulse is equal to the initial amplitude Vset0 of the first pulse. If the second judgment is no, then the judgment cycle ends.

[0125] Alternatively, a second determination is made as to whether the real-time resistance R is less than 0.8 times R0.

[0126] If the second decision result is yes, then the second line L2 and the third line L3 are connected to provide pulse signals to the gate end and the source end respectively using a high-speed pulse generator, and further perform a third judgment on whether the amplitude Vreset of the current second pulse is equal to the maximum amplitude Vreset-max of the second pulse.

[0127] If the third judgment result is negative, the amplitude of the current second pulse Vreset is increased by the step amplitude Vstep to calculate the adjusted amplitude of the second pulse Vreset.

[0128] If the third judgment result is yes, the judgment cycle ends. Alternatively, if the third judgment result is yes, a fourth judgment can be further executed to determine whether the amplitude of the current fourth pulse, Vg-reset, is equal to the maximum amplitude of the fourth pulse, Vg-reset-max. The steps of the fourth judgment are basically the same as those of the third judgment, and will not be described again here.

[0129] Next, the amplitudes of the first pulse (Vset), the second pulse (Vreset), the third pulse (Vg-set), and / or the fourth pulse (Vg-reset) are input into a high-speed pulse generator to provide the semiconductor device with pulse signals of adjusted amplitude. This allows the current to be read again and the real-time resistance to be calculated. Various decisions and judgments are then performed until the real-time resistance no longer satisfies the first and second decisions mentioned above, thus obtaining the relationship between the pulse amplitude and the resistance.

[0130] For example, the pulse width can be adjusted appropriately and provided to the three-terminal semiconductor device in the same way to obtain the relationship between pulse amplitude and resistance under different pulse width conditions.

[0131] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0132] It is important to note that the flowcharts and method descriptions in this application are merely illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the given order. Some steps may be performed in parallel, independently of each other, or in another suitable order. Furthermore, words such as "secondly," "then," "next," etc., are not intended to limit the order of steps; these words are merely used to guide the reader through the description of these methods.

[0133] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that connections, arrangements, or configurations must be made in the manner shown in the block diagrams. It should also be noted that in the apparatuses and methods of this application, components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered equivalent solutions to those in this application.

[0134] The following points need to be explained:

[0135] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0136] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0137] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A testing device, comprising: A testing interface device is configured to accommodate a semiconductor device under test and includes multiple testing interfaces, wherein the multiple testing interfaces are respectively used to connect to multiple terminals of the semiconductor device under test; A signal providing device is configured to provide at least one pulse signal having adjustable physical characteristics to the semiconductor device under test through at least one of a plurality of detection interfaces of the detection interface device, wherein the signal providing device includes a picosecond pulse generator and a power amplifier coupled to the picosecond pulse generator; A signal acquisition device is configured to acquire the at least one pulse signal; A status acquisition device is configured to acquire the real-time status of the semiconductor device under test between two detection interfaces in the detection interface device, wherein the real-time status of the semiconductor device under test depends on the physical characteristics of the at least one pulse signal. A preprocessing apparatus is configured to perform at least one preprocessing operation on the semiconductor device under test through at least two detection interfaces in the detection interface apparatus. The controller is configured to adjust the physical characteristics of the at least one pulse signal in response to the physical characteristics of the at least one pulse signal and the real-time state, and to provide the adjusted at least one pulse signal to the semiconductor device under test to reacquire the real-time state, so as to obtain the relationship between the physical characteristics of the at least one pulse signal and the real-time state of the semiconductor device under test. Multiple lines; and A switching device is configured to control the connection or disconnection of the plurality of lines. The switching device includes a first switch, a second switch, and a switching control software program. The first switch is a double-pole double-throw high-speed switch, and the second switch is a single-pole triple-throw high-speed switch. The switching control software program controls the first switch and the second switch to perform line switching. The plurality of detection interfaces include a first detection interface and a second detection interface, and the plurality of lines include the following lines: A first line connects the signal providing device and the signal acquiring device, wherein the signal providing device is connected to the signal acquiring device via the first switch. The second line connecting the signal providing device and the detection interface device A third line connects the signal providing device, the detection interface device, and the signal acquisition device. The signal providing device is connected to the first detection interface of the detection interface device via the first switch, and the second detection interface of the detection interface device is connected to the signal acquisition device via the second switch. A fourth line connects the signal providing device, the detection interface device, and the status acquisition device. The signal providing device is connected to the first detection interface of the detection interface device via the first switch, and the second detection interface of the detection interface device is connected to the status acquisition device via the second switch. A fifth line connects the preprocessing device and the detection interface device, wherein the preprocessing device is connected to the first detection interface of the detection interface device via the first switch, and the second detection interface of the detection interface device is connected to the preprocessing device via the second switch.

2. The testing equipment according to claim 1, wherein, The plurality of detection interfaces also includes a third detection interface, wherein the second line is configured as the third detection interface connecting the signal providing device and the detection interface device.

3. The testing equipment according to claim 1, wherein, The detection interface device is configured to accommodate two semiconductor devices to be tested, wherein, The first terminal of the semiconductor device under test is used to connect to the first detection interface of the detection interface device, and The second terminal of the semiconductor device under test is used to connect to the second detection interface of the detection interface device.

4. The testing equipment according to claim 2, wherein, The detection interface device is also configured to accommodate the three-terminal semiconductor device to be tested. The three-terminal semiconductor device includes a drain terminal, a source terminal, and a gate terminal, wherein... The first detection interface, the second detection interface, and the third detection interface are respectively used to connect to the drain terminal, the source terminal, and the gate terminal.

5. The testing equipment according to claim 1, wherein, The physical characteristics include pulse width or amplitude.

6. The testing equipment according to claim 5, wherein, The power amplifier receives a picosecond pulse signal input from the picosecond pulse generator and is configured to provide a gate pulse signal with adjustable pulse width and / or amplitude to the third detection interface and a drain pulse signal with adjustable pulse width and / or amplitude to the first detection interface.

7. The testing equipment according to claim 6, wherein, The pulse width of the at least one pulse signal is not greater than 100 ps, ​​and / or the amplitude of the at least one pulse signal is greater than 10 V.

8. The testing equipment according to claim 3 or 4, wherein, The signal acquisition device includes a high-speed oscilloscope and is configured to acquire an output voltage signal from the second detection interface of the detection interface device using the high-speed oscilloscope. The status acquisition device includes a current waveform analyzer and is configured to read a real-time current signal caused by at least one pulse signal with an adjustable amplitude from the second detection interface of the detection interface device by the current waveform analyzer, and then obtain the real-time resistance of the semiconductor device under test based on the real-time current signal read by the current waveform analyzer and the output voltage signal acquired by the high-speed oscilloscope.

9. The testing equipment according to claim 1, wherein, The preprocessing apparatus includes a semiconductor parameter analyzer, and the at least one preprocessing operation includes a formation operation, a setting operation, a resetting operation, and a reading operation in a DC state.

10. A testing method, comprising the following steps: Provide the semiconductor device to be tested; At least one preprocessing operation is performed on the semiconductor device under test using a preprocessing device; A signal providing device is used to provide at least one pulse signal with adjustable physical characteristics to the semiconductor device under test, wherein the signal providing device includes a picosecond pulse generator and a power amplifier coupled to the picosecond pulse generator; The at least one pulse signal is acquired using a signal acquisition device; The real-time state of the semiconductor device under test is acquired using a state acquisition device, wherein the real-time state of the semiconductor device under test depends on the physical characteristics of the at least one pulse signal; and In response to the physical characteristics of the at least one pulse signal and the real-time state, the physical characteristics of the at least one pulse signal are adjusted, and the adjusted at least one pulse signal is provided to the semiconductor device under test to reacquire the real-time state, so as to obtain the relationship between the physical characteristics of the at least one pulse signal and the real-time state of the semiconductor device under test. The method involves using a switching device to control the connection or disconnection of multiple lines. The switching device includes a first switch, a second switch, and switching control software. The first switch is a double-pole double-throw high-speed switch, and the second switch is a single-pole triple-throw high-speed switch. The switching control software controls the first and second switches to perform line switching. The semiconductor device under test includes a first terminal and a second terminal, and the testing method further includes one or more of the following steps: The signal providing device is connected to the first terminal to provide the at least one pulse signal, wherein the signal providing device is connected to the first terminal via the first switch; Before performing the at least one preprocessing operation, the preprocessing device is connected to the first terminal and the second terminal, wherein the preprocessing device is connected to the first terminal via the first switch and the preprocessing device is connected to the second terminal via the second switch; Before acquiring the at least one pulse signal, the signal providing device is connected to the signal acquisition device to detect the at least one pulse signal, wherein the signal providing device is connected to the signal acquisition device via the first switch; Before acquiring the real-time state of the semiconductor device under test, the signal providing device is connected to the first terminal, and the second terminal is connected to the state acquisition device to provide at least one pulse signal of an adjustable physical characteristic to the semiconductor device under test and to detect the real-time state flowing through the semiconductor device under test, wherein the signal providing device is connected to the first terminal via the first switch, and the second terminal is connected to the state acquisition device via the second switch; and After acquiring the real-time status of the semiconductor device under test, the signal providing device is connected to the first terminal, and the second terminal is connected to the signal acquisition device to acquire the output signal caused by the at least one pulse signal from the second terminal, wherein the signal providing device is connected to the first terminal via the first switch, and the second terminal is connected to the signal acquisition device via the second switch.

11. The test method according to claim 10, further comprising: The initial state of the semiconductor device under test is obtained according to the at least one preprocessing operation, wherein the at least one preprocessing operation includes a set operation and / or a reset operation; Based on the initial state of the semiconductor device under test, a first reference state and a second reference state are preset; Based on the at least one pulse signal acquired by the signal acquisition device, an initial value, a termination value, and a step value of the at least one pulse signal relative to a physical feature are preset. The at least one pulse signal includes a first pulse signal provided to the first terminal of the semiconductor device under test for the set operation and / or a second pulse signal for the reset operation; and The physical characteristics of the at least one pulse signal are adjusted, and the adjusted at least one pulse signal is provided to the semiconductor device under test.

12. The test method according to claim 11, wherein, The preset initial and final values ​​and step values ​​of the at least one pulse signal relative to the physical feature include the preset initial amplitude, final amplitude, and step amplitude of the at least one pulse signal, and... The adjustment of the physical characteristics of the at least one pulse signal in response to its physical characteristics and real-time state includes: - If the real-time state satisfies the first reference state; Connect the signal providing device to the first terminal, and connect the second terminal to the signal acquisition device. Determine whether the amplitude of the current first pulse signal has reached the termination amplitude of the first pulse signal; If the amplitude of the current first pulse signal does not reach the termination amplitude of the first pulse signal, the step amplitude is added to the amplitude of the current first pulse signal to obtain the amplitude of the next first pulse signal. - If the real-time state satisfies the second reference state; Connect the signal providing device to the first terminal, and connect the second terminal to the signal acquisition device. Determine whether the amplitude of the current second pulse signal has reached the termination amplitude of the second pulse signal; If the amplitude of the current second pulse signal does not reach the termination amplitude of the second pulse signal, the step amplitude is added to the amplitude of the current second pulse signal to obtain the amplitude of the next second pulse signal.

13. The test method according to claim 12, wherein, The semiconductor device under test further includes a third terminal, wherein the first terminal is the drain terminal, the second terminal is the source terminal, and the third terminal is the gate terminal; When the initial amplitude, termination amplitude, and step amplitude of the at least one pulse signal are preset based on the acquired at least one pulse signal, the at least one pulse signal, in addition to the first pulse signal and the second pulse signal, also includes a third pulse signal provided to the gate terminal of the semiconductor device under test for the set operation and / or a fourth pulse signal for the reset operation. When the signal providing device is connected to the drain terminal, the signal providing device is also connected to the gate terminal to provide the at least one pulse signal, wherein the signal providing device is used to provide the first pulse signal and the second pulse signal to the drain terminal, and to provide the third pulse signal and the fourth pulse signal to the gate terminal.

14. The test method according to claim 13, wherein, - When the amplitude of the current first pulse signal reaches the termination amplitude of the first pulse signal, Further determine whether the amplitude of the current third pulse signal has reached the termination amplitude of the third pulse signal; If the amplitude of the current third pulse signal does not reach the termination amplitude of the third pulse signal, the step amplitude is added to the amplitude of the current third pulse signal to obtain the amplitude of the next third pulse signal, and the amplitude of the next first pulse signal is set as the initial amplitude of the first pulse signal. and / or - When the amplitude of the current second pulse signal reaches the termination amplitude of the second pulse signal, Further determine whether the amplitude of the current fourth pulse signal has reached the termination amplitude of the fourth pulse signal; If the amplitude of the current fourth pulse signal does not reach the termination amplitude of the fourth pulse signal, the step amplitude is added to the amplitude of the current fourth pulse signal to obtain the amplitude of the next fourth pulse signal, and the amplitude of the next second pulse signal is set as the initial amplitude of the second pulse signal.

15. The test method according to claim 10, wherein, The usage status acquisition device acquires the real-time status of the semiconductor device under test from the semiconductor device under test, including: Using a current waveform analyzer included in the status acquisition device, the current signal flowing through the semiconductor device under test is read from the second terminal of the semiconductor device under test; The output voltage signal is acquired from the second terminal of the semiconductor device under test using a high-speed oscilloscope; and The real-time resistance of the semiconductor device under test is obtained based on the current signal and the output voltage signal.

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