Failure structures in semiconductor devices

Abstract

Failure structures in semiconductor devices are disclosed. A semiconductor device is provided. In embodiments, the semiconductor device includes a control region, a first power region, a second power region, an isolation region, and / or a short structure. The control region includes a control terminal. The first power region includes a first power terminal. The second power region includes a second power terminal. The isolation region is between the control region and the first power region. The short structure extends from the first power region through the isolation region to the control region. The short structure is configured to form a low resistance connection between the control region and the first power region during a failure state of the semiconductor device.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] Semiconductor devices such as transistors and thyristors may enter a failure state. A failure state can correspond to a short circuit between the power terminals of the semiconductor device. A failure state may cause the semiconductor device to explode, generate an electric arc, and / or damage one or more surrounding components. Summary of the Invention

[0003] This overview is provided to introduce, in a simplified form, the options of the concepts further described below in the detailed description. This overview is not intended to identify key elements or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0004] In one embodiment, a semiconductor device is provided. The semiconductor device may include a control region, a first power region, a second power region, an isolation region, and / or a short-circuit structure. The control region may include a control terminal. The first power region may include a first power terminal. The second power region may include a second power terminal. An isolation region may be located between the control region and the first power region. The short-circuit structure may extend from the first power region through the isolation region to the control region. The short-circuit structure may be configured to form a low-resistance connection between the control region and the first power region during a failure state of the semiconductor device.

[0005] In this embodiment, a semiconductor device is provided. The semiconductor device may include a semiconductor substrate, a control region, a first power region, a second power region, an isolation region, and / or a failure structure. The semiconductor substrate may include silicon carbide (SiC). The control region may include a control terminal. The first power region may include a first power terminal. The second power region may include a second power terminal. The isolation region may be located between the control region and the first power region. The isolation region may cover the semiconductor substrate. The failure structure may extend from the first power region through the isolation region to the control region. The failure structure may be configured to alter the properties of at least some of the materials between the control region and the first power region during a failure state of the semiconductor device.

[0006] In one embodiment, a semiconductor device is provided. The semiconductor device may include a semiconductor substrate, a control region, a first power region, a second power region, an isolation region, a transition structure, and / or a dielectric structure. The semiconductor substrate may include SiC. The control region may include a control terminal. The first power region may include a first power terminal. The second power region may include a second power terminal. The isolation region may be located between the control region and the first power region. The isolation region may cover the semiconductor substrate. The transition structure may extend from the first power region through the isolation region to the control region. The dielectric structure may surround a portion of the first power region. The dielectric structure may define an opening between the first power region and the transition structure.

[0007] To achieve the foregoing and related objectives, the following description and accompanying drawings illustrate certain illustrative aspects and implementations. These aspects and implementations indicate only some of the various ways in which one or more aspects may be employed. Other aspects, advantages, and novel features of this disclosure will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1A The illustration shows an example of a semiconductor device.

[0009] Figure 1B The illustration is in Figure 1A The cross-section of a semiconductor device as defined in the text.

[0010] Figure 1C The illustration is in Figure 1A The cross-section of a semiconductor device as defined in the text.

[0011] Figure 1D The illustration is in Figure 1A The cross-section of a semiconductor device during its failure state, as defined in the text.

[0012] Figure 1E The illustration shows an example of a semiconductor device.

[0013] Figure 1F The illustration is in Figure 1A The cross-section of a semiconductor device as defined in the text.

[0014] Figure 2A The illustration shows an example of a semiconductor device.

[0015] Figure 2B The illustration is in Figure 2A The cross-section of a semiconductor device as defined in the text.

[0016] Figure 2C The illustration is in Figure 2A The cross-section of a semiconductor device as defined in the text.

[0017] Figure 2D The illustration is in Figure 2A The cross-section of a semiconductor device during its failure state, as defined in the text.

[0018] Figure 2E The illustration is in Figure 2A The cross-section of a semiconductor device during its failure state, as defined in the text.

[0019] Figure 2F The illustration shows an example of a semiconductor device.

[0020] Figure 3A The illustration shows an example of a semiconductor device.

[0021] Figure 3B The illustration is in Figure 3A The cross-section of a semiconductor device as defined in the text.

[0022] Figure 3C The illustration is in Figure 3A The cross-section of a semiconductor device during its failure state, as defined in the text.

[0023] Figure 4 The diagram illustrates a line graph related to the operation of semiconductor devices.

[0024] Figure 5 The diagram illustrates a line graph related to the operation of semiconductor devices.

[0025] Figure 6 The diagram shows a line graph relating the temperature distribution of a semiconductor device during a failure state. Detailed Implementation

[0026] The claimed subject matter will now be described with reference to the accompanying drawings, wherein the same reference numerals are used throughout to refer to the same elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the claimed subject matter. However, it may be apparent that the claimed subject matter can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate the description of the claimed subject matter.

[0027] It should be understood that the following description of the embodiments should not be viewed in a limiting sense. The scope of this disclosure is not intended to be limited by the embodiments described below or by the drawings, which are to be regarded as illustrative only. The drawings are to be regarded as schematic representations, and the elements illustrated in the drawings are not necessarily shown to scale. Rather, various elements are shown so that their function and general purpose will become apparent to those skilled in the art.

[0028] All numerical values ​​in the detailed description herein and in the claims are modified by values ​​indicated by “about” or “approximately”, and take into account experimental errors and variations that would be expected by a person of ordinary knowledge in the art.

[0029] The terms “above” and / or “cover” are not to be interpreted as simply “directly above” and / or “having direct contact with”. Rather, if one element is “above” and / or “covers” another element (e.g., one zone covers another zone), then a further element (e.g., a further zone) may be located between the two elements (e.g., if the first zone is “above” and / or “covers” the second zone, then a further zone may be located between the first and second zones). Furthermore, if the first element is “above” and / or “covers” the second element, then at least some of the first elements may be vertically aligned with the second element such that a vertical line may intersect the first and second elements.

[0030] The semiconductor substrate or body may extend along a main extension plane. The term "horizontal" as used herein is intended to describe an orientation substantially parallel to the main extension plane. A first side or main horizontal side of the semiconductor substrate or body may extend substantially parallel to the horizontal direction, or may have a surface portion that surrounds the main extension plane at an angle of up to 8° (or up to 6°). The first or main horizontal side may be, for example, the surface of a wafer or die. Sometimes, the horizontal direction is also referred to as the lateral direction.

[0031] As used in this specification, the term "vertical" is intended to describe an orientation that is substantially perpendicular to the horizontal direction (e.g., parallel to the normal direction of a first side of the semiconductor substrate or body, or parallel to the normal direction of a surface segment of the first side of the semiconductor substrate or body).

[0032] A semiconductor device is provided. The semiconductor device may include a three-terminal device, such as a transistor and / or a thyristor. Alternatively and / or additionally, the semiconductor device may include a device having more than three terminals. The semiconductor device may include a control terminal (e.g., a gate), a first power terminal (e.g., a source terminal and / or an emitter terminal), and / or a second power terminal (e.g., a drain terminal and / or a collector terminal).

[0033] Semiconductor devices may enter a failure state. A failure state may correspond to a high current level flowing through the semiconductor device. Alternatively and / or additionally, a failure state may correspond to a high temperature of the semiconductor device. For example, a failure state may correspond to a semiconductor device having a short circuit between a first power terminal and a second power terminal, which may result in a high current level and / or a high temperature. A failure state of a semiconductor device may cause and / or result in damage to the semiconductor device and / or damage to one or more components surrounding the semiconductor device. For example, a semiconductor device may explode and / or generate an electric arc as a result of a high current level and / or a high temperature. Alternatively and / or additionally, a high current level and / or a high temperature may cause the bonding wiring to melt.

[0034] Semiconductor devices may have a short-circuit withstand time window, such as greater than and / or equal to 1 μs. For example, when a semiconductor device enters a failure state, it may cause damage and / or destruction after the period corresponding to the short-circuit withstand time window. Therefore, to prevent damage to one or more components, the semiconductor device may be turned off and / or shut down within the short-circuit withstand time window.

[0035] According to this disclosure, a semiconductor device is provided, comprising: a control region including control terminals; a first power region including first power terminals; a second power region including second power terminals; an isolation region between the control region and the first power region; and / or a failure structure extending from the first power region through the isolation region to the control region. The failure structure can be configured to form a low-resistance connection between the control region and the first power region during a failure state of the semiconductor device. Therefore, the semiconductor device can be turned off and / or shut down before causing damage to one or more surrounding components.

[0036] In embodiments of the currently disclosed embodiments, a semiconductor device is provided. The semiconductor device may include three-terminal devices, such as transistors and / or thyristors. Alternatively and / or additionally, the semiconductor device may include devices having more than three terminals. In some examples, the semiconductor device may include field-effect transistors (FETs), metal-oxide-semiconductor FETs (MOSFETs), metal-insulator-semiconductor FETs (MISFETs), metal-semiconductor FETs (MESFETs), insulated-gate FETs (IGFETs), insulated-gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), heterostructure FETs (HFETs), and / or modulation-doped FETs (MODFETs). Alternatively and / or additionally, the semiconductor device may include transistors of types not listed herein.

[0037] The semiconductor device may include: a control region including control terminals; a first power region including first power terminals; a second power region including second power terminals; an isolation region between the control region and the first power region; and / or a short-circuit structure extending from the first power region through the isolation region to the control region. The short-circuit structure may be configured to form a low-resistance connection between the control region and the first power region during a failure state of the semiconductor device.

[0038] A failure state may correspond to a high current level flowing through the semiconductor device (e.g., between a first power region and a second power region). A high current level may correspond to a current level exceeding the rated current of the semiconductor device (e.g., a high current level may exceed the rated current according to a threshold). Alternatively and / or additionally, a failure state may correspond to a high temperature at least a portion of the semiconductor device. High temperatures and / or high current levels may contribute to the explosion of the semiconductor device and / or damage to one or more components surrounding the semiconductor device.

[0039] A failure state can correspond to a semiconductor device having a short circuit between a first power terminal and a second power terminal. A short circuit can lead to high current levels and / or high temperatures. For example, a semiconductor device may enter a failure state in response to a short circuit occurring between the first and second power terminals.

[0040] In some examples, a low-resistance connection can correspond to a short circuit between the control region and the first power region. The semiconductor device can be turned off in response to the formation of the low-resistance connection. Current flow through the semiconductor device (e.g., current flow between the first and second power regions) can be mitigated (e.g., blocked and / or suppressed) by the semiconductor device in response to the formation of the low-resistance connection. The temperature of the semiconductor device can be reduced in response to the formation of the low-resistance connection. Therefore, the formation of a low-resistance connection can prevent the semiconductor device from exploding and / or from damaging one or more surrounding components.

[0041] In some examples, the first electric region includes a first portion adjacent to the short-circuit structure. A failure state of the semiconductor device may correspond to a temperature exceeding a first melting point of the first portion of the first electric region (e.g., between 500°C and 800°C and / or between 900°C and 1200°C). During a failure state of the semiconductor device, the material of the first portion of the first electric region melts to form a low-resistance connection.

[0042] In some examples, the failure state of a semiconductor device can correspond to a temperature exceeding the melting point of the short-circuit structure. During the failure state of the semiconductor device, the material of the short-circuit structure melts to form a low-resistance connection.

[0043] The short-circuit structure may include a transition structure extending from the first electric field region to the control region. In some examples, the transition structure includes a gap, a capillary, and / or a cavity (e.g., a hollow cavity).

[0044] In some examples, during the failure state of a semiconductor device, molten material in the first electric region passes through a transition structure and contacts the control region to form a low-resistance connection.

[0045] A semiconductor device may include a dielectric structure surrounding a portion of a first electric region. The dielectric structure may define an opening between the first electric region and a transition structure. During a failure state of the semiconductor device, molten material in the first electric region (e.g., molten material in a portion of the first electric region) can pass through the opening and the transition structure. The molten material can contact a control region to form a low-resistance connection.

[0046] The first electric field region may include a first portion and a second portion. The semiconductor device may include a dielectric structure surrounding at least some of the first portion of the first electric field region. A portion of an isolation region may be located between the first portion and the second portion of the first electric field region. The first portion of the first electric field region may be located between the second portion of the first electric field region and a transition structure. During a failure state of the semiconductor device, molten material from the first portion of the first electric field region may pass through the transition structure and contact the control region to form a low-resistance connection.

[0047] In some examples, the first material of the first portion of the first electric region may be the same as the second material of the second portion of the first electric region. In some examples, the first material and / or the second material may include aluminum and / or copper.

[0048] Alternatively and / or additionally, the first material may be different from the second material. For example, the first material may include aluminum. The second material may include copper.

[0049] Alternatively and / or additionally, the first and / or second materials may include germanium, (III) manganese oxide (Mn2O3), (II) nickel oxide (NiO), (III) cobalt oxide (Co2O3), (I) copper oxide (Cu2O), (III) iron oxide (Fe2O3), titanium dioxide (TiO2), aluminum oxide (Al2O3), beryllium oxide (BeO), magnesium oxide (MgO), zirconium dioxide (ZrO2), yttrium oxide (Y2O3), dysprosium oxide (Dy2O3), and / or germanium telluride (GeTe).

[0050] In some examples, the first melting point of the first material (e.g., between 500°C and 800°C) may be less than the second melting point of the second material (e.g., between 900°C and 1200°C). During the failure state, the temperature of the first electric region may exceed the first melting point and / or the temperature may not exceed the second melting point. Therefore, during the failure state, only a first portion of the first electric region may melt. Alternatively and / or additionally, the temperature of the first electric region may exceed both the first and second melting points. Therefore, both the first and second portions of the first electric region may melt during the failure state.

[0051] In some examples, the first electric region includes a first portion and a second portion. The first material (e.g., aluminum) of the first portion of the first electric region may be different from the second material (e.g., copper) of the second portion of the first electric region. The first portion of the first electric region may be located between the second portion of the first electric region and a transition structure. During a failure state of the semiconductor device, the molten material of the first portion of the first electric region passes through the transition structure and contacts the control region to form a low-resistance connection. In some examples, the first melting point of the first material (e.g., between 500°C and 800°C) is lower than the second melting point of the second material (e.g., between 900°C and 1200°C).

[0052] In some examples, the first electric region includes a first portion and a second portion. The first melting point of the first portion of the first electric region (e.g., between 500°C and 800°C) may be less than the second melting point of the second portion of the first electric region (e.g., between 900°C and 1200°C). The first portion of the first electric region may be located between the second portion of the first electric region and a transition structure. During a failure state of the semiconductor device, the molten material of the first portion of the first electric region passes through the transition structure and contacts the control region to form a low-resistance connection. In some examples, the first portion of the first electric region comprises aluminum and / or the second portion of the first electric region comprises copper.

[0053] In some examples, the semiconductor device includes a semiconductor substrate. An isolation region may cover the semiconductor substrate. The semiconductor substrate may include silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), and / or gallium(II) oxide (Ga2O3). Alternatively and / or additionally, the semiconductor substrate may include different materials, such as silicon.

[0054] The semiconductor substrate may have a band gap greater than 1.1 electron volts (eV). Alternatively and / or additionally, the semiconductor substrate may have a wide band gap (e.g., a band gap greater than 2 eV).

[0055] In the example, the semiconductor substrate may include SiC. The semiconductor substrate may include SiC in crystalline form. The semiconductor substrate may include a single SiC polytype (e.g., one of 4H-SiC polytype, 2H-SiC polytype, 6H-SiC polytype, etc.). Alternatively and / or additionally, the semiconductor substrate may include multiple SiC polytypes. The semiconductor substrate may include impurities and / or dopants at levels associated with fabrication tolerances.

[0056] In some examples, the control terminal includes a gate terminal. The first power terminal may include a source terminal and / or an emitter terminal. The second power terminal may include a drain terminal and / or a collector terminal.

[0057] In embodiments of the currently disclosed embodiments, a semiconductor device is provided. The semiconductor device may include: a semiconductor substrate comprising SiC; a control region including control terminals; a first power region including first power terminals; a second power region including second power terminals; an isolation region between the control region and the first power region; and / or a failure structure extending from the first power region through the isolation region to the control region. The isolation region may cover the semiconductor substrate. The failure structure may be configured to alter the properties of at least some materials between the control region and the first power region during a failure state of the semiconductor device.

[0058] In some examples, the characteristic can correspond to resistance. For instance, a failure structure can be configured to change the resistance between the control region and the first power region.

[0059] During the normal operation of a semiconductor device, the first temperature of the failed structure can be lower than the second temperature of the failed structure during the failed state. The first resistance of the failed structure during the normal operation can be higher than the second resistance of the failed structure during the failed state.

[0060] The normal state can correspond to the state of a semiconductor device before it enters a failure state.

[0061] In some examples, the material of the failed structure may have one or more properties (e.g., composition and / or one or more chemical properties) associated with the following: the material's electrical resistance decreases with increasing material temperature. The material may be connected to a control region and a first power region. In the example, the failed material has a negative temperature coefficient (NTC). In the example, the failed material may include one or more small bandgap materials, such as germanium. Alternatively and / or additionally, the failed material may include one or more metal oxide compositions, such as Mn₂O₃, NiO, Co₂O₃, Cu₂O, Fe₂O₃, TiO₂, Al₂O₃, BeO, MgO, ZrO₂, Y₂O₃, and / or Dy₂O₃. Alternatively and / or additionally, the failed material may include one or more phase change memory materials, such as GeTe.

[0062] A failure structure that changes from a first resistor to a second resistor can cause a reduction in the current flow through the semiconductor device (e.g., the current flow between the first and second power regions) and / or a decrease in the temperature of the semiconductor device. Therefore, damage to the semiconductor device and / or damage to one or more surrounding components can be prevented.

[0063] A failure structure with a second resistance can correspond to a low-resistance connection (and / or short circuit) between the control area and the first power area.

[0064] In embodiments of the currently disclosed embodiments, a semiconductor device is provided. The semiconductor device may include: a semiconductor substrate comprising SiC; a control region including control terminals; a first power region including a first power terminal; a second power region including a second power terminal; an isolation region between the control region and the first power region; a transition structure extending from the first power region through the isolation region to the control region; and / or a dielectric structure surrounding a portion of the first power region. The isolation region may cover the semiconductor substrate. The dielectric structure may define an opening between the first power region and the transition structure.

[0065] Figures 1A to 1F The illustrations depict various aspects of an exemplary embodiment of the semiconductor device 100. Figure 1A The illustration shows a portion of a semiconductor device 100. The semiconductor device 100 may include a first power region 102, and the first power region 102 includes a first power terminal. The first power terminal is located in... Figure 1A Not shown in the diagram. A first power terminal may be coupled to a first external circuit (e.g., a power source, a load of semiconductor device 100, and / or ground). The first power terminal may include a source terminal and / or an emitter terminal. One or more source structures and / or one or more emitter structures of one or more cells of semiconductor device 100 may be electrically connected to the first external circuit via a first power region 102 (e.g., a source bus structure and / or an emitter bus structure).

[0066] The semiconductor device 100 may include a control region 106, and the control region 106 includes control terminals. The control terminals are located in... Figure 1A Not shown. Control terminals may be coupled to a second external circuit (e.g., a controller and / or gate driver configured to control semiconductor device 100). Control terminals may include gate terminals. One or more gate structures of one or more cells of semiconductor device 100 may be electrically connected to the second external circuit via control region 106 (e.g., gate channel structure).

[0067] Semiconductor device 100 may include an isolation region 104 between a first power region 102 and a control region 106. The isolation region 104 may insulate the first power region 102 from the control region 106. The isolation region 104 may include a first dielectric material, such as borosilicate glass (BPSG), silicon phosphate glass (PSG), silicon dioxide (SiO2), and / or silicon oxynitride (SiON). In some examples, the first dielectric material may include a single type of dielectric material. Alternatively and / or additionally, the first dielectric material may include multiple types of dielectric materials (e.g., a stack of different dielectric materials).

[0068] Semiconductor device 100 may include in Figures 1B to 1D The diagram shows an isolation layer 114. Isolation layer 114 may cover the first power zone 102, control zone 106, and / or isolation zone 104. Isolation layer 114 may include a second dielectric material. The second dielectric material may be the same as the first dielectric material of isolation zone 104. Alternatively and / or additionally, the second dielectric material may be different from the first dielectric material.

[0069] Semiconductor device 100 may include a failure structure 108. The failure structure 108 may extend from the first power region 102 through the isolation region 104 to the control region 106.

[0070] Figure 1B The illustration is in Figure 1A The first electric field region 102 may cover region 118 and / or cell region 120 of the semiconductor device 100. Region 118 may include conductive material. Cell region 120 may include active cells, such as transistor cells (e.g., FET cells, MOSFET cells, MISFET cells, MESFET cells, IGFET cells, IGBT cells, HEMT cells, HFET cells, and / or MODFET cells). Region 118 may be located between the first electric field region 102 and cell region 120.

[0071] Semiconductor device 100 may include a base isolation region 116. Control region 106 and / or isolation region 104 may cover base isolation region 116. Base isolation region 116 may include a third dielectric material. The third dielectric material may be the same as the first dielectric material and / or the second dielectric material. Alternatively and / or additionally, the third dielectric material may be different from the first dielectric material and / or the second dielectric material.

[0072] Semiconductor device 100 may include semiconductor substrate 122 (e.g., semiconductor body). Isolation layer 114, first power region 102, base isolation region 116, isolation region 104 and / or region 118 may cover semiconductor substrate 122.

[0073] Semiconductor device 100 may include a second power region 124, and the second power region 124 includes a second power terminal. The second power terminal is not located in... Figure 1B As shown in the diagram. The second power terminal can be coupled to a third external circuit (e.g., a power source, a load of the semiconductor device 100, and / or ground). The second power terminal may include a drain terminal and / or a collector terminal. The semiconductor substrate 122 may be located between the base isolation region 116 and the second power region 124.

[0074] Figure 1C The illustration is in Figure 1A The cross-section BB of the semiconductor device 100 is defined in the middle. The failure structure 108 may cover the second base isolation region 128. The second base isolation region 128 may include a fourth dielectric material. The fourth dielectric material may be the same as the third dielectric material. Alternatively and / or additionally, the fourth dielectric material may be different from the third dielectric material. The second base isolation region 128 may be an extension of the base isolation region 116. Alternatively and / or additionally, the second base isolation region 128 may be separated from the base isolation region 116.

[0075] In some examples, the failure structure 108 may be configured to alter the properties of at least some materials between the control region 106 and the first power region 102 during a failure state of the semiconductor device 100. In some examples, the properties may correspond to resistance. A first temperature of the failure structure 108 during a normal state of the semiconductor device 100 may be lower than a second temperature of the failure structure 108 during the failure state. The normal state may correspond to the state of the semiconductor device 100 before it enters the failure state. A first resistance of the failure structure 108 during the normal state may be higher than a second resistance of the failure structure 108 during the failure state. In some examples, the failure material of the failure structure 108 may have one or more properties (e.g., composition and / or one or more chemical properties) associated with a decrease in resistance of the failure material as the temperature of the failure material increases. The failure material may be connected to the control region 106 and the first power region 102. In an example, the failure material has an NTC resistance.

[0076] Alternatively and / or additionally, failure structure 108 may include a short-circuit structure. The short-circuit structure may be configured to form a low-resistance connection between control region 106 and first power region 102 during a failure state.

[0077] For example, the short-circuit structure may include a transition structure extending from the first power region 102 to the control region 106. The transition structure may include a gap, a capillary, and / or a cavity (e.g., a hollow cavity). In some examples, the transition structure may include air, a process gas, and / or other substances.

[0078] Figure 1D The illustration is in Figure 1A The cross-section BB of the semiconductor device 100 during the failure state is defined in the middle. Figure 1D The illustrated semiconductor device 100 includes an embodiment of a failure structure 108 comprising a transition structure extending from a first power region 102 to a control region 106.

[0079] During the failure state, the temperature of the first electric region 102 may exceed its melting point. At least a portion of the first electric region 102 may melt during the failure state. The molten material 102M of the first electric region 102 may pass through the transition structure and contact the control region 106 to form a low-resistance connection. The molten material 102M of the first electric region 102 may flow through the transition structure via capillary action (e.g., capillary action and / or capillary effect). Alternatively and / or additionally, the material of the first electric region 102 may expand with melting and / or temperature increases (e.g., the material may expand in relation to its coefficient of thermal expansion). The expansion of the material may cause at least some of the material (e.g., the molten material 102M) to pass through (and / or flow through) the transition structure to form a low-resistance connection.

[0080] Alternatively and / or additionally, the temperature of control region 106 may exceed its melting point during the failure state (e.g., between 500°C and 800°C and / or between 900°C and 1200°C). At least a portion of control region 106 may melt during the failure state. The molten material of control region 106 may pass through a transition structure and contact the first electrical region 102 to form a low-resistance connection.

[0081] A low-resistance connection can correspond to a short circuit between control region 106 and first power region 102. Semiconductor device 100 can be turned off in response to the formation of a low-resistance connection. Current flow through semiconductor device 100 (e.g., current flow between first power region 102 and second power region 124) can be mitigated by semiconductor device 100 in response to the formation of a low-resistance connection. The temperature of semiconductor device 100 can be reduced in response to the formation of a low-resistance connection. Semiconductor device 100 can be able to block voltage, such as voltage exceeding a threshold, between the first power terminal and the second power terminal in response to the formation of a low-resistance connection.

[0082] Semiconductor device 100 may include a second failure structure 108A. The second failure structure 108A may be located on the opposite side of the control region 106 with respect to failure structure 108. Similar to failure structure 108, the second failure structure 108A may be configured to alter the properties of at least some materials between the control region 106 and the first power region 102 during a failure state, and / or failure structure 108 may include a second short-circuit structure configured to form part of a low-resistance connection during a failure state and / or form a second low-resistance connection between the control region 106 and the first power region 102.

[0083] Figure 1E An exemplary embodiment of the semiconductor device 100 is illustrated, wherein a first power region 102 includes a first portion 102A and a second portion 102B. The first portion 102A may be adjacent to a failed structure 108. The first portion 102A may be located between the failed structure 108 and the second portion 102B. A first material (e.g., aluminum) of the first portion 102A may be different from a second material (e.g., copper) of the second portion 102B. Alternatively and / or additionally, the first material may be the same as the second material. A first melting point of the first portion 102A (e.g., between 500°C and 800°C) may be less than a second melting point of the second portion 102B (e.g., between 900°C and 1200°C). During a failure state, the material of the first portion 102A may melt before the material of the second portion 102B melts. Alternatively and / or additionally, the material of the first portion 102A may melt during a failure state and / or the material of the second portion 102B may not melt during a failure state. The molten material of the first part 102A can pass through the failure structure 108 (e.g., a transition structure) and the contact control region 106 to form a low-resistance connection.

[0084] Figure 1F The illustration is in Figure 1AThe semiconductor device 100 defined herein includes a cross-section BB of an exemplary embodiment of a short-circuit structure configured to form a low-resistance connection during a failure state. The short-circuit structure may include multiple regions, such as a first region 140, a second region 142, and / or a third region 144. In some examples, one or more of the multiple regions may include a material and / or one or more other regions may include one or more voids. In an example, the first region 140 may include a first void, the second region 142 may include a material, and / or the third region 144 may include a second void. The material of the second region 142 (e.g., aluminum) may be different from the second material (e.g., copper) of the first region 102. Alternatively and / or additionally, the material may be the same as the second material. The melting point of the material (e.g., between 500°C and 800°C) may be less than the melting point of the second material (e.g., between 900°C and 1200°C). Alternatively and / or additionally, the melting point of the material may not be less than the melting point of the second material. During the failure state, the temperature of the material may exceed its melting point. During the failure state, at least some material may melt. The melted material in the second zone 142 can pass through the first zone 140 and / or the third zone 144. The melted material can contact the control zone 106 and the first power zone 102 to form a low-resistance connection.

[0085] Figures 2A to 2F The illustrations depict various aspects of an exemplary embodiment of the semiconductor device 200. Figure 2A The diagram illustrates a portion of a semiconductor device 200. The semiconductor device 200 may include a first power region 102. The semiconductor device 200 may include a control region 106. The semiconductor device 200 may include an isolation region 104 between the first power region 102 and the control region 106. The semiconductor device 200 may include... Figures 2B to 2E The diagram shows isolation layer 114. Isolation layer 114 may cover the first power zone 102, control zone 106, and / or isolation zone 104.

[0086] Semiconductor device 200 may include a failure structure 208. The failure structure 208 may extend from the first power region 102 through the isolation region 104 to the control region 106. The failure structure 208 may be adjacent to an endpoint of the control region 106. Alternatively and / or additionally, the failure structure 208 may partially surround a portion of the control region 106 at an endpoint of the control region 106. For example, the failure structure 208 may be adjacent to a first side of the control region 106 corresponding to an endpoint of the control region 106, a portion of a second side of the control region 106, and / or a portion of a third side of the control region 106. The third side of the control region 106 may be opposite to the second side of the control region 106.

[0087] Figure 2B The illustration is in Figure 2AThe semiconductor device 200 is defined by a cross-section CC. The semiconductor device 200 may include region 118 and / or cell region 120. The semiconductor device 200 may include a base isolation region 116. Control region 106, isolation region 104 and / or failure structure 208 may cover base isolation region 116.

[0088] Semiconductor device 200 may include semiconductor substrate 122. Isolation layer 114, first power region 102, base isolation region 116, isolation region 104, and / or region 118 may cover semiconductor substrate 122. Semiconductor device 200 may include second power region 124. Semiconductor substrate 122 may be located between base isolation region 116 and second power region 124.

[0089] As in Figure 2B As shown, the first portion of the failure structure 208 may be adjacent to the second side of the control region 106, and / or the second portion of the failure structure 208 may be adjacent to the third side of the control region 106.

[0090] Figure 2C The illustration is in Figure 2A The cross-section DD of the semiconductor device 200 is defined in the middle. (As in...) Figure 2C As shown, the third portion of the failure structure 208 may be adjacent to the first side of the control region 106 corresponding to the endpoint of the control region 106.

[0091] In some examples, the failure structure 208 may be configured to alter the properties of at least some materials between the control region 106 and the first power region 102 during a failure state of the semiconductor device 200. In some examples, the properties may correspond to resistance. A first temperature of the failure structure 208 during a normal state of the semiconductor device 200 may be lower than a second temperature of the failure structure 208 during the failure state. The normal state may correspond to the state of the semiconductor device 200 before it enters the failure state. A first resistance of the failure structure 208 during the normal state may be higher than the second resistance of the failure structure 208 during the failure state. In some examples, the failure material of the failure structure 208 may have one or more properties (e.g., composition and / or one or more chemical properties) associated with a decrease in resistance of the failure material as the temperature of the failure material increases. The failure material may be connected to the control region 106 and the first power region 102. In an example, the failure material has an NTC resistance.

[0092] Alternatively and / or additionally, failure structure 208 may include a short-circuit structure. The short-circuit structure may be configured to form a low-resistance connection between control region 106 and first power region 102 during a failure state.

[0093] For example, the short-circuit structure may include a transition structure extending from the first power region 102 to the control region 106. The transition structure may include a gap, a capillary, and / or a cavity (e.g., a hollow cavity). In some examples, the transition structure may include air, a process gas, and / or other substances.

[0094] Figure 2D The illustration is in Figure 2A The cross-section CC of the semiconductor device 200 during the failure state. Figure 2E The illustration is in Figure 2A The cross-section DD of the semiconductor device 200 in the failure state. Figures 2D to 2E The illustrated semiconductor device 200 includes an embodiment of a failure structure 208 that includes a transition structure extending from a first power region 102 to a control region 106.

[0095] During the failure state, the temperature of the first electric region 102 may exceed its melting point. At least a portion of the first electric region 102 may melt during the failure state. The molten material 102M of the first electric region 102 may pass through the transition structure and contact the control region 106 to form a low-resistance connection. The molten material 102M of the first electric region 102 may flow through the transition structure via capillary action. Alternatively and / or additionally, the material of the first electric region 102 may expand with the melting and / or increase in temperature. The expansion of the material may cause at least some material (e.g., the molten material 102M) to pass through (and / or flow through) the transition structure to form a low-resistance connection. The low-resistance connection may correspond to a short circuit between the control region 106 and the first electric region 102. The semiconductor device 200 may be turned off in response to the formation of the low-resistance connection. Current flow through the semiconductor device 200 (e.g., current flow between the first electric region 102 and the second electric region 124) may be mitigated by the semiconductor device 200 in response to the formation of the low-resistance connection. The temperature of the semiconductor device 200 can be reduced in response to the formation of a low-resistance connection.

[0096] Alternatively and / or additionally, the temperature of control region 106 may exceed its melting point during the failure state. At least a portion of control region 106 may melt during the failure state. The molten material of control region 106 may pass through a transition structure and contact the first electrical region 102 to form a low-resistance connection.

[0097] Figure 2FAn exemplary embodiment of the semiconductor device 200 is illustrated, wherein a first power region 102 includes a first portion 102A and a second portion 102B. The first portion 102A may be adjacent to a failure structure 208. The first portion 102A may be between the failure structure 208 and the second portion 102B. Molten material of the first portion 102A may pass through the failure structure 208 (e.g., a transition structure) and contact the control region 106 to form a low-resistance connection.

[0098] Figures 3A to 3C The illustrations depict various aspects of an exemplary embodiment of the semiconductor device 300. Figure 3A The illustration shows a portion of a semiconductor device 300. The semiconductor device 300 may include a first power region 102, which includes a first portion 102C and / or a second portion 102D. The semiconductor device 300 may include a control region 106. The semiconductor device 300 may include an isolation region 104 between the second portion 102D and the control region 106. The semiconductor device 300 may include... Figures 3B to 3C The diagram shows isolation layer 114. Isolation layer 114 may cover the first power zone 102, control zone 106, and / or isolation zone 104.

[0099] In some examples, semiconductor device 300 may include a failure structure 308. Failure structure 308 may extend from the first portion 102C through isolation region 104 to control region 106. Failure structure 308 may be adjacent to an endpoint of control region 106. Alternatively and / or additionally, failure structure 308 may partially surround a portion of control region 106 at an endpoint of control region 106. For example, failure structure 308 may be adjacent to a first side of control region 106 corresponding to an endpoint of control region 106, a portion of a second side of control region 106, and / or a portion of a third side of control region 106 (similar to...). Figure 2A (Exemplary embodiment illustrated in the figure). The third side of the control region 106 may be opposite to the second side of the control region 106. Alternatively and / or additionally, the failure structure 308 may be adjacent to the first side of the control region 106 corresponding to an endpoint and / or may not be adjacent to the second and / or third side of the control region 106.

[0100] Semiconductor device 300 may include at least some dielectric structures 330 surrounding a first portion 102C. A portion of isolation region 104 may be between the first portion 102C and the second portion 102D. In some examples, dielectric structure 330 may define a first opening on a first side 332 of dielectric structure 330 between the first portion 102C and the second portion 102D. Dielectric structure 330 may define a second opening on a second side 334 of dielectric structure 330 between the first portion 102C and the failure structure 308.

[0101] Figure 3B The illustration is in Figure 3A The semiconductor device 300 is defined in the cross-section EE. The semiconductor device 300 may include region 118 and / or cell region 120. The semiconductor device 300 may include a base isolation region 116. Control region 106, isolation region 104, first portion 102C, and / or failure structure 308 may cover the base isolation region 116. In some examples, dielectric structure 330 may include at least some isolation regions 104, at least some isolation layers 114, and / or at least some base isolation regions 116 surrounding the first portion 102C.

[0102] Semiconductor device 300 may include a semiconductor substrate 122. An isolation layer 114, a first power region 102, a base isolation region 116, an isolation region 104, and / or a region 118 may cover the semiconductor substrate 122. Semiconductor device 300 may include a second power region 124. The semiconductor substrate 122 may be located between the base isolation region 116 and the second power region 124. In some examples, semiconductor device 300 may include a p-well 336.

[0103] In some examples, the failure structure 308 may be configured to alter the properties of at least some materials between the control region 106 and the first portion 102C during a failure state of the semiconductor device 300. In some examples, the properties may correspond to resistance. A first temperature of the failure structure 308 during a normal state of the semiconductor device 300 may be lower than a second temperature of the failure structure 308 during the failure state. The normal state may correspond to the state of the semiconductor device 300 before it enters the failure state. A first resistance of the failure structure 308 during the normal state may be higher than a second resistance of the failure structure 308 during the failure state. In some examples, the failure material of the failure structure 308 may have one or more properties (e.g., composition and / or one or more chemical properties) associated with a decrease in resistance of the failure material as the temperature of the failure material increases. The failure material may be connected (via a second opening) to the first portion 102C and to the control region 106. In an example, the failure material has an NTC resistance.

[0104] Alternatively and / or additionally, failure structure 308 may include a short-circuit structure. The short-circuit structure may be configured to form a low-resistance connection between control region 106 and first power region 102 during a failure state.

[0105] For example, the short-circuit structure may include a transition structure extending from the first portion 102C to the control region 106. The transition structure may include a void, a capillary, and / or a cavity (e.g., a hollow cavity). In some examples, the transition structure may include air, a process gas, and / or other substances.

[0106] Figure 3C The illustration is in Figure 3A The cross-section EE of the semiconductor device 300 during the failure state is defined in the middle. Figure 3C The illustrated semiconductor device 300 includes an embodiment of a failure structure 308 comprising a transition structure extending from a first portion 102C to a control region 106.

[0107] During the failure state, the temperature of the first portion 102C may exceed its melting point. At least a portion of the first portion 102C may melt during the failure state. The molten material 102M of the first portion 102C may contact the control region 106 through a transition structure and / or a second opening to form a low-resistance connection. The low-resistance connection may correspond to a short circuit between the control region 106 and the first power region 102. The semiconductor device 300 may be turned off in response to the formation of the low-resistance connection. Current flow through the semiconductor device 300 (e.g., current flow between the first power region 102 and the second power region 124) may be mitigated by the semiconductor device 300 in response to the formation of the low-resistance connection. The temperature of the semiconductor device 300 may be reduced in response to the formation of the low-resistance connection.

[0108] The molten material 102M of the first part 102C can flow through the transition structure via capillary action (e.g., capillary action and / or capillary effect). Alternatively and / or additionally, the material of the first part 102C can expand as the material melts and / or the temperature increases. The expansion of the material can cause at least some material (e.g., molten material 102M) to pass through (and / or flow through) the transition structure to form a low-resistance connection.

[0109] In some examples, the size (e.g., volume) of the dielectric structure 330 and / or the size (e.g., volume) of the transition structure can be configured such that expansion of the material within the dielectric structure 330 causes the material (e.g., molten material 102M) to at least partially fill the transition structure and / or the contact control region 106. For example, the size of the dielectric structure 330 and / or the size of the transition structure can be configured based on the coefficient of thermal expansion of the first portion 102C within the dielectric structure 330. For example, the coefficient of thermal expansion of the first portion 102C can be determined to correspond to a first percentage increase in volume of the first portion 102C in response to the semiconductor device 300 entering a failure state. The size of the transition structure can be determined based on the first percentage and / or the volume of the first portion 102C (and / or the volume of the dielectric structure 330). Alternatively and / or additionally, the volume of the transition structure can be determined based on the amount of increase in volume of the first portion 102C in response to the semiconductor device 300 entering a failure state (e.g., the amount of increase in volume of the first portion 102C can correspond to the first percentage multiplied by the volume of the first portion 102C). For example, the volume of the transition structure can be approximately equal to the increase in volume of the first portion 102C. Alternatively and / or additionally, the volume of the transition structure can be less than the increase in volume of the first portion 102C. Alternatively and / or additionally, the volume of the transition structure can be greater than the increase in volume of the first portion 102C.

[0110] In relation to Figure 3A In the example, it can be determined (based on the coefficient of thermal expansion of the first portion 102C within the dielectric structure 330) that the transition structure area of ​​the transition structure is approximately 10% (and / or a different percentage) of the dielectric structure area of ​​the dielectric structure 330, which can cause the material to at least partially fill the transition structure and / or contact control region 106 when the material melts and / or expands during the failure state. The dimensions a, b, and / or h associated with the dielectric structure area (in...) Figure 3A (as shown in) and / or the dimensions e and / or b (as shown in) associated with the area of ​​the transition structure. Figure 3A(As shown in the diagram) can be configured such that the area of ​​the transition structure is approximately 10% of the area of ​​the dielectric structure. In some examples, a corresponds to the length of the first side 332 of the dielectric structure 330, b corresponds to the length of the second side 334 of the dielectric structure 330, h corresponds to the distance between the first side 332 and the second side 334 of the dielectric structure 330, b corresponds to the length of the first side of the transition structure adjacent to the second side 334 of the dielectric structure 330, and / or e corresponds to the length of the second side of the transition structure. For example, the area of ​​the dielectric structure can be equal to h(a+b) / 2 and / or the area of ​​the transition structure can be equal to e×b. Dimensions a, b, h, and / or e can be determined based on 10%×h(a+b) / 2=e×b. In the example, e=10μm, b=20μm, h=50μm, and / or a=60μm.

[0111] In some examples, at least some materials of the first part 102C may be different from at least some materials of the second part 102D. For example, at least some materials of the first part 102C may include aluminum and / or at least some materials of the second part 102D may include copper. Alternatively and / or additionally, the materials of the first part 102C may be the same as the materials of the second part 102D. The first melting point of at least some of the first part 102C may be lower than the second melting point of at least some of the second part 102D. During the failure state, at least some materials of the first part 102C may melt before at least some materials of the second part 102D melt. Alternatively and / or additionally, at least some materials of the first part 102C may melt during the failure state and / or at least some materials of the second part 102D may not melt during the failure state.

[0112] Figure 4The diagram illustrates a line graph 400 associated with the operation of an exemplary semiconductor device. The exemplary semiconductor device may include a control terminal (e.g., a gate terminal), a first power terminal (e.g., a source terminal and / or an emitter terminal), and / or a second power terminal (e.g., a drain terminal and / or a collector terminal). Line graph 400 includes a current curve 402, a power voltage curve 404, a control voltage curve 406, and an energy curve 408. The horizontal axis of line graph 400 may correspond to time. The vertical axis of current curve 402 may correspond to the current level in amperes flowing through the second power terminal (and / or flowing through the exemplary semiconductor device). The vertical axis of power voltage curve 404 may correspond to the voltage level in volts between the first and second power terminals. The vertical axis of control voltage curve 406 may correspond to the voltage level in volts at the control terminal (e.g., the voltage between the control terminal and the first power terminal). The vertical axis of energy curve 408 may correspond to the energy level in joules dissipated by the exemplary semiconductor device. The energy level of energy curve 408 can be proportional to and / or correlated with the temperature of the exemplary semiconductor device.

[0113] The exemplary semiconductor device may enter a failure state at a first time 4001. For example, a short circuit between the first power terminal and the second power terminal may occur at the first time 4001. In response to the exemplary semiconductor device entering a failure state, the current level, energy level, and / or temperature of the exemplary semiconductor device may increase. At a second time 4003, a low-resistance connection is formed between the first power terminal and the control terminal using one or more techniques presented herein. By forming a low-resistance connection, the exemplary semiconductor device may be turned off and / or shut down before high current levels and / or high energy levels cause the exemplary semiconductor device to explode, generate an electric arc, and / or cause damage to one or more surrounding components.

[0114] Figure 5 The diagram illustrates a line graph 500 associated with the operation of an exemplary semiconductor device. The exemplary semiconductor device may include a control terminal (e.g., a gate terminal), a first power terminal (e.g., a source terminal and / or an emitter terminal), and / or a second power terminal (e.g., a drain terminal and / or a collector terminal). Line graph 500 includes a current curve 502, a control voltage curve 504, and a power voltage curve 506. The horizontal axis of line graph 500 may correspond to time. The vertical axis of current curve 502 may correspond to the current level in amperes flowing through the second power terminal (and / or flowing through the exemplary semiconductor device). The vertical axis of control voltage curve 504 may correspond to the voltage level in volts at the control terminal (e.g., the voltage between the control terminal and the first power terminal). The vertical axis of power voltage curve 506 may correspond to the voltage level in volts between the first power terminal and the second power terminal.

[0115] The exemplary semiconductor device may enter a failure state at a first time 5001. This failure state may correspond to a short-circuit pulse. During the short-circuit pulse, the current level, energy level, and / or temperature of the exemplary semiconductor device may increase. During the short-circuit pulse, at a second time 5003, a low-resistance connection is formed between the first power terminal and the control terminal using one or more techniques presented herein. By forming the low-resistance connection, the exemplary semiconductor device can be turned off and / or shut down before high current levels and / or high energy levels cause the exemplary semiconductor device to explode, generate an electric arc, and / or cause damage to one or more surrounding components. Alternatively and / or additionally, as shown in the power voltage curve 506, the exemplary semiconductor device may, after forming the low-resistance connection, block the voltage between the first power terminal and the second power terminal, such as during time period 5005.

[0116] Figure 6 The diagram illustrates a line graph 600 relating to the temperature distribution of an exemplary semiconductor device during a failure state. The exemplary semiconductor device may include: a control region including control terminals (e.g., a gate terminal); a first power region including first power terminals (e.g., a source terminal and / or an emitter terminal); and / or a second power region including second power terminals (e.g., a drain terminal and / or a collector terminal). Line graph 600 includes a temperature profile 602. The vertical axis of line graph 600 may correspond to a temperature level. The horizontal axis of line graph 600 may correspond to a distance from a first side of the exemplary semiconductor device. The first side of the exemplary semiconductor device may be close to the first power region and / or far from the second power region. For example, the first power region may be at a distance of 604 from the first side of the exemplary semiconductor device and / or the second power region may be at a distance of 608 from the first side of the exemplary semiconductor device. Alternatively and / or additionally, one or more components of the exemplary semiconductor device may be between a distance of 604 and a distance of 606 from the first side of the exemplary semiconductor device. The maximum temperature 610 of temperature profile 602 may correspond to a region of the exemplary semiconductor device. The distance between this zone and the first power zone can be less than the distance between this zone and the second power zone.

[0117] In some examples, the semiconductor substrate of the exemplary semiconductor device may include a first material. The first material may include SiC and / or various wide bandgap materials. In contrast to some implementations of semiconductor devices including other semiconductor materials, where the temperature of the first electric region may not exceed the melting point of the first electric region, the exemplary semiconductor device having the first material can cause a maximum temperature 610 and / or the temperature of the first electric region to exceed the melting point of the first electric region (and / or the melting point of a portion of the first electric region) during a failure state. For example, the maximum temperature 610 may be between 600°C and 1200°C. In examples where the exemplary semiconductor device includes a transition structure, the temperature of the first electric region may exceed the melting point of the first electric region and / or the molten material of the first electric region may be used through the transition structure to form a low-resistance connection between the first electric region and the control region. Unlike some implementations of semiconductor devices including other semiconductor materials, the exemplary semiconductor device having the first material can remain functional during a failure state (e.g., the exemplary semiconductor device can function at a maximum temperature 610). In some examples, in response to forming a low-resistance connection, the exemplary semiconductor device can mitigate current flow between the first electric region and the second electric region.

[0118] It will be understood that by applying one or more of the techniques described herein, such as by implementing a failure structure in a semiconductor device, the semiconductor device can be turned off within a reduced amount of time (e.g., within the short-circuit withstand time window of the semiconductor device) after entering a failure state. This can prevent the semiconductor device from exploding and / or generating an electric arc by the semiconductor device and / or can prevent damage to one or more surrounding components. Therefore, incorporating a failure structure into a semiconductor device can result in increased safety associated with the operation of the semiconductor device. Furthermore, implementing a failure structure in a semiconductor device can result in reduced manufacturing costs. For example, some implementations of semiconductor devices that do not include a failure structure as described herein may require more expensive alternatives to prevent damage to surrounding components, such as expensive gate drivers, short-circuit detection systems, desaturation detection circuits, current sensing systems, explosion-proof enclosures, etc.

[0119] It will be understood that combinations of one or more embodiments described herein (including combinations of embodiments described with respect to different figures) are contemplated.

[0120] Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing the claims.

[0121] Any aspect or design described herein as an "example" is not necessarily to be construed as advantageous over other aspects or designs. Rather, the use of the term "example" is intended to present one possible aspect and / or implementation that may relate to the technology presented herein. Such examples are not necessarily necessary for such technology or are not intended to be limiting. Various embodiments of such technology may include such examples, alone or in combination with other features, and / or the illustrated examples may be varied and / or omitted.

[0122] As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or explicitly stated from the context, "X adopts A or B" is intended to mean any natural inclusive substitution. That is, "X adopts A or B" is satisfied in any of the foregoing examples if X adopts A; X adopts B; or X adopts both A and B. Furthermore, unless otherwise specified or explicitly stated from the context that a singular form is involved, the quantifiers "a" and "an" as used in this application and the appended claims can generally be interpreted as meaning "one or more". Additionally, unless otherwise specified, "first", "second", etc., are not intended to imply temporal, spatial, or sequential aspects. Rather, such terms are used only as identifiers, names, etc., for features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B, or two different or two identical elements, or the same element.

[0123] Furthermore, while this disclosure has been shown and described with respect to one or more implementations, equivalent changes and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This disclosure includes all such modifications and changes and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the components described above (e.g., elements, resources, etc.), unless otherwise indicated, the terminology used to describe such components is intended to correspond to any component that performs the specified function of the described component (e.g., functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function of the example implementation of this disclosure illustrated herein. Moreover, while specific features of this disclosure may have been disclosed with respect to only one of several implementations, such features may be combined with one or more other features of other implementations, as may be desirable and advantageous for any given or particular application. Furthermore, the use of the terms “comprising,” “having,” “having,” “with,” or variations thereof in the detailed description or claims, in a manner similar to the term “comprising,” is intended to be inclusive.

[0124] While the subject matter has been described with reference to illustrative embodiments, this description is not intended to be construed as limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of this disclosure, will be apparent to those skilled in the art upon reference to the description. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. A semiconductor device, comprising: The control area includes control terminals; The first power zone includes a first power terminal; The second power zone includes a second power terminal; The isolation zone is located between the control zone and the first power zone; as well as A short-circuit structure extending from the first electric region through the isolation region to the control region, wherein the short-circuit structure is configured to form a low-resistance connection between the control region and the first electric region during a failure state of the semiconductor device.

2. The semiconductor device according to claim 1, wherein: The first power zone includes a first portion adjacent to the short-circuit structure; The failure state of a semiconductor device corresponds to the temperature of the first portion of the first electric region exceeding the first melting point of the first portion of the first electric region; as well as During the failure state of a semiconductor device, the material of a first portion of the first electric region melts to form a low-resistance connection between the control region and the first electric region.

3. The semiconductor device according to claim 1, wherein: The failure state of a semiconductor device corresponds to a short circuit between the first power region and the second power region.

4. The semiconductor device according to claim 1, wherein: The short-circuit structure includes the transition structure extending from the first power zone to the control zone.

5. The semiconductor device according to claim 4, wherein: During the failure state of a semiconductor device, the molten material in the first electric region passes through the transition structure and contacts the control region to form a low-resistance connection between the control region and the first electric region.

6. The semiconductor device according to claim 4, comprising: A dielectric structure, which surrounds a portion of the first electric region, wherein: The dielectric structure is defined by the opening between the first electric field region and the transition structure; and During the failure state of a semiconductor device, the molten material in the first electric region passes through the opening and transition structure and contacts the control region to form a low-resistance connection between the control region and the first electric region.

7. The semiconductor device according to claim 4, wherein, The first power zone comprises a first part and a second part, and the semiconductor devices include: Dielectric structures, which surround at least some of the first portions of the first electric region, wherein: A portion of the isolation zone lies between the first part of the first power zone and the second part of the first power zone; The first part of the first power zone lies between the second part of the first power zone and the transition structure; and During the failure state of the semiconductor device, the molten material of the first portion of the first electric region passes through the transition structure and contacts the control region to form a low-resistance connection between the control region and the first electric region.

8. The semiconductor device according to claim 7, wherein: The first material of the first part of the first power zone is the same as the second material of the second part of the first power zone.

9. The semiconductor device according to claim 7, wherein: The first material of the first part of the first power zone is different from the second material of the second part of the first power zone.

10. The semiconductor device according to claim 9, wherein: The first melting point of the first material is less than the second melting point of the second material.

11. The semiconductor device according to claim 4, wherein: The first power zone includes a first part and a second part, wherein the first material of the first part of the first power zone is different from the second material of the second part of the first power zone; The first part of the first power zone is located between the second part of the first power zone and the transition structure; as well as During the failure state of the semiconductor device, the molten material of the first portion of the first electric region passes through the transition structure and contacts the control region to form a low-resistance connection between the control region and the first electric region.

12. The semiconductor device according to claim 11, wherein: The first melting point of the first material is less than the second melting point of the second material.

13. The semiconductor device according to claim 4, wherein: The first electric zone includes a first part and a second part, wherein the first melting point of the first part of the first electric zone is less than the second melting point of the second part of the first electric zone; The first part of the first power zone is located between the second part of the first power zone and the transition structure; as well as During the failure state of the semiconductor device, the molten material of the first portion of the first electric region passes through the transition structure and contacts the control region to form a low-resistance connection between the control region and the first electric region.

14. The semiconductor device according to claim 13, wherein: The first part of the first power zone includes aluminum; and The second part of the first power zone includes copper.

15. The semiconductor device according to claim 1, comprising: A semiconductor substrate comprising at least one of silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or gallium oxide (II) (GaO), wherein an isolation region covers the semiconductor substrate, and wherein the semiconductor substrate has a band gap greater than 1.1 electron volts (eV).

16. The semiconductor device according to claim 1, wherein: The control terminals include the gate terminal; The first power terminal includes at least one of a source terminal or a transmitter terminal; as well as The second power terminal includes at least one of a drain terminal or a collector terminal.

17. The semiconductor device according to claim 1, wherein: The failure state of a semiconductor device corresponds to the temperature of the short-circuit structure exceeding the melting point of the short-circuit structure; as well as During the failure state of a semiconductor device, the material of the short-circuit structure melts to form a low-resistance connection between the control region and the first power region.

18. A semiconductor device, comprising: Semiconductor substrates, including silicon carbide (SiC); The control area includes control terminals; The first power zone includes a first power terminal; The second power zone includes a second power terminal; An isolation region is located between the control region and the first power region, wherein the isolation region covers the semiconductor substrate; as well as A failure structure extending from a first electric region through an isolation region to a control region, wherein the failure structure is configured to alter the properties of at least some materials between the control region and the first electric region during a failure state of the semiconductor device, thereby forming a low-resistance connection between the control region and the first electric region.

19. The semiconductor device according to claim 18, wherein: The failure structure includes at least one of the following: germanium, manganese(III) oxide (Mn2O3), nickel(II) oxide (NiO), cobalt(III) oxide (Co2O3), cuprous(I) oxide (Cu2O), iron(III) oxide (Fe2O3), titanium dioxide (TiO2), aluminum oxide (Al2O3), beryllium oxide (BeO), magnesium oxide (MgO), zirconium dioxide (ZrO2), yttrium oxide (Y2O3), dysprosium oxide (Dy2O3), or germanium telluride (GeTe); The characteristic corresponds to resistance; The first temperature of the failed structure during the normal state of the semiconductor device is lower than the second temperature of the failed structure during the failed state of the semiconductor device. as well as The first resistance of the failed structure during the normal state of the semiconductor device is higher than the second resistance of the failed structure during the failed state of the semiconductor device.

20. A semiconductor device, comprising: Semiconductor substrates, including silicon carbide (SiC); The control area includes control terminals; The first power zone includes a first power terminal; The second power zone includes a second power terminal; An isolation region is located between the control region and the first power region, wherein the isolation region covers the semiconductor substrate; A transition structure that extends from the first power zone through the isolation zone to the control zone; as well as A dielectric structure surrounding a portion of a first electric region, wherein the dielectric structure defines an opening between the first electric region and a transition structure.

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