Display panel, preparation method thereof and display device
By setting grooves on the insulating layer and covering the shielded signal lines, the crosstalk problem between signal lines in the display panel is solved, signal stability is improved, and a thinner and lighter design is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2021-02-09
- Publication Date
- 2026-06-02
Smart Images
Figure CN112864179B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology
[0002] With advancements in display technology, users have increasingly higher demands for visual experience. Furthermore, as the number of display products increases, people are also placing higher demands on display quality. Summary of the Invention
[0003] The embodiments of this disclosure provide a display panel and a method for manufacturing the same, as well as a display device, which can avoid signal interference.
[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:
[0005] On one hand, a display panel is provided. The display panel has a display area and a peripheral area located outside the display area. The display panel includes a substrate, at least one first signal line, at least one second signal line, an insulating layer, and a shielding signal line. The at least one first signal line is disposed on the substrate and located within the peripheral area. The at least one second signal line is disposed on the substrate and located within the peripheral area; the at least one second signal line and the at least one first signal line are disposed in the same layer. The insulating layer covers the at least one first signal line and the at least one second signal line; the insulating layer has at least one groove on its surface away from the substrate; the orthographic projection of the bottom surface of the groove onto the substrate lies between the orthographic projections of the first signal line and the second signal line onto the substrate. The shielding signal line covers the at least one groove.
[0006] In some embodiments, the bottom surface of the groove is closer to the substrate than the top surface of at least one of the first signal line and the second signal line, along a direction perpendicular to the plane of the substrate.
[0007] In some embodiments, the first signal line and the second signal line are adjacent to each other. The width of the orthographic projection of the bottom surface of the groove onto the substrate is less than or equal to the distance between two adjacent edges of the orthographic projections of the first signal line and the second signal line onto the substrate.
[0008] In some embodiments, the width of the orthographic projection of the bottom surface of the groove onto the substrate is 2 μm to 10 μm.
[0009] In some embodiments, the first signal line extends in the same direction as the second signal line. The groove extends along the extension directions of the first signal line and the second signal line.
[0010] In some embodiments, the orthographic projection of the shielded signal line on the substrate overlaps the orthographic projections of the first signal line on the substrate and the second signal line on the substrate.
[0011] In some embodiments, the shielded signal line is located within the peripheral area and surrounds the display area.
[0012] In some embodiments, the first signal line is configured to transmit a first signal; the second signal line is configured to transmit a second signal. Both the first signal and the second signal are pulse signals, and the first signal and the second signal are different. The shielded signal line is configured to transmit a DC signal.
[0013] In some embodiments, the first signal and the second signal have the same pulse period; the first signal and the second signal have a phase difference.
[0014] In some embodiments, the pulse period is 4 μs to 100 μs.
[0015] In some embodiments, the display panel further includes a plurality of light-emitting devices. The plurality of light-emitting devices are disposed on the substrate and located within the display area. Each light-emitting device includes a first electrode and a second electrode; the first electrode is closer to the substrate than the second electrode. The second electrode is coupled to the shielded signal line.
[0016] In some embodiments, the first electrode of the light-emitting device is disposed in the same layer as the shielded signal line. The insulating layer has a double-layer structure.
[0017] In some embodiments, the first electrode of the light-emitting device is located further away from the substrate than the shielded signal line. The insulating layer is a single-layer structure.
[0018] In some embodiments, the display panel further includes: a plurality of pixel circuits and a driving circuit. The plurality of pixel circuits are disposed on the substrate and located within the display area. The driving circuit is disposed on the substrate and located within the peripheral area. The driving circuit is coupled to the plurality of pixel circuits, the first signal line, and the second signal line, respectively. The driving circuit is configured to provide a driving signal to the plurality of pixel circuits in response to a first signal received at the first signal line and a second signal received at the second signal line, so as to drive the plurality of pixel circuits to operate.
[0019] On the other hand, a display device is provided. The display device includes a display panel as described in any of the above embodiments and a control chip. The control chip is coupled to the display panel. The control chip is configured to provide signals to the display panel.
[0020] In another aspect, a method for manufacturing a display panel is provided. The method includes: providing a substrate having a display area and a peripheral area outside the display area; forming at least one first signal line and at least one second signal line within the peripheral area of the substrate; forming an insulating layer covering the at least one first signal line and the at least one second signal line; forming at least one groove on a surface of the insulating layer away from the substrate; the orthographic projection of the bottom surface of the groove onto the substrate lies between the orthographic projections of the first signal line and the second signal line onto the substrate; and forming a shielding signal line covering the at least one groove.
[0021] In some embodiments, forming the insulating layer includes: forming an insulating material layer on the side of the at least one first signal line and the at least one second signal line away from the substrate; forming a photoresist layer on the insulating material layer; exposing the photoresist layer using a halftone mask, developing the photoresist layer to form a photoresist layer completely removed region, a photoresist layer partially retained region, and a photoresist layer completely retained region; etching the insulating material layer to remove the portion of the insulating material layer located in the photoresist layer completely removed region; using an ashing process to remove the portion of the photoresist layer located in the photoresist layer partially retained region; etching the portion of the insulating material layer located in the photoresist layer partially retained region to form the at least one groove; and peeling off the remaining photoresist layer to obtain the insulating layer.
[0022] Therefore, embodiments of this disclosure provide a display panel and its manufacturing method, as well as a display device. At least one first signal line and at least one second signal line in the display panel are covered by an insulating layer. At least one groove is provided on the insulating layer, with the groove positioned between adjacent first and second signal lines. A shielding signal line covers at least one groove. In this way, the shielding signal line can shield the first and second signal lines, preventing signal crosstalk between them and improving the display effect. Furthermore, the insulating layer is thinner at the groove location, and the shielding signal line is located within the groove, which does not increase the film thickness of the display panel, thus facilitating a thinner and lighter display panel. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.
[0024] Figure 1 A top view of a display panel according to some embodiments;
[0025] Figure 2 for Figure 1 A cross-sectional view of the display panel along the A1-B1 direction;
[0026] Figure 3 Another top view of the display panel according to some embodiments;
[0027] Figure 4 for Figure 3 A cross-sectional view of the display panel along the A2-B2 direction;
[0028] Figure 5 for Figure 3 A cross-sectional view of the display panel along the A3-B3 direction;
[0029] Figure 6 A timing diagram of a first signal, a second signal, and a DC signal according to some embodiments;
[0030] Figure 7 This is yet another top view of a display panel according to some embodiments;
[0031] Figure 8 This is a structural diagram of a pixel circuit according to some embodiments;
[0032] Figure 9 for Figure 1 A cross-sectional view of the display panel along the D1-D2 direction;
[0033] Figure 10A This is a structural diagram of a display panel according to some embodiments;
[0034] Figure 10B This is another structural diagram of a display panel according to some embodiments;
[0035] Figure 11 This is a structural diagram of a drive circuit according to some embodiments;
[0036] Figure 12 This is another structural diagram of a drive circuit according to some embodiments;
[0037] Figure 13 This is a structural diagram of a shift register according to some embodiments;
[0038] Figure 14 This is yet another structural diagram of a display panel according to some embodiments;
[0039] Figure 15This is yet another structural diagram of a display panel according to some embodiments;
[0040] Figure 16 This is a structural diagram of a display device according to some embodiments;
[0041] Figure 17A This is a process diagram of a method for manufacturing a display panel according to some embodiments;
[0042] Figure 17B This is another process diagram of a method for manufacturing a display panel according to some embodiments;
[0043] Figure 18A This is yet another process diagram of a method for manufacturing a display panel according to some embodiments;
[0044] Figure 18B This is yet another process diagram of a method for manufacturing a display panel according to some embodiments;
[0045] Figure 18C This is yet another process diagram of a method for manufacturing a display panel according to some embodiments;
[0046] Figure 19 This is yet another process diagram of a method for manufacturing a display panel according to some embodiments. Detailed Implementation
[0047] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.
[0048] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.
[0049] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.
[0050] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.
[0051] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.
[0052] As used herein, “about” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).
[0053] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
[0054] In display panels, due to space constraints, the spacing between adjacent signal lines is relatively small. During signal transmission, crosstalk can easily occur between adjacent signal lines, reducing signal stability, affecting the normal operation of some circuits in the display panel, and thus degrading the display effect.
[0055] Embodiments of this disclosure provide a display panel. For example... Figure 1 As shown, the display panel 100 has a display area (Active Area, AA) and a peripheral area S. For example, the peripheral area S is located on at least one side outside the display area AA. For example, see reference... Figure 1 The display area AA is the region defined by the dashed box. The surrounding area S may surround the display area AA.
[0056] For example, the display panel 100 includes a plurality of subpixels P disposed in the display area AA. For instance, the plurality of subpixels P may be arranged in an array. For example, along... Figure 1 Subpixels P arranged in a row along the X direction (i.e., the horizontal direction) are called the same pixel. Figure 1 Subpixels P arranged in a row along the Y-direction (i.e., the vertical direction) are called pixels in the same column. For example, each pixel includes multiple subpixels; these multiple subpixels include a first-color subpixel, a second-color subpixel, and a third-color subpixel. For example, the first, second, and third colors are the three primary colors; for example, the first, second, and third colors are red, green, and blue, respectively; that is, the multiple subpixels include red subpixels, green subpixels, and blue subpixels.
[0057] For example, in the embodiments of this disclosure, a spatial rectangular coordinate system is established with the substrate of the display panel as a reference. In this spatial rectangular coordinate system, the X and Y directions are parallel to the plane where the substrate is located, and the Z direction is perpendicular to the plane where the substrate is located.
[0058] For example, refer to Figure 1 and Figure 2 The display panel 100 includes a substrate 101, at least one first signal line 10, at least one second signal line 20, and an insulating layer 40. The at least one first signal line 10, at least one second signal line 20, a shielded signal line 30, and the insulating layer 40 are all disposed on the substrate 101. The at least one first signal line 10 and the at least one second signal line 20 are both located within a peripheral area S. The insulating layer 40 covers the at least one first signal line 10 and the at least one second signal line 20, meaning the insulating layer 40 is disposed on the side of the at least one first signal line 10 and the at least one second signal line 20 away from the substrate 101, i.e., above the at least one first signal line 10 and the at least one second signal line 20.
[0059] For example, substrate 101 may include a rigid substrate such as glass (or a hard substrate), or a flexible substrate such as PI (Polyimide); it may also include a film layer (e.g., a buffer layer) disposed on the rigid or flexible substrate. For example, the material of insulating layer 40 may include organic materials (e.g., resin materials) or inorganic materials (e.g., silicon oxide or silicon nitride).
[0060] For example, at least one first signal line and at least one second signal line are disposed in the same layer. For example, the film layer containing the first and second signal lines can be considered a first conductive layer. For example, the material of the first and second signal lines is the same, such as metals including molybdenum (Mo), aluminum (Al), and copper (Cu). For example, the first and second signal lines can be formed simultaneously, for example, the first and second signal lines can be patterned from the same film layer. This reduces production steps and simplifies the process. For example, one first signal line and one second signal line are adjacent. For example, in the film layer containing the first and second signal lines, there are no other signal lines between the first and second signal lines.
[0061] The first signal line is configured to transmit a first signal. The second signal line is configured to transmit a second signal. Both the first and second signals are pulse signals, and the first and second signals are different. For example, refer to... Figure 6The first signal K1 and the second signal K2 have the same pulse period and a phase difference. A pulse period refers to the duration from the rising edge (or falling edge) of one pulse of the pulse signal (e.g., the first signal or the second signal) to the rising edge (or falling edge) of the next pulse. For example, the rising edge (or falling edge) of the pulse of the first signal and the rising edge (or falling edge) of the pulse of the second signal are not at the same time; for example, the interval between the rising edge (or falling edge) of the pulse of the first signal and the rising edge (or falling edge) of the pulse of the second signal is greater than 0 and less than one pulse period. For example, the phase difference between the first signal and the second signal is half the pulse period. For example, both the first signal and the second signal can be AC signals; for example, both the first signal and the second signal can be clock signals and have the same clock period. For example, the phase difference between the first signal and the second signal is equal to half the pulse period; for example, the first signal and the second signal are inverted signals.
[0062] For example, both the first signal and the second signal can be high-frequency signals; for example, the pulse period of the first signal and the pulse period of the second signal are 4μs to 100μs, such as 5μs, 10μs, 25μs, 50μs, or 80μs. For example, the frequency of the first signal and the frequency of the second signal are 10000Hz to 250000Hz, such as 12500Hz, 20000Hz, 40000Hz, 100000Hz, or 200000Hz.
[0063] In this case, refer to Figure 2 The insulating layer 40 has at least one groove 41 on its surface away from the substrate 101. The orthographic projection of the bottom surface of a groove 41 (i.e., the surface of the groove 41 closest to the substrate 101) F3 onto the substrate 101 lies between the orthographic projections of a first signal line 10 and a second signal line 20 onto the substrate 101. For example, the first signal line 10 and the second signal line 20 are adjacent. For example, the depth direction of at least one groove 41 (e.g.) Figure 2 The Z-direction in the image is perpendicular to the substrate 101. For example, in the surface of the insulating layer on the side away from the substrate, corresponding to the portion between the first signal line and the second signal line, a groove is formed by recessing the insulating layer toward the substrate side in a direction perpendicular to the substrate. Exemplarily, the depth of the groove is less than the thickness of the insulating layer; for example, the bottom surface and sidewalls of the groove are both made of the insulating layer.
[0064] Furthermore, refer to Figure 1 and Figure 2The display panel 100 also includes a shielded signal line 30. The shielded signal line 30 covers the recess 41. For example, the shielded signal line 30 is disposed on the side of the insulating layer 40 away from the substrate 101. For example, the shielded signal line covers the bottom surface and sidewalls of the recess.
[0065] For example, the shielded signal line is configured to transmit a DC signal. For instance, refer to... Figure 6 The voltage (or current) amplitude of the DC signal K3 remains constant or approximately constant (e.g., the amplitude varies within a small range). For example, the DC signal can be a low DC voltage; for example, the shielded signal line can be a power supply voltage line configured to transmit a low power supply voltage V. SS .
[0066] In this situation, because the first signal transmitted on the first signal line and the second signal transmitted on the second signal line are different and change frequently over time, crosstalk can easily occur between the first and second signals during transmission, leading to reduced signal stability and affecting the normal operation of some circuits in the display panel. Since the DC signal transmitted on the shielded signal line within the groove remains constant or nearly constant, it can shield the first and second signal lines, thus preventing crosstalk between them. Furthermore, the insulating layer is thinner at the groove location, and the shielded signal line is located within the groove, which does not increase the film thickness of the display panel, contributing to a thinner and lighter display panel.
[0067] Therefore, embodiments of this disclosure provide a display panel in which at least one first signal line and at least one second signal line are covered by an insulating layer. At least one groove is provided on the insulating layer, with the groove positioned between adjacent first and second signal lines. A shielding signal line covers at least one groove. In this way, the shielding signal line can shield the first and second signal lines, preventing signal crosstalk between them. Furthermore, the insulating layer is thinner at the groove location, and the shielding signal line is located within the groove, thus not increasing the film thickness of the display panel, which is beneficial for achieving a thinner and lighter display panel.
[0068] For example, refer to Figure 2Along a direction perpendicular to the plane of substrate 101 (e.g., the Z direction), the bottom surface of groove 41 is closer to substrate 101 than at least one of the top surface F1 of the first signal line 10 and the top surface F2 of the second signal line 20. That is, compared to the surface F1 of the first signal line 10 away from substrate 101 and the surface F2 of the second signal line 20 away from substrate 101, the surface F3 of groove 41 near substrate 101 is closer to substrate 101. For example, along a direction parallel to the plane of substrate and perpendicular to the extension direction of the first signal line, the orthographic projection of the shielding signal line on the first signal line may overlap with the sidewall of the first signal line near the second signal line; similarly, along a direction parallel to the plane of substrate and perpendicular to the extension direction of the second signal line, the orthographic projection of the shielding signal line on the second signal line may overlap with the sidewall of the second signal line near the first signal line. This expands the shielding range of the shielding signal line on the first and second signal lines, thereby improving the shielding effect of the shielding signal line and preventing signal interference between the first and second signal lines.
[0069] For example, refer to Figure 1 and Figure 2 The width W of the orthographic projection of the bottom surface of the groove 41 onto the substrate 101 is less than or equal to the distance Q between two adjacent edges in the orthographic projections of the first signal line 10 and the second signal line 20 onto the substrate 101. For example, in the plane of the substrate, the orthographic projection of the bottom surface of the groove onto the substrate is perpendicular to the extension direction of the first signal line or the second signal line (e.g., in...). Figure 1 The dimension in the X direction is the width of the orthographic projection of the bottom surface of the groove onto the substrate. In this way, the shielded signal line located within the groove can shield the first and second signal lines to avoid signal interference.
[0070] For example, refer to Figure 1 and Figure 2 The width W of the orthographic projection of the surface of the groove 41 on the substrate 101 is 2 μm to 10 μm. For example, the width W can be 4 μm, 6 μm, 7 μm or 9 μm. For example, the width W can be 3 μm to 5 μm.
[0071] In some embodiments, the orthogonal projection of the shielded signal line 30 on the substrate 101 covers the orthogonal projection of the first signal line 10 on the substrate 101 and the orthogonal projection of the second signal line 20 on the substrate 101. In this way, the shielded signal line can cover the groove, the first signal line, and the second signal line, which can improve the shielding effect of the shielded signal line on the first signal line and the second signal line and avoid signal interference between the first signal line and the second signal line.
[0072] In some embodiments, reference Figure 1The extension direction of the first signal line 10 is the same as the extension direction of the second signal line 20. The groove 41 extends along the extension direction of the first signal line 10 and the second signal line 20; that is, the extension direction of the groove 41 is the same as the extension direction of either the first signal line 10 or the second signal line 20. For example, the groove 41, the first signal line 10, and the second signal line 20 all extend along... Figure 1 The groove extends in the X direction. For example, in the extension direction of the first signal line, the length of the groove is equal to or approximately equal to the length of the first signal line; or, in the extension direction of the second signal line, the length of the groove is equal to or approximately equal to the length of the second signal line. This improves the shielding effect of the shielded signal line on the first and second signal lines, preventing signal interference between them.
[0073] For example, refer to Figure 3 and Figure 4 The display panel 100 also includes a first conductive pattern 110. The first conductive pattern 110 is disposed on the substrate 101 and located on the side of the first signal line 10 close to the substrate 101. The orthographic projection of the first conductive pattern 110 on the substrate 101 overlaps with the orthographic projection of the first signal line 10 on the substrate 101. The first conductive pattern 110 and the first signal line 10 are coupled. For example, the first signal line 10 contacts the first conductive pattern 110 through a plurality of first vias 111 (e.g., at least two first vias) located on a film layer between the film layer containing the first signal line 10 and the film layer containing the first conductive pattern 110. For example, the material of the first conductive pattern can be the same as the material of the first signal line. In this case, the first conductive pattern can be used to transmit a first signal, that is, the first signal is transmitted by the first signal line in the first conductive layer and the first conductive pattern in the second conductive layer. In this way, the resistance of the first signal line can be reduced, the signal transmission loss on the first signal line can be reduced, and the signal transmission effect can be improved. In addition, two adjacent first vias can be interconnected along the extension direction of the first signal line.
[0074] For example, refer to Figure 3 and Figure 5The display panel 100 also includes a second conductive pattern 120. The second conductive pattern 120 is disposed on the substrate 101 and located on the side of the second signal line 20 closest to the substrate 101. The orthographic projection of the second conductive pattern 120 onto the substrate 101 overlaps with the orthographic projection of the second signal line 20 onto the substrate 101. The second conductive pattern 120 and the second signal line 20 are coupled. For example, the second signal line 20 contacts the second conductive pattern 120 through a plurality of second vias 121 (e.g., at least two second vias) located on a film layer between the film layer containing the second signal line 20 and the film layer containing the conductive pattern 120. For example, the material of the second conductive pattern can be the same as the material of the second signal line. In this case, the second conductive pattern can be used to transmit a second signal, i.e., the second signal is transmitted by the second signal line in the first conductive layer and the second conductive pattern in the second conductive layer. This reduces the resistance of the second signal line, decreases signal transmission loss on the second signal line, and thus improves signal transmission efficiency. Furthermore, adjacent second vias can be interconnected along the extension direction of the second signal line.
[0075] For example, the first conductive pattern and the second conductive pattern are disposed in the same layer. For instance, the film layer containing the first and second conductive patterns can be considered as the second conductive layer. The material of the first conductive pattern and the second conductive pattern is the same, for example, the material can be a metal including molybdenum (Mo), aluminum (Al), copper (Cu), etc. For instance, the first and second conductive patterns can be formed simultaneously; for example, the first and second conductive patterns can be patterned and formed from the same film layer. This reduces production steps and simplifies the process.
[0076] In some embodiments, reference Figure 7 The display panel 100 also includes a plurality of pixel circuits 50. The plurality of pixel circuits 50 are disposed on the substrate 101 and located within the display area AA; for example, one pixel circuit 50 is contained within a sub-pixel P. In some embodiments, the display panel also includes a plurality of light-emitting devices. The plurality of light-emitting devices are disposed on the substrate and located within the display area AA. One light-emitting device is contained within a sub-pixel. For example, one pixel circuit is coupled to one light-emitting device, and the pixel circuit is used to provide a driving current to drive the light-emitting device to operate. For example, refer to... Figure 9 The display panel 100 also includes a third conductive pattern 130 disposed on the side of the first electrode 71 near the substrate 101; the first electrode 71 of the light-emitting device 70 is coupled to the pixel circuit 50 through the third conductive pattern 130.
[0077] Exemplary, the embodiments of this disclosure do not limit the specific structure of the pixel circuit, and can be designed according to actual conditions. Exemplary, the pixel circuit is composed of electronic devices such as thin-film transistors (TFTs) and capacitors (C). For example, the pixel circuit may include two thin-film transistors (one switching transistor and one driving transistor) and a capacitor, forming a 2T1C structure; of course, the pixel circuit may also include two or more thin-film transistors (multiple switching transistors and one driving transistor) and at least one capacitor, as shown in reference [reference needed]. Figure 8 The pixel circuit 20 may include a capacitor Cst and seven transistors (six switching transistors M1, M2, M3, M5, M6, and M7, and one driving transistor M4), forming a 7T1C structure. It should be noted that the accompanying drawings of this disclosure (e.g., Figure 9 (e.g., using a transistor in a pixel circuit as an example to represent a pixel circuit, but the actual structure of a pixel circuit is not limited to this.)
[0078] For example, such as Figure 8 As shown, the gate of some switching transistors (e.g., M1, M7) is used to receive the reset signal Reset. The gate of another set of switching transistors (e.g., M2, M3) is used to receive the gate drive signal Gate. The gate of yet another set of switching transistors (e.g., M5, M6) is used to receive the light emission control signal EM. For example, in response to the reset signal Reset, transistors M1 and M7 are turned on. The initial signal Initial is transmitted through transistors M1 and M7 to the gate (g) of the driving transistor M4 and the light-emitting device 70, respectively, to reset the light-emitting device 70 and the gate of the driving transistor M4. Then, under the control of the gate drive signal Gate, transistor M2 is turned on, and the gate (g) of the driving transistor M4 is coupled to its drain (d), making the driving transistor M4 a diode. At this time, the data signal Data is written to the source (s) of the driving transistor M4 through transistor M2, compensating for the threshold voltage (Vth) of the driving transistor M4. Subsequently, under the control of the light emission control signal EM, transistors M5 and M6 are turned on, and the high power supply voltage (or the first power supply voltage) V... DD With low supply voltage (or second supply voltage) V SS The current path between them is open. The drive current (I) generated by the drive transistor M4 is... sd The current is transmitted to the light-emitting device 70 through the above-mentioned current path to drive the light-emitting device 70 to emit light.
[0079] For example, the light-emitting device can be a current-driven device, or more specifically, a current-driven light-emitting diode, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED).
[0080] For example, refer to Figure 9 Each light-emitting device 70 includes a first electrode 71 and a second electrode 72. The first electrode 71 is closer to the substrate 101 than the second electrode 72. For example, the first electrode and the second electrode are respectively an anode and a cathode. For example, refer to Figure 9 The light-emitting device 70 further includes a light-emitting functional layer 73 located between the second electrode 72 and the first electrode 71. This light-emitting functional layer may include, for example, a light-emitting layer, a hole transporting layer (HTL) located between the light-emitting layer and the first electrode, and an electron transporting layer (ETL) located between the light-emitting layer and the second electrode. Of course, in some embodiments, a hole injection layer (HIL) may also be provided between the hole transporting layer and the first electrode, and an electron injection layer (EIL) may be provided between the electron transporting layer and the second electrode, as needed.
[0081] For example, the first electrode may be formed of a transparent conductive material with a high work function, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc gallium oxide (GZO), zinc oxide (ZnO), indium oxide (In2O3), zinc aluminum oxide (AZO), and carbon nanotubes; the second electrode may be formed of a material with high conductivity and low work function, such as alloys like magnesium-aluminum alloy (MgAl) and lithium-aluminum alloy (LiAl), or elemental metals like magnesium (Mg), aluminum (Al), lithium (Li), and silver (Ag). The material of the light-emitting layer can be selected according to the different colors of the emitted light. For example, the material of the light-emitting layer includes fluorescent light-emitting materials or phosphorescent light-emitting materials. For example, in at least one embodiment of this disclosure, the light-emitting layer may employ a doping system, that is, dopant materials are mixed into the main light-emitting material to obtain a usable light-emitting material. For example, the main light-emitting material may be a metal compound, anthracene derivative, aromatic diamine compound, triphenylamine compound, aromatic triamine compound, benzidine diamine derivative, and triarylamine polymer, etc.
[0082] For example, refer to Figure 9 The display panel 100 also includes a pixel defining layer (PDL), which can be used to define the area where a sub-pixel is located. For example, it can be used to define the formation position of the light-emitting functional layer of the light-emitting device 70. For example, the light-emitting functional layer 420 is located in the opening of the pixel defining layer (PDL).
[0083] The second electrode is coupled to the shielded signal line. For example, reference... Figure 10A and Figure 10B The display panel 100 also includes a fourth conductive pattern 140, which is closer to the substrate 101 than the second electrode 72. The second electrode 72 is coupled to the fourth conductive pattern 140, and the fourth conductive pattern 140 is coupled to the shielded signal line 30. For example, refer to Figure 10A The fourth conductive pattern 140 is arranged on the same layer as the shielded signal line 30; or, refer to Figure 10B The fourth conductive pattern 140 is disposed in the same layer as the first electrode 71, and the fourth conductive pattern 140 and the first electrode 71 are made of the same material. It should be noted that... Figure 10A and Figure 10B This is for illustrative purposes only; the specific structure and connection method can be designed according to actual conditions. The second electrode receives a DC signal from the shielded signal line; this DC signal is a low-voltage DC signal.
[0084] In some embodiments, reference Figure 1The shielded signal line 30 is located within the peripheral area S and surrounds the display area AA. The second electrodes of multiple light-emitting devices in the display area AA can be coupled to the shielded signal line, allowing for relatively uniform reception of DC signals (e.g., low DC voltage) transmitted from the shielded signal line, thereby reducing impedance. For example, the second electrode covers the display area AA; the second electrode covering the display area AA can be formed by a vapor deposition process.
[0085] In some embodiments, such as Figure 7 As shown, the display panel 100 also includes a driving circuit 60. The driving circuit 60 is disposed on the substrate 101 and located within the peripheral region S. The driving circuit 60 is coupled to a plurality of pixel circuits 50, a first signal line 10, and a second signal line 20.
[0086] The driving circuit is configured to provide driving signals to multiple pixel circuits in response to a first signal received at a first signal line and a second signal received at a second signal line, thereby driving the multiple pixel circuits to operate. For example, the multiple pixel circuits are arranged in an array; the driving circuit provides driving signals to each row of pixel circuits sequentially, enabling the multiple pixel circuits to operate row by row. Exemplarily, the driving signals provided by the driving circuit may include a gate scan signal or an emission control signal (EM).
[0087] For example, the driving circuit includes multiple shift registers. For instance, see reference... Figure 11 and Figure 12 The driving circuit 60 includes multiple shift registers SR (e.g., SR(1), SR(2), SR(3), SR(4)...). For example, multiple shift registers SR are cascaded; for example, a first-stage shift register (e.g., Figure 11 The input of the shift register SR(1) in the middle is connected to the start signal line (e.g., Figure 11 The start signal line (STV) is coupled, the output Oput of shift register SR(1) is coupled to the input Iput of shift register SR(2), the output Oput of shift register SR(2) is coupled to the input Iput of shift register SR(3), the output Oput of shift register SR(3) is coupled to the input Iput of shift register SR(4), and so on.
[0088] For example, a shift register is coupled to a row of pixel circuitry, and this shift register is used to output a drive signal to the row of pixel circuitry. For example, see reference... Figure 11The shift register SR in the driving circuit 60 outputs a gate drive signal, Gate. For example, the first-stage shift register SR(1) outputs a gate drive signal Gate(1) to drive the first row of pixel circuits; the second-stage shift register SR(2) outputs a gate drive signal Gate(2) to drive the second row of pixel circuits; the third-stage shift register SR(3) outputs a gate drive signal Gate(3) to drive the third row of pixel circuits; the fourth-stage shift register SR(4) outputs a gate drive signal Gate(4) to drive the fourth row of pixel circuits, and so on. For example, see reference... Figure 12 The driving signal output by the shift register SR in the driving circuit 60 is the light emission control signal EM. For example, the first-stage shift register SR(1) outputs the light emission control signal EM(1) to drive the first row of pixel circuits to work, the second-stage shift register SR(2) outputs the light emission control signal EM(2) to drive the second row of pixel circuits to work, the third-stage shift register SR(3) outputs the light emission control signal EM(3) to drive the third row of pixel circuits to work, the fourth-stage shift register SR(4) outputs the light emission control signal EM(4) to drive the fourth row of pixel circuits to work, and so on.
[0089] In this case, there can be multiple driving circuits. For example, multiple driving circuits include a first driving circuit and a second driving circuit. The first driving circuit is used to output a gate scan signal, and the second driving circuit is used to output a light emission control signal. At least one first signal line includes two first signal lines, with the first driving circuit coupled to one of the two first signal lines and the second driving circuit coupled to the other of the two first signal lines. The first signals transmitted on the two first signal lines are different; for example, the first signals transmitted on the two first signal lines can be of the same type, but with different signal timing and voltage amplitudes. Similarly, at least one second signal line includes two second signal lines, with the first driving circuit coupled to one of the two second signal lines and the second driving circuit coupled to the other of the two second signal lines. The second signals transmitted on the two second signal lines are different; for example, the second signals transmitted on the two second signal lines can be of the same type, but with different signal timing and voltage amplitudes.
[0090] Exemplary, the embodiments of this disclosure do not limit the specific structure of the driving circuit, and can be designed according to actual conditions. Similarly, the embodiments of this disclosure do not limit the specific structure of the shift register, and can be designed according to actual conditions. Exemplary, the shift register is composed of electronic devices such as transistors and capacitors. For example, refer to... Figure 13The shift register SR can include multiple transistors (e.g., T1, T2, T3, T4, T5, T6, T7, T8, T9) and a capacitor (e.g., Ct). The control electrode and first electrode of transistor T1 are coupled to the input terminal Iput; the first electrode of transistor T2 is coupled to the first clock signal terminal CK1; the second electrode of transistor T2 is coupled to the output terminal Oput; the control electrode and first electrode of transistor T4 are coupled to the second clock signal terminal CK2; and the first electrode of transistor T5 is coupled to the second clock signal terminal CK2. Additionally, the control electrode of transistor T3 is coupled to the noise reduction signal terminal RST, and transistors T3, T6, T7, T8, and T9 are all coupled to the voltage terminal VL. For example, an odd-stage shift register (e.g., Figure 11 In the SR(1) and SR(3) shift registers, the first clock signal terminal CK1 is coupled to the first signal line 10 and can transmit the first signal. The second clock signal terminal CK2 is coupled to the second signal line 20 and can transmit the second signal. Even-stage shift registers (e.g.) Figure 11 In the SR(2) and SR(4) signals, the first clock signal terminal CK1 is coupled to the second signal line 20, and the second clock signal terminal CK2 is coupled to the first signal line 10. At this time, both the first and second signals are clock signals and are inverted signals of each other. In addition, the voltage terminal VL is coupled to the voltage line VGL, for example, the voltage line VGL is used to transmit DC low voltage signals.
[0091] By way of example, the embodiments of this disclosure do not limit the driving method of the display panel, and can be designed according to actual conditions. For example, Figure 7 This illustration only shows a single-sided driving method (i.e., a driving circuit 60 is provided on one side of the peripheral area S of the display panel 100, and the pixel circuits in the sub-pixels are driven sequentially row by row from one side). For example, the display panel can employ dual-sided simultaneous driving (i.e., driving the pixel circuits in the peripheral area S of the display panel 100 along the row direction of the pixel circuit arrangement (or the row direction of the sub-pixel arrangement, for example...). Figure 7 In the X-direction of the display panel 100, two driving circuits 60 are respectively arranged on two sides, and the pixel circuits in the sub-pixels are driven sequentially from both sides row by row through the two driving circuits 60. For example, the display panel 100 can adopt a dual-sided cross-drive (that is, driving circuits 60 are respectively arranged on two sides along the row direction of the pixel circuit arrangement in the peripheral area S of the display panel 100, and the pixel circuits in the sub-pixels are driven sequentially from both sides row by row through the two driving circuits 60 alternately). In this case, at least one first signal line includes multiple first signal lines, at least one second signal line includes multiple second signal lines, and the multiple first signal lines and multiple second signal lines are respectively located outside the opposite sides of the display area in the row direction of the pixel circuit arrangement.
[0092] In some embodiments, such as Figure 14As shown, the first electrode 71 of the light-emitting device 70 is disposed in the same layer as the shielded signal line 30. For example, the material of the shielded signal line is the same as the material of the first electrode. For example, the material of the shielded signal line may include a transparent conductive material, such as ITO. For example, the shielded signal line and the first electrode may be formed by the same film layer pattern. This simplifies the process steps and saves costs. Furthermore, the thickness of the film layer between the shielded signal line and the second electrode is relatively small, which facilitates the coupling of the second electrode and the shielded signal line.
[0093] For example, the insulating layer has a double-layer structure; that is, the insulating layer has two layers, specifically, there are two insulating layers between the film layer containing the first signal line and the second signal line and the film layer containing the shielded signal line. For example, refer to... Figure 14 The double-layer insulating layer 40 includes a first insulating layer PLN1 and a second insulating layer PLN2. The first insulating layer PLN1 and the second insulating layer PLN2 are stacked along a direction perpendicular to the substrate 101, and the second insulating layer PLN2 is farther from the substrate 101 than the first insulating layer PLN1. Exemplarily, the bottom surface of the groove is formed by the first insulating layer, and the sidewalls of the groove are formed by the second insulating layer and the first insulating layer. For example, along a direction perpendicular to the plane of the substrate, the groove extends through the second insulating layer, and the depth of the groove is greater than the thickness of the second insulating layer and less than the thickness of the insulating layer (i.e., the sum of the thicknesses of the first and second insulating layers).
[0094] In some embodiments, such as Figure 15 As shown, the first electrode 71 of the light-emitting device 70 is farther from the substrate 101 than the shielding signal line 30. For example, the material of the shielding signal line may include a metallic material. Exemplarily, the insulating layer is a single-layer structure, meaning there is one insulating layer between the film layers containing the first and second signal lines and the film layer containing the shielding signal line. For example, refer to... Figure 15 The single-layer insulating layer 40 can be considered as the first insulating layer (PLN1). In this case, the film thickness between the film layer containing the first signal line and the second signal line and the film layer containing the shielding signal line is small, thereby improving the shielding effect of the shielding signal line on signal interference between the first signal line and the second signal line. Furthermore, in this case, the film layer located between the film layer containing the first electrode of the light-emitting device and the film layer containing the shielding signal line can be considered as the second insulating layer (PLN2).
[0095] For example, when the display panel does not include the first conductive pattern and the second conductive pattern, the insulating film layer located between the film layer containing the first signal line and the second signal line (e.g., the first conductive layer) and the film layer containing the shielding signal line can be double-layered, for example, a first insulating layer (PLN1) and a second insulating layer (PLN2). As another example, when the display panel includes the first conductive pattern and the second conductive pattern, the insulating film layer located between the film layer containing the first signal line and the second signal line (e.g., the first conductive layer) and the film layer containing the shielding signal line can be a single layer, for example, the first insulating layer (PLN1). The film layer located between the film layer containing the first conductive pattern and the second conductive pattern (e.g., the second conductive layer) and between the film layer containing the first signal line and the second signal line (e.g., the first conductive layer) can be an interlayer dielectric layer (ILD); the film layer located between the film layer containing the first electrode of the light-emitting device and the film layer containing the shielding signal line can be the second insulating layer (PLN2).
[0096] Additionally, for example, the transistor includes an active pattern (i.e., an active layer), a gate (e.g., a control electrode), a source, and a drain. The display panel also includes a gate insulating layer (GI) located between the gate of the transistor and the active pattern. The source and drain are located on the side of the gate away from the substrate, and the source and drain are disposed in the same layer and coupled to the active pattern. For example, an interlayer dielectric (ILD) exists between the source and drain and the gate. For example, the source and drain can be disposed in the same layer as the first signal line and the second signal line; or, for example, the film layer containing the source and drain can be closer to the substrate than the film layer containing the first signal line and the second signal line. For example, a first insulating layer (PLN1) exists between the film layer containing the first signal line and the second signal line and the film layer containing the source and drain.
[0097] Exemplary, the embodiments of this disclosure do not limit the type of transistor, and the design can be made according to actual conditions. For example, the transistors used in the embodiments of this disclosure can be P-type transistors or N-type transistors, and can be bottom-gate transistors or top-gate transistors. For example, the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors (FETs), or other switching devices with the same characteristics, and the embodiments of this disclosure do not limit this. For example, the transistors used can include metal oxide thin-film transistors (e.g., thin-film transistors with active patterns made of IGZO) and low-temperature polycrystalline silicon thin-film transistors (e.g., thin-film transistors with active patterns made of P-Si), etc. The control electrode of each transistor is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, their source and drain can be structurally indistinguishable; that is, the first electrode and the second electrode of the transistor in the embodiments of this disclosure can be structurally indistinguishable.
[0098] Embodiments of this disclosure provide a display device. The display device includes the display substrate described in any of the foregoing embodiments. For example, such as... Figure 16 As shown, the display device 200 also includes a control chip 300, which is coupled to the display panel 100. Exemplarily, the control chip may include a timing controller (TCON). The control chip is configured to provide signals to the display panel. For example, the control chip may provide a first signal to a first signal line in the display panel, a second signal to a second signal line, and a DC signal to a shielded signal line.
[0099] In addition, the display device may also include an outer frame disposed around the display panel.
[0100] Exemplarily, the aforementioned display device can be any device that displays images, whether moving (e.g., video) or stationary (e.g., still images), and whether text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.
[0101] It should be noted that, for clarity, the entire structure of the display panel is not described. To achieve the necessary functions of the display panel, those skilled in the art can configure other structures according to specific application scenarios, and this disclosure does not impose any limitations on this. Display devices have the same beneficial effects as the aforementioned display panel, and will not be elaborated upon here.
[0102] Embodiments of this disclosure provide a method for manufacturing a display panel. For example, the display panel can be any of the display panels described in the above embodiments, for example, referring to... Figure 1 The display panel 100 in the middle.
[0103] The preparation method includes the following steps:
[0104] S10, Reference Figure 1 A substrate 101 is provided. The substrate 101 has a display area AA and a peripheral area S located outside the display area AA.
[0105] For example, the substrate can be a glass plate, a quartz plate, a metal plate, or a resin-based plate. For instance, the substrate material can include organic materials, such as resin materials like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. For instance, the substrate can be formed from multiple material layers; for example, the substrate can include a base plate, which can be made of the aforementioned materials. A buffer layer can be formed on the surface of the base plate as a transition layer, which can prevent harmful substances in the substrate from penetrating the interior of the display panel and increase the adhesion of the film layers in the display panel to the substrate. For example, the buffer layer material can include silicon oxide, silicon nitride, or silicon oxynitride.
[0106] S20, Reference Figure 1At least one first signal line 10 and at least one second signal line 20 are formed in the peripheral region S of the substrate 101. The position of one first signal line 10 is adjacent to the position of one second signal line 20.
[0107] For example, refer to Figure 17A and Figure 17B A conductive thin film 801 is formed in the peripheral region S of the substrate 101, and the conductive thin film 801 is patterned to obtain at least one first signal line 10 and at least one second signal line 20.
[0108] For example, driving circuits and pixel circuits can be formed on the substrate. The fabrication method for forming the driving circuits and pixel circuits on the substrate depends on the type of transistor; for example, the transistor can be a top-gate, bottom-gate, dual-gate, or other type of thin-film transistor. The process of forming the driving circuit layer on the substrate can be found in conventional processes and will not be elaborated here. For example, refer to... Figure 17A and Figure 17B Pixel circuits 50 can be formed within the display area AA of substrate 101; for example, the source and drain of each transistor in the pixel circuit can be formed simultaneously with the formation of at least one first signal line and at least one second signal line.
[0109] S30, Reference Figure 2 An insulating layer 40 is formed. The insulating layer 40 covers at least one first signal line 10 and at least one second signal line 20. At least one groove 41 is formed on the surface of the insulating layer 40 on the side away from the substrate 101. The orthographic projection of the bottom surface F3 of a groove 41 onto the substrate 101 lies between the orthographic projections of adjacent first signal lines 10 and second signal lines 20 onto the substrate 101.
[0110] For example, the insulating layer can be made of organic materials, such as epoxy resin, polyimide, polyamide, acrylic acid, or other suitable materials.
[0111] For example, forming an insulating layer may include:
[0112] refer to Figure 18A An insulating material layer 802 is formed on the side of at least one first signal line 10 and at least one second signal line 20 away from the substrate 101. For example, insulating material can be deposited on the side of at least one first signal line 10 and at least one second signal line 20 away from the substrate 101 to obtain the insulating material layer 802. (Reference) Figure 18B A photoresist layer 803 is formed on the insulating material layer 802. For example, the material of this photoresist layer is a photosensitive resin material, such as photoresist; for example, the photosensitive resin material is a positive photoresist. (Reference) Figure 18BA halftone mask 90 is used to expose the photoresist layer 803, and the photoresist layer 803 is developed to form a photoresist layer completely removed area 813, a photoresist layer partially retained area 823, and a photoresist layer completely retained area 833. For example, the photoresist layer completely removed area can correspond to the portion of the via to be formed in the insulating material layer, the photoresist layer partially retained area can correspond to the portion of the groove to be formed in the insulating material layer, and the photoresist layer completely retained area can correspond to the remaining portion in the insulating material layer.
[0113] For example, refer to Figure 18B The halftone mask 90 includes a first region 91, a second region 92, and a third region 93. The transmittance of the first region 91, the second region 92, and the third region 93 decreases sequentially. For example, the first region 91 can be configured as an aperture, and the third region 93 can be configured as opaque. Thus, by designing the transmittance of the first region 91, the second region 92, and the third region 93, and controlling the exposure intensity during exposure, the portion of the photoresist layer 803 corresponding to the first region 91 is fully exposed, the portion of the photoresist layer 803 corresponding to the second region 92 is fully exposed, and the portion of the photoresist layer 803 corresponding to the third region 93 is not exposed.
[0114] refer to Figure 18B and Figure 18C The insulating material layer 802 is etched to remove the portion of the insulating material layer 802 located in the area 813 where the photoresist layer is completely removed. An ashing process is used to remove the portion of the photoresist layer 803 located in the photoresist semi-retained area 823. The portion of the insulating material layer 802 located in the photoresist semi-retained area 823 is etched again to form at least one groove 41. The remaining photoresist layer 803 is peeled off to obtain the insulating layer 40.
[0115] It should be noted that by using the above steps to form the insulating layer, either a single-layer or a double-layer insulating layer can be obtained. (Refer to...) Figure 14 The double-layer insulating layer 40 includes a first insulating layer (PLN1) and a second insulating layer (PLN2); Reference Figure 15 The double-layer insulating layer 40 includes a first insulating layer (PLN1). The specific preparation process of the double-layer insulating layer can be found in the description above and will not be repeated here.
[0116] S40, Reference Figure 1 and Figure 2 A shielded signal line 30 is formed, which covers at least one groove 41. For example, a conductive material can be deposited on a substrate to obtain a conductive material layer, and the conductive material layer can be patterned to obtain the shielded signal line.
[0117] For example, refer to Figure 19While forming the shielded signal line 30 in the peripheral region S of the substrate 101, a third conductive pattern 130 can be formed in the display area AA. This third conductive pattern 130 is coupled to the pixel circuit 50 through a via located on the insulating layer 40. For example, the third conductive pattern is coupled to the drain of the driving transistor in the pixel circuit. Then, refer to... Figure 15 During the formation of the light-emitting device 70 on the substrate, the first electrode 71 of the light-emitting device 70 can be coupled to the pixel circuit 50 through the third conductive pattern 130. In this case, the shielded signal line is closer to the substrate than the first electrode of the light-emitting device.
[0118] For example, refer to Figure 14 The insulating layer 40 has a double-layer structure, which includes a first insulating layer (PLN1) and a second insulating layer (PLN2). A transparent conductive material layer can be formed on the second insulating layer (PLN2). The transparent conductive material layer is patterned to obtain a shielded signal line, and the first electrode of the light-emitting device is obtained simultaneously.
[0119] It should be noted that the beneficial effects of the above-described method for preparing the display panel are the same as those of the display panels described in some of the above embodiments, and will not be repeated here.
[0120] It should be noted that the accompanying drawings of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general designs. For clarity, the thickness of layers or regions in the drawings used to describe the embodiments of this disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale. Without conflict, the embodiments of this disclosure and the features within them can be combined to obtain new embodiments.
[0121] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A display panel, characterized by, The display panel includes a display area and a peripheral area located outside the display area; the display panel includes: Substrate; At least one first signal line is disposed on the substrate and located within the peripheral region; At least one second signal line is disposed on the substrate and located within the peripheral region; the at least one second signal line and the at least one first signal line are disposed on the same layer; the extension direction of the first signal line is the same as the extension direction of the second signal line; An insulating layer covers the at least one first signal line and the at least one second signal line; the insulating layer has at least one groove on its surface away from the substrate; the orthographic projection of the bottom surface of the groove onto the substrate lies between the orthographic projections of the first signal line and the second signal line onto the substrate; the groove extends along the extension direction of the first signal line and the second signal line. Shield the signal line, covering at least one of the grooves; Multiple pixel circuits are disposed on the substrate and located within the display area; A driving circuit is disposed on the substrate and located within the peripheral region; the driving circuit is coupled to the plurality of pixel circuits, the first signal line and the second signal line respectively. Multiple light-emitting devices are disposed on the substrate and located within the display area; each light-emitting device includes a first electrode and a second electrode; the first electrode is closer to the substrate than the second electrode; A conductive pattern is closer to the substrate than the second electrode, the second electrode is coupled to the conductive pattern, and the conductive pattern is coupled to the shielded signal line; The shielded signal line is configured to transmit a DC signal; the driving circuit is configured to provide a driving signal to the plurality of pixel circuits in response to a first signal received at the first signal line and a second signal received at the second signal line, so as to drive the plurality of pixel circuits to operate.
2. The display panel of claim 1, wherein, Along a direction perpendicular to the plane of the substrate, the bottom surface of the groove is closer to the substrate than the top surface of at least one of the first signal line and the second signal line.
3. The display panel of claim 1, wherein, The first signal line and the second signal line are adjacent to each other; The width of the orthographic projection of the bottom surface of the groove onto the substrate is less than or equal to the distance between two adjacent edges of the first signal line and the second signal line in their orthographic projections onto the substrate.
4. The display panel of claim 1, wherein, The width of the orthographic projection of the bottom surface of the groove onto the substrate is 2μm to 10μm.
5. The display panel of claim 1, wherein, The orthographic projection of the shielded signal line on the substrate overlaps the orthographic projections of the first signal line and the second signal line on the substrate.
6. The display panel of claim 1, wherein, The shielded signal line is located within the peripheral area and surrounds the display area.
7. The display panel of claim 1, wherein, The first signal line is configured to transmit a first signal; the second signal line is configured to transmit a second signal; both the first signal and the second signal are pulse signals, and the first signal and the second signal are different.
8. The display panel of claim 7, wherein, The first signal and the second signal have the same pulse period; the first signal and the second signal have a phase difference.
9. The display panel of claim 8, wherein, The pulse period is 4μs~100μs.
10. The display panel of claim 1, wherein, The first electrode of the light-emitting device is disposed in the same layer as the shielded signal line; The insulating layer has a double-layer structure.
11. The display panel of claim 1, wherein, The first electrode of the light-emitting device is farther away from the substrate than the shielding signal line; The insulating layer has a single-layer structure.
12. A display device, characterized by comprising: include: The display panel as described in any one of claims 1 to 11; The control chip is coupled to the display panel; The control chip is configured to provide signals to the display panel.
13. A method for manufacturing a display panel, characterized by, include: A substrate is provided, the substrate having a display area and a peripheral area located outside the display area; At least one first signal line and at least one second signal line are formed in the peripheral region of the substrate; the extension direction of the first signal line and the extension direction of the second signal line are the same. An insulating layer is formed, the insulating layer covering the at least one first signal line and the at least one second signal line; at least one groove is formed on the surface of the insulating layer on the side away from the substrate; the orthographic projection of the bottom surface of the groove on the substrate lies between the orthographic projections of the first signal line and the second signal line on the substrate; The groove extends along the extending directions of the first signal line and the second signal line; A shielded signal line is formed, the shielded signal line covering the at least one groove; The display panel includes: Multiple pixel circuits are disposed on the substrate and located within the display area; A driving circuit is disposed on the substrate and located within the peripheral region; the driving circuit is coupled to the plurality of pixel circuits, the first signal line and the second signal line respectively. Multiple light-emitting devices are disposed on the substrate and located within the display area; each light-emitting device includes a first electrode and a second electrode; the first electrode is closer to the substrate than the second electrode; A conductive pattern is closer to the substrate than the second electrode, the second electrode is coupled to the conductive pattern, and the conductive pattern is coupled to the shielded signal line; The shielded signal line is configured to transmit a DC signal; the driving circuit is configured to provide a driving signal to the plurality of pixel circuits in response to a first signal received at the first signal line and a second signal received at the second signal line, so as to drive the plurality of pixel circuits to operate.
14. The method of claim 13, wherein, The formation of the insulating layer includes: An insulating material layer is formed on the side of the at least one first signal line and the at least one second signal line away from the substrate; A photoresist layer is formed on the insulating material layer; The photoresist layer is exposed using a halftone mask, and the photoresist layer is developed to form a photoresist layer completely removed area, a photoresist layer partially retained area, and a photoresist layer completely retained area. The insulating material layer is etched to remove the portion of the insulating material layer located in the area where the photoresist layer has been completely removed; An ashing process is used to remove the portion of the photoresist layer located in the semi-retained region of the photoresist layer. The portion of the insulating material layer located in the semi-retained area of the photoresist layer is etched to form the at least one groove; The remaining photoresist layer is peeled off to obtain the insulating layer.