Dram testing method, apparatus, readable storage medium, and electronic device

Abstract

The application discloses a DRAM test method, device, readable storage medium and electronic equipment, through two rounds of tests on the DRAM to be tested, each first preset read-write unit of the DRAM to be tested is traversed based on a preset interval and a preset test unit until all storage units of the DRAM to be tested are traversed, for the target test unit traversed, data read-write operation is performed on the target test unit based on preset test data, the read data is compared with the corresponding written data, the final test result is obtained through the comparison result of the two rounds of tests, the non-continuous access mode with a certain interval can be simulated, the previous test blind area is covered and the chip defects which are difficult to be found in the prior art are detected, the multi-storage unit faults such as bridge faults and coupling faults are excited, the fault coverage is improved, the reliability of the test result is enhanced, and therefore the product yield is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of DRAM chip testing, and in particular to a DRAM testing method and device, readable storage medium and electronic equipment. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is an indispensable component of modern computer systems, which can be applied to Double Data Rate (DDR) modules for personal computers or servers and Low Power Double Data Rate (LPDDR) chips for embedded ARM architecture.

[0003] The basic storage unit of LPDDR is a cell, and computers and embedded systems store and read data by writing high or low levels in the cell.

[0004] In addition, current DRAM uses burst read and write mode for efficient access rate, that is, read and write operations in a memory array are performed in units of burst length (BL), and a plurality of bit (such as 8 bits, 16 bits or 32 bits) column addresses are read and written at a time, and data composed of 0 and 1 is accessed in each burst length. For example, the addressed address is 0 row, and the burst length is 8 bits, so 1 bit of data is written to each bit in the space from 0 row 0 column to 0 row 7 column, a total of 8 bits, the second burst length is from 0 row 8 column to 15 column, and so on. When the memory locations of a row are all written, the Memory Controller (MC) positions the address of the next row and continues the same operation.

[0005] In actual use, random access of the memory occupies a certain proportion, and compared with continuous access, the addresses obtained by random access have a certain uncertainty. In the failure model of the memory, some faults are more likely to be triggered by non-continuous access, such as coupling fault (CF). In order to fit the use case, in the testing process, the actual memory faults existing in the actual use need to be triggered with a greater probability, and a non-continuous access mode with a certain interval needs to be used. SUMMARY

[0006] The technical problem solved by the present application is to provide a DRAM testing method, device, readable storage medium and electronic equipment, which can improve the coverage rate of faults when testing DRAM.

[0007] To solve the above technical problems, a technical solution adopted by the present application is:

[0008] A DRAM testing method, comprising the steps of:

[0009] performing two rounds of testing on the DRAM to be tested to obtain a first comparison result and a second comparison result respectively;

[0010] the testing comprises:

[0011] writing preset test data to the DRAM to be tested until all memory cells of the DRAM to be tested are written with data;

[0012] traversing each first preset read-write cell of the DRAM to be tested in a preset test unit based on a preset interval until all memory cells of the DRAM to be tested are traversed;

[0013] for a target test cell traversed, performing data read-write operation on the target test cell based on the preset test data, and comparing the read data with the corresponding written data;

[0014] the first preset read-write cells of the first round of testing and the second round of testing are different;

[0015] obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result.

[0016] In order to solve the above technical problems, another technical solution adopted by the present application is:

[0017] A DRAM testing device, comprising:

[0018] a data read-write module, configured to perform two rounds of testing on the DRAM to be tested to obtain a first comparison result and a second comparison result respectively;

[0019] the testing comprises:

[0020] writing preset test data to the DRAM to be tested until all memory cells of the DRAM to be tested are written with data;

[0021] traversing each first preset read-write cell of the DRAM to be tested in a preset test unit based on a preset interval until all memory cells of the DRAM to be tested are traversed;

[0022] for a target test cell traversed, performing data read-write operation on the target test cell based on the preset test data, and comparing the read data with the corresponding written data;

[0023] the first preset read-write cells of the first round of testing and the second round of testing are different;

[0024] a test module configured to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result.

[0025] To solve the above technical problems, the present application adopts another technical solution:

[0026] A computer readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement each step of the DRAM test method.

[0027] To solve the above technical problems, the present application adopts another technical solution:

[0028] An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing each step of the DRAM test method when executing the computer program.

[0029] The present application has the beneficial effects that: by performing two rounds of testing on the DRAM to be tested, each first preset read-write unit of the DRAM to be tested is traversed based on a preset interval and in units of a preset test unit until all storage units of the DRAM to be tested are traversed, for a target test unit that is traversed, data read-write operations are performed on the target test unit based on the preset test data, the read data is compared with the corresponding written data, and the final test result is obtained through the comparison results of the two rounds of testing. Since partial faults are more likely to be triggered using non-continuous access, each first preset read-write unit of the DRAM to be tested is traversed based on a preset interval and in units of a preset test unit, which can simulate a non-continuous access mode with a certain interval, cover the previous test blind area and detect chip defects that are difficult to be found in the prior art, trigger multi-storage unit faults such as bridge faults and coupling faults, improve the fault coverage rate, and enhance the reliability of the test result, thereby improving the product yield. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A step flowchart of a DRAM test method according to an embodiment of the present application;

[0031] Figure 2 A structural schematic diagram of a DRAM test device according to an embodiment of the present application;

[0032] Figure 3 A structural schematic diagram of an electronic device according to an embodiment of the present application;

[0033] Figure 4 A schematic diagram of preset test data and the inverse of the preset test data in a DRAM test method according to an embodiment of the present application;

[0034] Figure 5 A flow chart of a test procedure in a DRAM test method of an embodiment of the present application;

[0035] Figure 6 A schematic diagram of a memory array of a DRAM to be tested in a DRAM test method of an embodiment of the present application;

[0036] Figure 7 A schematic diagram of a preset test cell traversal order in a first round of testing in a DRAM test method of an embodiment of the present application;

[0037] Figure 8 A schematic diagram of a preset test cell traversal order in a second round of testing in a DRAM test method of an embodiment of the present application;

[0038] Figure 9 A schematic diagram of a first traversal of all rows of a memory array in a DRAM test method of an embodiment of the present application;

[0039] Figure 10 A schematic diagram of a second traversal of all rows of a memory array in a DRAM test method of an embodiment of the present application;

[0040] Figure 11 A schematic diagram of a third traversal of all rows of a memory array in a DRAM test method of an embodiment of the present application;

[0041] Figure 12 A schematic diagram of a fourth traversal of all rows of a memory array in a DRAM test method of an embodiment of the present application;

[0042] Figure 13 A schematic diagram of a first traversal of all columns of a memory array in a DRAM test method of an embodiment of the present application;

[0043] Figure 14 A schematic diagram of a second traversal of all columns of a memory array in a DRAM test method of an embodiment of the present application;

[0044] Figure 15 A schematic diagram of a third traversal of all columns of a memory array in a DRAM test method of an embodiment of the present application;

[0045] Figure 16 A schematic diagram of a fourth traversal of all columns of a memory array in a DRAM test method of an embodiment of the present application. DETAILED DESCRIPTION

[0046] To make the technical contents, purposes and effects of the present application clear, the following will be described in detail in conjunction with the embodiments and the accompanying drawings.

[0047] Please refer toFigure 1 The embodiment of the present application provides a DRAM testing method, comprising the steps of:

[0048] Two rounds of testing are performed on the DRAM to be tested, and a first comparison result and a second comparison result are obtained respectively;

[0049] The testing comprises:

[0050] The preset test data is written into the DRAM to be tested until all the storage units of the DRAM to be tested are written with data;

[0051] Each first preset read-write unit of the DRAM to be tested is traversed based on a preset interval and in a preset test unit until all the storage units of the DRAM to be tested are traversed;

[0052] For a target test unit traversed, data read-write operation is performed on the target test unit based on the preset test data, and the read data is compared with the corresponding written data;

[0053] The first preset read-write unit of the first round of testing is different from that of the second round of testing;

[0054] The test result of the DRAM to be tested is obtained according to the first comparison result and the second comparison result.

[0055] From the above description, the beneficial effects of the present application are that: through two rounds of testing on the DRAM to be tested, each first preset read-write unit of the DRAM to be tested is traversed based on a preset interval and in a preset test unit until all the storage units of the DRAM to be tested are traversed, for a target test unit traversed, data read-write operation is performed on the target test unit based on the preset test data, and the read data is compared with the corresponding written data, the final test result is obtained through the comparison results of the two rounds of testing, since the non-continuous access is more likely to trigger part of the faults, each first preset read-write unit of the DRAM to be tested is traversed based on a preset interval and in a preset test unit, the non-continuous access mode with a certain interval can be simulated, the previous testing blind area is covered and the chip defects that are difficult to be found in the prior art are detected, the multi-storage unit faults such as bridge faults and coupling faults are triggered, the fault coverage is improved, the reliability of the test result is enhanced, and thus the product yield is improved.

[0056] Further, the writing of the preset test data into the DRAM to be tested until all the storage units of the DRAM to be tested are written with data comprises:

[0057] write the preset test data from a low address of each second preset read-write unit of the DRAM to be tested in units of preset burst length until all memory cells of the DRAM to be tested are written with data.

[0058] As can be seen from the above description, by writing preset test data to the DRAM to be tested in units of burst length, the data writing speed can be improved, and the time complexity is low, which is suitable for mass production testing.

[0059] Further, the traversing each first preset read-write unit of the DRAM to be tested in units of preset test unit based on preset interval until all memory cells of the DRAM to be tested are traversed includes:

[0060] starting from a preset position of each first preset read-write unit, traversing all preset test units in each preset interval in each first preset read-write unit;

[0061] adjacent preset test units in a first preset direction in all preset test units in each preset interval in the DRAM to be tested are spaced by the preset interval, and adjacent preset test units in a second preset direction are spaced by the preset interval;

[0062] setting the preset position of each first preset read-write unit to the next position adjacent thereto, and returning to execute the step of starting from the preset position of each first preset read-write unit until all memory cells of the DRAM to be tested are traversed.

[0063] As can be seen from the above description, starting from a preset position of each first preset read-write unit, traversing all preset test units in each preset interval in each first preset read-write unit, setting the preset position of each first preset read-write unit to the next position adjacent thereto, and returning to execute the step of starting from the preset position of each first preset read-write unit until all memory cells of the DRAM to be tested are traversed simulates non-continuous access with a certain interval, realizes skip access to the DRAM to be tested, can cover the previous test blind area and detect chip defects that are difficult to be found in the prior art, excites multiple memory cell faults, and thus improves fault coverage.

[0064] Further, adjacent preset test units in a first preset direction in all preset test units in each preset interval in the DRAM to be tested are spaced by the preset interval, and adjacent preset test units in a second preset direction are spaced by the preset interval includes:

[0065] According to the preset interval, a corresponding continuous number of first preset read-write units are selected in a cycle until all first preset read-write units of the DRAM to be tested are traversed;

[0066] For each selected continuous number of first preset read-write units, the preset positions of each first preset read-write unit are sequentially incremented by one according to the sequence order of the first preset read-write units.

[0067] As can be seen from the above description, according to the preset interval, a corresponding continuous number of first preset read-write units are selected in a cycle, for each selected continuous number of first preset read-write units, the preset positions of each first preset read-write unit are sequentially incremented by one according to the sequence order of the first preset read-write units, which can ensure that the interval between adjacent preset test units in the first preset direction is a preset interval, and the interval between adjacent preset test units in the second preset direction is a preset interval. Since random access of memory occupies a certain proportion in actual use, the actual use environment of the DRAM chip by the user can be well simulated, and the reliability and accuracy of the test are ensured.

[0068] Further, the data read-write operation based on the preset test data to the target test unit includes:

[0069] reading data of the target test unit and comparing the read data with the corresponding written data;

[0070] writing the inverse of the preset test data to the target test unit, reading data of the target test unit, and comparing the read data with the corresponding written data.

[0071] As can be seen from the above description, for the traversed target test unit, the written data is first read, then the inverse of the preset test data is written, and then the written data is read, which can stimulate a single storage unit, improve fault coverage, and ensure the reliability and accuracy of the test.

[0072] Further, the first preset read-write unit includes a row or a column.

[0073] As can be seen from the above description, the test personnel can set the first preset read-write unit to be a row or a column according to needs, which is highly flexible.

[0074] Further, the test result of the DRAM to be tested according to the first comparison result and the second comparison result includes:

[0075] If the first comparison result and the second comparison result are consistent, the test result is successful; otherwise, the test result is failed.

[0076] From the above description, by obtaining the first comparison result and the second comparison result through two rounds of tests respectively, the chip defects that are difficult to find can be detected, the fault coverage during testing is improved, and the reliability of testing is ensured.

[0077] Please refer to Figure 2 Another embodiment of the present application provides a DRAM testing device, comprising:

[0078] A data read-write module is configured to perform two rounds of tests on the DRAM to be tested to obtain a first comparison result and a second comparison result respectively.

[0079] The testing comprises:

[0080] The preset test data is written into the DRAM to be tested until all the memory cells of the DRAM to be tested are written with data.

[0081] Each first preset read-write cell of the DRAM to be tested is traversed based on a preset interval and in a preset test unit until all the memory cells of the DRAM to be tested are traversed.

[0082] For a target test cell that is traversed, a data read-write operation is performed on the target test cell based on the preset test data, and the read data is compared with the corresponding written data.

[0083] The first preset read-write cells of the first round of testing and the second round of testing are different.

[0084] A testing module is configured to obtain a testing result of the DRAM to be tested according to the first comparison result and the second comparison result.

[0085] Another embodiment of the present application provides a computer readable storage medium having a computer program stored thereon, and the computer program is executed by a processor to implement each step of the above DRAM testing method.

[0086] Please refer to Figure 3 Another embodiment of the present application provides an electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor implements each step of the above DRAM testing method when executing the computer program.

[0087] The above DRAM testing method, device, computer readable storage medium, and electronic device can be applied to the testing of any type of DRAM, such as each generation of DDR and LPDDR products, which will be described in detail in the following specific embodiments.

[0088] Embodiment one

[0089] Please refer toFigure 1 The DRAM testing method of the embodiment includes the following steps:

[0090] S1. Two rounds of testing are performed on the DRAM to be tested, and first and second comparison results are obtained respectively;

[0091] The testing includes:

[0092] S11. The preset test data is written into the DRAM to be tested until all the memory cells of the DRAM to be tested are written with data;

[0093] Specifically, the preset test data is written into each second preset read-write unit of the DRAM to be tested from the low address of the second preset read-write unit in units of preset burst length until all the memory cells of the DRAM to be tested are written with data;

[0094] The second preset read-write unit can be flexibly set according to actual needs, for example, it can be set as a column or a row;

[0095] The burst length (BL) is determined by the JEDEC standard or can be freely set, that is, a plurality of bits (for example, 8 bits or 16 bits) are operated at a time to perform corresponding reading and writing. For example, when writing data based on a row, if the addressed address is 0 row and the burst length is 8 bits, the first 8 bits of the data to be written are written into the position of 0 row and 0 column at the same time, then the second burst length writes the 9-16 bits of the data to be written, and the writing is continuously performed until the memory position of 0 row is completely written. Then, the address of the next row is repositioned, and the operation of the previous row is continued until the data is completely written. Reading data is also an operation similar to this;

[0096] In the embodiment, the second preset read-write unit is a row, as shown in Figure 6 ;

[0097] For example, the preset test data is written into the first column of the first row, and after the first row is written, the preset test data is written into the first column of the second row, and so on, until each row of the DRAM to be tested is written with data;

[0098] S12. Each first preset read-write unit of the DRAM to be tested is traversed in units of preset test units based on a preset interval until all the memory cells of the DRAM to be tested are traversed;

[0099] The first preset read-write unit includes a column or a row;

[0100] Specifically, starting from the preset position of each first preset read-write unit, all preset test units in each first preset read-write unit are traversed at every preset interval;

[0101] The preset interval can be flexibly set according to actual needs.

[0102] In this embodiment, the preset interval is 3.

[0103] The preset interval is set between adjacent preset test units in a first preset direction and between adjacent preset test units in a second preset direction.

[0104] The first preset direction and the second preset direction are different, for example, the first preset direction is row and the second preset direction is column, or the first preset direction is column and the second preset direction is row.

[0105] The preset position of each first preset read-write unit is set to the next position adjacent thereto, and the step of starting from the preset position of each first preset read-write unit is executed until all storage units of the DRAM to be tested are traversed.

[0106] For example, there are 10 rows and 10 columns in the storage array, the preset interval is 2, and starting from the first column of the first row, there are 4 preset test units in the first row, and the 4 preset test units in the first row are traversed; starting from the second column of the second row, there are 3 preset test units in the second row, and the 3 preset test units in the second row are traversed; starting from the third column of the third row, there are 3 preset test units in the third row, and the 3 preset test units in the third row are traversed; starting from the first column of the fourth row, there are 4 preset test units in the fourth row, and the 4 preset test units in the fourth row are traversed, and so on, until all rows are traversed.

[0107] After the first row traversal is performed, the preset position of each row is set to the next position adjacent thereto, i.e., the preset position of the first row is set to the second position, the preset position of the second row is set to the third position, the preset position of the third row is set to the fourth position, the preset position of the fourth row is set to the second position, and so on, and the step of starting from the preset position of each first preset read-write unit is executed until all storage units of the DRAM to be tested are traversed.

[0108] For example, when performing the second traversal, the preset position of the first row is set as the second column, 3 preset test units of the first row are traversed, the preset position of the second row is set as the third column, 3 preset test units of the second row are traversed, the preset position of the third row is set as the fourth column, 4 preset test units of the third row are traversed, the preset position of the fourth row is set as the second column, 3 preset test units of the fourth row are traversed, and so on, until all rows are traversed;

[0109] The preset interval between adjacent preset test units along the first preset direction and the preset interval between adjacent preset test units along the second preset direction in every interval of preset intervals of all preset test units in the DRAM to be tested include that:

[0110] According to the preset interval, a corresponding continuous number of first preset read-write units are selected until all first preset read-write units of the DRAM to be tested are traversed;

[0111] For the continuous number of first preset read-write units selected each time, the preset positions of the first preset read-write units are sequentially increased by one according to the sequence order of the first preset read-write units;

[0112] For example, the preset interval is 4, and 5 continuous rows are selected until all rows are traversed;

[0113] For the 5 rows selected each time, if the preset position of the first row is the first one, the preset position of the second row is the second one, the preset position of the third row is the third one, the preset position of the fourth row is the fourth one, and the preset position of the fifth row is the fifth one; if the preset position of the first row is the second one, the preset position of the second row is the third one, the preset position of the third row is the fourth one, the preset position of the fourth row is the fifth one, and the preset position of the fifth row is the sixth one;

[0114] For the target test unit traversed, a data read-write operation is performed on the target test unit based on the preset test data, and the read data is compared with the corresponding written data;

[0115] Specifically, the data of the target test unit is read, and the read data is compared with the corresponding written data;

[0116] The inverse of the preset test data is written to the target test unit, the data of the target test unit is read, and the read data is compared with the corresponding written data;

[0117] After the first round of testing is completed, a second round of testing is performed, and the first preset read-write unit of the first round of testing is different from the first preset read-write unit of the second round of testing;

[0118] In this embodiment, the first preset read-write unit of the first round of testing is a row, and the first preset read-write unit of the second round of testing is a column.

[0119] S2, obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result;

[0120] If the first comparison result and the second comparison result are consistent, the test result is success; otherwise, the test result is failure.

[0121] In this embodiment, the specific reference Figures 4-16 , first, the DRAM to be tested is tested in the first round, as shown in Figure 5

[0122] This round of testing is Column Fast testing, that is, the first preset read-write unit is a row, which means that the traversal of the preset test unit is performed in the column direction first, as shown in Figure 7 , in the order of D1 to D 20 ; each traversed target test unit is subjected to a Column Fast combination operation of Read / D-Write D-Read D, which is divided into three parts, Read / D means reading the data of the target test unit, comparing the read data with / D, Write D means writing D to the target test unit, and Read D means reading the data of the target test unit, comparing the read data with D;

[0123] As shown in Figure 4 , 5 , the test data written is defined as / D=10101010……1010, and its inverse is D=01010101……0101, assuming that the preset burst length is BL=8bit, then / D=10101010, D=01010101;

[0124] S1, the address to be positioned is the 0th row and the 0th column, and test data / D is written from the storage unit corresponding to the 0th row and the 0th column starting from BL, after writing the 0th row, test data / D is written from the 1st row and the 0th column, and so on, until the entire storage array is written with data, as shown in Figure 6

[0125] S2.1, starting from (R0, C0) of R0 row, all preset test units in R0 row are traversed every 3 intervals, and Column Fast combination operation is performed on the traversed target test unit;

[0126] ​​S2.2, starting from (R1, C1) of R1 row, traversing every 3 intervals of all preset test units in R1 row, and performing Column Fast combination operation on the target test unit traversed;

[0127] S2.3, starting from (R2, C2) of R2 row, traversing every 3 intervals of all preset test units in R2 row, and performing Column Fast combination operation on the target test unit traversed;

[0128] S2.4, starting from (R3, C3) of R3 row, traversing every 3 intervals of all preset test units in R3 row, and performing Column Fast combination operation on the target test unit traversed;

[0129] As shown in FIG. 2, all rows of the storage array are sequentially traversed according to steps S2.1 to S2.4 until all rows of the storage array are traversed; Figure 9

[0130] S3.1, starting from (R0, C1) of R0 row, traversing every 3 intervals of all preset test units in R0 row, and performing Column Fast combination operation on the target test unit traversed;

[0131] S3.2, starting from (R1, C2) of R1 row, traversing every 3 intervals of all preset test units in R1 row, and performing Column Fast combination operation on the target test unit traversed;

[0132] S3.3, starting from (R2, C3) of R2 row, traversing every 3 intervals of all preset test units in R2 row, and performing Column Fast combination operation on the target test unit traversed;

[0133] S3.4, starting from (R3, C0) of R0 row, traversing every 3 intervals of all preset test units in R0 row, and performing Column Fast combination operation on the target test unit traversed;

[0134] As shown in FIG. 3, all rows of the storage array are sequentially traversed according to steps S3.1 to S3.4 until all rows of the storage array are traversed; Figure 10

[0135] S4.1, starting from (R0, C2) of R0 row, traversing every 3 intervals of all preset test units in R0 row, and performing Column Fast combination operation on the target test unit traversed;

[0136] ​​S4.2 Starting from (R1, C3) in row R1, traverse all preset test units in row R1 every 3 intervals, and perform Column Fast combination operation on the target test unit traversed.

[0137] S4.3 Starting from (R2, C0) in row R2, traverse all preset test units in row R2 every 3 intervals, and perform Column Fast combination operation on the target test unit traversed.

[0138] S4.4 Starting from (R3, C1) in row R3, traverse all preset test units in row R0 every 3 intervals, and perform Column Fast combination operation on the target test unit traversed.

[0139] like Figure 11 As shown, all rows of the storage array are traversed sequentially according to steps S4.1 to S4.4 until all rows of the storage array have been traversed;

[0140] S5.1 Starting from (R0, C3) in row R0, traverse all preset test units in row R0 every 3 intervals, and perform Column Fast combination operation on the target test unit traversed.

[0141] S5.2 Starting from (R1, C0) in row R1, traverse all preset test units in row R1 every 3 intervals, and perform Column Fast combination operation on the target test unit traversed.

[0142] S5.3 Starting from (R2, C1) in row R2, traverse all preset test units in row R2 every 3 intervals, and perform Column Fast combination operation on the target test unit traversed.

[0143] S5.4 Starting from (R3, C2) in row R3, traverse all preset test units in row R0 every 3 intervals, and perform Column Fast combination operation on the target test unit traversed.

[0144] like Figure 12 As shown, all rows of the storage array are traversed sequentially according to steps S5.1 to S5.4 until all rows of the storage array have been traversed.

[0145] Obtain the first comparison result;

[0146] like Figure 5 As shown, the second round of testing is a Row Fast test, meaning the first preset read / write unit is a column, which means that the preset test units are traversed first in the Row direction, as shown below. Figure 8As shown, the sequence of D1 to D 24 is performed; each target test cell being traversed is subjected to a Row Fast combination operation of Read D-Write / D-Read / D, which is divided into three parts, Read D refers to reading the data of the target test cell, comparing the read data with D, Write / D refers to writing / D into the target test cell, and Read / D refers to reading the data of the target test cell, comparing the read data with / D;

[0147] S6.1, starting from (R0, C0) of R0 row, traversing all preset test cells every 3 intervals in C0 column, and performing a Row Fast combination operation on the target test cell being traversed;

[0148] S6.2, starting from (R1, C1) of R1 row, traversing all preset test cells every 3 intervals in C1 column, and performing a Row Fast combination operation on the target test cell being traversed;

[0149] S6.3, starting from (R2, C2) of R2 row, traversing all preset test cells every 3 intervals in C2 column, and performing a Row Fast combination operation on the target test cell being traversed;

[0150] S6.4, starting from (R3, C3) of R3 row, traversing all preset test cells every 3 intervals in C3 column, and performing a Row Fast combination operation on the target test cell being traversed;

[0151] As shown, all columns of the storage array are sequentially traversed according to steps S6.1 to S6.4 until all columns of the storage array are traversed; Figure 13

[0152] S7.1, starting from (R1, C0) of R0 row, traversing all preset test cells every 3 intervals in C0 column, and performing a Row Fast combination operation on the target test cell being traversed;

[0153] S7.2, starting from (R2, C1) of R1 row, traversing all preset test cells every 3 intervals in C1 column, and performing a Row Fast combination operation on the target test cell being traversed;

[0154] S7.3, starting from (R3, C2) of R2 row, traversing all preset test cells every 3 intervals in C2 column, and performing a Row Fast combination operation on the target test cell being traversed;

[0155] ​S7.4, starting from (R0, C3) of R3 row, traversing all preset test units in C3 column every 3 intervals, and performing Row Fast combination operation on the target test unit traversed;

[0156] As shown in Figure 14 , all columns of the storage array are traversed in sequence according to steps S7.1 to S7.4 until all columns of the storage array are traversed;

[0157] S8.1, starting from (R2, C0) of R0 row, traversing all preset test units in C0 column every 3 intervals, and performing Row Fast combination operation on the target test unit traversed;

[0158] S8.2, starting from (R3, C1) of R1 row, traversing all preset test units in C1 column every 3 intervals, and performing Row Fast combination operation on the target test unit traversed;

[0159] S8.3, starting from (R0, C2) of R2 row, traversing all preset test units in C2 column every 3 intervals, and performing Row Fast combination operation on the target test unit traversed;

[0160] S8.4, starting from (R1, C3) of R3 row, traversing all preset test units in C3 column every 3 intervals, and performing Row Fast combination operation on the target test unit traversed;

[0161] As shown in Figure 15 , all columns of the storage array are traversed in sequence according to steps S8.1 to S8.4 until all columns of the storage array are traversed;

[0162] S9.1, starting from (R3, C0) of R0 row, traversing all preset test units in C0 column every 3 intervals, and performing Row Fast combination operation on the target test unit traversed;

[0163] S9.2, starting from (R0, C1) of R1 row, traversing all preset test units in C1 column every 3 intervals, and performing Row Fast combination operation on the target test unit traversed;

[0164] S9.3, starting from (R1, C2) of R2 row, traversing all preset test units in C2 column every 3 intervals, and performing Row Fast combination operation on the target test unit traversed;

[0165] S9.4, starting from (R3, C3) of R3 row, traversing all preset test units in C3 column every 3 intervals, and performing Row Fast combination operation on the target test unit traversed;

[0166] As shown in Figure 16 , all columns of the storage array are traversed in sequence according to steps S9.1 to S9.4 until all columns of the storage array are traversed;

[0167] The second comparison result is obtained;

[0168] If the first comparison result and the second comparison result are consistent, the test result is success; otherwise, the test result is failure.

[0169] Embodiment Two

[0170] The difference between this embodiment two and embodiment one is that the second preset read-write unit is a column, the first preset read-write unit of the first round of test is a column, the first preset read-write unit of the second round of test is a row, and the preset interval is 2;

[0171] S1, the addressed address is the 0th column and the 0th row, and test data / D is written from the storage unit corresponding to the 0th column and the 0th row according to BL, that is, test data / D is written from the 0th column and the 0th row to the 12th column and the 0th row, after writing, test data / D is written from the 0th column and the 1st row, after writing all rows from the 0th column to the 7th column, test data / D is written in all rows from the 8th column to the 13th column in the order of rows, and so on, until the entire storage array is written with data;

[0172] S2.1, starting from (R0, C0) of R0 row, traversing all preset test units in C0 column every 2 intervals, and performing Row Fast combination operation on the target test unit traversed;

[0173] S2.2, starting from (R1, C1) of R1 row, traversing all preset test units in C1 column every 2 intervals, and performing Row Fast combination operation on the target test unit traversed;

[0174] S2.3, starting from (R2, C2) of R2 row, traversing all preset test units in C2 column every 2 intervals, and performing Row Fast combination operation on the target test unit traversed;

[0175] All columns of the storage array are traversed in sequence according to steps S2.1 to S2.3 until all columns of the storage array are traversed;

[0176] S3.1, starting from (R1, C0) of R0 row, traversing every 2 intervals of all preset test units in C0 column, and performing Row Fast combination operation on the target test unit traversed;

[0177] S3.2, starting from (R2, C1) of R1 row, traversing every 2 intervals of all preset test units in C1 column, and performing Row Fast combination operation on the target test unit traversed;

[0178] S3.3, starting from (R0, C2) of R2 row, traversing every 2 intervals of all preset test units in C2 column, and performing Row Fast combination operation on the target test unit traversed;

[0179] Traverse all columns of the storage array according to steps S3.1 to S3.3 in turn until all columns of the storage array are traversed;

[0180] S4.1, starting from (R2, C0) of R0 row, traversing every 2 intervals of all preset test units in C0 column, and performing Row Fast combination operation on the target test unit traversed;

[0181] S4.2, starting from (R0, C1) of R1 row, traversing every 2 intervals of all preset test units in C1 column, and performing Row Fast combination operation on the target test unit traversed;

[0182] S4.3, starting from (R1, C2) of R2 row, traversing every 2 intervals of all preset test units in C2 column, and performing Row Fast combination operation on the target test unit traversed;

[0183] Traverse all columns of the storage array according to steps S4.1 to S4.3 in turn until all columns of the storage array are traversed;

[0184] Obtain the first comparison result;

[0185] In the second round of tests, the first preset read-write unit is the row:

[0186] S5.1, starting from (R0, C0) of R0 row, traversing every 2 intervals of all preset test units in R0 row, and performing Column Fast combination operation on the target test unit traversed;

[0187] S5.2, starting from (R1, C1) of R1 row, traversing every 2 intervals of all preset test units in R1 row, and performing Column Fast combination operation on the target test unit traversed;

[0188] S5.3, starting from (R2, C2) of the R2 row, traversing every 2 preset test units in the R2 row, and performing a Column Fast combination operation on a target test unit traversed;

[0189] The steps S5.1 to S5.3 are sequentially performed on all rows of the storage array until all rows of the storage array are traversed;

[0190] S6.1, starting from (R0, C1) of the R0 row, traversing every 2 preset test units in the R0 row, and performing a Column Fast combination operation on a target test unit traversed;

[0191] S6.2, starting from (R1, C2) of the R1 row, traversing every 2 preset test units in the R1 row, and performing a Column Fast combination operation on a target test unit traversed;

[0192] S6.3, starting from (R2, C0) of the R2 row, traversing every 2 preset test units in the R2 row, and performing a Column Fast combination operation on a target test unit traversed;

[0193] The steps S6.1 to S6.3 are sequentially performed on all rows of the storage array until all rows of the storage array are traversed;

[0194] S7.1, starting from (R0, C2) of the R0 row, traversing every 2 preset test units in the R0 row, and performing a Column Fast combination operation on a target test unit traversed;

[0195] S7.2, starting from (R1, C0) of the R1 row, traversing every 2 preset test units in the R1 row, and performing a Column Fast combination operation on a target test unit traversed;

[0196] S7.3, starting from (R2, C1) of the R2 row, traversing every 2 preset test units in the R2 row, and performing a Column Fast combination operation on a target test unit traversed;

[0197] The steps S7.1 to S7.3 are sequentially performed on all rows of the storage array until all rows of the storage array are traversed;

[0198] A second comparison result is obtained;

[0199] If the first comparison result and the second comparison result are consistent, the test result is success; otherwise, the test result is failure.

[0200] Embodiment three

[0201] Please refer to Figure 2 A DRAM testing device, comprising:

[0202] A data read-write module, configured to perform two rounds of testing on the DRAM to be tested, and obtain a first comparison result and a second comparison result respectively.

[0203] The testing comprises:

[0204] The testing comprises:

[0205] The testing comprises:

[0206] The testing comprises:

[0207] The testing comprises:

[0208] The testing comprises:

[0209] Embodiment four

[0210] A computer readable storage medium, having a computer program stored thereon, wherein the computer program, when executed by a processor, can implement each step of the DRAM testing method in Embodiment one or Embodiment two.

[0211] Embodiment five

[0212] Please refer to Figure 3 An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor, when executing the computer program, implements each step of the DRAM testing method in Embodiment one or Embodiment two.

[0213] In summary, the DRAM detection method, device, readable storage medium and electronic equipment provided by the application can improve the data writing speed and reduce the time complexity, and are convenient for mass production testing. The preset position of each first preset read-write unit is set as the next position adjacent thereto, and the step of starting from the preset position of each first preset read-write unit is returned to be executed until all the memory cells of the DRAM to be tested are traversed, thereby simulating discontinuous access with a certain interval. For the target test cell traversed, the data of the target test cell is read first, and the read data is compared with the corresponding written data. Then, the inverse of the preset test data is written to the target test cell, and the data of the target test cell is read, and the read data is compared with the corresponding written data, so that a single memory cell can be excited. Since random access of the memory occupies a certain proportion in actual use, skip access is realized for the DRAM to be tested, the actual use environment of the user for the DRAM chip can be well simulated, the previous test blind area is covered, and chip defects that are difficult to be found in the prior art are detected, so that multi-memory cell faults such as bridge faults and coupling faults are excited, the fault coverage is improved, the reliability of the test result is enhanced, and the product yield is improved.

[0214] In the above-described embodiments provided in the present application, it should be understood that the disclosed method, device, computer readable storage medium and electronic equipment can be implemented in other manners. For example, the above-described device embodiments are merely illustrative. For example, the division of the modules is merely a logical function division. In actual implementation, another division manner can be adopted. For example, a plurality of components or modules can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the above-described modules can be indirect coupling or communication connection through some interfaces, devices or components or modules, and can be electrical, mechanical or in other forms.

[0215] The components described as separate components may or may not be physically separate, and the components shown as components may or may not be physical modules, i.e., they may be located in one place or distributed on multiple network modules. Some or all of the components can be selected as needed to achieve the purpose of the embodiment.

[0216] In addition, the functional modules in each embodiment of the application can be integrated into one processing module, or each component can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be realized in the form of hardware or in the form of a software functional module.

[0217] The integrated module, if realized in the form of a software functional module and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various program code storage media.

[0218] It should be noted that for the foregoing method embodiments, in order to facilitate description, they are all described as a combination of a series of actions, but those skilled in the art should know that the application is not limited by the order of the described actions, because according to the application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily essential to the application.

[0219] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0220] The above is only an embodiment of the application, and does not limit the patent scope of the application, and any equivalent transformation or direct or indirect application in related technical fields based on the content of the specification and drawings of the application is also included in the patent protection scope of the application.

Claims

1. A DRAM testing method, characterized in that, Including the following steps: The DRAM to be tested was subjected to two rounds of testing, and the first comparison result and the second comparison result were obtained respectively. The tests include: Preset test data is written to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data; Based on a preset interval, each first preset read / write unit of the DRAM to be tested is traversed in a preset test unit until all memory units of the DRAM to be tested have been traversed. For each target test unit traversed, data read and write operations are performed on the target test unit based on the preset test data, and the read data is compared with the corresponding written data. The first preset read / write unit is different between the first round of testing and the second round of testing; The test results of the DRAM to be tested are obtained based on the first comparison result and the second comparison result; The step of traversing each first preset read / write unit of the DRAM under test based on a preset interval and in units of preset test units until all memory units of the DRAM under test have been traversed includes: Starting from the preset position of each first preset read / write unit, all preset test units in each first preset read / write unit at each preset interval are traversed; In the DRAM to be tested, among all the preset test units spaced at a preset interval, adjacent preset test units along the first preset direction are spaced at the preset interval, and adjacent preset test units along the second preset direction are spaced at the preset interval. Set the preset position of each of the first preset read / write units to the next position adjacent to it, and return to execute the steps starting from the preset position of each of the first preset read / write units until all memory cells of the DRAM to be tested have been traversed. In the DRAM to be tested, the preset interval is the distance between adjacent preset test units along a first preset direction, and the preset interval is the distance between adjacent preset test units along a second preset direction, including: According to the preset interval, a corresponding number of consecutive first preset read / write units are selected cyclically until all first preset read / write units of the DRAM to be tested have been traversed; For each consecutive number of first preset read / write units selected, the preset positions of each first preset read / write unit are sequentially incremented by one according to the sequence number of the first preset read / write units.

2. The DRAM testing method according to claim 1, characterized in that, The process of writing preset test data into the DRAM under test until all memory cells of the DRAM under test have been written with data includes: The preset test data is written starting from the low-order address of each second preset read / write cell of the DRAM under test, in units of a preset burst length, until all memory cells of the DRAM under test have been written with data.

3. The DRAM testing method according to claim 1, characterized in that, The step of performing data read / write operations on the target test unit based on the preset test data, and comparing the read data with the corresponding written data, includes: Read the data from the target test unit and compare the read data with the corresponding written data; Write the inverse of the preset test data to the target test unit, and read the data of the target test unit, comparing the read data with the corresponding written data.

4. A DRAM testing method according to any one of claims 1 to 3, characterized in that, The first preset read / write unit includes rows or columns.

5. A DRAM testing method according to any one of claims 1 to 3, characterized in that, The process of obtaining the test results of the DRAM to be tested based on the first comparison result and the second comparison result includes: If both the first comparison result and the second comparison result are consistent, the test result is successful; otherwise, the test result is unsuccessful.

6. A DRAM testing apparatus, characterized in that, include: The data read / write module is used to perform two rounds of testing on the DRAM under test, and obtain the first comparison result and the second comparison result respectively. The tests include: Preset test data is written to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data; Based on a preset interval, each first preset read / write unit of the DRAM to be tested is traversed in a preset test unit until all memory units of the DRAM to be tested have been traversed. For each target test unit traversed, data read and write operations are performed on the target test unit based on the preset test data, and the read data is compared with the corresponding written data. The first preset read / write unit is different between the first round of testing and the second round of testing; The testing module is used to obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result; The step of traversing each first preset read / write unit of the DRAM under test based on a preset interval and in units of preset test units until all memory units of the DRAM under test have been traversed includes: Starting from the preset position of each first preset read / write unit, all preset test units in each first preset read / write unit at each preset interval are traversed; In the DRAM to be tested, among all the preset test units spaced at a preset interval, adjacent preset test units along the first preset direction are spaced at the preset interval, and adjacent preset test units along the second preset direction are spaced at the preset interval. Set the preset position of each of the first preset read / write units to the next position adjacent to it, and return to execute the steps starting from the preset position of each of the first preset read / write units until all memory cells of the DRAM to be tested have been traversed. In the DRAM to be tested, the preset interval is the distance between adjacent preset test units along a first preset direction, and the preset interval is the distance between adjacent preset test units along a second preset direction, including: According to the preset interval, a corresponding number of consecutive first preset read / write units are selected cyclically until all first preset read / write units of the DRAM to be tested have been traversed; For each consecutive number of first preset read / write units selected, the preset positions of each first preset read / write unit are sequentially incremented by one according to the sequence number of the first preset read / write units.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the various steps of the DRAM testing method as described in any one of claims 1 to 5.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements each step of the DRAM testing method as described in any one of claims 1 to 5.

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