Method for obtaining test algorithm fault coverage and related device

Abstract

The present disclosure provides a method for obtaining fault coverage of a test algorithm and related equipment, and belongs to the technical field of semiconductor integrated circuit testing. The method comprises: obtaining a fault characteristic equation of a fault model of an object to be tested; obtaining an algorithm logic equation of a test algorithm; and determining whether the test algorithm covers the fault model according to the algorithm logic equation and the fault characteristic equation. The present disclosure provides a scheme for obtaining fault coverage of a test algorithm with low cost and high efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor integrated circuit testing technology, and more specifically, to a method for obtaining fault coverage of a test algorithm, an apparatus for obtaining fault coverage of a test algorithm, a computer device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] With technological advancements, the increasing density of memory has brought greater challenges to memory testing. As semiconductor process dimensions continue to shrink, the types of potential memory failures are becoming more diverse, leading to a sharp increase in testing time and costs. Therefore, research into memory testing methods is receiving increasing attention. Within acceptable testing cost and time constraints, accurate fault models and effective testing algorithms are crucial; the selection of memory testing algorithms and the implementation methods are key aspects of memory testing.

[0003] The development of memory (e.g., RAM) failure models is an ongoing process, which has led to many test algorithm designs not taking into account the latest failures, resulting in unclear memory failure coverage capabilities of the test algorithms.

[0004] In related technologies, one method for analyzing the coverage capability of test algorithms is for experienced individuals to perform manual analysis, which results in high costs and low efficiency. Summary of the Invention

[0005] The purpose of this disclosure is to provide a method, apparatus, computer device, computer-readable storage medium, and computer program product for obtaining test algorithm fault coverage, which can at least reduce the cost of obtaining test algorithm fault coverage and improve the efficiency of obtaining test algorithm fault coverage.

[0006] This disclosure provides a method for obtaining the fault coverage of a test algorithm, comprising: obtaining the fault characteristic formula of the fault model of the object under test; obtaining the algorithm logic formula of the test algorithm; and determining whether the test algorithm covers the fault model based on the algorithm logic formula and the fault characteristic formula.

[0007] This disclosure provides an apparatus for obtaining the fault coverage of a test algorithm, comprising: an obtaining unit for obtaining fault characteristic expressions of a fault model of a test object; the obtaining unit further for obtaining the algorithmic logic expression of the test algorithm; and a processing unit for determining whether the test algorithm covers the fault model based on the algorithmic logic expression and the fault characteristic expressions.

[0008] This disclosure provides a computer device including a processor, a memory, and an input / output interface. The processor is connected to both the memory and the input / output interface. The input / output interface is used to receive and output data. The memory is used to store a computer program. The processor is used to invoke the computer program to cause the computer device containing the processor to execute the method for obtaining the fault coverage of a test algorithm according to any embodiment of this disclosure.

[0009] This disclosure provides a computer-readable storage medium storing a computer program adapted to be loaded and executed by a processor, such that a computer device having the processor performs a method for obtaining fault coverage of a test algorithm according to any embodiment of this disclosure.

[0010] This disclosure provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods provided in various alternative embodiments of this disclosure.

[0011] This disclosure provides a method, apparatus, computer device, computer-readable storage medium, and computer program product for obtaining fault coverage of a test algorithm through some embodiments. By obtaining the fault characteristic formula of the fault model of the object under test and the algorithm logic formula of the test algorithm, it is possible to determine whether the test algorithm covers the fault model based on the obtained algorithm logic formula and fault characteristic formula. This method can be implemented automatically without the need for manual analysis, thus improving efficiency and reducing costs. Attached Figure Description

[0012] Figure 1 This is a network interaction architecture diagram of a method for obtaining fault coverage of a test algorithm provided in an embodiment of this disclosure.

[0013] Figure 2 This is a flowchart of a method for obtaining fault coverage of a test algorithm in an exemplary embodiment of this disclosure.

[0014] Figure 3 This is a schematic diagram of the March (progressive algorithm) C-algorithm in an exemplary embodiment of this disclosure.

[0015] Figure 4 This is a state diagram of a normal unit in an exemplary embodiment of this disclosure, as well as state diagrams of SA0 fault and SA1 fault.

[0016] Figure 5This is a flowchart of a method for obtaining fault coverage of a test algorithm in another exemplary embodiment of this disclosure.

[0017] Figure 6 This is a flowchart of a method for obtaining fault coverage of a test algorithm in yet another exemplary embodiment of this disclosure.

[0018] Figure 7 This is a schematic diagram illustrating the fault coverage capability of the March C-algorithm in an exemplary embodiment of this disclosure.

[0019] Figure 8 This is a flowchart of a method for obtaining fault coverage of a test algorithm in another exemplary embodiment of this disclosure.

[0020] Figure 9 This is a flowchart of a method for obtaining fault coverage of a test algorithm in another exemplary embodiment of this disclosure.

[0021] Figure 10 This is a flowchart of a method for obtaining fault coverage of a test algorithm in another exemplary embodiment of this disclosure.

[0022] Figure 11 This is a schematic diagram illustrating the fault coverage capability of the March-class algorithm in another exemplary embodiment of this disclosure.

[0023] Figure 12 This is a schematic diagram of a coverage capability model in an exemplary embodiment of this disclosure.

[0024] Figure 13 This is a schematic diagram of a fault selection algorithm based on a coverage capability model in an exemplary embodiment of this disclosure.

[0025] Figure 14 This is a schematic diagram of the structure of an apparatus for obtaining the fault coverage of a test algorithm in an exemplary embodiment of this disclosure.

[0026] Figure 15 This is a schematic diagram of the structure of a computer device provided in an embodiment of this disclosure. Detailed Implementation

[0027] It should be understood that "several" in this article refers to one or more, and "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0028] Figure 1 This is a schematic diagram of the operating environment in some embodiments of this disclosure. For example... Figure 1As shown, each user's terminal device (i.e., user device 104, which may include user devices 104a, 104b and 104c, for example) is connected to server 112 via network 106.

[0029] When a user inputs a fault model and a test algorithm through user device 104 (which can be any one or more of user devices 104a, 104b, and 104c), user device 104 sends the fault model and test algorithm to server 112 through network 106.

[0030] In some embodiments, server 112 may receive a fault model and a test algorithm sent by user equipment 104, determine a fault characteristic formula based on the fault model, determine an algorithm logic formula based on the test algorithm, determine whether the test algorithm can cover the fault model based on the fault characteristic formula and the algorithm logic formula, and return the result of whether the test algorithm can cover the fault model to user equipment 104 for display on the display screen of user equipment 104.

[0031] In other embodiments, server 112 may also return the fault characteristic formula and algorithm logic formula to user equipment 104, and user equipment 104 may determine whether the test algorithm can cover the fault model based on the fault characteristic formula and algorithm logic formula.

[0032] In some other embodiments, the user equipment 104 may determine the fault characteristic formula based on the fault model, determine the algorithm logic formula based on the test algorithm, and determine whether the test algorithm can cover the fault model based on the fault characteristic formula and the algorithm logic formula.

[0033] In this embodiment of the disclosure, server 112 may be the server where the application installed on the user device is located, or it may belong to the user device (i.e., the background of the user device), etc., and there is no limitation here.

[0034] The user equipment can be a mobile phone (such as user equipment 104c) or a laptop computer (such as user equipment 104b), or a playback device in a vehicle (such as user equipment 104a), etc., and there are no restrictions here. Figure 1 The user equipment described herein is only a portion of the equipment exemplified, and the user equipment in this disclosure is not limited to this. Figure 1 The equipment listed in the text.

[0035] It is understood that the user equipment mentioned in the embodiments of this disclosure can be a computer device, and the computer device in the embodiments of this disclosure includes, but is not limited to, terminal devices or servers. In other words, the computer device can be a server or a terminal device, or a system composed of a server and a terminal device. Optionally, the data involved in the embodiments of this disclosure can be stored in the computer device, or the data can be stored based on cloud storage technology, without limitation.

[0036] Please refer to Figure 2 The diagram illustrates a flowchart of a method for obtaining fault coverage of a test algorithm according to an exemplary embodiment of this disclosure. This method can be performed by a computer device, such as a terminal device and / or a server.

[0037] The fault coverage of the test algorithm in this disclosure refers to the ratio between the number of fault types that the test algorithm can detect among a number of (two or more) memory (e.g., memory, which will be used as an example below, but this disclosure is not limited to this) faults and the total number of memory fault types.

[0038] like Figure 2 As shown, the method provided in this disclosure embodiment may include:

[0039] In S210, the fault characteristic formula of the fault model of the object under test is obtained.

[0040] In this embodiment of the disclosure, the object under test may include any type of memory, such as RAM (Random Access Memory).

[0041] A RAM model can include a memory array, read / write circuitry, data registers, row decoding circuitry, column decoding circuitry, memory address registers, and refresh logic. Therefore, RAM failures can include decoder failures, read / write logic module failures, and memory cell array failures.

[0042] RAM can further include SRAM (Static Random-Access Memory) and DRAM (Dynamic Random-Access Memory).

[0043] Taking SRAM as an example, the fault models of SRAM can include fixed faults or fixed-type faults (Stuck at Fault, stuck at 1 / 0, also known as sticky faults), open faults (Stuck open Fault, WL (word line) open), transition faults (TF, BL (bit line) open), coupling faults (CF, short circuit between data), etc.

[0044] A fixed fault (SAF) refers to a memory array cell where the value is fixed at 0 (SA0, Stuck-At-0) or 1 (SA1, Stuck-At-1), and cannot be changed regardless of any operation performed. A fixed fault can be detected by writing 0 to the memory cell under test and then reading it back out, followed by writing 1 and reading it back out.

[0045] A transition fault (also known as a transition failure, TF) refers to a situation where a memory cell in a memory array malfunctions during read / write operations, preventing data from being written and thus preventing a normal transition, such as a 0-1 transition. Specifically, the value in the memory cell cannot transition from 0 to 1 (TF(0->1)) or from 1 to 0 (TF(1->0)). Transition faults can be detected by writing a 1-to-0 transition and then reading back 0, followed by writing a 0-to-1 transition and then reading back 1.

[0046] Coupling faults (CF) refer to situations in a memory array where parasitic effects cause signal interference, resulting in a change in the value of one memory cell leading to a change in the value of another memory cell (called a coupled cell). CF can be further categorized into the following types:

[0047] 1) Inversion fault (CFin): The coupled unit undergoes a state change opposite to that of the storage unit;

[0048] 2) Idempotent coupling fault (CFid): When the value of a memory cell changes, the value of the coupled cell changes to a specific value (0 or 1);

[0049] 3) State-coupled fault (CFst: state): A specific state of a memory cell causes the coupled cell to jump to a certain state (0 or 1);

[0050] 4) Bridging Faults (BF): These faults are mainly caused by short circuits or bridging between two or more units, and are usually triggered by a specific value. Bridging coupling faults are further divided into "AND bridging faults (ABF)" and "OR bridging faults (OBF)," whose behavior is similar to "AND logic" and "OR logic," respectively.

[0051] 5) Dynamic Coupling Fault (CFdyn).

[0052] Coupling faults can be detected by performing write and read operations on all memory cells in ascending order first, and then in descending order.

[0053] In this embodiment of the disclosure, the read-write access sequence required to detect the fault model is referred to as the fault characteristic formula of the fault model. For example, the read-write access sequence required to detect each memory fault is referred to as the fault characteristic formula of the corresponding memory fault.

[0054] In S220, the algorithm logic formula for the test algorithm is obtained.

[0055] In this embodiment of the disclosure, the read and write access sequences that different test algorithms can generate are referred to as the algorithmic logic formulas of the corresponding test algorithms.

[0056] In an exemplary embodiment, the testing algorithm may include a March-type algorithm. March-type algorithms can include various March algorithms. The March algorithm is an algorithm based on a memory fault model, offering high coverage and relatively convenient detection. It has evolved and improved based on fault type detection, forming many variations of the March algorithm. These different types of March algorithm variations are collectively referred to as March-type algorithms. These variations of the March algorithm access each memory cell using different methods, performing corresponding operations each time a read or write operation is performed. Different traversal methods during the detection process will detect different fault types, and the time consumption will also vary. The March algorithm has low time complexity and high fault coverage, making it easy to implement BIST (Built-in SelfTest), suitable for application in memory testing. It should be noted that although the following embodiments use March-type algorithms as examples, this disclosure does not limit the type of testing algorithm; any algorithm capable of implementing memory fault detection can be used.

[0057] In S230, based on the algorithm logic formula and the fault characteristic formula, it is determined whether the test algorithm covers the fault model.

[0058] In this embodiment of the disclosure, it can be determined whether the test algorithm can cover the corresponding fault model by judging whether the algorithm logic formula of the test algorithm matches the fault characteristic formula of the fault model.

[0059] The method for obtaining fault coverage of a test algorithm provided in this embodiment obtains the fault characteristic formula of the fault model of the object under test and the algorithm logic formula of the test algorithm. Thus, it can determine whether the test algorithm covers the fault model based on the obtained algorithm logic formula and fault characteristic formula. This method can be implemented automatically without manual analysis, thereby improving efficiency and reducing costs.

[0060] The March algorithm can be a finite sequence of several march elements (MEs):

[0061] 1. ME is specified by address direction and some read / write operations.

[0062] 2. All operations on the ME element are completed before proceeding to the next address, and consist of the following:

[0063] W: Write operation; R: Read operation

[0064] ↑: Address increment (from 0 to M, where M is a positive integer greater than or equal to 1, and M is the number of memory units to be read / written).

[0065] ↓: Addresses decrease (from M to 0)

[0066] Address incrementing or address decrementing

[0067] 0: pattern 1: the opposite of 0

[0068] The March algorithm can include the March C algorithm, the March C- algorithm, and the March C+ algorithm, and can be implemented using a state machine.

[0069] Figure 3 The description of the March C-algorithm consists of 6 MEs, assuming the test range is 0-100 (i.e., M=100):

[0070] The behavior of the first ME is: when the address direction is random, it can be set to increment or decrement. Taking address increment as an example, address 0 is written with a value of 0; address 1 is written with a value of 0; ... until address 100 is written with a value of 0.

[0071] The behavior of the second ME is as follows: the address direction is incrementing. The value is read from address 0, and it is determined whether it is 0. Then, a value of 1 is written to address 0. The value is read from address 1, and it is determined whether it is 0. Then, a value of 1 is written to address 1. ... until the value is read from address 100, and it is determined whether it is 0. Then, a value of 1 is written to address 100.

[0072] The behavior of the third ME is as follows: the address direction is incrementing. The value is read from address 0, and it is determined whether it is a 1 value. Then, a 0 value is written to address 0. The value is read from address 1, and it is determined whether it is a 1 value. Then, a 0 value is written to address 1. ... until the value is read from address 100, and it is determined whether it is a 1 value. Then, a 0 value is written to address 100.

[0073] The behavior of the fourth ME is the same as that of the second ME, except that the address direction is decreasing, that is, it starts from address 100 and ends at address 0.

[0074] The behavior of the fifth ME is the same as that of the third ME, except that the address direction is decreasing, that is, it starts from address 100 and ends at address 0.

[0075] The behavior of the sixth ME is: when the address direction is random, it can be set to increment or decrement. Taking address increment as an example, the value is read from address 0 and it is determined whether it is 0; the value is read from address 1 and it is determined whether it is 0; ... until the value is read from address 100 and it is determined whether it is 0.

[0076] In related technologies, each memory element (ME) of the test algorithm is manually analyzed. However, due to the large number of faults and limited manpower, this method is difficult to guarantee efficiency and has incalculable costs. Extending it to memory faults across multiple cells (storage units) is even more impractical.

[0077] Taking memory as an example, memory function failures can be divided into single-cell (only one cell) failures and multi-cell (multiple cells, assuming N cells, then it is called an N-cell failure, where N is a positive integer greater than 1) failures based on the number of memory cells involved.

[0078] Single-cell faults refer to faults that occur independently within the same memory cell and are not affected by other memory cells. Single-cell faults can include transition faults (TF), state faults (SF), write interference faults (WDF), read corruption faults (RDF), deceptive read corruption faults (DRDF), and erroneous read faults (IRF). In this embodiment, for single-cell faults, the faulty memory cell is called the Vcell (victim cell), and the Vcell is only affected by itself.

[0079] Figure 4 This describes a single-cell fault. For example... Figure 4 As shown, the state diagram of a good cell is illustrated, along with state diagrams for SA0 and SA1 faults. Figure 4 In the diagram, S0 and S1 represent two states of Vcell: S0 represents a value of 0, and S1 represents a value of 1. Under normal conditions: after S0 passes through W1 (write 1), its value becomes 1, entering state S1; after S0 passes through W0 (write 0), its value remains 0, and its state remains S0. A fault in SA0 manifests as Vcell being unable to be written with 1, meaning that state S0 remains S0 even after passing through W1. A fault in SA1 manifests as Vcell being unable to be written with 0, meaning that state S1 remains S1 even after passing through W0.

[0080] In this embodiment of the disclosure, for multi-cell failures, the following description will take a two-cell memory failure as an example. In a two-cell failure, the cell that fails is called Vcell, and the other memory cell that affects Vcell is called Acell (aggressor cell). The solution provided in this embodiment of the disclosure can be extended to handle multi-cell memory failures.

[0081] Two-cell failures, also known as dual-cell failures, two-cell failures, or coupling failures (CF), refer to failures occurring between two memory cells, where the value of one cell changes due to the state or operation of the other. Coupling failures can be further categorized into inverted coupling failures (CFin), idempotent coupling failures (CFid), state coupling failures (CFst), coupling interference failures (CFds), coupling transition failures (CFtr), coupled write corruption failures (CFwd), coupled read corruption failures (CFrd), coupled deceptive read corruption failures (CFdrd), and coupled erronic read failures (CFir), among others.

[0082] As can be seen from the above, there are many types of memory (e.g., RAM) functional failures. There are as many as 600 known single-cell failures and two-cell failures alone. Moreover, the relationship between multiple failures is not independent. In other words, when a March algorithm is designed for a memory failure A, the March algorithm may not only cover memory failure A, but may also cover memory failure B. This also leads to the uncertainty of the memory failure coverage capability of the March algorithm.

[0083] Figure 5 This is a flowchart of a method for obtaining fault coverage of a test algorithm in another exemplary embodiment of this disclosure. Figure 5As shown, the method provided in this disclosure can solve the fault coverage capability of March-type algorithms based on a fault and algorithm model, and further obtain the fault coverage rate of the test algorithm. The method may include:

[0084] In S510, algorithms and fault models are established.

[0085] In this embodiment of the disclosure, establishing an algorithm model means obtaining the algorithmic logic formula of the test algorithm, and establishing a fault model means determining the fault model of the object under test and obtaining the fault characteristic formula of the fault model.

[0086] In this embodiment of the disclosure, the faults and algorithms are modeled and defined as follows:

[0087] Fault Feature Expression: A regular expression is a string that uses a single string to describe and match a certain syntactic rule. For example, [1-9][0-9]? can match numbers from 1 to 99 ([1-9] matches a single number from 1 to 9, [0-9]? matches zero or more numbers). In this embodiment of the disclosure, the regular expression generated for each fault is defined as a fault feature expression.

[0088] In this embodiment of the disclosure, the algorithm logic expression can be obtained from the algorithm expression of the test algorithm.

[0089] In the algorithm expression:

[0090] U: Indicates address increment; D: Indicates address decrement.

[0091] A: Indicates address increment or decrement; R: Indicates reading 0.

[0092] r: indicates reading 1; W: indicates writing 0

[0093] w: indicates writing 1; L: indicates delay.

[0094] For example, the ME of the March class algorithm is {↑(w0); ↑(r0); ↓(w1); ↓(r1);}, and the corresponding algorithm expression can be represented as UWURDwDr.

[0095] In the algorithmic logic, taking the above algorithmic expression UWURDwDr as an example:

[0096] If the fault type is a single-cell fault, its corresponding algorithm logic can be represented as 1W1R1w1r, which is called the first-order algorithm logic or first-order algorithm logic. The numbers "1,2,3,.." in the algorithm logic represent storage units (cells). Since a single-cell fault only involves one storage unit, there is only the number 1. 1W1R1w1r means performing WRwr operations on cell 1 in sequence.

[0097] If the fault type is a two-unit fault, its corresponding algorithm logic can be represented as 1W2W1R2R2w1w2r1r, which is called a second-order algorithm logic. In the algorithm logic, the number "1" represents unit 1 and "2" represents unit 2. 1W2W1R2R2w1w2r1r means writing 0 to unit 1, writing 0 to unit 2, reading 0 to unit 1, reading 0 to unit 2, writing 1 to unit 2, writing 1 to unit 1, reading 1 to unit 2, and reading 1 to unit 1 in sequence.

[0098] In S520, the fault coverage capability of the March-type algorithm is solved.

[0099] In S520, a fault coverage capability of March-type algorithms is solved using a fault and algorithm-based model. Both S510 and S520 are related to the number of memory units involved in memory faults, with multi-unit memory faults being particularly complex.

[0100] In S530, a model for generating algorithm coverage capabilities is created.

[0101] Use S520 to generate coverage models of all March-class algorithms for several memory functional faults.

[0102] The method for obtaining fault coverage of test algorithms provided in this disclosure innovatively solves the memory fault coverage capability of March-type algorithms. This method is low in cost and high in efficiency.

[0103] In an exemplary embodiment, determining whether the test algorithm covers the fault model based on the algorithm logic expression and the fault characteristic expression may include: determining whether the algorithm logic expression matches the fault characteristic expression; if the algorithm logic expression matches the fault characteristic expression, then determining that the test algorithm covers the fault model; if the algorithm logic expression does not match the fault characteristic expression, then determining that the test algorithm does not cover the fault model.

[0104] Figure 6 This is a flowchart of a method for obtaining fault coverage of a test algorithm in yet another exemplary embodiment of this disclosure. Figure 6 As shown, the method provided in this disclosure embodiment may include:

[0105] In S610, the fault characteristic formula of the fault model is generated.

[0106] In S620, the algorithm logic formula for the test algorithm is generated.

[0107] In S630, it is determined whether the algorithm logic of the test algorithm matches the fault characteristic formula of the fault model; if they match, S640 is executed; if they do not match, S650 is executed.

[0108] In S640, if the algorithm logic of the test algorithm matches the fault characteristic of the fault model, then the algorithm is determined to cover the fault.

[0109] In S650, if the algorithm logic of the test algorithm does not match the fault characteristic formula of the fault model, the algorithm is determined to be unable to cover the fault.

[0110] In this embodiment, the main idea for solving the fault coverage capability of March-type algorithms is as follows: The March algorithm consists of a finite number of read operations (MEs), and each ME is composed of a finite number of basic read and write operations. For a given fault, as long as one or more MEs form an access sequence that satisfies the fault detection requirements, the March algorithm can cover the fault. In other words, it is only necessary to match the read and write access sequence required for fault detection with the read and write access sequence of the March algorithm.

[0111] Figure 7 The example provided illustrates the problem by solving for the fault coverage capability of the March C-algorithm. Figure 7 As shown, the ME in the March C-algorithm includes w1 and r1 read / write operations, as well as w0 and r0 read / write operations. The w1 and r1 read / write operations can detect SA0 faults, and the w0 and r0 read / write operations can detect SA1 faults. Therefore, the March C-algorithm can cover both SA0 and SA1 faults.

[0112] Figure 6 The embodiment is a flowchart of the fault coverage capability of any March algorithm in the March class of algorithms based on the fault and algorithm model. S610 to S650 above are represented by A in the following embodiment.

[0113] In an exemplary embodiment, obtaining the fault characteristic formula of the fault model of the object under test may include: obtaining the fault model of the object under test; generating a fault expression of the fault model based on the fault model; and generating the fault characteristic formula of the fault model based on the fault expression.

[0114] Figure 8 This is a flowchart of a method for obtaining fault coverage of a test algorithm in another exemplary embodiment of this disclosure. Figure 8 As shown, Figure 8 The method provided in the embodiments and Figure 6 The method provided in the embodiments differs from that in that S610 may further include:

[0115] In S611, the fault model is read.

[0116] In this embodiment of the disclosure, the fault model can be represented as: Name; operation of cell1; operation of cell2; vcell. Wherein, "Name" represents the name of the fault model.

[0117] For example, the fault model represented by CFds;0w1;0;2 is as follows: The fault model is named CFds, and the behavior described is that when cell1 performs w0, w1, if the value in cell2 is 0, then the value of cell2 (vcell=2) will change from 0 to 1, causing a memory fault. The last number "2" indicates that Vcell is the second unit, i.e., cell2.

[0118] In S612, the fault expression of the fault model is generated.

[0119] In this embodiment of the disclosure, a fault expression is used to represent memory faults. The numbers 1, 2, ..., k in the fault expression represent k memory locations from low to high address, where k is a positive integer greater than or equal to 1. DB represents the data state of the k memory locations before the fault occurred, referred to as the data background; SO represents an operation command that caused the fault, referred to as sensitization; and RC represents the operation that detects the fault, referred to as detection.

[0120] For example, the fault expression for a two-cell fault CFds;0w1;0;2 can be represented as DB:(1W,2W),SO:(1w),RC:(2R), where 1W and 2W indicate that cell1 performs a W operation and cell2 performs a W operation; 1w indicates that cell1 performs a w operation; and 2R indicates that cell2 performs an R operation.

[0121] In S613, fault characteristic expressions are generated based on fault expressions.

[0122] The method for obtaining fault coverage of a test algorithm provided in this disclosure first represents the fault model as a fault expression, and then transitions from the fault expression to a fault characteristic formula. This can generate a correct fault characteristic formula, which is less prone to deviation and thus improves accuracy.

[0123] In an exemplary embodiment, obtaining the algorithmic logic formula of the test algorithm may include: obtaining the progressive element sequence of the test algorithm; generating the algorithmic expression of the test algorithm based on the progressive element sequence of the test algorithm; determining the fault type of the fault model based on the fault characteristic formula; and determining the algorithmic logic formula based on the algorithmic expression and the fault type.

[0124] In an exemplary embodiment, the algorithmic logic expression may include a first-order algorithmic logic expression. Specifically, determining the algorithmic logic expression based on the algorithmic expression and the fault type may include: if the fault type is a single-unit fault, then generating a first-order algorithmic logic expression for the test algorithm based on the algorithmic expression.

[0125] In an exemplary embodiment, the algorithmic logic expression may include an N-order algorithmic logic expression, where N is a positive integer greater than 1. Determining the algorithmic logic expression based on the algorithmic expression and the fault type may include: if the fault type is an N-unit fault, then generating an N-order algorithmic logic expression for the test algorithm based on the algorithmic expression.

[0126] Figure 9 This is a flowchart of a method for obtaining fault coverage of a test algorithm in another exemplary embodiment of this disclosure. Figure 9 As shown, Figure 9 The method provided in the embodiments and Figure 6 The method described in the embodiments differs from the method provided in that S620 may further include:

[0127] In S621, the fault characteristic formula of the fault model is read.

[0128] For example, the above can be read Figure 8 The fault characteristic formula generated in the example.

[0129] In S622, the test algorithm is read.

[0130] Specifically, the ME sequence of the test algorithm can be read.

[0131] In S623, determine whether the current fault is a single-unit fault; if it is a single-unit fault, execute S624; if it is not a single-unit fault, execute S625.

[0132] In this embodiment of the disclosure, the current fault can be determined as a single-unit fault or a multi-unit fault based on the fault characteristic formula of the read fault model. The example of a two-unit fault is used to illustrate a multi-unit fault, but this disclosure is not limited to this.

[0133] In S624, if the current fault is a single-cell fault, the first-order algorithm logic of the test algorithm for reading is generated.

[0134] In S625, if the current fault is a two-unit fault, a second-order algorithm logic expression for the test algorithm to be read is generated.

[0135] If the current fault is an N-unit fault, then generate the N-order algorithm logic for the test algorithm to be read.

[0136] The method for obtaining fault coverage of a test algorithm provided in this disclosure can determine whether the fault type is a single-cell fault or a multi-cell fault based on the fault characteristic formula of the generated fault model. If it is a single-cell fault, a first-order algorithm logic formula of the test algorithm can be generated. If it is an N-cell fault, an N-order algorithm logic formula of the test algorithm can be generated. That is, the method is flexible in design and can be extended to multi-cell memory faults.

[0137] In an exemplary embodiment, the fault models may include m types, and the test algorithms may include n types, where m and n are both positive integers greater than or equal to 1. The method may further include: obtaining a coverage result indicating whether each test algorithm can cover each fault model; and generating a coverage capability model of the n test algorithms on the m fault models based on the coverage result.

[0138] Specifically, the algorithmic logic formula for each test algorithm and the fault characteristic formula for each fault model can be obtained separately. The algorithmic logic formula for each test algorithm is then matched with the fault characteristic formula for each fault model to determine which fault models(s) each test algorithm can cover and which cannot. Based on which fault models(s) each test algorithm can cover and cannot cover, a coverage capability model of n test algorithms on m fault models is generated. The following example... Figure 10 The embodiments are provided as examples, but this disclosure is not limited thereto.

[0139] Figure 10 The flowchart provided in the embodiment can continuously verify the coverage capability of Algo_num (i.e., n = Algo_num) test algorithms in Trait_num (i.e., m = Trait_num) faults.

[0140] like Figure 10 As shown, the method provided in this disclosure embodiment may include:

[0141] In S1010, set Trait_num = number of fault characteristics and Algo_num = number of test algorithms that need to be verified.

[0142] In S1020, it is determined whether Algo_num is greater than 0; if it is greater than 0, then S1030 is executed; if it is less than or equal to 0, then jump to S1080.

[0143] In S1030, set Trait_count = Trait_num.

[0144] In S1040, determine whether Trait_count is greater than 0; if it is greater than 0, execute the above process A in S1050; if it is less than or equal to 0, execute S1070.

[0145] In S1050, execute the above process A.

[0146] S1050 executes sub-procedure A, whose function is to determine whether a test algorithm can detect a specific fault. Specifically, this may include the following steps:

[0147] Step 1. Begin.

[0148] Step 2. Read the fault model (the fault model is the input);

[0149] Step 3. Generate the fault expression for the fault model.

[0150] Step 4. Generate the fault characteristic formula of the fault model based on the fault expression.

[0151] Step 5. Read the fault characteristic formula generated in Step 4 above.

[0152] Step 6. Read the test algorithm to be verified.

[0153] Step 7. Determine whether it is a multi-unit fault based on the fault characteristic code read in Step 5. If yes, proceed to Step 9; otherwise, proceed to Step 8.

[0154] Step 8. If it is not a multi-unit fault, generate the first-order algorithm logic of the test algorithm read in step 6, and then execute step 10.

[0155] Step 9. If it is a two-unit fault in a multi-unit fault, generate the second-order algorithm logic expression of the test algorithm read in step 6, and then execute step 10.

[0156] Step 10. If the algorithm logic expression matches the fault characteristic expression, then proceed to step 12; if the algorithm logic expression does not match the fault characteristic expression, then proceed to step 13.

[0157] Step 11. Assert that the test algorithm cannot cover the fault, and proceed to step 13.

[0158] Step 12. Assert that the test algorithm can cover the fault (coverage result output), then proceed to step 13.

[0159] Step 13. End.

[0160] In S1060, Trait_count = Trait_count - 1, and then jump to S1040 above.

[0161] In S1070, set Algo_num = Algo_num-1, and then jump to S1020 above.

[0162] End in S1080.

[0163] The method for obtaining fault coverage of test algorithms provided in this disclosure can obtain the coverage capability of n test algorithms on m fault models, thereby generating a coverage capability model of n test algorithms on m fault models based on the coverage capability of n test algorithms on m fault models.

[0164] In an exemplary embodiment, the fault expression may sequentially include a data background, a sensitivity operation, and a detection operation. The data background represents the data state of k storage units before the fault occurs, the sensitivity operation represents the operation command that causes the fault, and the detection operation represents the operation that detects the fault, where k is a positive integer greater than or equal to 1. The fault characteristic expression may sequentially include the data background, an operation that ensures the data background is not changed, the sensitivity operation, an operation that ensures the sensitivity operation is not changed, and the detection operation.

[0165] The following is based on Figure 11 Let's illustrate with examples. Figure 11 In this embodiment, the fault model is assumed to be TF;1W0;1, meaning the fault model is named TF, and the last number "1" indicates that Vcell is cell1. Vcell originally had a value of 1, and when cell1 was written with a value of 0, Vcell failed, but the value remained at 1. Therefore, the fault expression of this fault model can be represented as DB:(1w), SO:(1W), RC:(1R). That is, the original value of Vcell is 1, which is DB, corresponding to operation 1w, which performs a w operation on cell1; a fault occurs when 0 is written, corresponding to SO, where 1W represents performing a w operation on cell1; then the value remains at 1, RC is the operation to detect the fault, and 1R is performing an R operation on cell1 to detect the fault.

[0166] Based on the fault expressions DB:(1w), SO:(1W), RC:(1R), the fault characteristic formula for this fault model can be generated as 1w[^wW]*1W[^wW]*1R. Here, "[^wW]" is a regular expression syntax indicating that the characters w and W cannot appear, ensuring that DB is valid. Through DB, cel is written with a specific value and will not be rewritten with other values ​​before RC. That is, DB + operation to ensure DB is not changed + SO + operation to ensure SO is not changed + RC. It should be noted that the operations to ensure DB and SO are not changed are not [^Ww] for every fault; they vary depending on the fault. This operation is performed to ensure that the operations of DB and SO do not fail, that is, to ensure that the fault has been formed.

[0167] Figure 11The examples use the SCAN and MATS++ algorithms from the March class of algorithms for illustration.

[0168] The SCAN algorithm consists of a sequence of four MEs:

[0169] The behavior of the first ME is as follows: the address direction is incrementing, with 0 written to address 0; 0 written to address 1; ... until 0 is written to address 100.

[0170] The behavior of the second ME is as follows: the address direction is incrementing, the value is read from address 0 and it is determined whether it is 0; the value is read from address 1 and it is determined whether it is 0; ... until the value is read from address 100 and it is determined whether it is 0.

[0171] The behavior of the third ME is as follows: the address direction is incrementing, with a value of 1 written to address 0; a value of 1 written to address 1; ... until a value of 1 is written to address 100.

[0172] The behavior of the fourth ME is as follows: the address direction is incrementing, the value is read from address 0 and it is determined whether it is 1; the value is read from address 1 and it is determined whether it is 1; ... until the value is read from address 100 and it is determined whether it is 1.

[0173] Therefore, the algorithm expression of the SCAN algorithm can be obtained as UWURUwUr. According to the above fault characteristic formula 1w[^wW]*1W[^wW]*1R, it can be determined as a single unit fault. Therefore, the first-order algorithm logic formula of the SCAN algorithm is: 1W1R1w1r.

[0174] The MATS++ algorithm consists of a sequence of three MEs:

[0175] The behavior of the first ME is: the address direction is random. Taking increment as an example, address 0 is written with a value of 0; address 1 is written with a value of 0; ... until address 100 is written with a value of 0.

[0176] The behavior of the second ME is as follows: the address direction is incrementing. The value is read from address 0, and it is determined whether it is 0. Then 1 is written into address 0; the value is read from address 1, and it is determined whether it is 0. Then 1 is written into address 1; ... until the value is read from address 100, and it is determined whether it is 0. Then 1 is written into address 100.

[0177] The behavior of the third ME is as follows: the address direction is decreasing. The value is read from address 100 and it is checked whether it is 1. Then the value is written to address 100 and the value is read from address 100 again and it is checked whether it is 0. The value is read from address 99 and it is checked whether it is 1. Then the value is written to address 99 and the value is read from address 99 again and it is checked whether it is 0. ... until the value is read from address 0 and it is checked whether it is 1. Then the value is written to address 0 and the value is read from address 0 again and it is checked whether it is 0.

[0178] Therefore, the algorithm expression of the MATS++ algorithm can be obtained as AWURwDrWR. According to the above fault characteristic formula 1w[^wW]*1W[^wW]*1R, it can be determined as a single unit fault. Therefore, the first-order algorithm logic formula of the MATS++ algorithm is: 1W1R1w1r1W1R.

[0179] Then, based on the rules of regular expression matching, it can be determined whether the algorithm's logical expression contains the fault characteristic expression. If it does, it matches; otherwise, it does not. The fault characteristic expression is represented using regular expression rules and can be expanded into other strings according to the rules. For example, "1w[^wW]*1W[^wW]*1R" can be expanded into 1w1r1W1R, thus matching the first-order logical expression of the MATS++ algorithm, 1W1R1w1r1W1R. However, it cannot be expanded into the first-order logical expression of the SCAN algorithm, 1W1R1w1r. Therefore, it is determined that the SCAN algorithm cannot cover the fault model TF;1W0;1, while the MATS++ algorithm can cover the fault model TF;1W0;1.

[0180] The method provided in this disclosure generates a fault characteristic formula for a fault model through a fault expression, namely DB + operation to ensure that DB is not changed + SO + operation to ensure that SO is not changed + RC. This ensures that the operations of DB and SO will not fail, and that a fault has been formed, thereby improving the stability of fault detection.

[0181] Figure 12 This is a schematic diagram of a coverage capability model in an exemplary embodiment of this disclosure. Figure 12 In this embodiment, it is assumed that the fault coverage capabilities of each test algorithm (SCAN;4, MATS;4, MATS+5, MATS++6, MARCHING 1 / 0;14, MARCH X;6) on various fault models (SF;0;1, SF;1;1, TF;0w1;1, TF;1w0;1, WDF;0w0;1, WDF;1w1;1, RDF;0;1, RDF;1;1, IRF;0;1, IRF;1;1, DRDF;0r0;1, DRDF;1r1;1, CFst;0;0;2) are tested respectively, thereby generating a coverage capability model of all tested March-class algorithms for several memory function faults. Figure 12 In the table, "T" is an abbreviation for "TRUE", which means that the corresponding test algorithm can cover the corresponding fault model, and "F" is an abbreviation for "FALSE", which means that the corresponding test algorithm cannot cover the corresponding fault model.

[0182] In related technologies, due to the unclear fault coverage capability of test algorithms and the large number of test algorithms, it is impossible to select a suitable test algorithm when performing memory testing, let alone the optimal test algorithm, which makes it impossible to carry out a lot of subsequent work. In order to solve this problem, the solution provided by the embodiments of this disclosure can analyze the coverage capability of test algorithms and determine the corresponding test algorithm for a specific fault model based on the generated coverage capability model.

[0183] In an exemplary embodiment, the method provided in this disclosure may further include: determining a target test algorithm for a target fault model based on the coverage capability model, wherein the test algorithm includes the target test algorithm; and / or determining a combination of target test algorithms for multiple target fault models based on the coverage capability model, wherein the combination of target test algorithms includes multiple test algorithms; wherein the fault model may include the target fault model.

[0184] The coverage capability model based on the March algorithm allows for the selection of a target test algorithm (e.g., a target March algorithm) from the March-class algorithms to test the target fault model, according to actual needs. For example, ... Figure 13 As shown, if we only want to target the fault model DRDF;0r0;1, then according to the coverage capability model, the MARCHING 1 / 0:14 algorithm should be selected as the target test algorithm, instead of selecting all test algorithms.

[0185] If it is necessary to test multiple faults, that is, to test multiple target fault models, a method for selecting algorithm combinations can be designed based on the coverage capability model, so as to minimize or reduce the number of test algorithms included in the selected target test algorithm combination and minimize or reduce the testing time.

[0186] The method provided in this disclosure, when applied to memory fault detection, is a method for obtaining fault coverage of memory testing algorithms. On one hand, by designing a unified and effective representation model for memory faults and testing algorithms, it is possible to effectively verify the coverage capability of multiple testing algorithms for multiple memory faults, and this method is low-cost and highly efficient. On the other hand, the memory functional faults verified by the method provided in this disclosure can include single-cell faults and multi-cell faults. Furthermore, the coverage capability model generated based on this method can be used to select targeted testing algorithms or combinations of targeted testing algorithms for specific faults.

[0187] Figure 14 This is a schematic diagram of the structure of an apparatus for obtaining the fault coverage of a test algorithm according to an exemplary embodiment of this disclosure. Figure 14As shown, the apparatus 1400 for obtaining the fault coverage of a test algorithm provided in this embodiment of the present disclosure may include an obtaining unit 1410 and a processing unit 1420.

[0188] The obtaining unit 1410 can be used to obtain the fault characteristic formula of the fault model of the object under test. The obtaining unit 1410 can also be used to obtain the algorithm logic formula of the test algorithm. The processing unit 1420 can be used to determine whether the test algorithm covers the fault model based on the algorithm logic formula and the fault characteristic formula. Figure 14 Other aspects of the apparatus provided in the embodiments can be referred to in the other embodiments described above.

[0189] This disclosure provides an apparatus for obtaining the fault coverage of a test algorithm, which can run on a computer device. See also... Figure 15 , Figure 15 This is a schematic diagram of the structure of a computer device provided in an embodiment of this disclosure. Figure 15 As shown, the computer device in this embodiment may include one or more processors 1501, a memory 1502, and an input / output interface 1503. The processor 1501, memory 1502, and input / output interface 1503 are connected via a bus 1504. The memory 1502 stores a computer program, which includes program instructions. The input / output interface 1503 receives and outputs data, such as for data interaction between the host machine and the computer device, or for data interaction between various virtual machines within the host machine. The processor 1501 executes the program instructions stored in the memory 1502.

[0190] The processor 1501 can perform the following operations: obtain the fault characteristic formula of the fault model of the object under test; obtain the algorithm logic formula of the test algorithm; and determine whether the test algorithm covers the fault model based on the algorithm logic formula and the fault characteristic formula.

[0191] The memory 1502 may include read-only memory and random access memory, and provides instructions and data to the processor 1501 and input / output interface 1503. A portion of the memory 1502 may also include non-volatile random access memory. For example, the memory 1502 may also store device type information.

[0192] In practice, the computer device can execute the implementation methods provided in the steps shown in the figure above through its built-in functional modules. For details, please refer to the implementation methods provided in the steps shown in the figure above, which will not be repeated here.

[0193] This disclosure provides a computer device including a processor, an input / output interface, and a memory. The processor retrieves a computer program from the memory and executes the steps of the method shown in the figure above.

[0194] This disclosure also provides a computer-readable storage medium storing a computer program adapted to be loaded by a processor and executed by the method for obtaining the fault coverage of the test algorithm provided in the steps shown in the figure above. For details, please refer to the implementation of the steps shown in the figure above, which will not be repeated here.

[0195] This disclosure also provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods provided in the various alternatives shown in the figures above.

[0196] The above-disclosed embodiments are merely preferred embodiments of this disclosure and should not be construed as limiting the scope of this disclosure. Therefore, any equivalent variations made in accordance with this disclosure shall still fall within the scope of this disclosure.

Claims

1. A method for obtaining fault coverage of a memory testing algorithm, characterized in that, include: Obtain the fault characteristic formula of the fault model of the memory under test; Obtain the algorithmic logic of the test algorithm; Based on the algorithm logic and the fault characteristic formula, determine whether the test algorithm covers the fault model; Determining whether the test algorithm covers the fault model based on the algorithm logic and the fault characteristic formula includes: Determine whether the algorithm logic matches the fault characteristic expression; If the algorithm's logical expression matches the fault characteristic expression, then the test algorithm is determined to cover the fault model. If the algorithm logic does not match the fault characteristic expression, then it is determined that the test algorithm does not cover the fault model; The fault models include m types, and the test algorithms include n types, where m and n are both positive integers greater than or equal to 1; The method further includes: Obtain the coverage results for each test algorithm to determine whether it can cover each fault model; Based on the coverage results, generate coverage capability models of n test algorithms on m fault models; Also includes: Based on the coverage capability model, a target test algorithm is determined for the target fault model, and the test algorithm includes the target test algorithm; And / or, Based on the coverage capability model, a combination of target test algorithms is determined for multiple target fault models, and the combination of target test algorithms includes multiple test algorithms; The fault model includes the target fault model.

2. The method as described in claim 1, characterized in that, Obtain the fault characteristic formula of the fault model of the memory under test, including: Obtain the fault model of the memory under test; Generate the fault expression for the fault model based on the fault model; The fault characteristic formula of the fault model is generated based on the fault expression.

3. The method as described in claim 2, characterized in that, The fault expression includes, in sequence, data background, sensitization operation, and detection operation. The data background represents the data state of k storage units before the fault occurs. The sensitization operation represents the operation command that causes the fault. The detection operation represents the operation that detects the fault. k is a positive integer greater than or equal to 1. The fault characteristic formula sequentially includes the data background, the operation to ensure that the data background is not changed, the sensitization operation, the operation to ensure that the sensitization operation is not changed, and the detection operation.

4. The method as described in claim 1, characterized in that, Obtain the algorithmic logic of the test algorithm, including: Obtain the progressive element sequence of the test algorithm; The algorithmic expression of the test algorithm is generated based on the progressive element sequence of the test algorithm; The fault type of the fault model is determined based on the fault characteristic formula; The algorithm logic formula is determined based on the algorithm expression and the fault type.

5. The method as described in claim 4, characterized in that, The algorithm logic includes a first-order algorithm logic; The process of determining the algorithm logic formula based on the algorithm expression and the fault type includes: If the fault type is a single-unit fault, then the first-order algorithm logic expression of the test algorithm is generated according to the algorithm expression.

6. The method as described in claim 5, characterized in that, The algorithm logic includes an N-order algorithm logic, where N is a positive integer greater than 1; The process of determining the algorithm logic formula based on the algorithm expression and the fault type includes: If the fault type is an N-unit fault, then the N-order algorithm logic expression of the test algorithm is generated according to the algorithm expression.

7. The method as described in claim 1, characterized in that, The memory to be tested includes RAM.

8. The method as described in claim 1, characterized in that, The testing algorithm includes a progressive algorithm.

9. An apparatus for obtaining fault coverage of a memory testing algorithm, characterized in that, include: The acquisition unit is used to acquire the fault characteristic formula of the fault model of the memory under test; The obtaining unit is also used to obtain the algorithmic logic formula of the test algorithm; A processing unit is configured to determine whether the test algorithm covers the fault model based on the algorithm logic formula and the fault characteristic formula; the fault model includes m types, and the test algorithm includes n types, where m and n are both positive integers greater than or equal to 1; the processing unit is further configured to obtain the coverage result of each test algorithm covering each fault model; generate a coverage capability model of the n test algorithms on the m fault models based on the coverage result; determine a target test algorithm for a target fault model based on the coverage capability model, the test algorithm including the target test algorithm; and / or determine a combination of target test algorithms for multiple target fault models based on the coverage capability model, the combination of target test algorithms including multiple test algorithms; wherein, the fault model includes the target fault model; The determination of whether the test algorithm covers the fault model based on the algorithm logic and the fault characteristic formula includes: Determine whether the algorithm logic matches the fault characteristic expression; If the algorithm's logical expression matches the fault characteristic expression, then the test algorithm is determined to cover the fault model. If the algorithm logic does not match the fault characteristic expression, then it is determined that the test algorithm does not cover the fault model.

10. A computer device, characterized in that, include: One or more processors; A memory configured to store one or more programs that, when executed by one or more processors, cause the computer device to perform the method as described in any one of claims 1 to 8.

11. A computer-readable storage medium storing a computer program, characterized in that, The computer program causes the computer device to perform the method as described in any one of claims 1 to 8.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 8.

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