Semiconductor packaging including interposer layer

Abstract

Semiconductor package including an interposer. A semiconductor package includes: a package substrate, a lower chip, an interposer and an upper chip stacked on the package substrate, and bonding wires electrically connecting the lower chip to the package substrate. The lower chip includes: a first lower chip pad and a second lower chip pad spaced apart from each other on an upper surface of the lower chip, a wire bonding pad bonded to the bonding wire on the upper surface of the lower chip, and a lower chip redistribution line electrically connecting the second lower chip pad to the wire bonding pad. The interposer includes: an upper chip connection pad on an upper surface of the interposer, a lower chip connection pad on a lower surface of the interposer, and a through-hole electrode electrically connecting the upper chip connection pad to the lower chip connection pad.

Description

Technical Field

[0001] The present disclosure relates generally to a semiconductor package, and more particularly, to a semiconductor package having an interposer. Background Art

[0002] Generally, a semiconductor package is configured to include a substrate and a semiconductor chip mounted on the substrate. The semiconductor chip may be electrically connected to the substrate through a connection member such as a bump or a wiring.

[0003] Recently, according to the demand for high performance and high integration of semiconductor packages, various structures of semiconductor packages for stacking multiple semiconductor chips on a substrate have been proposed. As an example, a technology of electrically connecting multiple semiconductor chips stacked on a substrate to each other using wire bonding or through silicon via (TSV) technology has been proposed. Summary of the invention

[0004] According to one embodiment, a semiconductor package may include: a package substrate; a lower chip, an interposer, and an upper chip, the lower chip, the interposer, and the upper chip being stacked on the package substrate; and a bonding wire, the bonding wire electrically connecting the lower chip to the package substrate. The lower chip may include: a first lower chip pad and a second lower chip pad, the first lower chip pad and the second lower chip pad being spaced apart from each other on the upper surface of the lower chip and electrically connected to each other through internal wiring of the lower chip; a wire bonding pad, the wire bonding pad being bonded to the bonding wire on the upper surface of the lower chip; and a lower chip redistribution line, the lower chip redistribution line electrically connecting the second lower chip pad to the wire bonding pad. The interposer may include: an upper chip connection pad electrically connected to the upper chip on the upper surface of the interposer; a lower chip connection pad electrically connected to the first lower chip pad on the lower surface of the interposer; and a through-hole electrode electrically connecting the upper chip connection pad to the lower chip connection pad.

[0005] According to another embodiment, a semiconductor package may include: a package substrate; a lower chip disposed on the package substrate and electrically connected to the package substrate by wire bonding; an interposer disposed on the lower chip and including a through-hole electrode electrically connected to the lower chip; and an upper chip disposed on the interposer and electrically connected to the through-hole electrode. The upper chip is electrically connected to the package substrate through the interposer and the lower chip.

[0006] According to another embodiment, a semiconductor package may include: a package substrate; a first stacking structure, the first stacking structure being arranged on the package substrate; a second stacking structure, the second stacking structure being arranged on the first stacking structure; a first bonding wire, the first bonding wire electrically connecting the package substrate to a first lower chip of the first stacking structure; and a second bonding wire, the second bonding wire electrically connecting the package substrate to a second lower chip of the second stacking structure. The first stacking structure includes a first lower chip, a first interposer, and a first upper chip, and the second stacking structure includes a second lower chip, a second interposer, and a second upper chip. The first interposer includes a first through-hole electrode electrically connecting the first lower chip to the first upper chip, and the second interposer includes a second through-hole electrode electrically connecting the second lower chip to the second upper chip. The first upper chip is electrically connected to the package substrate through the first interposer and the first lower chip, and the second upper chip is electrically connected to the package substrate through the second interposer and the second lower chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a cross-sectional view schematically showing a semiconductor package according to one embodiment of the present disclosure.

[0008] Figure 2 and Figure 3 is a plan view schematically showing a semiconductor chip according to an embodiment of the present disclosure.

[0009] Figure 4A and Figure 4B is a diagram schematically showing an interposer of a semiconductor package according to an embodiment of the present disclosure.

[0010] Figure 5 is a diagram schematically illustrating a method for exchanging electrical signals between a semiconductor chip and a package substrate according to an embodiment of the present disclosure.

[0011] Figure 6 is a diagram schematically showing an internal circuit configuration of a semiconductor package according to an embodiment of the present disclosure.

[0012] Figure 7 is a cross-sectional view schematically showing a semiconductor package according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] The terms used herein may correspond to words selected considering their functions in the embodiments presented, and the meanings of these terms may be interpreted as different meanings according to the ordinary technicians in the field to which these embodiments belong. If specifically defined, these terms may be interpreted according to these definitions. Unless otherwise defined, the terms used herein (including technical terms and scientific terms) have the same meanings as those generally understood by ordinary technicians in the field to which the embodiments belong. In the description of the examples disclosed herein, descriptions such as "first" and "second", "top" and "bottom or bottom", "left" and "right" are used to distinguish components, and are not used to limit the components themselves or to represent a specific order.

[0014] The semiconductor chip described herein may include a semiconductor substrate in which an electronic circuit is integrated and cut into a form of a die. The semiconductor chip may correspond to a memory chip, a logic chip (including an application-specific integrated circuit (ASIC) chip) or a system on chip (SoC). The memory chip may include a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a NAND flash memory circuit, a NOR flash memory circuit, a magnetic random access memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory (FeRAM) circuit or a phase change random access memory (PcRAM) circuit integrated on a semiconductor substrate. The logic chip may include a logic circuit integrated on a semiconductor substrate. The semiconductor chip may be referred to as a semiconductor die according to its shape after the relationship cutting process.

[0015] In this specification, a semiconductor package may include a package substrate on which a semiconductor chip is mounted. The package substrate may include at least one layer of an integrated circuit pattern and may be referred to as a printed circuit board (PCB) in this specification.

[0016] As an embodiment, the semiconductor package may include a plurality of semiconductor chips mounted on a package substrate. In the semiconductor package, any one of the plurality of semiconductor chips may be configured as a master chip, and the remaining semiconductor chips may be configured as slave chips. Then, the semiconductor package may use the master chip to control the memory unit of the slave chip. The master chip may directly exchange signals with the package substrate, and the slave chip may exchange signals with the package substrate through the master chip.

[0017] Semiconductor packages can be used in various communication systems such as mobile phones, electronic systems related to biotechnology or healthcare, or wearable electronic systems.

[0018] Throughout the specification, the same reference numerals refer to the same elements. Even if a reference numeral is not mentioned or described with reference to a drawing, it may be mentioned or described with reference to another drawing. In addition, even if a reference numeral is not shown in a drawing, it may be mentioned or described with reference to another drawing.

[0019] Figure 1 is a cross-sectional view schematically showing a semiconductor package 1 according to an embodiment of the present disclosure. Figure 1 , the semiconductor package 1 may include a lower chip 200, an interposer 300, and an upper chip 400 stacked on a package substrate 100. The semiconductor package 1 may include bonding wires 50a and 50b electrically connecting the lower chip 200 to the package substrate 100.

[0020] The lower chip 200 and the upper chip 400 may be semiconductor chips including integrated circuits. The lower chip 200 may be electrically connected to the package substrate 100 using bonding wires 50a and 50b by a wire bonding method. Therefore, the lower chip 200 may directly exchange electrical signals with the package substrate 100. On the other hand, the upper chip 400 may first be electrically connected to the lower chip 200 using through via electrodes 330a and 330b in the interposer 300, and then may be electrically connected to the package substrate 100 through the lower chip 200. That is, the upper chip 400 may exchange electrical signals with the package substrate 100 through the interposer 300 and the lower chip 200.

[0021] Reference Figure 1 , a package substrate 100 may be provided. The package substrate 100 may have an upper surface 100S1 and a lower surface 100S2 opposite to the upper surface 100S1. Although not shown, the package substrate 100 may include at least one layer of an integrated circuit pattern.

[0022] Connection pads 110a and 110b for wire bonding with the lower chip 200 may be provided on the upper surface 100S1 of the package substrate 100. In addition, a connection structure 550 for electrical connection with other semiconductor packages or PCB may be provided on the lower surface 100S2. The connection structure 550 may include, for example, bumps and solder balls.

[0023] The lower chip 200 may be disposed on the package substrate 100. The lower chip 200 may be bonded to the package substrate 100 through an adhesive layer 510. The adhesive layer 510 may include a polymer material having non-conductivity.

[0024] The lower chip 200 may have an upper surface 200S1 and a lower surface 200S2. In addition, the first lower chip pads 210a and 210b and the second lower chip pads 220a and 220b may be spaced apart from each other on the upper surface 200S1 of the lower chip 200. The first lower chip pads 210a and 210b may be connected to the lower chip connection pads 320a and 320b of the interposer 300, respectively, through the first bumps 520.

[0025] The second lower chip pads 220a and 220b may be spaced apart from the first lower chip pads 210a and 210b in a lateral direction (i.e., in a direction parallel to the x-direction), respectively. The second lower chip pads 220a and 220b may be electrically connected to the first lower chip pads 210a and 210b, respectively, through internal wiring (not shown) of the lower chip 200.

[0026] Wire bonding pads 230a and 230b may be disposed in an edge region of an upper surface 200S1 of the lower chip 200. Wire bonding pads 230a and 230b may contact bonding wires 50a and 50b, respectively. Wire bonding pads 230a and 230b may be electrically connected to second lower chip pads 220a and 220b through lower chip redistribution lines 240a and 240b, respectively.

[0027] The interposer 300 may be disposed above the lower chip 200. The interposer 300 may have an upper surface 300S1 and a lower surface 300S2. The lower chip connection pads 320a and 320b electrically connected to the lower chip 200 may be disposed on the lower surface 300S2. As described above, the lower chip connection pads 320a and 320b may be connected to the first lower chip pads 210a and 210b of the lower chip 200 respectively through the first bump 520. At the same time, the upper chip connection pads 310a and 310b electrically connected to the upper chip 400 may be disposed on the upper surface 300S1. As described below, the upper chip connection pads 310a and 310b may be connected to the first upper chip pads 410a and 410b respectively through the second bump 530.

[0028] Refer again Figure 1, the edge portion of the interposer 300 may be disposed at a position recessed in a lateral direction from the edge portion of the lower chip 200 and the upper chip 400. As an example, the sidewall surface 300E1 of the interposer 300 may be disposed at a position recessed in a lateral direction (i.e., in a D1 direction parallel to the x-axis) from the sidewall surface 200E1 of the lower chip 200 and the sidewall surface 400E1 of the upper chip 400. Similarly, the other sidewall surface 300E2 of the interposer 300 may be disposed at a position recessed in a lateral direction (i.e., in a D2 direction parallel to the x-axis) from the other sidewall surface 200E2 of the lower chip 200 and the other sidewall surface 400E2 of the upper chip 400. Therefore, the width in the interposer 300 along the direction parallel to the x-axis may be smaller than the width in the lower chip 200 and the upper chip 400 along the direction parallel to the x-axis. At least a portion of the bonding wires 50a and 50b may be accommodated in the recessed space. Therefore, bonding between the wire bonding pads 230 a and 230 b of the lower chip 200 and the bonding wires 50 a and 50 b may be stably performed.

[0029] The interposer 300 may include through-hole electrodes 330a and 330b that electrically connect the upper chip connection pads 310a and 310b to the lower chip connection pads 320a and 320b, respectively. Figure 4A , Figure 4B and Figure 5 As described, the interposer 300 may further include first to fourth interposer redistribution lines 341, 342, 351, and 352 to be arranged on the upper surface 300S1 and the lower surface 300S2 so as to connect the upper chip connection pads 310a and 310b and the lower chip connection pads 320a and 320b to the through-hole electrodes 330a and 330b, respectively.

[0030] The upper chip 400 may be disposed above the interposer 300. The upper chip 400 may have an upper surface 400S1 and a lower surface 400S2. The first upper chip pads 410a and 410b and the second upper chip pads 420a and 420b may be disposed on the upper surface 400S1 of the upper chip 400 facing the interposer 300. The first upper chip pads 410a and 410b may be connected to the upper chip connection pads 310a and 310b of the interposer 300, respectively, through the second bumps 530. The second upper chip pads 420a and 420b may be spaced apart from the first upper chip pads 410a and 410b in the lateral direction (i.e., in a direction parallel to the x-direction), and may not participate in the electrical connection with an external device including the interposer 300, the lower chip 200, and the package substrate 100.

[0031] In one embodiment, the lower chip 200 and the upper chip 400 may be chips of the same type. However, compared to the upper chip 400, the lower chip 200 may further include wire bonding pads 230a and 230b and lower chip redistribution lines 240a and 240b on the upper surface 200S1 of the lower chip 200. In this case, the lower chip redistribution lines 240a and 240b may be connected to the second lower chip pads 220a and 220b. The lower chip 200 and the upper chip 400 may be arranged to overlap each other in a direction parallel to the z-axis.

[0032] In other embodiments not shown, the lower chip 200 and the upper chip 400 may have the same configuration. That is, the upper chip 400 may include a wire bonding pad in an edge region of the upper surface, and further include an upper chip redistribution line electrically connecting the wire bonding pad to the second upper chip pads 420a and 420b. However, in this case, the wire bonding pad of the upper chip is not electrically connected to the package substrate 100 by bonding wires.

[0033] In one embodiment, the lower chip 200 and the upper chip 400 may be memory chips. In this case, the lower chip 200 may be a master chip, and the upper chip 400 may be a slave chip. The lower chip 200 may be directly connected and electrically connected to the package substrate 100 using bonding wires 50a and 50b. The upper chip 400 may first be electrically connected to the lower chip 200 through via electrodes 330a and 330b, and may then be electrically connected to the package substrate 100 through the internal wiring of the lower chip 200, the input / output circuit, and the bonding wires 50a and 50b.

[0034] Figure 2 and Figure 3 Schematically shows a plan view of a semiconductor chip of a semiconductor package according to an embodiment of the present disclosure. Specifically, Figure 2 Schematically shows Figure 1 The lower chip 200. Figure 3 Schematically shows Figure 1 The upper chip 400. Figure 4A and Figure 4B Schematically illustrates an interposer of a semiconductor package according to an embodiment of the present disclosure. More specifically, Figure 4A It is schematically shown Figure 1 A plan view of the interposer 300, and Figure 4B yes Figure 4A A perspective view of portion B of through-hole electrode arrangement area A.

[0035] Reference Figure 2, the lower chip 200 may have a short axis along a direction parallel to the x-axis and a long axis along a direction parallel to the y-axis. In addition, the lower chip 200 may have a central axis Cy-200 disposed along the long axis. The lower chip 200 may have a predetermined width W200 in the short axis direction, and may have a predetermined length L200 in the long axis direction. The central axis Cy-200 may be configured to pass through half of the width W200 of the lower chip 200.

[0036] The first lower chip pads 210a and 210b, the second lower chip pads 220a and 220b, and the wire bonding pads 230a and 230b can be arranged on the upper surface 200S1 of the lower chip 200 along the long axis direction (i.e., the direction parallel to the y direction). The first lower chip pads 210a and 210b, the second lower chip pads 220a and 220b, and the wire bonding pads 230a and 230b can be respectively arranged to form a pair of pads symmetrical about the central axis Cy-200. In a specific embodiment, the first lower chip pads 210a and 210b can be arranged to be closer to the central axis Cy-200 than the second lower chip pads 220a and 220b and the wire bonding pads 230a and 230b. In addition, the second lower chip pads 220 a and 220 b may be disposed closer to the central axis Cy- 200 than the wire bonding pads 230 a and 230 b .

[0037] Based on the center axis Cy-200, the first lower chip pads 210a and 210b can be classified as the first lower chip left pad 210a and the first lower chip right pad 210b. Based on the center axis Cy-200, the second lower chip pads 220a and 220b can be classified as the second lower chip left pad 220a and the second lower chip right pad 220b. Based on the center axis Cy-200, the wire bonding pads 230a and 230b can be classified as the wire bonding left pad 230a and the wire bonding right pad 230b.

[0038] like Figure 2 As shown, the surface area of ​​each of the first lower chip pads 210a and 210b may be smaller than the surface area of ​​each of the second lower chip pads 220a and 220b. As an example, the first lower chip pads 210a and 210b may each have a smaller size than the second lower chip pads 220a and 220b.

[0039] Compared with the second lower chip pads 220a and 220b, the first lower chip pads 210a and 210b can be relatively densely arranged in the through-hole electrode arrangement area A. The first lower chip pads 210a and 210b can be arranged in the through-hole electrode arrangement area A at a predetermined interval S1 along the central axis Cy-200. In addition, the second lower chip pads 220a and 220b can be continuously arranged outside the through-hole electrode arrangement area A at the same predetermined interval S2 along the central axis Cy-200. When the first lower chip pads 210a and 210b are arranged in a direction parallel to the y-axis, the first lower chip pads 210a and 210b can be arranged between the second lower chip pads 220a and 220b. That is, the first lower chip pads 210a and 210b and the second lower chip pads 220a and 220b can be arranged alternately in a direction parallel to the y-axis.

[0040] Refer to Figure 1 and Figure 2 , electrical signals can be communicated between the first lower chip pads 210a and 210b of the lower chip 200 and the first upper chip pads 410a and 410b of the upper chip 400 through the through-hole electrodes 330a and 330b. That is, the first lower chip pads 210a and 210b can be used as signal input / output pads of the lower chip 200 to exchange electrical signals with the upper chip 400.

[0041] Return to reference Figure 1 , lower chip redistribution lines 240a and 240b may be disposed on an upper surface 200S1 of the lower chip 200. The lower chip redistribution lines 240a and 240b may electrically connect the wire bonding pads 230a and 230b to the second lower chip pads 220a and 220b. The lower chip redistribution lines 240a and 240b may be configured as lines symmetrical about the central axis Cy-200. In a specific example, based on the central axis Cy-200, the lower chip redistribution lines 240a and 240b may be classified as lower chip left redistribution lines 240a and lower chip right redistribution lines 240b.

[0042] As described above, the electrical signals reaching the wire bonding pads 230a and 230b from the package substrate 100 through the bonding wires 50a and 50b can be transmitted to the second lower chip pads 220a and 220b through the lower chip redistribution lines 240a and 240b, respectively. Subsequently, the electrical signals reaching the second lower chip pads 220a and 220b can be transmitted to the internal integrated circuit. Some electrical signals can be output through the first lower chip pads 210a and 210b to be input to the first upper chip pads 410a and 410b of the upper chip 400 through the through-hole electrodes 330a and 330b of the interposer 300.

[0043] Reference Figure 3 , an upper chip 400 is disclosed. The upper chip 400 may have a short axis along a direction parallel to the x-direction and a long axis along a direction parallel to the y-direction. In addition, the upper chip 400 may have a central axis Cy-400 arranged along the long axis. The upper chip 400 may have a predetermined width W400 along the short axis direction, and may have a predetermined length L400 along the long axis direction. The central axis Cy-400 may be configured to pass through half of the width W400 of the upper chip 400. In one embodiment, when the upper chip 400 is arranged to overlap with the lower chip 200, the central axis Cy-400 of the upper chip 400 may overlap with the central axis Cy-200 of the lower chip 200.

[0044] The first upper chip pads 410a and 410b and the second upper chip pads 420a and 420b can be arranged on the upper surface 400S1 of the upper chip 400 along the long axis direction (i.e., the direction parallel to the y-axis). The first upper chip pads 410a and 410b and the second upper chip pads 420a and 420b can be respectively arranged to form a pair of pads symmetrical about the central axis Cy-400. In a specific example, the first upper chip pads 410a and 410b can be arranged to be closer to the central axis Cy-400 than the second upper chip pads 420a and 420b. Based on the central axis Cy-400, the first upper chip pads 410a and 410b can be classified as the first upper chip left pad 410a and the first upper chip right pad 410b. The second upper chip pads 420 a and 420 b may be classified into a second upper chip left pad 420 a and a second upper chip right pad 420 b based on the center axis Cy- 400 .

[0045] like Figure 3 As shown, the surface area of ​​each of the first upper chip pads 410a and 410b may be smaller than the surface area of ​​each of the second upper chip pads 420a and 420b. As an example, each of the first upper chip pads 410a and 410b may have a smaller size than each of the second upper chip pads 420a and 420b.

[0046] Compared with the second upper chip pads 420a and 420b, the first upper chip pads 410a and 410b may be relatively densely arranged in the through-hole electrode arrangement region A. The first upper chip pads 410a and 410b may be arranged at a predetermined interval S1 along the central axis Cy-400 in the through-hole electrode arrangement region A. Meanwhile, the second upper chip pads 420a and 420b may be continuously arranged at the same predetermined interval S2 along the central axis Cy-400 on the upper surface 400S1.

[0047] Refer to Figure 1 and Figure 3 , electrical signals can be communicated between the first upper chip pads 410a and 410b of the upper chip 400 and the first lower chip pads 210a and 210b of the lower chip 200 through the through-hole electrodes 330a and 330b, respectively. That is, the first upper chip pads 410a and 410b can be used as signal input / output pads of the upper chip for exchanging electrical signals with the lower chip 200. The second upper chip pads 420a and 420b can be connected to the input / output circuit blocks 400A1 and 400A2 inside the upper chip 400, as will be described later Figure 6 However, the second upper chip pads 420a and 420b are not directly connected to components of external devices such as the interposer 300, the lower chip 200, and the package substrate 100. Here, directly connected may mean that the second upper chip pads 420a and 420b are connected to external components through external connection structures such as bumps or bonding wires.

[0048] In some other embodiments not shown, the upper chip 400 may be connected to Figure 2 The lower chip 200 shown in FIG. 4 has substantially the same configuration. That is, the upper chip 400 may have a wire bonding pad in the edge region of the upper surface 400S1. The position of the wire bonding pad may be the same as that of the lower chip 200 shown in FIG. Figure 2 The wire bonding pads 230a and 230b of the lower chip 200 are shown to be located in the same position. In addition, the upper chip 400 may have upper chip redistribution lines connecting the wire bonding pads to the second upper chip pads 420a and 420b.

[0049] Reference Figure 4A and Figure 4B , the interposer 300 may be disposed between the lower chip 200 and the upper chip 400. The interposer 300 may have a short axis along a direction parallel to the x direction and a long axis along a direction parallel to the y direction. In addition, the interposer 300 may have a central axis Cy-300 disposed along the long axis. The interposer 300 may have a predetermined width W300 along the short axis direction, and may have a predetermined length L300 along the long axis direction. The central axis Cy-300 may be configured to pass through half of the width W300 of the interposer 300. In one embodiment, when the upper chip 400, the interposer 300, and the lower chip 200 are arranged to overlap each other, the central axis Cy-400 of the upper chip 400, the central axis Cy-300 of the interposer 300, and the central axis Cy-200 of the lower chip 200 may overlap each other.

[0050] The upper chip connection pads 310a and 310b may be arranged along the long axis direction (i.e., the direction parallel to the y-axis) on the upper surface 300S1 of the interposer 300. In one embodiment, the upper chip connection pads 310a and 310b may be respectively configured as a pair of pads symmetrical about the central axis Cy-300. The upper chip connection pads 310a and 310b may be classified as an upper left pad 310a and an upper right pad 310b that are symmetrical to each other about the central axis Cy-300. The upper left pad 310a and the upper right pad 310b may be spaced apart from each other at a predetermined interval S1 along a direction parallel to the Y-axis. Although in Figure 4A Although not specifically shown in the figure, the lower chip connection pads 320a and 320b can be arranged on the lower surface 300S2 of the interposer 300 along the long axis direction. In one embodiment, the lower chip connection pads 320a and 320b can be respectively configured as a pair of pads symmetrical about the central axis Cy-300. The lower chip connection pads 320a and 320b can be arranged to overlap with the upper chip connection pads 310a and 310b.

[0051] Reference Figure 4A and Figure 4B , a first interposer redistribution line 341 extending from the upper left pad 310a and reaching the first via extension pad 341p may be disposed on the upper surface 300S1 along a direction parallel to the y-axis. The first via extension pad 341p may be connected to the first via electrode 330a. In addition, a second interposer redistribution line 342 extending from the upper right pad 310b and reaching the second via extension pad 342p may be disposed on the upper surface 300S1 along a direction parallel to the y-axis. The second via extension pad 342p may be connected to the second via electrode 330b.

[0052] Reference Figure 4B , the lower chip connection pads 320a and 320b disposed on the lower surface 300S2 of the interposer 300 may be classified as the lower left pad 320a and the lower right pad 320b symmetrical about the central axis Cy-300. In this case, the third interposer redistribution line 351 extending from the lower right pad 320b and reaching the third through-hole extension pad 351p may be disposed on the lower surface 300S2 in a direction parallel to the y-axis. The third through-hole extension pad 351p may be connected to the first through-hole electrode 330a. In addition, the fourth interposer redistribution line 352 extending from the lower left pad 320a and reaching the fourth through-hole extension pad 352p may be disposed on the lower surface 300S2 in a direction parallel to the y-axis. The fourth through-hole extension pad 352p may be connected to the second through-hole electrode 330b.

[0053] In one embodiment, the lower left pad 320a may be disposed directly below the upper left pad 310a and disposed to face the upper left pad 310a. In addition, the lower right pad 320b may be disposed directly below the upper right pad 310b and disposed to face the upper right pad 310b. In other words, the lower left pad 320a and the upper left pad 310a may be disposed to overlap each other in the vertical direction (i.e., the direction parallel to the z-axis), and the lower right pad 320b and the upper right pad 310b may be disposed to overlap each other in the vertical direction (i.e., the direction parallel to the z-axis).

[0054] Figure 5 Schematic diagram schematically illustrating a method for exchanging electrical signals between a semiconductor chip and a packaging substrate according to an embodiment of the present disclosure. Figure 5 In the above reference Figure 1 , Figure 2 , Figure 3 , Figure 4A and Figure 4B The configuration of the lower chip 200, the interposer 300 and the upper chip 400 of the semiconductor package 1 described above is used to schematically describe the method of exchanging electrical signals. Figure 5 Not shown in FIG.

[0055] Reference Figure 5 and Figure 1 , the electrical signal exchange between the package substrate 100 and the lower chip 200 can be performed as follows. As an example, the electrical signal of the package substrate 100 can be input to the wire bonding left pad 230a and the wire bonding right pad 230b through the bonding wires 50a and 50b, respectively. The input signal can reach the second lower chip left pad 220a and the second lower chip right pad 220b through the lower chip left redistribution line 240a and the lower chip right redistribution line 240b, respectively, and then can be moved to the functional block inside the lower chip 200 through the internal wiring. It will be used later Figure 6 Functional blocks are described. In addition, the semiconductor package 1 may have an electrical signal path from the lower chip 200 to the package substrate 100 in contrast to the above-described path.

[0056] At the same time, the electrical signal exchange between the package substrate 100 and the upper chip 400 can be performed as follows. As an example, the electrical signal can be input from the package substrate 100 to the bonding left pad 230a of the lower chip 200 through the bonding lead 50a. The electrical signal can be transmitted to the second lower chip left pad 220a through the lower chip left redistribution line 240a. The electrical signal can reach the first lower chip left pad 210a through the internal circuit wiring. Thereafter, the electrical signal can be transmitted from the first lower chip left pad 210a to the lower left pad 320a of the interposer 300 through the first bump 520. Subsequently, the electrical signal can reach the upper right pad 310b through the fourth interposer redistribution line 352, the fourth through-hole extension pad 352p, the second through-hole electrode 330b, the second through-hole extension pad 342p and the second interposer redistribution line 342. The electrical signal can reach the first upper right chip pad 410b of the upper chip 400 from the upper right pad 310b through the second bump 530. In this way, the semiconductor package 1 can have an electrical signal path from the package substrate 100 to the upper chip 400 through the lower chip 200 and the interposer 300. In addition, in contrast to this path, the semiconductor package 1 can have an electrical signal path from the upper chip 400 to the package substrate 100 through the interposer 300 and the lower chip 200. Figure 5 , a portion of the electrical signal path between the lower chip 200 and the upper chip 400 of the electrical signal path between the package substrate 100 and the upper chip 400 is shown as “ F1 ”.

[0057] Similarly, as another example, an electrical signal may be input from the package substrate 100 to the wire bonding right pad 230b of the lower chip 200 through the bonding wire 50b. The electrical signal may be transmitted to the second lower chip right pad 220b through the lower chip right redistribution line 240b. The electrical signal may reach the first lower chip right pad 210b through the internal circuit wiring. Thereafter, the electrical signal may be transmitted from the first lower chip right pad 210b to the lower right pad 320b of the interposer 300 through the first bump 520. Then, the electrical signal may reach the upper left pad 310a through the third interposer redistribution line 351, the third through-hole extension pad 351p, the first through-hole electrode 330a, the first through-hole extension pad 341p, and the first interposer redistribution line 341. The electrical signal may reach the first upper chip left pad 410a of the upper chip 400 from the upper left pad 310a through the second bump 530. Thus, the semiconductor package 1 may have an electrical signal path from the package substrate 100 to the upper chip 400 through the lower chip 200 and the interposer 300. In addition, in contrast to this path, the semiconductor package 1 may have an electrical signal path from the upper chip 400 to the package substrate 100 through the interposer 300 and the lower chip 200.

[0058] Figure 6 is a diagram schematically showing an internal circuit configuration of a semiconductor package according to an embodiment of the present disclosure. Figure 6 The above reference may be schematically shown Figure 1 A diagram of an internal circuit of a semiconductor package 1 is described.

[0059] Reference Figure 6 The package substrate 100 may include connection pads 110a and 110b disposed on the upper surface 100S1 and connected to the bonding wires 50a and 50b. In addition, the package substrate 100 may include a connection structure 550 disposed on the lower surface 100S2 and provided for electrical connection with another semiconductor package or a printed circuit board.

[0060] The lower chip 200 may include: first and second input / output circuit blocks 200A1 and 200A2; a first address and command circuit block 200B1 connected to the first input / output circuit block 200A1; a first data transmission circuit block 200B2 connected to the second input / output circuit block 200A2; and a first memory unit core block 200C. The first memory unit core block 200C may be connected to the first address and command circuit block 200B1 and the first data transmission circuit block 200B2.

[0061] The upper chip 400 may include a second address and command circuit block 400B1 and a second data transmission circuit block 400B2 connected to a pair of first upper chip pads 210a and 210b, respectively. In addition, the upper chip 400 may include a second memory cell core block 400C connected to the second address and command circuit block 400B1 and the second data transmission circuit block 400B2. The upper chip 400 may have third and fourth input / output circuit blocks 400A1 and 400A2 connected to the second upper chip pads 420a and 420b, respectively. However, the second upper chip pads 420a and 420b are not directly connected to external components such as the package substrate 100, the lower chip 200, and the interposer 300.

[0062] In one embodiment, the electrical signal exchange between the package substrate 100 and the semiconductor chips 200 and 400 can be performed as follows. The electrical signals of the package substrate 100 can be input to the second lower chip pads 220a and 220b through the connection pads 110a and 110b, the bonding wires 50a and 50b, the wire bonding pads 230a and 230b of the lower chip 200, and the lower chip redistribution lines 240a and 240b. Among the input electrical signals, some input signals along the first lower chip internal wiring 200I1 can pass through the first input / output circuit block 200A1, and can be converted into the first address and command signal by the first address and command circuit block 200B1, and then can be transmitted to the first memory unit core block 200C. In addition, among the input electrical signals, some other input signals along the second lower chip internal wiring 200I2 can pass through the second input / output circuit block 200A2 and can be converted into data signals by the first data sending circuit block 200B2 and then can be transmitted to the first memory unit core block 200C.

[0063] At the same time, the first lower chip internal wiring 200I1 of the lower chip 200 can be connected to the first upper chip internal wiring 400I1 of the upper chip 400 through the first lower chip left pad 210a, the first bump 520, the lower left pad 320a of the interposer 300, the first internal wiring 360a of the interposer 300 (which includes a through-hole electrode and a redistribution line), the upper right pad 310b, the second bump 530 and the first upper chip right pad 410b. Therefore, among the electrical signals of the packaging substrate 100, some electrical signals output from the first address and command circuit 200B1 of the lower chip 200 can be input to the second address and command circuit block 400B1 along the first upper chip internal wiring 400I1 of the upper chip 400. The electrical signals can be converted into second address and command signals by the second address and command circuit block 400B1, and then transmitted to the second memory cell core block 400C.

[0064] Therefore, in one embodiment of the present disclosure, the upper chip 400 may exchange electrical signals with the package substrate 100 using an electrical signal path via the lower chip 200 and the interposer 300. That is, the upper chip 400 may not apply the fourth input / output circuit block 400A1 via the second upper chip right pad 420b.

[0065] Similarly, the second lower chip internal wiring 200I2 of the lower chip 200 can be connected to the second upper chip internal wiring 400I2 through the first lower chip right pad 210b, the first bump 520, the lower right pad 320b of the interposer 300, the second internal wiring 360b of the interposer 300 (which includes a through-hole electrode and a redistribution line), the upper left pad 310a, the second bump 530, and the first upper chip left pad 410a. Therefore, among the electrical signals of the packaging substrate 100, some electrical signals output from the first data transmission circuit block 200B2 of the lower chip 200 can be input to the second data transmission circuit block 400B2 along the second upper chip internal wiring 400I2. The electrical signal can be converted into a data signal by the second data transmission circuit block 400B2, and then transmitted to the second memory unit core block 400C.

[0066] In addition, refer again Figure 6 , the electrical signal output from the first memory cell core block 200C of the lower chip 200 may pass through the first address and command circuit block 200B1 and the first input / output circuit block 200A1 along the first lower chip internal wiring 200I1 to reach the second lower chip left pad 220a, or may pass through the first data transmission circuit block 200B2 and the second input / output circuit block 200A2 along the second lower chip internal wiring 200I2 to reach the second lower chip right pad 220b. Thereafter, the electrical signal may be transmitted to the wire bonding pads 230a and 230b through the lower chip redistribution lines 240a and 240b, and then transmitted to the package substrate 100 through the bonding wires 50a and 50b.

[0067] In addition, the electrical signal output from the second memory cell core block 400C of the upper chip 400 may pass through the second address and command circuit block 400B1 along the first upper chip internal wiring 400I1 to reach the first upper chip right pad 410b, or may pass through the second data transmission circuit block 400B2 along the second upper chip internal wiring 400I2 to reach the first upper chip left pad 410a. Afterwards, the electrical signal may reach the upper chip connection pads 310a and 310b of the interposer 300 through the second bump 530. Subsequently, the electrical signal may pass through the first internal wiring 360a and the second internal wiring 360b of the interposer 300 to reach the lower chip connection pads 320a and 320b of the interposer 300. Subsequently, the electrical signal may be input to the first lower chip pads 210a and 210b of the lower chip 200 through the first bump 520. The input electrical signal can be sent to the second lower chip pads 220a and 220b along the first lower chip internal wiring 200I1 and the second lower chip internal wiring 200I2, respectively. Subsequently, the electrical signal can be moved to the wire bonding pads 230a and 230b through the lower chip redistribution lines 240a and 240b, and then can be sent to the package substrate 100 through the bonding wires 50a and 50b, respectively.

[0068] In other words, the first input / output circuit block 200A1 and the second input / output circuit block 200A2 can receive the electrical signal of the package substrate 100 transmitted through the bonding wires 50a and 50b, the wire bonding pads 230a and 230b, the lower chip redistribution lines 240a and 240b, and the second lower chip pad 220a, respectively. In addition, the first input / output circuit block 200A1 and the second input / output circuit block 200A2 can transmit the received electrical signal to the first address and command block 200B1 and the first data transmission circuit block 200B2, respectively, using the internal wiring of the lower chip 200. The first address and command block 200B1 and the first data transmission circuit block 200B2 can receive the transmitted electrical signal, respectively. The first address and command block 200B1 and the first data transmission circuit block 200B2 transmit the received electrical signal to the first memory cell core block 200C of the lower chip 200, respectively.

[0069] In addition, the interposer 300 can receive some electrical signals of the package substrate 100 through the first lower chip pads 320a and 320b. In addition, the interposer 300 can send some received electrical signals to the first upper chip pads 410a and 410b of the upper chip 400 using the internal wiring of the interposer 300. The second address and command block 400B1 and the second data transmission circuit block 400B2 can receive electrical signals respectively transmitted to the first upper chip pads 410a and 410b using the internal wiring of the upper chip 400. In addition, the second address and command block 400B1 and the second data transmission circuit block 400B2 can respectively transmit the received electrical signals to the second memory cell core block 400C of the upper chip 400.

[0070] As described above, one embodiment of the present disclosure may provide a semiconductor package having a lower chip, an interposer, and an upper chip stacked on a package substrate. In the semiconductor package, the lower chip may exchange electrical signals with the package substrate using bonding wires. The upper chip is connected to the lower chip through the interposer, and may exchange electrical signals with the package substrate via the lower chip. Therefore, the upper chip may omit a direct electrical connection with the package substrate, thereby avoiding the use of input / output circuits in the upper chip, redistribution lines on the upper chip, and wire bonding pads that may be involved in the electrical connection between the upper chip and the package substrate. Therefore, the parasitic capacitance generated in the upper chip during the input / output processing of the electrical signal may be reduced.

[0071] Therefore, in one embodiment of the present disclosure, a semiconductor package structure capable of improving a signal transmission speed of a semiconductor package by reducing parasitic capacitance generated in a semiconductor chip stacked on a package substrate may be provided.

[0072] Figure 7 2 is a cross-sectional view schematically showing a semiconductor package 2 according to another embodiment of the present disclosure. Figure 7 , the semiconductor package 2 may have a further stacked Figure 1 The second lower chip 1200, the second interposer 1300, and the second upper chip 1400 on the semiconductor package 1 are described. In this case, the second lower chip 1200 may be electrically connected to the connection pads 110c and 110d of the package substrate 100 through the bonding wires 50c and 50d.

[0073] The semiconductor package 2 may include a package substrate 100, a first stack structure 2a disposed on the package substrate 100, and a second stack structure 2b disposed on the first stack structure 2a. The first stack structure 2a may include a first lower chip 200, a first interposer 300, and a first upper chip 400. The second stack structure 2b may include a second lower chip 1200, a second interposer 1300, and a second upper chip 1400. An adhesive layer 540 may be disposed between the first upper chip 400 of the first stack structure 2a and the second lower chip 1200 of the second stack structure 2b so that the first stack structure 2a and the second stack structure 2b may be bonded to each other.

[0074] In addition, the semiconductor package 2 may include: first bonding leads 50a and 50b, which electrically connect the first lower chip 200 of the first stacking structure 2a to the packaging substrate 100; and second bonding leads 50c and 50d, which electrically connect the second lower chip 1200 of the second stacking structure 2b to the packaging substrate 100.

[0075] The configuration of the first lower chip 200, the first interposer 300, and the first upper chip 400 of the first stack structure 2a may be the same as that described above with reference to Figure 1 The configurations of the lower chip 200, the interposer 300, and the upper chip 400 of the described semiconductor package 1 are the same. That is, components having the same reference numerals are substantially the same components, and thus repeated descriptions of these components will be omitted here.

[0076] The configuration of the second lower chip 1200, the second interposer 1300, and the second upper chip 1400 of the second stacked structure 2b may be substantially the same as the configuration of the first lower chip 200, the first interposer 300, and the first upper chip 400 of the first stacked structure 2a. As an example, the pads 1210a, 1210b, 1220a, and 1220b of the second lower chip 1200 may have the same configuration as the pads 210a, 210b, 220a, and 220b of the first lower chip 200. In addition, the wire bonding pads 1230a and 1230b of the second lower chip 1200 may have the same configuration as the wire bonding pads 230a and 230b of the first lower chip 200. In addition, the redistribution lines 1240a and 1240b of the second lower chip 1200 may have the same configuration as the redistribution lines 240a and 240b of the first lower chip 200. In addition, the pads 1410a, 1410b, 1420a, and 1420b of the second upper chip 1400 may have the same configuration as the pads 410a, 410b, 420a, and 420b of the first upper chip 400. In addition, the upper chip connection pads 1310a and 1310b, the second through-hole electrodes 1330a and 1330b, and the lower chip connection pads 1320a and 1320b of the second interposer 1300 may have the same configuration as the upper chip connection pads 310a and 310b, the first through-hole electrodes 330a and 330b, and the lower chip connection pads 320a and 320b of the first interposer 300. The second lower chip 1200 and the second interposer 1300 may be electrically connected to each other through the third bump 550, and the second interposer 1300 and the second upper chip 1400 may be electrically connected to each other through the fourth bump 560.

[0077] The first lower chip 200 may be electrically connected to the package substrate 100 through bonding wires 50a and 50b. The bonding wires 50a and 50b may electrically connect the wire bonding pads 230a and 230b of the first lower chip 200 to the connection pads 110a and 110b of the package substrate 100. On the other hand, after the first upper chip 400 is connected to the first lower chip 200 using the first interposer 300, the first upper chip 400 may be electrically connected to the package substrate 100 through the first lower chip 200.

[0078] The second lower chip 1200 may be electrically connected to the package substrate 100 through bonding wires 50c and 50d. The bonding wires 50c and 50d may electrically connect the wire bonding pads 1230a and 1230b of the second lower chip 1200 to the connection pads 110c and 110d of the package substrate 100. On the other hand, after being connected to the second lower chip 1200 using the second interposer 1300, the second upper chip 1400 may be electrically connected to the package substrate 100 via the second lower chip 1200.

[0079] Reference Figure 7 , the edge portion of the first interposer 300 may be disposed at a position recessed in a lateral direction (i.e., a direction parallel to the x-axis) from the edge portion of the first upper chip 400 and the edge portion of the first lower chip 200. As an example, the two sidewall surfaces 300E1 and 300E2 of the first interposer 300 may be disposed at a position recessed in a lateral direction (i.e., a direction parallel to the x-axis) from the two sidewall surfaces 400E1 and 400E2 of the first upper chip 400 and the two sidewall surfaces 200E1 and 200E2 of the first lower chip 200, respectively. The edge portion of the second interposer 1300 may be disposed at a position recessed in a lateral direction (i.e., a direction parallel to the x-axis) from the edge portion of the second upper chip 1400 and the edge portion of the second lower chip 1200. As an example, both sidewall surfaces 1300E1 and 1300E2 of the second interposer 1300 may be disposed at positions recessed from both sidewall surfaces 1400E1 and 1400E2 of the second upper chip 1400 and both sidewall surfaces 1200E1 and 1200E2 of the second lower chip 1200 in a lateral direction (i.e., a direction parallel to the x-axis), respectively.

[0080] exist Figure 7 In the present invention, although a semiconductor package structure in which two stack structures 2a and 2b having substantially the same configuration are stacked on a package substrate 100 is disclosed, in some other embodiments, the number of stack structures stacked on the package substrate 100 may not be limited thereto. That is, in other embodiments, a semiconductor package in which at least three stack structures according to embodiments of the present disclosure are stacked on the package substrate 100 may be implemented.

[0081] As described above, one embodiment of the present disclosure provides a semiconductor package having a lower chip, an interposer, and an upper chip stacked sequentially on a package substrate. In the semiconductor package, the lower chip can be connected to the package substrate using wire bonding. The upper chip can be connected to the lower chip through a through-hole electrode of the interposer, and can be electrically connected to the package substrate via the lower chip.

[0082] In one embodiment of the present disclosure, the upper chip can be electrically connected to the package substrate through the interposer and the lower chip without being directly connected to the package substrate. Therefore, in order to exchange signals with the package substrate, the upper chip may not apply input / output pads and input / output circuits associated with wire bonding. As a result, during the operation of the semiconductor package, the parasitic capacitance generated in the input / output pads and input / output circuits of the upper chip can be reduced. In this way, one embodiment of the present disclosure can provide a semiconductor package structure that can reduce the parasitic capacitance generated in the semiconductor chip, thereby improving the performance of the semiconductor package such as signal transmission speed. As described above, one embodiment of the present disclosure has been disclosed and shown in the accompanying drawings. Various other modifications can be made according to the technical spirit proposed in the present disclosure.

[0083] CROSS-REFERENCE TO RELATED APPLICATIONS

[0084] This application claims priority to Korean Patent Application No. 10-2019-0157705, filed on November 29, 2019, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package, comprising: Package substrate; a lower chip, an interposer, and an upper chip stacked on the package substrate; as well as bonding wires electrically connecting the lower chip to the package substrate, Wherein, the lower chip comprises: a first lower chip pad and a second lower chip pad, the first lower chip pad and the second lower chip pad being spaced apart from each other on an upper surface of the lower chip and being electrically connected to each other via a functional block inside the lower chip through internal wiring; a wire bonding pad bonded to the bonding wire on an upper surface of the lower chip; and a lower chip redistribution line disposed on an upper surface of the lower chip and electrically connecting the second lower chip pad to the wire bonding pad, Wherein, the intermediate layer includes: an upper chip connection pad electrically connected to the upper chip on an upper surface of the interposer; a lower chip connection pad electrically connected to the first lower chip connection pad on a lower surface of the interposer; and a through-hole electrode electrically connecting the upper chip connection pad to the lower chip connection pad, wherein the electrical signal of the package substrate is transmitted from the wire bonding pad to the second lower chip pad through the lower chip redistribution line, and the electrical signal is transmitted from the second lower chip pad to the first lower chip pad via the functional block, The functional blocks include an input / output circuit block, an address and command block, and a data transmission circuit block. wherein the first lower chip pads include a first lower chip left pad and a first lower chip right pad that are configured in pair and transmit electrical signals different from each other, The lower chip connection pads include a lower left pad disposed directly above the first lower chip left pad and a lower right pad disposed directly above the first lower chip right pad. The upper chip connection pad includes an upper left pad disposed directly above the lower left pad and an upper right pad disposed directly above the lower right pad, and Wherein, the first lower chip left pad is electrically connected to the lower left pad and the upper right pad, and the first lower chip right pad is electrically connected to the lower right pad and the upper left pad.

2. The semiconductor package according to claim 1, wherein The upper chip comprises: a first upper chip pad disposed on an upper surface of the upper chip facing the interposer; and a second upper chip pad spaced apart from the first upper chip pad in a lateral direction on the upper surface of the upper chip, Wherein, the first upper chip pad is connected to the upper chip connection pad, and the second upper chip pad is not electrically connected to the interposer.

3. The semiconductor package according to claim 2, further comprising: a first bump disposed between the first lower chip pad and the lower chip connection pad; as well as A second bump is disposed between the first upper chip pad and the upper chip connection pad.

4. The semiconductor package according to claim 1, wherein: The lower chip is directly and electrically connected to the package substrate, and The upper chip is electrically connected to the packaging substrate through the interposer and the lower chip.

5. The semiconductor package according to claim 1, wherein The lower chip includes a pair of the first lower chip pads, a pair of the second lower chip pads, and a pair of the wire bonding pads, and Wherein, the upper chip includes a pair of first upper chip pads.

6. The semiconductor package according to claim 5, wherein: The lower chip comprises: a first input / output circuit block and a second input / output circuit block, the first input / output circuit block and the second input / output circuit block being connected to a pair of the second lower chip pads, respectively; a first address and command block connected to the first input / output circuit block; a first data transmission circuit block connected to the second input / output circuit block; and a first memory unit core block connected to the first address and command block and the first data transmission circuit block, and Wherein, the upper chip comprises: a second address and command block and a second data transmission circuit block, the second address and command block and the second data transmission circuit block being respectively connected to a pair of the upper chip pads; and A second memory unit core block connected to the second address and command block and the second data transmission circuit block.

7. The semiconductor package according to claim 6, in, The first input / output circuit block and the second input / output circuit block respectively receive electrical signals of the package substrate transmitted through the bonding wires, the wire bonding pads, the lower chip redistribution lines, and the second lower chip pads; The first input / output circuit block and the second input / output circuit block respectively transmit the received electrical signal to the first address and command block and the first data transmission circuit block using internal wiring of the lower chip; The first address and command block and the first data transmission circuit block respectively receive the transmitted electrical signal; and The first address and command block and the first data transmission circuit block respectively transmit the received electrical signal to the first memory cell core block of the lower chip.

8. The semiconductor package according to claim 7, in, The interposer receives a portion of the electrical signal of the package substrate through the first lower chip pad; The interposer transmits a portion of the received electrical signal to the first upper chip pad of the upper chip using the internal wiring of the interposer; the second address and command block and the second data transmission circuit block respectively receive the electrical signal transmitted to the first upper chip pad using internal wiring of the upper chip; and The second address and command block and the second data transmission circuit block transmit the received electrical signal to the second memory cell core block of the upper chip, respectively.

9. The semiconductor package according to claim 1, wherein: The edge portion of the interposer is disposed at a position recessed from edge portions of the upper chip and the lower chip in a lateral direction.

10. The semiconductor package according to claim 1, wherein The upper chip connection pads and the lower chip connection pads are each arranged as a pair of pads symmetrical about a central axis of the interposer.

11. The semiconductor package according to claim 10, wherein: The interposer includes the upper left pad and the upper right pad symmetrical about a central axis of the interposer, and includes the lower left pad and the lower right pad as the lower chip connection pad, the lower left pad is arranged to overlap with the upper left pad, and the lower right pad is arranged to overlap with the upper right pad, and The upper left pad is electrically connected to the lower right pad through a first through-hole electrode, and the upper right pad is electrically connected to the lower left pad through a second through-hole electrode.

12. The semiconductor package according to claim 11, wherein The intermediate layer includes: a first interposer redistribution line disposed on an upper surface of the interposer and electrically connecting the upper left pad to the first via electrode; a second interposer redistribution line disposed on an upper surface of the interposer and electrically connecting the upper right pad to the second via electrode; a third interposer redistribution line disposed on a lower surface of the interposer and electrically connecting the lower right pad to the first via electrode; and A fourth interposer redistribution line is disposed on a lower surface of the interposer and electrically connects the lower left pad to the second via electrode.

13. A semiconductor package, comprising: Package substrate; a lower chip, the lower chip being disposed on the packaging substrate and electrically connected to the packaging substrate through wire bonding; an interposer disposed on the lower chip and including a through-hole electrode electrically connected to the lower chip; and an upper chip disposed on the interposer and electrically connected to the through-hole electrodes, wherein the upper chip is electrically connected to the packaging substrate through the interposer and the lower chip, and Wherein, the lower chip comprises: a first lower chip pad and a second lower chip pad, the first lower chip pad and the second lower chip pad being spaced apart from each other on an upper surface of the lower chip and being electrically connected to each other via a functional block inside the lower chip through internal wiring; a wire bonding pad bonded to a bonding wire on an upper surface of the lower chip; and a lower chip redistribution line electrically connecting the second lower chip pad to the wire bonding pad, wherein the electrical signal of the package substrate is transmitted from the wire bonding pad to the second lower chip pad through the lower chip redistribution line, and the electrical signal is transmitted from the second lower chip pad to the first lower chip pad via the functional block, The functional blocks include an input / output circuit block, an address and command block, and a data transmission circuit block. wherein the first lower chip pads include a first lower chip left pad and a first lower chip right pad that are configured in pair and transmit electrical signals different from each other, wherein the interposer comprises a lower chip connection pad on a lower surface of the interposer and an upper chip connection pad on an upper surface of the interposer, The lower chip connection pads include a lower left pad disposed directly above the first lower chip left pad and a lower right pad disposed directly above the first lower chip right pad. The upper chip connection pad includes an upper left pad disposed directly above the lower left pad and an upper right pad disposed directly above the lower right pad, and Wherein, the first lower chip left pad is electrically connected to the lower left pad and the upper right pad, and the first lower chip right pad is electrically connected to the lower right pad and the upper left pad.

14. The semiconductor package according to claim 13, wherein: The first lower chip pad is electrically connected to the through-hole electrode, and Wherein, the lower chip redistribution line is arranged on the upper surface of the lower chip.

15. The semiconductor package according to claim 14, wherein: The upper chip connection pads are electrically connected to the upper chip on the upper surface of the interposer; and Wherein, the through-hole electrode electrically connects the lower chip connection pad to the upper chip connection pad.

16. The semiconductor package according to claim 15, wherein: The upper chip includes an upper chip bond pad connected to the upper chip connection pad on an upper surface of the upper chip facing the interposer.

17. The semiconductor package according to claim 13, wherein: The edge portion of the interposer is disposed at a position recessed from edge portions of the upper chip and the lower chip in a lateral direction.

18. A semiconductor package, comprising: Package substrate; A first stacking structure, the first stacking structure is arranged on the packaging substrate, the first stacking structure comprises a first lower chip, a first interposer and a first upper chip; a second stacking structure, the second stacking structure being disposed on the first stacking structure, the second stacking structure comprising a second lower chip, a second interposer, and a second upper chip; a first bonding wire electrically connecting the package substrate to the first lower chip of the first stacked structure; as well as a second bonding wire electrically connecting the package substrate to the second lower chip of the second stack structure, wherein the first interposer comprises a first through-hole electrode, the first through-hole electrode electrically connecting the first lower chip to the first upper chip, and the second interposer comprises a second through-hole electrode, the second through-hole electrode electrically connecting the second lower chip to the second upper chip, wherein the first upper chip is electrically connected to the package substrate through the first interposer and the first lower chip, and wherein the second upper chip is electrically connected to the packaging substrate through the second interposer and the second lower chip, Wherein, the first lower chip comprises: a first lower chip pad and a second lower chip pad, the first lower chip pad and the second lower chip pad being spaced apart from each other on an upper surface of the first lower chip and being electrically connected to each other via a functional block inside the first lower chip through internal wiring; a wire bonding pad bonded to the bonding wire on an upper surface of the first lower chip; and a lower chip redistribution line disposed on an upper surface of the first lower chip and electrically connecting the second lower chip pad to the wire bonding pad, Wherein, the first intermediary layer comprises: an upper chip connection pad electrically connected to the first upper chip on an upper surface of the first interposer; a lower chip connection pad electrically connected to the first lower chip connection pad on a lower surface of the first interposer, wherein the electrical signal of the package substrate is transmitted from the wire bonding pad to the second lower chip pad through the lower chip redistribution line, and the electrical signal is transmitted from the second lower chip pad to the first lower chip pad via the functional block, The functional blocks include an input / output circuit block, an address and command block, and a data transmission circuit block. wherein the first lower chip pads include a first lower chip left pad and a first lower chip right pad that are configured in pair and transmit electrical signals different from each other, The lower chip connection pads include a lower left pad disposed directly above the first lower chip left pad and a lower right pad disposed directly above the first lower chip right pad. The upper chip connection pad includes an upper left pad disposed directly above the lower left pad and an upper right pad disposed directly above the lower right pad, and Wherein, the first lower chip left pad is electrically connected to the lower left pad and the upper right pad, and the first lower chip right pad is electrically connected to the lower right pad and the upper left pad.

19. The semiconductor package according to claim 18, wherein: The edge portion of the first interposer is disposed at a position recessed from the edge portion of the first upper chip and the edge portion of the first lower chip in a lateral direction, and The edge portion of the second interposer is disposed at a position recessed from the edge portion of the second upper chip and the edge portion of the second lower chip in a lateral direction. 20 . The semiconductor package of claim 18 , further comprising an adhesive layer disposed between the first upper chip of the first stack structure and the second lower chip of the second stack structure.

Images