Display substrate, manufacturing method thereof, and display device

Abstract

The present invention provides a display substrate, a manufacturing method thereof, and a display device, wherein the display substrate includes a gate line extending along a first direction and a data line extending along a second direction, and the gate line and the data line cross to enclose a plurality of sub-pixel areas; wherein the gate line includes a first transmission segment and a second transmission segment arranged alternately, wherein the second transmission segment includes at least two signal transmission lines, each signal transmission line is respectively connected to two adjacent first transmission segments in the first direction, and the orthographic projection of the data line on the substrate substrate and the orthographic projection of the signal transmission line on the substrate substrate have an overlapping area; the data line includes a first part and a second part extending along the second direction, and a third part connecting the first part and the second part, and the extension direction of the third part is at an angle to the second direction. The display substrate, the manufacturing method thereof, and the display device provided by the present invention can reduce the layout difficulty of the repair structure in the display substrate and improve the manufacturing efficiency of the display device.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] With the continuous advancement of technology and the improvement of people's living standards, people's demand for display is also increasing. In order to meet the needs of consumers, many manufacturers have begun to design 8K or even higher resolution display devices.

[0003] In the related art, as the PPI (pixels per inch) of the display device becomes higher and higher, the space inside the display device becomes smaller and smaller, and the signal lines are inevitably more and more closely packed together, which makes the spatial design of the repair structure used to improve the product yield very difficult. Summary of the invention

[0004] Embodiments of the present invention provide a display substrate and a manufacturing method thereof and a display device to alleviate the problem in the related art that the spatial design of a repair structure in a high PPI display device is very difficult.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0006] In a first aspect, an embodiment of the present invention provides a display substrate, comprising gate lines extending along a first direction and data lines extending along a second direction, wherein the first direction and the second direction intersect, and the gate lines and the data lines cross to enclose a plurality of sub-pixel regions; wherein:

[0007] At least one gate line comprises a first transmission segment and a second transmission segment which are alternately arranged, wherein the second transmission segment comprises at least two signal transmission lines, each signal transmission line is respectively connected to two adjacent first transmission segments in the first direction, and an orthographic projection of at least one data line on the substrate and an orthographic projection of one signal transmission line of the at least one gate line on the substrate have an overlapping area;

[0008] At least one data line includes a first portion and a second portion extending along the second direction, and a third portion connecting the first portion and the second portion, and an extending direction of the third portion forms an angle with the second direction.

[0009] Furthermore, the display unit in the display substrate includes a first sub-pixel, a second sub-pixel and a third sub-pixel arranged in sequence along the first direction, wherein two first data lines are arranged between the first sub-pixel and the second sub-pixel, and a second data line is arranged between the second sub-pixel and the third sub-pixel, and the second data line includes a first portion and a second portion extending along the second direction, and a third portion connecting the first portion and the second portion, and an extension direction of the third portion forms an angle with the second direction.

[0010] Further, a width of the third portion of the second data line in a direction perpendicular to the extension direction of the second data line is greater than a width of the second portion of the second data line in the first direction.

[0011] Furthermore, the capacitor and the transistor in the first sub-pixel are symmetrically arranged with the capacitor and the transistor in the second sub-pixel.

[0012] Furthermore, at least one first portion of the second data line is located on the same straight line extending along the second direction, at least one second portion of the second data line is located on the same straight line extending along the second direction, and the first portion and the second portion of the second data line are respectively located on different straight lines.

[0013] Furthermore, the second transmission segment includes a first sub-transmission segment and the second sub-transmission segment, and the orthographic projection of the first sub-transmission segment on the substrate substrate and the orthographic projection of the two first data lines on the substrate substrate have an overlapping area; the orthographic projection of the second sub-transmission segment on the substrate substrate and the orthographic projection of the one second data line on the substrate substrate have an overlapping area.

[0014] Furthermore, a sensing line extending along the second direction is further disposed on a side of the third sub-pixel away from the second sub-pixel.

[0015] Furthermore, the second transmission segment includes a third sub-transmission segment, and an orthographic projection of the third sub-transmission segment on the substrate and an orthographic projection of the sensing line on the substrate have an overlapping area.

[0016] Further, the sensing line includes a first portion and a second portion, and a width of the first portion of the sensing line in the first direction is different from a width of the second portion of the sensing line in the first direction.

[0017] Furthermore, an orthographic projection of the first portion of the sensing line on the substrate and an orthographic projection of the gate line on the substrate have an overlapping area; and the second portion of the sensing line is located between two adjacent first portions in the second direction and respectively connects the two adjacent first portions.

[0018] Further, a width of the first portion of the sensing line in the first direction is smaller than a width of the second portion of the sensing line in the first direction.

[0019] Furthermore, an auxiliary electrode line extending along the second direction is further disposed on a side of the third sub-pixel away from the second sub-pixel.

[0020] Furthermore, an orthographic projection of the third sub-transmission segment on the base substrate also has an overlapping area with an orthographic projection of the auxiliary electrode line on the base substrate.

[0021] Further, the auxiliary electrode line includes a first portion and a second portion, and a width of the first portion of the auxiliary electrode line in the first direction is different from a width of the second portion of the auxiliary electrode line in the first direction.

[0022] Furthermore, the orthographic projection of the first part of the auxiliary electrode line on the base substrate has an overlapping area with the orthographic projection of the gate line on the base substrate; the second part of the auxiliary electrode line is located between two adjacent first parts in the second direction and respectively connects the two adjacent first parts.

[0023] Further, a width of the first portion of the auxiliary electrode line in the first direction is smaller than a width of the second portion of the auxiliary electrode line in the first direction.

[0024] Furthermore, a power line extending along the second direction is further disposed on a side of the first sub-pixel away from the second sub-pixel.

[0025] Furthermore, the second transmission segment includes a fourth sub-transmission segment, and an orthographic projection of the fourth sub-transmission segment on the base substrate and an orthographic projection of the power line on the base substrate have an overlapping area.

[0026] Further, the power line includes a first portion and a second portion, and a width of the first portion of the power line in the first direction is different from a width of the second portion of the power line in the first direction.

[0027] Furthermore, the orthographic projection of the first part of the power line on the base substrate has an overlapping area with the orthographic projection of the gate line on the base substrate; the second part of the power line is located between two adjacent first parts in the second direction and respectively connects the two adjacent first parts.

[0028] Further, a width of the first portion of the power line in the first direction is smaller than a width of the second portion of the auxiliary electrode line in the first direction.

[0029] Further, each sub-pixel region includes a pixel driving circuit, and the pixel driving circuit includes a first transistor, a second transistor, a third transistor, a storage capacitor and a light-emitting element;

[0030] The control electrode of the first transistor is connected to the first gate line, the first electrode of the first transistor is connected to the data line, and the second electrode of the first transistor is connected to the first electrode plate of the storage capacitor;

[0031] The control electrode of the second transistor is connected to the second gate line, the first electrode of the second transistor is connected to the touch sensing line, and the second electrode of the second transistor is connected to the second electrode plate of the storage capacitor;

[0032] The control electrode of the third transistor is connected to the second electrode of the first transistor, the first electrode of the third transistor is connected to a power line, and the second electrode of the third transistor is connected to the light emitting element.

[0033] Furthermore, an insulating layer is arranged between the first plate of the storage capacitor and the second plate of the storage capacitor, the second plate includes two sub-plates that are parallel to each other and electrically connected, the first plate is arranged between the two sub-plates of the second plate, and the two sub-plates have portions that are opposite to the first plate respectively.

[0034] Furthermore, the sub-pixel area includes a thin film transistor array layer located on the substrate, the thin film transistor array layer includes a shading pattern, a buffer layer covering the shading pattern, an active layer located on the buffer layer, a gate metal layer located on the active layer and the buffer layer, an insulating layer covering the buffer layer, the active layer and the gate metal layer, and a metal pattern located on the insulating layer.

[0035] Furthermore, the first electrode of the first transistor includes a first via hole opened in the thin film transistor array layer, and the first via hole penetrates the insulating layer to connect the first metal part in the metal pattern with the active layer; the second electrode of the first transistor includes a second via hole opened in the thin film transistor array layer, and the second via hole penetrates the insulating layer to connect the second metal part in the metal pattern with the active layer and the gate metal layer respectively.

[0036] Furthermore, the first electrode of the second transistor includes a third via hole opened in the thin film transistor array layer, the third via hole penetrates the insulating layer, so that the third metal part in the metal pattern is connected to the active layer; the second electrode of the second transistor includes a fourth via hole and a fifth via hole opened in the thin film transistor array layer, the fourth via hole penetrates the insulating layer, so that the fourth metal part in the metal pattern is connected to the active layer, the fifth via hole penetrates the insulating layer and the buffer layer, and the fourth metal part is connected to the shading pattern through the fifth via hole.

[0037] Furthermore, the first electrode of the third transistor includes a sixth via hole opened in the thin film transistor array layer, the sixth via hole penetrates the insulating layer, so that the fifth metal part in the metal pattern is connected to the active layer; the second electrode of the third transistor includes a seventh via hole and an eighth via hole opened in the thin film transistor array layer, the seventh via hole penetrates the insulating layer, so that the sixth metal part in the metal pattern is connected to the active layer, the eighth via hole penetrates the insulating layer and the buffer layer, and the sixth metal part is connected to the shading pattern through the eighth via hole.

[0038] Furthermore, the first gate line is located between the first via hole and the sixth via hole.

[0039] Furthermore, the first sub-transmission segment is located in a region surrounded by the first via hole and the sixth via hole of the first sub-pixel and the first via hole and the sixth via hole of the second sub-pixel.

[0040] Furthermore, the second sub-transmission segment is located in a region surrounded by the first via hole and the sixth via hole of the second sub-pixel and the first via hole and the sixth via hole of the third sub-pixel.

[0041] Furthermore, the second gate line is located between the fourth via hole and the eighth via hole.

[0042] Furthermore, the resistance values ​​of different data lines are substantially equal.

[0043] Furthermore, the capacitance values ​​of parasitic capacitors generated by coupling different data lines with any other signal line are substantially equal, and the numbers of parasitic capacitors generated by coupling different data lines with other signal lines are substantially equal.

[0044] In a second aspect, an embodiment of the present invention further provides a display device, comprising the display substrate as described above.

[0045] In a third aspect, an embodiment of the present invention further provides a method for manufacturing a display substrate, the method comprising:

[0046] Providing a substrate;

[0047] A gate line extending along a first direction is formed on the substrate, wherein at least one gate line comprises a first transmission segment and a second transmission segment arranged alternately, the second transmission segment comprises at least two signal transmission lines, and each signal transmission line is respectively connected to two adjacent first transmission segments in the first direction;

[0048] Data lines extending along a second direction are formed on the base substrate, wherein an orthographic projection of at least one data line on the base substrate and an orthographic projection of the second transmission segment on the base substrate have an overlapping area, and at least one data line includes a first portion and a second portion extending along the second direction, and a third portion connecting the first portion and the second portion, and an extension direction of the third portion forms an angle with the second direction.

[0049] In the technical solution provided by the present invention, each second transmission segment as a repair structure includes at least two signal transmission lines, so that when one of the signal transmission lines is short-circuited with the data line (Data Gate Short, referred to as DGS), the signal transmission line can be cut off to ensure that the data signal is smoothly transmitted in the data line and the gate scanning signal is smoothly transmitted in the remaining signal transmission lines, thereby improving the yield of the display device. By bending at least one data line, it is possible to free up space in a high PPI display device to accommodate the second transmission segment, reduce the layout difficulty of the second transmission segment in the display substrate, and improve the manufacturing efficiency of the display device. Therefore, the technical solution provided by the present invention can reduce the layout difficulty of the repair structure in the display substrate and improve the manufacturing efficiency of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0051] Figure 1 A schematic structural diagram of a display substrate provided by an embodiment of the present invention;

[0052] Figure 2 for Figure 1 A schematic diagram of the structure of two adjacent pixel units located in the same row;

[0053] Figure 3 for Figure 2 A schematic diagram of the structure of the data line 120B;

[0054] Figure 4 for Figure 2 A cross-sectional view of the second transmission section in the embodiment of the present invention taken along the second direction;

[0055] Figure 5 A schematic structural diagram of a pixel driving circuit in a display substrate provided by another embodiment of the present invention;

[0056] Figure 6 for Figure 2 Schematic diagram of the center section line and via position;

[0057] Figure 7 for Figure 6 Sectional view along line Ⅰ-Ⅰ';

[0058] Figure 8 for Figure 6 The cross-sectional view along the line II-II';

[0059] Fig. 9 for Figure 2 Schematic diagram of the location of parasitic capacitors;

[0060] Fig.10 A method for manufacturing a display substrate is provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] In the related art, as the PPI (pixels per inch) of the display device becomes higher and higher, the space inside the display device becomes smaller and smaller, and the signal lines are inevitably more and more closely packed together, which makes the spatial design of the repair structure used to improve the product yield very difficult.

[0063] In view of the above problems, the embodiments of the present invention provide a display substrate and a display device, which can solve the problem that the spatial design of the repair structure in the high PPI display device in the related art is very difficult.

[0064] An embodiment of the present invention provides a display substrate, such as Figures 1 to 3As shown, it includes a gate line 110 extending along a first direction and a data line 120 extending along a second direction, the first direction and the second direction intersect, and the gate line 110 and the data line 120 cross to enclose a plurality of sub-pixel areas 130; wherein at least one gate line 110 includes first transmission segments 111 and second transmission segments 112 arranged alternately, wherein the second transmission segment 112 includes at least two signal transmission lines 1121, each signal transmission line 1121 is respectively connected to two adjacent first transmission segments 111 in the first direction, and the orthographic projection of at least one data line 120 on the substrate substrate has an overlapping area with the orthographic projection of one signal transmission line 1121 of the at least one gate line 110 on the substrate substrate;

[0065] At least one data line 120 includes a first portion 121 and a second portion 122 extending along the second direction, and a third portion 123 connecting the first portion 121 and the second portion 122 , wherein an extending direction of the third portion 123 forms an angle with the second direction 122 .

[0066] In an embodiment of the present invention, each second transmission segment as a repair structure includes at least two signal transmission lines, so that when a short circuit DGS occurs between one of the signal transmission lines and the data line, the signal transmission line can be cut off to ensure that the data signal is smoothly transmitted in the data line and the gate scanning signal is smoothly transmitted in the remaining signal transmission lines, thereby improving the yield of the display device. By bending at least one data line, a space that can accommodate the second transmission segment can be vacated in a high PPI display device, reducing the layout difficulty of the second transmission segment in the display substrate and improving the manufacturing efficiency of the display device. Therefore, the technical solution provided by the present invention can reduce the layout difficulty of the repair structure in the display substrate and improve the manufacturing efficiency of the display device.

[0067] In the embodiment of the present invention, a display unit in the display substrate may be a three-color pixel including a red sub-pixel (R), a green sub-pixel (G) and a blue sub-pixel (B). Figure 2 As shown; it may also include other color sub-pixels such as white sub-pixels and yellow sub-pixels.

[0068] In the embodiment of the present invention, the first direction is Figure 2 The second direction is the horizontal direction (i.e., the row direction of the pixel arrangement). Figure 2 The longitudinal direction (i.e., the column direction of pixel arrangement) is taken as an example for explanation.

[0069] like Figure 3As shown, each gate line 110 includes a plurality of first transmission segments 111 and a plurality of second transmission segments 112. The first transmission segments 111 and the second transmission segments 112 are arranged alternately and transmit the same gate scanning signal together. The number of signal transmission lines 1121 in the plurality of second transmission segments 112 can be uniform, for example: each second transmission segment 112 includes two signal transmission lines 1121, such as Figure 2 As shown; the number of signal transmission lines 1121 in the plurality of second transmission segments 112 may also be different, for example: some of the second transmission segments 112 include two signal transmission lines, and some of the second transmission segments 112 include three signal transmission lines.

[0070] Taking each second transmission section 112 including two signal transmission lines 1121 as an example, Figure 2 The cross-sectional views of the second transmission section 112 cut along the second direction are as follows Figure 4 As shown, it includes two signal transmission lines 1121 for transmitting gate scanning signals.

[0071] The second transmission section 112 is designed to avoid a short circuit DGS between the gate line 110 and the data line 120, so as to prevent the gate scanning signal and the data signal from being unable to be transmitted normally due to the DGS. When a signal transmission line and the data line 120 are short-circuited in a second transmission section 112, the data line 120 can be restored by cutting off the short-circuited signal transmission line to transmit the data signal normally, and the gate scanning signal can also be transmitted normally through other signal transmission lines.

[0072] The multiple data lines 120 can be arranged with one column of sub-pixels between them. In this case, the number of second transmission segments 112 in each gate line 110 is equal to the number of data lines 120, that is, the orthographic projections of the multiple second transmission segments 112 of a gate line 110 on the substrate overlap with the orthographic projections of the multiple data lines on the substrate one by one.

[0073] The data line 120 includes a first portion 121 and a second portion 122 extending along the second direction, and a third portion 123 whose extending direction forms an angle with the second direction. The bending angle of the third portion 123 relative to the second direction, i.e., the angle between the extending direction of the third portion 123 and the second defense line, is an acute angle.

[0074] Since the second transmission segment 112 of the gate line 110 includes at least two signal transmission lines, the space occupied by the second transmission segment 112 is relatively large. In an embodiment of the present invention, in order to enable the second transmission segment 112 to be arranged between two sub-pixels, at least one data line is bent to free up space for the layout of the second transmission segment 112, thereby reducing the difficulty of layout of the second transmission segment 112 in the display substrate and improving the manufacturing efficiency of the display device.

[0075] Furthermore, if Figure 2 As shown, the display unit in the display substrate includes a first sub-pixel 131, a second sub-pixel 132 and a third sub-pixel 133 arranged in sequence along the first direction, wherein two first data lines 120A are arranged between the first sub-pixel 131 and the second sub-pixel 132, and one second data line 120B is arranged between the second sub-pixel 132 and the third sub-pixel 133, wherein as Figure 3 As shown, the second data line 120B includes a first portion 121 and a second portion 122 extending along the second direction, and a third portion 123 connecting the first portion 121 and the second portion 122, and an extending direction of the third portion 123 forms an angle with the second direction.

[0076] The data lines in this embodiment are arranged in a manner that two of three consecutive data lines are arranged close to each other, and the other data line is spaced apart from the two data lines by a column of sub-pixels, and each display unit includes only 3 sub-pixels.

[0077] Among them, Figure 2 As shown, the second transmission segment 112 includes a first sub-transmission segment 112-1 and a second sub-transmission segment 112-2, and the first transmission segment 111 is between the first sub-transmission segment 112-1 and the second sub-transmission segment 112-2. The first sub-transmission segment 112-1 includes at least two signal transmission lines 1121, wherein each signal transmission line 1121 is connected to two first transmission segments 111 adjacent to the first sub-transmission segment 112-1 in the first direction. The second sub-transmission segment 112-2 includes at least two signal transmission lines 1121, wherein each signal transmission line 1121 is connected to two first transmission segments 111 adjacent to the second sub-transmission segment 112-2 in the first direction.

[0078] The orthographic projection of the first sub-transmission segment 112-1 on the substrate substrate and the orthographic projection of the two first data lines 120A on the substrate substrate have an overlapping area, which can avoid the occurrence of DGS between this gate line 110 and at least one of the two first data lines 120A close to each other; the orthographic projection of the second sub-transmission segment 112-2 on the substrate substrate and the orthographic projection of a second data line 120B on the substrate substrate have an overlapping area, which can avoid the occurrence of DGS between this gate line 110 and a separately set second data line 120B.

[0079] In this case, the number of the second transmission segments 112 in each gate line 110 is equal to 2 / 3 of the number of the data lines 120. It can be seen that compared with the former, Figure 2 The structure shown can reduce the number of the second transmission segments 112, thereby optimizing the spatial layout of the display substrate and reducing the manufacturing cost of the display substrate.

[0080] The orthographic projection of at least one data line 120 on the substrate substrate has an overlapping area with the orthographic projection of a signal transmission line 1121 of at least one gate line 110 on the substrate substrate. Specifically, it can be understood that the orthographic projection of any data line 120 on the substrate substrate has an overlapping area with the orthographic projection of at least two signal transmission lines in a second transmission segment 112 of the gate line 110 on the substrate substrate. Figure 2 As shown, of the two first data lines 120A disposed close to each other, the orthographic projection of one on the substrate substrate has an overlapping area with the orthographic projection of a signal transmission line 1121 of the gate line 110 on the substrate substrate, and the orthographic projection of the other on the substrate substrate has an overlapping area with the orthographic projection of the signal transmission line 1121 of the same gate line 110 on the substrate substrate.

[0081] like Figure 3 As shown, the first portion 121 and the second portion 122 of the data line 120 are substantially parallel, and the first portion 121 and the second portion 122 are respectively connected via the two ends of the third portion 123 to enable smooth transmission of data signals. Taking the transmission of the data signal from the first portion 121 to the second portion 122 as an example: it can be understood that the data line starts to bend from the end position of the first portion 121 and ends at the beginning of the second portion 122, wherein the bent portion is the third portion 123.

[0082] There may be multiple first parts 121 , second parts 122 and third parts 123 , so that one data line 120 can be bent at multiple positions, thereby making layout space for multiple second transmission segments 112 distributed in multiple rows.

[0083] Furthermore, the width of the third portion 123 of the second data line 120B in a direction perpendicular to the extending direction thereof is greater than the width of the second portion 122 of the second data line 120B in the first direction.

[0084] Since the second data line 120B is a bent and extended data line, its length is greater than that of the first data line 120A. Thus, the resistance of the second data line 120B will be greater than that of the first data line 120A. By designing the width of the third portion 123 of the second data line 120B in a direction perpendicular to its extension to be greater than the width of the second portion 122 of the second data line 120B in the first direction, the resistance of the second data line 120B can be reduced as a whole, thereby reducing the resistance difference between the first data line 120A and the second data line 120, and reducing the delay difference of the data signal on the first data line 120A and the second data line 120, respectively.

[0085] Furthermore, if Figure 2As shown, the capacitor and the transistor in the first sub-pixel 131 are symmetrically arranged with the capacitor and the transistor in the second sub-pixel 132 .

[0086] Since the two first data lines 120A corresponding to the first sub-pixel 131 and the second sub-pixel 132 are located between the first sub-pixel 131 and the second sub-pixel 132, by symmetrically arranging the capacitor and the transistor in the first sub-pixel 131 and the capacitor and the transistor in the second sub-pixel 132, it is possible to ensure that the interface of the first sub-pixel 131 connecting to the first data line 120A is close to the side where the second sub-pixel 132 is located, and the interface of the second sub-pixel 132 connecting to the first data line 120A is close to the side where the first sub-pixel 131 is located, thereby simplifying the structural design while ensuring signal connection, eliminating the need for additional design of the internal structure of the sub-pixel, and saving the production time of the display substrate.

[0087] Furthermore, if Figure 3 As shown, at least one first portion 121 of the second data line 120B is located on the same straight line extending along the second direction, at least one second portion 122 of the second data line 120B is located on the same straight line extending along the second direction, and the first portion and the second portion of the second data line 120B are respectively located on different straight lines.

[0088] In this way, the second data line 120B can extend directionally between the straight line where the first part 121 is located and the straight line where the second part 122 is located, which is convenient for cooperating with the sub-pixels distributed in the array, improving the regularity of signal transmission of the display substrate and simplifying the difficulty of signal control of the display substrate.

[0089] In an optional embodiment, if Figure 2 As shown, a sensing line 140 extending along the second direction is further disposed on a side of the third sub-pixel 131 away from the second sub-pixel 132 .

[0090] In this embodiment, the display substrate integrates a touch sensing function, and the sensing line 140 is used to determine the position of the user's touch when the user's finger touches the display substrate. Specifically, the sensing line 140 is used to detect the capacitance of each touch electrode of the display substrate, and when the capacitance value of the capacitance of a part of the area is detected to change, the area is determined to be the position of the user's touch. Of course, the sensing line 140 can also determine the touch position by detecting the resistance, which is not limited here.

[0091] Furthermore, if Figure 2 As shown, the second transmission segment 112 includes a third sub-transmission segment 112 - 3 , and the orthographic projection of the third sub-transmission segment 112 - 3 on the substrate has an overlapping area with the orthographic projection of the sensing line 140 on the substrate.

[0092] The third sub-transmission segment 112 - 3 includes at least two signal transmission lines 1121 , wherein each signal transmission line 1121 is connected to two first transmission segments 111 adjacent to the third sub-transmission segment 112 - 3 in the first direction.

[0093] There is an overlapping area between the orthographic projection of the third sub-transmission segment 112-3 on the substrate and the orthographic projection of the sensing line 140 on the substrate. When a short circuit occurs between a signal transmission line 1121 and the sensing line 140 in the third sub-transmission segment 112-3, the sensing line 140 can be restored by cutting off the short-circuited signal transmission line 1121 so as to transmit the sensing signal normally. At the same time, the gate scanning signal can also be transmitted normally from other signal transmission lines, thereby avoiding abnormal transmission of the gate scanning signal and the sensing signal.

[0094] In this embodiment, the third sub-transmission segment 112 - 3 can be used to prevent the gate line 110 and the sensing line 140 from being short-circuited, thereby improving the production yield of the display device.

[0095] The sensing line 140 includes a first portion 141 and a second portion 142 , and the width of the first portion 141 of the sensing line 140 in the first direction is different from the width of the second portion 142 of the sensing line 140 in the first direction to adapt to the layout space of the bent data line 120 .

[0096] Specifically, the orthographic projection of the first portion 141 of the sensing line 140 on the substrate has an overlapping area with the orthographic projection of the gate line 110 on the substrate; the second portion 142 of the sensing line 140 is located between two adjacent first portions 141 in the second direction and respectively connects the two adjacent first portions 141.

[0097] Since the orthographic projection of the sensing line 140 on the substrate coincides with the orthographic projection of the third sub-transmission segment 112-3 of the gate line 110 on the substrate, and the third sub-transmission segment 112-3 includes at least two signal transmission lines 1121, the volume occupied by the third sub-transmission segment 112-3 is relatively large. Therefore, in order to free up layout space for the third sub-transmission segment 112-3, the width of the first portion 141 of the sensing line 140 in the first direction is designed to be smaller than the width of the second portion 142 of the sensing line 140 in the first direction.

[0098] It should be noted that, when the width of the sensing line 140 meets the current resistance performance, the sensing line 140 can be designed with different widths in the first direction without affecting the touch performance of the display substrate.

[0099] In another optional embodiment, if Figure 2As shown, an auxiliary electrode line 150 extending along the second direction is further disposed on a side of the third sub-pixel 133 away from the second sub-pixel 132 .

[0100] In this embodiment, the display substrate also includes an auxiliary electrode line 150, which is connected to the cathode in the display substrate to reduce the resistance of the cathode, thereby reducing the voltage drop (IR Drop, a phenomenon in which the voltage drops or increases on the power supply and ground network in an integrated circuit) of the display substrate, thereby improving the display effect of the display device.

[0101] Furthermore, the orthographic projection of the third sub-transmission segment 112 - 3 on the base substrate also has an overlapping area with the orthographic projection of the auxiliary electrode line 150 on the base substrate.

[0102] There is an overlapping area between the orthographic projection of the third sub-transmission segment 112-3 on the substrate and the orthographic projection of the auxiliary electrode line 150 on the substrate. When a short circuit occurs between a signal transmission line 1121 and the auxiliary electrode line 150 in the third sub-transmission segment 112-3, the auxiliary electrode line 150 can be restored by cutting off the short-circuited signal transmission line 1121, thereby transmitting the sensing signal normally, and the gate scanning signal can be transmitted normally from other signal transmission lines, thereby avoiding abnormal transmission of the gate scanning signal and the auxiliary electrical signal.

[0103] In this embodiment, the third sub-transmission segment 112 - 3 can be used to prevent the gate line 110 and the auxiliary electrode line 150 from being short-circuited, thereby improving the production yield of the display device.

[0104] In the case where the display substrate includes both the sensing line 140 and the auxiliary electrode line 150, the orthographic projection of the third sub-transmission segment 112-3 on the base substrate can coincide with the orthographic projection of the sensing line 140 on the base substrate and the orthographic projection of the auxiliary electrode line 150 on the base substrate, that is, one third sub-transmission segment 112-3 can prevent the gate line 110 from short-circuiting with the sensing line 140, and / or the gate line 110 from short-circuiting with the auxiliary electrode line 150, thereby improving the production yield of the display device. In addition, the number of the third sub-transmission segments 112-3 can be reduced, which not only saves the material of the gate line 110 but also reduces the space occupied by the gate line 110, thereby optimizing the spatial design of the display substrate.

[0105] Furthermore, if Figure 2 As shown, the auxiliary electrode line 150 includes a first part 151 and a second part 152. The width of the first part 151 of the auxiliary electrode line 150 in the first direction is different from the width of the second part 152 of the auxiliary electrode line 150 in the first direction to adapt to the layout space of the bent data line 120.

[0106] Specifically, the orthographic projection of the first part 151 of the auxiliary electrode line 150 on the base substrate has an overlapping area with the orthographic projection of the gate line 110 on the base substrate; the second part 152 of the auxiliary electrode line 150 is located between two adjacent first parts 141 in the second direction and respectively connects the two adjacent first parts 151.

[0107] Since the orthographic projection of the auxiliary electrode line 150 on the base substrate coincides with the orthographic projection of the third sub-transmission segment 112-3 of the gate line 110 on the base substrate, and the third sub-transmission segment 112-3 includes at least two signal transmission lines 1121, the volume occupied by the third sub-transmission segment 112-3 is relatively large. Therefore, in order to free up layout space for the third sub-transmission segment 112-3, the width of the first part 151 of the auxiliary electrode line 150 in the first direction is designed to be smaller than the width of the second part 152 of the auxiliary electrode line 150 in the first direction.

[0108] It should be noted that the auxiliary electrode lines 150 may be designed with different widths in the first direction as long as the widths meet the current resistance performance.

[0109] In another optional embodiment, if Figure 2 As shown, a power line 160 extending along the second direction is further disposed on a side of the first sub-pixel 131 away from the second sub-pixel 132 .

[0110] In this embodiment, the display substrate further includes a power line 160, which is used to provide a high-level signal to the electrode in the sub-pixel region to charge the electrode and realize normal light emission in the sub-pixel region.

[0111] Furthermore, the second transmission segment 112 includes a fourth sub-transmission segment 112 - 4 , and an orthographic projection of the fourth sub-transmission segment 112 - 4 on the base substrate has an overlapping area with an orthographic projection of the power line 160 on the base substrate.

[0112] The fourth sub-transmission segment 112 - 4 includes at least two signal transmission lines 1121 , wherein each signal transmission line 1121 is connected to two first transmission segments 111 adjacent to the fourth sub-transmission segment 112 - 4 in the first direction.

[0113] There is an overlapping area between the orthographic projection of the fourth sub-transmission segment 112-4 on the substrate and the orthographic projection of the power line 160 on the substrate. When a short circuit occurs between a signal transmission line 1121 and the power line 160 in the fourth sub-transmission segment 112-4, the power line 160 can be restored by cutting off the short-circuited signal transmission line 1121 so as to transmit high-level signals normally. At the same time, the gate scanning signal can be transmitted normally from other signal transmission lines, thereby avoiding abnormal transmission of the gate scanning signal and the high-level signal.

[0114] In this embodiment, the fourth sub-transmission segment 112 - 4 can be used to prevent the gate line 110 and the power line 160 from being short-circuited, thereby improving the production yield of the display device.

[0115] Furthermore, the power line 160 includes a first portion 161 and a second portion 162 , and the width of the first portion 161 of the power line 160 in the first direction is different from the width of the second portion 162 of the power line 160 in the first direction to adapt to the layout space of the bending data line 120 .

[0116] Specifically, the orthographic projection of the first part 161 of the power line 160 on the base substrate has an overlapping area with the orthographic projection of the gate line 110 on the base substrate; the second part 162 of the power line 160 is located between two adjacent first parts 161 in the second direction and respectively connects the two adjacent first parts 161.

[0117] Since the orthographic projection of the power line 160 on the substrate coincides with the orthographic projection of the fourth sub-transmission segment 112-4 of the gate line 110 on the substrate, and the fourth sub-transmission segment 112-4 includes at least two signal transmission lines 1121, the volume occupied by the fourth sub-transmission segment 112-4 is relatively large. Therefore, in order to free up layout space for the fourth sub-transmission segment 112-4, the width of the first portion 161 of the power line 160 in the first direction is designed to be smaller than the width of the second portion 162 of the power line 160 in the first direction.

[0118] It should be noted that, when the width of the power line 160 meets the current resistance performance, the power line 160 can be designed with different widths in the first direction without affecting the touch performance of the display substrate.

[0119] It should be noted that in this embodiment, Figure 2The positions of the sensing line 140, the auxiliary electrode line 150 and the power line 160 are described by referring to the positional relationship in the pixel unit composed of the first sub-pixel 131, the second sub-pixel 132 and the third sub-pixel 133. In an actual display substrate, the positions of the sensing line, the auxiliary electrode line and the power line are not completely applicable to other pixel units. For example, the sensing line and the auxiliary electrode line may be located on the side of two sub-pixels close to each other away from the independently arranged sub-pixel, and the power line may be located on the side of the independently arranged sub-pixel away from the two sub-pixels close to each other.

[0120] In another optional embodiment, if Figure 5 As shown, each sub-pixel region includes a pixel driving circuit 134, and the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor Cst and a light emitting element EL;

[0121] The control electrode of the first transistor T1 is connected to the first gate line G1, the first electrode of the first transistor T1 is connected to the data line Data, and the second electrode of the first transistor T1 is connected to the first electrode plate of the storage capacitor Cst;

[0122] The control electrode of the second transistor T2 is connected to the second gate line G2, the first electrode of the second transistor T2 is connected to the sensing line 140, and the second electrode of the second transistor T2 is connected to the second electrode plate of the storage capacitor Cst;

[0123] The control electrode of the third transistor T3 is connected to the second electrode of the first transistor T1 , the first electrode of the third transistor T3 is connected to the power line 160 , and the second electrode of the third transistor T3 is connected to the light emitting element EL.

[0124] In this embodiment, the pixel driving circuit adopts a 3T1C design, and can enable the sub-pixel to realize both the display function and the touch sensing function through a time-sharing driving method.

[0125] During the display period, the first gate line G1 provides a turn-on signal to the first transistor T1, so that the first electrode of the first transistor T1 and the second electrode of the first transistor T1 are conductive; the second gate line G2 provides a turn-off signal to the second transistor T2, so that the first electrode of the second transistor T2 and the second electrode of the second transistor T2 are disconnected, so that the data signal in the data line Date can be written into the storage capacitor Cst, driving the light-emitting element EL to emit light.

[0126] During the sensing period, the first gate line G1 provides a shutdown signal to the first transistor T1, so that the first electrode of the first transistor T1 is disconnected from the second electrode of the first transistor T1; the second gate line G2 provides a conduction signal to the second transistor T2, so that the first electrode of the second transistor T2 is connected to the second electrode of the second transistor T2, so that the sensing signal in the sensing line 140 can be written into the storage capacitor Cst to detect whether the screen is touched.

[0127] The pixel driving circuit may further include an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC), and two switches (S1 and S2) are used to control the connection between the ADC and the DAC and the sensing line 140 to help the sensing line 140 realize the touch sensing function.

[0128] Furthermore, if Figure 5 As shown, an insulating layer is arranged between the first plate 410 of the storage capacitor Cst and the second plate 420 of the storage capacitor Cst, the second plate includes two sub-plates (421 and 422) parallel to each other and electrically connected, the first plate 410 is arranged between the two sub-plates (421 and 422) of the second plate 420, and the two sub-plates (421 and 422) have portions facing each other with the first plate 410 respectively.

[0129] In this embodiment, the storage capacitor Cst is made of three layers of substantially parallel plates.

[0130] The second electrode plate 420 of the storage capacitor Cst is set as two sub-electrode plates (421 and 422) parallel to each other, which are respectively opposite to the first electrode plate. When the total opposite area of ​​the first electrode plate 410 and the second electrode plate 420 is equal to the total opposite area of ​​the two layers of electrode plates in the related art, the size of the storage capacitor Cst can be reduced without changing the storage capacitance value, thereby reducing the size of the array substrate row driver (Gate Driver on Array, GOA for short) circuit, which is convenient for optimizing the internal space of the high PPI device.

[0131] The second electrode plate 420 of the storage capacitor Cst is set as two sub-plates (421 and 422) parallel to each other. The total area of ​​the first electrode plate 410 and the second electrode plate 420 facing each other can be doubled without changing the size of the storage capacitor Cst, thereby increasing the storage capacitance value of the storage capacitor Cst.

[0132] In an optional embodiment, if Figure 7 and Figure 8 As shown, Figure 7 for Figure 6 The cross-sectional view along the Ⅰ-Ⅰ' line, Figure 8 for Figure 6 The cross-sectional view along the line II-II' is shown in the figure. Figure 6 and Figure 2 The sub-pixel region 130 includes a thin film transistor array layer 710 located on the substrate 700, the thin film transistor array layer 710 includes a light shielding pattern 711, a buffer layer 712 covering the light shielding pattern, an active layer 713 located on the buffer layer 712, and a gate metal layer (including Figure 6 The first gate line G1 and the second gate line G2 in the structure are provided, and an insulating layer 714 covering the buffer layer 712 , the active layer 713 and the gate metal layer, and a metal pattern 715 located on the insulating layer 714 .

[0133] In this embodiment, the shading pattern 711 is used to block light on one side of the substrate 700 to prevent the light from affecting the active layer 713 and reducing the performance of each transistor, wherein the buffer layer 712 covering the shading pattern 711 can provide a flat surface for the active layer 713.

[0134] The thin film transistor array layer 710 may include Figure 5 The first transistor T1, the second transistor T2 and the third transistor T3 are shown. The metal pattern 715 may include a plurality of metal parts separated from each other, the active layer 712 includes a plurality of active segments, and the two metal parts are connected to the same active segment in the active layer 712 through vias to form the first electrode or the second electrode in the transistor. The active layer 712 may be made of indium gallium zinc oxide (IGZO).

[0135] In addition, if Figure 7 As shown, the sub-pixel area also includes a protective layer 716 covering the metal pattern 715, a resin layer 717 covering the protective layer 716, and an anode 718 covering a portion of the resin layer 717, wherein the sub-pixel area also includes a via Z penetrating the protective layer 716 and the resin layer 717, and the anode 718 is connected to the metal pattern 715 through the via Z.

[0136] In addition, the sub-pixel region further includes a cathode 719 and a light-emitting layer 720 between the anode 718 and the cathode 719. A pixel defining layer 721 is further included between the light-emitting layers 720 in two adjacent sub-pixel regions to insulate the light-emitting layers 720 in the two sub-pixel regions from each other.

[0137] Among them, Figure 7As shown, the first electrode of the first transistor T1 includes a first via A opened in the thin film transistor array layer 710, and the first via A penetrates the insulating layer 714 to connect the first metal part 7151 in the metal pattern 715 with the active layer 713; the second electrode of the first transistor T1 includes a second via B opened in the thin film transistor array layer 710, and the second via B penetrates the insulating layer 714 to connect the second metal part 7152 in the metal pattern with the active layer 713 and the gate metal layer respectively.

[0138] In this embodiment, from Figure 6 It can be seen from the figure that the first metal portion 7151 is connected to the data line 120. Figure 7 It can be seen that the first via A penetrates the insulating layer 714 to connect the first metal portion 7151 with the first active segment 7131. Figure 7 It can be seen that the second via B penetrates the insulating layer 714 to connect the second metal part 7152 with the first active section 7131 and the first gate line G1. The orthographic projections of the first via A and the second via B on the base substrate 700 are both located inside the orthographic projection of the first active section 7131 on the base substrate 700. The orthographic projection of the second metal part 7152 on the base substrate 700 covers the orthographic projection of the first gate line G1 on the base substrate 700.

[0139] When the first gate line G1 provides a high level signal, the first electrode (first metal portion 7151) of the first transistor T1 and the second electrode (second metal portion 7152) of the first transistor T1 are turned on, thereby transmitting the data signal to the second electrode of the first transistor T1.

[0140] like Figure 7 As shown, the first electrode of the second transistor T2 includes a third via hole C opened in the thin film transistor array layer 710, and the third via hole C penetrates the insulating layer 714, so that the third metal part 7153 in the metal pattern 715 is connected to the active layer 713; the second electrode of the second transistor T2 includes a fourth via hole D and a fifth via hole E opened in the thin film transistor array layer 710, and the fourth via hole D penetrates the insulating layer 714, so that the fourth metal part 7154 in the metal pattern 715 is connected to the active layer 713, and the fifth via hole E penetrates the insulating layer 714 and the buffer layer 712, and the fourth metal part 7154 is connected to the light shielding pattern 711 through the fifth via hole E.

[0141] from Figure 7 It can be seen that the third via C penetrates the insulating layer 714 to connect the third metal portion 7153 with the second active segment 7132. Figure 7It can be seen that the fourth via D penetrates the insulating layer 714 to connect the fourth metal portion 7154 to the second active segment 7132, and the fifth via E penetrates the insulating layer 714 and the buffer layer 712. The orthographic projection of the third via C on the base substrate 700, the orthographic projection of the fourth via D on the base substrate 700, and the orthographic projection of the second gate line G2 on the base substrate are all located within the orthographic projection of the second active segment 7132 on the base substrate 700.

[0142] When the second gate line G2 provides a high level signal, the first electrode (third metal portion 7153) of the second transistor T2 and the second electrode (fourth metal portion 7154) of the second transistor T2 are turned on, thereby transmitting the sensing signal to the second electrode of the second transistor T2.

[0143] like Figure 8 As shown, the first electrode of the third transistor T3 includes a sixth via hole F opened in the thin film transistor array layer 710, and the sixth via hole F penetrates the insulating layer 714, so that the fifth metal part 7155 in the metal pattern 715 is connected to the active layer 713; the second electrode of the third transistor T3 includes a seventh via hole G and an eighth via hole H opened in the thin film transistor array layer 710, and the seventh via hole G penetrates the insulating layer 714, so that the sixth metal part 7156 in the metal pattern 715 is connected to the active layer 713, and the eighth via hole H penetrates the insulating layer 714 and the buffer layer 712, and the sixth metal part 7156 is connected to the light shielding pattern 711 through the eighth via hole H.

[0144] from Figure 6 It can be seen from FIG. 7 that the fifth metal portion 7155 is connected to the power line 160. Figure 8 It can be seen that the sixth via F penetrates the insulating layer 714 to connect the fifth metal portion 7155 to the third active segment 7133. Figure 7 It can be seen that the seventh via hole G penetrates the insulating layer 714 to connect the sixth metal portion 7156 with the third active segment 7133, and the eighth via hole H penetrates the insulating layer 714 and the buffer layer 712 to connect the sixth metal portion 7156 with the light shielding pattern 711. The orthographic projection of the sixth via hole F on the base substrate and the orthographic projection of the seventh via hole G on the base substrate are both located within the orthographic projection of the third active segment 7133 on the base substrate.

[0145] When the first gate line G1 provides a high-level signal and transmits the high-level signal to the control electrode of the third transistor T3, the first electrode (the fifth metal part 7155) of the third transistor T3 and the second electrode (the sixth metal part 7156) of the third transistor T3 are turned on, thereby transmitting the high-level signal to the second electrode of the third transistor T3 to charge the light-emitting element EL.

[0146] Among them, Figure 6 As shown, the first gate line G1 is located between the first via hole A and the sixth via hole F.

[0147] like Figure 6 As shown, the first sub-transmission segment 112 - 1 is located in a region enclosed by the first via hole A and the sixth via hole F of the first sub-pixel 131 and the first via hole A and the sixth via hole F of the second sub-pixel 132 .

[0148] like Figure 6 As shown, the second sub-transmission segment 112 - 2 is located in a region enclosed by the first via hole A and the sixth via hole F of the second sub-pixel 132 and the first via hole A and the sixth via hole F of the third sub-pixel 133 .

[0149] In addition, if Figure 6 As shown, the second gate line G2 is located between the fourth via hole D and the eighth via hole H.

[0150] Furthermore, the resistance values ​​of different data lines 120 are substantially equal.

[0151] In this embodiment, all data lines 120 may be bent (i.e., including the third portion 123 whose extension direction forms an angle with the second direction), or only some data lines may be bent. In either case, the resistance values ​​of different data lines 120 are substantially equal.

[0152] The resistance calculation formula of the data line 120 is: R=Rs×(L / W), where Rs is the unit resistance value, and Rs is the same under the same process and the same material, L is the total length of the data line, and W is the average width of the data line.

[0153] In the case where all the data lines 120 are bent, the resistance values ​​of all the data lines can be unified by unifying the extension length of the data lines 120 and the width of each part.

[0154] In the case where only a portion of the data lines are bent, since the length of the bent data lines is longer than that of the straight-extending data lines, the average width of the bent data lines needs to be greater than the average width of the straight-extending data lines, so that the resistance of the bent data lines is equal to the resistance of the straight-extending data lines. Specifically, the average width of the data lines can be increased by increasing the width of the third portion 123.

[0155] In this embodiment, by unifying the resistance values ​​of all the data lines 120 in the display substrate, the phenomenon of transmission delay of some data signals due to different resistances of the data lines can be avoided, thereby improving the display effect of the display device.

[0156] Furthermore, the capacitance values ​​of parasitic capacitors generated by coupling different data lines 120 with any other signal lines are equal, and the numbers of parasitic capacitors generated by coupling different data lines 120 with other signal lines are equal.

[0157] like Fig. 9 As shown, the data line 120 will couple with the surrounding signal lines during the data signal transmission process to generate parasitic capacitance. For example, a data line 120 will couple with each signal transmission line 1121 in the second transmission section 112 whose orthographic projection on the substrate substrate has an overlapping area with its orthographic projection on the substrate substrate and generate a parasitic capacitance ( Fig. 9 The solid line frame in the middle is the position of the parasitic capacitor), when the display substrate also includes other signal lines whose orthographic projections on the base substrate have overlapping areas with their orthographic projections on the base substrate, the data line 120 will also couple with each of these signal lines to generate a parasitic capacitor.

[0158] The magnitude of the parasitic capacitance is related to the area of ​​the overlapped region between the orthographic projection of the signal line on the substrate and the orthographic projection of the data line 120 on the substrate. When the areas of the overlapped regions are equal, the generated parasitic capacitance is also equal. In this embodiment, the areas of the overlapped regions between the orthographic projection of the data line 120 on the substrate and the orthographic projections of different signal lines on the substrate are equal, that is, the capacitance values ​​of the parasitic capacitances generated by the data line 120 and different signal lines are equal.

[0159] In this embodiment, by making the capacitance values ​​of the parasitic capacitances generated by coupling each data line 120 with any other signal line equal, and the numbers of the parasitic capacitances generated by coupling different data lines 120 with other signal lines equal, the total capacitance values ​​of the parasitic capacitances generated by coupling different data lines 120 can be made equal.

[0160] In this way, it can be ensured that when the gate line 110 writes data signals to the sub-pixels in the same row, the delay time of the data signals of each sub-pixel is the same, so that the time for writing data signals to each sub-pixel is the same, thereby ensuring the display effect of the display device. For example, when grayscale display is performed (the same grayscale data is written to the sub-pixels in the same row), it can be ensured that the charging voltages of the sub-pixels in the same row are the same.

[0161] An embodiment of the present invention further provides a display device, comprising the display substrate as described above.

[0162] The display device can be a monitor, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, etc.

[0163] The present invention also provides a method for manufacturing a display substrate. Fig.10 As shown, the method includes:

[0164] Step 901: providing a substrate;

[0165] Step 902: forming a gate line extending along a first direction on the substrate, wherein at least one gate line comprises a first transmission segment and a second transmission segment arranged alternately, the second transmission segment comprises at least two signal transmission lines, and each signal transmission line is respectively connected to two adjacent first transmission segments in the first direction;

[0166] Step 903: forming data lines extending along a second direction on the base substrate, wherein an orthographic projection of at least one data line on the base substrate and an orthographic projection of the second transmission segment on the base substrate have an overlapping area, and at least one data line comprises a first portion and a second portion extending along the second direction, and a third portion connecting the first portion and the second portion, and an extension direction of the third portion forms an angle with the second direction.

[0167] In an embodiment of the present invention, each second transmission segment as a repair structure includes at least two signal transmission lines, so that when a short circuit DGS occurs between one of the signal transmission lines and the data line, the signal transmission line can be cut off to ensure that the data signal is smoothly transmitted in the data line and the gate scanning signal is smoothly transmitted in the remaining signal transmission lines, thereby improving the yield of the display device. By bending at least one data line, a space that can accommodate the second transmission segment can be vacated in a high PPI display device, reducing the layout difficulty of the second transmission segment in the display substrate and improving the manufacturing efficiency of the display device. Therefore, the technical solution provided by the present invention can reduce the layout difficulty of the repair structure in the display substrate and improve the manufacturing efficiency of the display device.

[0168] In the embodiment of the present invention, a display unit in the display substrate may be a three-color pixel including a red sub-pixel (R), a green sub-pixel (G) and a blue sub-pixel (B). Figure 2 As shown; it may also include other color sub-pixels such as white sub-pixels and yellow sub-pixels.

[0169] In the embodiment of the present invention, the first direction is Figure 2 The second direction is the horizontal direction (i.e., the row direction of the pixel arrangement). Figure 3 The longitudinal direction (i.e., the column direction of pixel arrangement) is taken as an example for explanation.

[0170] like Figure 2 As shown, each gate line 110 includes a plurality of first transmission segments 111 and a plurality of second transmission segments 112. The first transmission segments 111 and the second transmission segments 112 are arranged alternately and transmit the same gate scanning signal together. The number of signal transmission lines 1121 in the plurality of second transmission segments 112 can be uniform, for example: each second transmission segment 112 includes two signal transmission lines 1121, such as Figure 2 As shown; the number of signal transmission lines 1121 in the plurality of second transmission segments 112 may also be different, for example: some of the second transmission segments 112 include two signal transmission lines, and some of the second transmission segments 112 include three signal transmission lines.

[0171] Taking each second transmission section 112 including two signal transmission lines 1121 as an example, Figure 2 The cross-sectional views of the second transmission section 112 cut along the second direction are as follows Figure 4 As shown, it includes two signal transmission lines 1121 for transmitting gate scanning signals.

[0172] The second transmission section 112 is designed to avoid a short circuit DGS between the gate line 110 and the data line 120, so as to prevent the gate scanning signal and the data signal from being unable to be transmitted normally due to the DGS. When a signal transmission line and the data line 120 are short-circuited in a second transmission section 112, the data line 120 can be restored by cutting off the short-circuited signal transmission line to transmit the data signal normally, and the gate scanning signal can also be transmitted normally through other signal transmission lines.

[0173] The multiple data lines 120 can be arranged with one column of sub-pixels between them. In this case, the number of second transmission segments 112 in each gate line 110 is equal to the number of data lines 120, that is, the orthographic projections of the multiple second transmission segments 112 of a gate line 110 on the substrate overlap with the orthographic projections of the multiple data lines on the substrate one by one.

[0174] The data line 120 includes a first portion 121 and a second portion 122 extending along the second direction, and a third portion 123 whose extending direction forms an angle with the second direction. The bending angle of the third portion 123 relative to the second direction, i.e., the angle between the extending direction of the third portion 123 and the second defense line, is an acute angle.

[0175] Since the second transmission segment 112 of the gate line 110 includes at least two signal transmission lines, the space occupied by the second transmission segment 112 is relatively large. In an embodiment of the present invention, in order to enable the second transmission segment 112 to be arranged between two sub-pixels, at least one data line is bent to free up space for the layout of the second transmission segment 112, thereby reducing the difficulty of layout of the second transmission segment 112 in the display substrate and improving the manufacturing efficiency of the display device.

[0176] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0177] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0178] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A display substrate, comprising gate lines extending along a first direction and data lines extending along a second direction, wherein the first direction and the second direction intersect, and the gate lines and the data lines intersect to form a plurality of sub-pixel regions; wherein: At least one gate line comprises a first transmission segment and a second transmission segment which are alternately arranged, wherein the second transmission segment comprises at least two signal transmission lines, each signal transmission line is respectively connected to two adjacent first transmission segments in the first direction, and an orthographic projection of at least one data line on the substrate substrate has an overlapping area with an orthographic projection of one signal transmission line of the at least one gate line on the substrate substrate; At least one data line includes a first portion and a second portion extending along the second direction, and a third portion connecting the first portion and the second portion, wherein an extending direction of the third portion forms an angle with the second direction; The display unit in the display substrate includes a first sub-pixel, a second sub-pixel and a third sub-pixel arranged in sequence along the first direction, wherein two first data lines are arranged between the first sub-pixel and the second sub-pixel, and a second data line is arranged between the second sub-pixel and the third sub-pixel, and the second data line includes a first part and a second part extending along the second direction, and a third part connecting the first part and the second part, and an extension direction of the third part forms an angle with the second direction.

2. The display substrate according to claim 1, characterized in that: A width of the third portion of the second data line in a direction perpendicular to the extension direction of the third portion of the second data line is greater than a width of the second portion of the second data line in the first direction.

3. The display substrate according to claim 1, characterized in that: The capacitor and the transistor in the first sub-pixel are symmetrically arranged with the capacitor and the transistor in the second sub-pixel.

4. The display substrate according to claim 1, characterized in that: At least one first portion of the second data line is located on the same straight line extending along the second direction, at least one second portion of the second data line is located on the same straight line extending along the second direction, and the first portion and the second portion of the second data line are located on different straight lines.

5. The display substrate according to claim 1, characterized in that: The second transmission segment includes a first sub-transmission segment and a second sub-transmission segment, and the orthographic projection of the first sub-transmission segment on the substrate substrate overlaps with the orthographic projection of the two first data lines on the substrate substrate; the orthographic projection of the second sub-transmission segment on the substrate substrate overlaps with the orthographic projection of the one second data line on the substrate substrate.

6. The display substrate according to claim 5, characterized in that: A sensing line extending along the second direction is further disposed on a side of the third sub-pixel away from the second sub-pixel.

7. The display substrate according to claim 6, characterized in that: The second transmission segment includes a third sub-transmission segment, and an orthographic projection of the third sub-transmission segment on the substrate and an orthographic projection of the sensing line on the substrate have an overlapping area.

8. The display substrate according to claim 6, characterized in that: The sensing line includes a first portion and a second portion, and a width of the first portion of the sensing line in the first direction is different from a width of the second portion of the sensing line in the first direction.

9. The display substrate according to claim 8, characterized in that: The orthographic projection of the first part of the sensing line on the substrate and the orthographic projection of the gate line on the substrate have an overlapping area; the second part of the sensing line is located between two adjacent first parts in the second direction and respectively connects the two adjacent first parts.

10. The display substrate according to claim 9, characterized in that: A width of the first portion of the sensing line in the first direction is smaller than a width of the second portion of the sensing line in the first direction.

11. The display substrate according to claim 7, characterized in that: An auxiliary electrode line extending along the second direction is further disposed on a side of the third sub-pixel away from the second sub-pixel.

12. The display substrate according to claim 11, characterized in that: The orthographic projection of the third sub-transmission segment on the base substrate also has an overlapping area with the orthographic projection of the auxiliary electrode line on the base substrate.

13. The display substrate according to claim 11, characterized in that: The auxiliary electrode line includes a first portion and a second portion, and a width of the first portion of the auxiliary electrode line in the first direction is different from a width of the second portion of the auxiliary electrode line in the first direction.

14. The display substrate according to claim 13, characterized in that: The orthographic projection of the first part of the auxiliary electrode line on the base substrate has an overlapping area with the orthographic projection of the gate line on the base substrate; the second part of the auxiliary electrode line is located between two adjacent first parts in the second direction and respectively connects the two adjacent first parts.

15. The display substrate according to claim 14, characterized in that: A width of the first portion of the auxiliary electrode line in the first direction is smaller than a width of the second portion of the auxiliary electrode line in the first direction.

16. The display substrate according to claim 11, characterized in that: A power line extending along the second direction is further disposed on a side of the first sub-pixel away from the second sub-pixel.

17. The display substrate according to claim 16, characterized in that: The second transmission segment includes a fourth sub-transmission segment, and an orthographic projection of the fourth sub-transmission segment on the base substrate has an overlapping area with an orthographic projection of the power line on the base substrate.

18. The display substrate according to claim 16, characterized in that: The power line includes a first portion and a second portion, and a width of the first portion of the power line in the first direction is different from a width of the second portion of the power line in the first direction.

19. The display substrate according to claim 18, characterized in that: The orthographic projection of the first part of the power line on the base substrate and the orthographic projection of the gate line on the base substrate have an overlapping area; the second part of the power line is located between two adjacent first parts in the second direction and respectively connects the two adjacent first parts.

20. The display substrate according to claim 19, characterized in that: A width of the first portion of the power line in the first direction is smaller than a width of the second portion of the auxiliary electrode line in the first direction.

21. The display substrate according to claim 6, characterized in that: Each sub-pixel region includes a pixel driving circuit, and the pixel driving circuit includes a first transistor, a second transistor, a third transistor, a storage capacitor and a light-emitting element; The control electrode of the first transistor is connected to the first gate line, the first electrode of the first transistor is connected to the data line, and the second electrode of the first transistor is connected to the first electrode plate of the storage capacitor; The control electrode of the second transistor is connected to the second gate line, the first electrode of the second transistor is connected to the sensing line, and the second electrode of the second transistor is connected to the second electrode plate of the storage capacitor; The control electrode of the third transistor is connected to the second electrode of the first transistor, the first electrode of the third transistor is connected to a power line, and the second electrode of the third transistor is connected to the light emitting element.

22. The display substrate according to claim 21, characterized in that: An insulating layer is arranged between the first plate of the storage capacitor and the second plate of the storage capacitor, the second plate includes two sub-plates which are parallel to each other and electrically connected, the first plate is arranged between the two sub-plates of the second plate, and the two sub-plates respectively have portions facing the first plate.

23. The display substrate according to claim 22, characterized in that: The sub-pixel area includes a thin film transistor array layer located on the substrate, the thin film transistor array layer includes a shading pattern, a buffer layer covering the shading pattern, an active layer located on the buffer layer, a gate metal layer located on the active layer and the buffer layer, an insulating layer covering the buffer layer, the active layer and the gate metal layer, and a metal pattern located on the insulating layer.

24. The display substrate according to claim 23, characterized in that: The first electrode of the first transistor includes a first via hole opened in the thin film transistor array layer, and the first via hole penetrates the insulating layer to connect the first metal part in the metal pattern with the active layer; the second electrode of the first transistor includes a second via hole opened in the thin film transistor array layer, and the second via hole penetrates the insulating layer to connect the second metal part in the metal pattern with the active layer and the gate metal layer respectively.

25. The display substrate according to claim 24, characterized in that: The first electrode of the second transistor includes a third via hole opened in the thin film transistor array layer, and the third via hole penetrates the insulating layer so that the third metal part in the metal pattern is connected to the active layer; the second electrode of the second transistor includes a fourth via hole and a fifth via hole opened in the thin film transistor array layer, and the fourth via hole penetrates the insulating layer so that the fourth metal part in the metal pattern is connected to the active layer, and the fifth via hole penetrates the insulating layer and the buffer layer, and the fourth metal part is connected to the shading pattern through the fifth via hole.

26. The display substrate according to claim 25, characterized in that: The first electrode of the third transistor includes a sixth via hole opened in the thin film transistor array layer, the sixth via hole penetrates the insulating layer, so that the fifth metal part in the metal pattern is connected to the active layer; the second electrode of the third transistor includes a seventh via hole and an eighth via hole opened in the thin film transistor array layer, the seventh via hole penetrates the insulating layer, so that the sixth metal part in the metal pattern is connected to the active layer, the eighth via hole penetrates the insulating layer and the buffer layer, and the sixth metal part is connected to the shading pattern through the eighth via hole.

27. The display substrate according to claim 26, characterized in that: The first gate line is located between the first via hole and the sixth via hole.

28. The display substrate according to claim 27, characterized in that: The first sub-transmission segment is located in a region surrounded by the first via hole and the sixth via hole of the first sub-pixel and the first via hole and the sixth via hole of the second sub-pixel.

29. The display substrate according to claim 27, characterized in that: The second sub-transmission segment is located in a region surrounded by the first via hole and the sixth via hole of the second sub-pixel and the first via hole and the sixth via hole of the third sub-pixel.

30. The display substrate according to claim 26, characterized in that The second gate line is located between the fourth via hole and the eighth via hole.

31. The display substrate according to claim 1, characterized in that: The resistance values ​​of different data lines are approximately equal.

32. The display substrate according to claim 1, characterized in that: The capacitance values ​​of parasitic capacitors generated by coupling different data lines with any other signal lines are equal, and the numbers of parasitic capacitors generated by coupling different data lines with other signal lines are equal.

33. A display device, characterized in that: Comprising a display substrate as described in any one of claims 1-32.

34. A method for manufacturing a display substrate, characterized in that: For manufacturing a display substrate according to any one of claims 1 to 32, the method comprising: Providing a substrate; A gate line extending along a first direction is formed on the substrate, wherein at least one gate line comprises a first transmission segment and a second transmission segment arranged alternately, the second transmission segment comprises at least two signal transmission lines, and each signal transmission line is respectively connected to two adjacent first transmission segments in the first direction; Data lines extending along a second direction are formed on the base substrate, wherein an orthographic projection of at least one data line on the base substrate and an orthographic projection of the second transmission segment on the base substrate have an overlapping area, and at least one data line includes a first portion and a second portion extending along the second direction, and a third portion connecting the first portion and the second portion, and an extension direction of the third portion forms an angle with the second direction.

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