Persistent storage clear

Abstract

The present invention provides a data processing device comprising a volatile storage circuit for storing data while power is supplied. A persistent storage circuit stores the data in the absence of power, and a transfer circuit transfers the data from the volatile storage circuit to the persistent storage circuit. The transfer circuit is adapted to transfer the data from the volatile storage circuit to the persistent storage circuit in response to main power becoming unavailable to the volatile storage circuit. The transfer circuit is adapted to transfer a subset of the data from the volatile storage circuit to the persistent storage circuit in response to an explicit request including an indication of the subset of data.

Description

Technical Field

[0001] The present disclosure relates to data processing and, more particularly, to data storage. DETAILED DESCRIPTION

[0002] In volatile memory circuits, data is retained only when power is supplied to the circuit. In contrast, persistent memory circuits are able to store data even when no power is supplied. Data processing devices can utilize both forms of storage. However, because persistent memory devices tend to be slower than volatile memory devices, there is a trade-off between whether data is retained in volatile memory devices (where it may be lost or corrupted) or whether data is retained in persistent memory devices (where it is less likely to be lost or corrupted, but will be subject to longer delays). Data can be stored in both forms of storage simultaneously. However, providing coherency / consistency results in increased bandwidth between the memory circuits, especially if large amounts of data are involved. Summary of the Invention

[0003] From a first exemplary configuration, a data processing device is provided, which includes: a volatile storage circuit for storing data while power is provided; a persistent storage circuit for storing data in the absence of power; and a transfer circuit for transferring data from the volatile storage circuit to the persistent storage circuit, wherein the transfer circuit is suitable for transferring data from the volatile storage circuit to the persistent storage circuit in response to main power becoming unavailable to the volatile storage circuit; and the transfer circuit is suitable for transferring a subset of data from the volatile storage circuit to the persistent storage circuit in response to an explicit request including an indication of the subset of data.

[0004] From a second exemplary configuration, a method is provided that includes: transferring data from a volatile storage circuit to a persistent storage circuit in response to main power becoming unavailable to the volatile storage circuit; receiving an explicit request that includes an indication of a subset of the data in the volatile storage circuit; and transferring the subset of the data from the volatile storage circuit to the persistent storage circuit in response to the explicit request.

[0005] From the third exemplary configuration, a data processing device is provided, which includes: a device for storing data while power is provided; a device for storing data in the absence of power; and a device for transferring data from the device for storing data while power is provided to the device for storing data in the absence of power, wherein the device for transferring data is used to: transfer data from the device for storing data while power is provided to the device for storing data in the absence of power in response to the main power supply becoming unavailable to the device for storing data while power is provided; and the device for transferring data is also used to: transfer a subset of data from the device for storing data while power is provided to the device for storing data in the absence of power in response to an explicit request including an indication of a subset of the data. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention will now be further described, by way of example only, with reference to embodiments of the invention as shown in the accompanying drawings, in which:

[0007] Figure 1 schematically illustrates an apparatus according to some embodiments;

[0008] Figure 2 schematically illustrates an apparatus according to some embodiments;

[0009] Figure 3 The byte-addressable nature of persistent storage circuitry is shown;

[0010] Figure 4 schematically illustrates an apparatus according to some embodiments;

[0011] Figure 5A and Figure 5B shows the use of page table entries (PTEs) and interconnect routing tables for specifying usage patterns according to some embodiments;

[0012] Figure 6 illustrates offloading of a transmission process according to some embodiments; and

[0013] Figure 7 Data processing methods according to some embodiments are shown.

[0014] DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

[0015] Before discussing the embodiments with reference to the drawings, the following description of the embodiments is provided.

[0016] According to some aspects, a data processing apparatus is provided, comprising: a volatile storage circuit for storing data while power is provided; a persistent storage circuit for storing data in the absence of power; and a transfer circuit for transferring data from the volatile storage circuit to the persistent storage circuit, wherein the transfer circuit is adapted to transfer the data from the volatile storage circuit to the persistent storage circuit in response to main power becoming unavailable to the volatile storage circuit; and the transfer circuit is adapted to transfer a subset of the data from the volatile storage circuit to the persistent storage circuit in response to an explicit request including an indication of the subset of the data.

[0017] Within a data processing device, a persistence point is defined. Data stored before this persistence point is susceptible to loss in the event of a power failure. After the persistence point, actions are taken to ensure that the data mapped to the persistent storage medium remains unchanged even in the event of a power failure. This can be achieved by retaining the data in a persistent storage device. Alternatively, the data can be retained in a volatile storage device that uses an auxiliary power supply to provide sufficient time for the data to be transferred to the persistent storage device in the event of a main power failure. The auxiliary power supply can be a dedicated power supply or even the capacitor of a failed main power supply. Within the data processing device, a deep persistence point is also defined, which itself exceeds the persistence point (for example, anything that exceeds the deep persistence point also exceeds the persistence point). The deep persistence point defines a point at which data is more strongly "guaranteed" to be retained in the event of a main power failure. This can include isolation for scenarios other than a main power failure, such as a host processor crash or a battery backup failure. For example, a persistence point can provide one level of assurance, while a deep persistence point can provide a higher level of assurance. Thus, the deep persistence point can define the starting point of the persistent storage circuit itself. In such systems, data can be controlled so that it is stored at deep persistence points. This can be important for particularly valuable data such as logs (in a logging file system) or database maintenance records, where preventing data loss is particularly important and stronger "guarantees" are required in terms of the security of the data. Therefore, a subset of data can be explicitly requested (e.g., as a result of a runtime operation, rather than as a response to an event such as a power outage) to be transferred through a deep persistence point (e.g., to a persistent storage circuit). Because the subset of data is specified (e.g., the data is filtered), bandwidth can be maintained by not requiring all data in volatile storage to be transferred to persistent storage.

[0018] In some embodiments, additional volatile storage circuitry is provided, wherein the transfer circuitry is adapted to search a subset of the data from the volatile storage circuitry without searching the additional volatile storage circuitry. Thus, the extent to which the data is identified or analyzed can be limited. For example, in some embodiments, an explicit request to transfer a subset of data can be accompanied by an indication to limit the search to the volatile storage circuitry behind a "persistence point." Since we are only interested in transferring a subset of data that has been "guaranteed" or committed to persistence, previously requested by the CPU (or other device) and confirmed by the portion of the volatile storage circuitry residing behind the persistence point, there is no need to search elsewhere, and snooping or searching of, for example, upstream volatile caches (particularly above the persistence point) can be limited.

[0019] In some embodiments, a subset of data is indicated by an address identifier. The address identifier may be provided relative to one or more specified locations to be transferred to the persistent storage device. For example, this may be a starting point together with an offset, or as part of a range.

[0020] In some embodiments, the subset of data is indicated by at least one of a virtual machine identifier, an application space identifier, or a usage pattern of a memory location. A virtual machine identifier (VMID) can be used to indicate the memory used by a particular virtual machine. In contrast, an application space identifier (ASID) can be used to identify memory used by a particular application. The usage pattern indicates how the memory is used. For example, memory that is actually backed by persistent media can be used as volatile storage without forcing or ensuring that updates are actually confirmed as persistent. Thus, in this particular example, the usage pattern would reflect the fact that, although the storage is backed by persistent storage, the usage pattern is that of volatile storage.

[0021] In some embodiments, usage patterns are defined relative to virtual memory addresses. For example, a particular virtual memory address may be indicated as a region of memory to be used in a persistent manner. This may be represented, for example, by a single bit.

[0022] In some embodiments, usage patterns are defined relative to at least partial physical memory addresses. For example, a particular physical memory address may be indicated as a region of memory that will be used in a persistent manner. Partial physical addresses may occur when the conversion from virtual to physical occurs in multiple steps. For example, a virtual address may be converted to at least a partial physical address (e.g., an intermediate address), which is then converted to a physical address.

[0023] In some embodiments, the usage mode is defined by page table entries or by interconnect routing circuitry. Page table entries are used, for example, in translation lookaside buffers and / or page walk circuitry to translate (at least partially) from virtual addresses to physical addresses. Interconnect routing circuitry is used to determine, based on, for example, the address of a particular request, which hardware the request should be sent to. In either of these examples, a new field may be added to indicate the usage mode.

[0024] In some embodiments, the volatile storage circuitry and the persistent storage circuitry comprise part of a memory hierarchy. The memory hierarchy typically involves smaller, faster, higher-level caches and larger, slower, lower-level caches. Data can be transferred between caches so that infrequently accessed data or data not recently accessed is stored at the lower levels of the memory hierarchy, and recently accessed data is stored at the higher levels of the memory hierarchy. In such a hierarchy, the lower levels may be backed by permanent storage devices such as an SCM.

[0025] In some embodiments, the volatile storage circuit is a last level cache or a higher level cache in the memory hierarchy. The last level cache (LLC) can be considered the last storage circuit in the memory hierarchy in the form of a cache. Subsequent (lower) levels of the hierarchy are supporting storage for such storage class memories (SCMs). Such caches can be shared among multiple processors. However, this is not required.

[0026] In some embodiments, the data processing device includes a backup energy source for supplying power to the volatile storage circuit in response to a primary power source becoming unavailable to the volatile storage circuit. The backup energy source is selected to have sufficient capacity to address a worst-case scenario, wherein, in the event that the primary power source becomes unavailable, all volatile storage passing through the persistence point is transferred to the persistent storage device. Note that the backup energy source is not necessarily an energy supply. If the capacitance of the failed primary power source is sufficient to transfer all relevant data, this can serve as the backup energy source itself.

[0027] In some embodiments, a data processing device includes processing circuitry configured to execute a stream of instructions, wherein the processing circuitry is adapted to transmit a signal to the transfer circuitry to indicate a subset of data. Thus, the signal regarding the data to be transferred from the volatile storage device to the persistent storage device may be initiated by the processing circuitry, such as a CPU, executing the instructions.

[0028] In some embodiments, the persistent storage circuit is adapted to receive a signal from the processing circuit indicating a location in the persistent storage circuit at which data is to be accessed. The persistent storage circuit may be byte-addressable in that individual bytes stored in the persistent storage circuit can be addressed without the use of a device driver. This contrasts with other forms of storage that store or access blocks of data (perhaps storing 4kB of data) rather than individual bytes at a time. By having byte-addressable storage, the latency between the CPU and the storage circuit itself can be improved in situations where a device driver is required to act as an intermediary.

[0029] In some embodiments, the persistent storage circuit is adapted to receive a signal from the transmission circuit indicating a location in the persistent storage circuit at which data is to be accessed.

[0030] In some embodiments, the signal indicates a location in the persistent storage circuit where the data is to be written.

[0031] In some embodiments, the processing circuitry is adapted to continue executing an instruction stream while a subset of the data is transferred from the volatile storage circuitry to the persistent storage circuitry. This enables the processing circuitry to continue working while the data is being transferred from the volatile storage device to the persistent storage device. Thus, the work of performing the transfer is "offloaded" from the processing circuitry.

[0032] Specific embodiments will now be described with reference to the accompanying drawings.

[0033] Figure 1 An apparatus 100 is shown according to some embodiments. The apparatus includes a central processing unit (CPU) 110 that executes a stream of instructions. During execution of these instructions, the CPU 110 may utilize one or more storage circuits in the form of a cache 120 and a storage class memory (SCM) 150.

[0034] A power supply 190 is provided within the device 100. The power supply 190 supplies power to each of the CPU 120 and the memory circuits 120, 150. Each memory circuit is accessible as long as power is supplied from the power supply 190. However, the cache 120 is "volatile," meaning that any data stored therein may be lost if it becomes unpowered. The cache 120 is provided with a backup battery 170. In the event of a power outage, the cache 120 is designed to transfer stored data to the SCM 150. In this way, even though the cache is a volatile storage device, it may be able to function in a persistent manner by providing a promise or guarantee to retain the data it has stored in the event of a power failure. Therefore, these caches reside behind a persistence point 160. Data stored in the cache 120, marked as persistent with a promise or guarantee of future persistence, will be preserved even in the event of a power failure.

[0035] However, there is no guarantee that such persistent data will always be saved. For example, if the battery backup 170 fails at the same time as the power supply 190, or if it has failed previously and was not marked as a problem, the data stored in the cache 120 will not be likely to be transferred to the SCM 150. Therefore, in some cases, a stronger commitment or guarantee may be needed. This may be the case with more critical data, such as database maintenance records or logs in a journaling file system. Therefore, the present apparatus 100 also defines a deep persistence point 170 in which a stronger commitment or guarantee of data continuity is provided. In fact, in this example, the deep persistence point 170 is set at the boundary of the SCM 150. Therefore, in this example, data stored outside of the deep persistence point 170 is always persistently stored.

[0036] In the above paragraphs, the situation where a power failure occurs has been described. However, it should be understood that there are other forms of failure that can occur. For example, power spikes, minor errors or defects in the circuit, and certain forms of attacks (e.g., RowHammer in the case of DRAM) can cause a single bit in the storage circuit to be flipped. This can be mitigated by technologies such as ECC. However, not all errors can be repaired or completely suppressed in this way. Therefore, it may be advantageous to store data at a deep persistence point 170 in order to limit the extent to which these errors may occur.

[0037] In addition to automatically transferring data from the volatile storage circuits to the persistent storage circuits via the persistence point 160 in the event of a power failure, the CPU 110 may also proactively push a subset of the data stored in the cache 120 to the persistent storage circuits 150. Figure 4 This technique is described in more detail.

[0038] Figure 2 An apparatus 100 according to some embodiments is shown. The apparatus is similar to the reference Figure 1 The apparatus shown is similar to that shown, except that the apparatus includes a memory hierarchy 195 containing storage circuits in the form of a level 1 cache 120, a level 2 cache 130, a level 3 cache 140, and storage class memory (SCM) 150. Those circuits toward the top of the memory hierarchy 195, such as the level 1 cache 120, are smaller and faster than those storage circuits at the bottom of the hierarchy 195, such as the SCM 150.

[0039] The L1 cache 120, L2 cache 130, and L3 cache 140 are constructed from "volatile" media, such that any data they store may be lost if they become unpowered. The L2 cache 130 and L3 cache 140 are provided with backup batteries 170, 175. In the event of a power outage, these caches 130, 140 are designed to transfer stored data to the SCM 150. In this way, even though the L2 cache 130 and L3 cache 140 are volatile storage devices, they may be able to function in a persistent manner by providing a commitment or guarantee to retain the data they have stored in the event of a power failure. Therefore, these two caches reside behind the persistence point 160. The L1 cache 120 (before the persistence point 160) does not provide such a mechanism. Within the hierarchy 195, the L3 cache 140 is described as the last level cache (LLC). The LLC is the last cache to appear in the hierarchy 195.

[0040] Note that although Figure 2 The present technology is shown described with respect to the memory hierarchy 195, but is also applicable to other locations where data is buffered for writing. For example, it is applicable to the interconnect and memory controller that may be located between the level 3 cache 140 and the SCM 150.

[0041] Figure 3 The behavior of the SCM 150 is shown. Specifically, Figure 3 This figure illustrates how SCM 150 can be used as a byte-addressable storage device. With byte-addressable storage, a processor, such as CPU 110, can execute instructions to write or store to specific bytes within storage circuit 150. Furthermore, transfer circuitry, which copies data from volatile storage to persistent storage or SCM 150, can issue writes to access specific bytes within the storage circuit. These writes are directly interpreted by storage circuit 150. In other words, there is no need to provide a device driver to interpret writes from CPU 110, and no additional signals need to be sent by the device driver to the storage circuit. One consequence is that data does not necessarily need to be accessed block by block. Specifically, non-byte-addressable storage circuits are often block-oriented, requiring access to a large number of bytes simultaneously. Therefore, a device driver typically acts as a buffer or intermediary between the storage circuit and the CPU, pulling in the required block, performing accesses on the block to affect the required bytes, and then returning the block to the storage device. However, such loads and saves from the buffer can be time-consuming because they require translation between the storage circuit and the CPU. Consequently, block-based storage devices are often slower than byte-addressable storage devices. This is not to say, of course, that any storage circuit that operates on groups of bytes simultaneously is a "block-based storage device." Rather, the differentiating factor may be considered to be the presence of a device driver.

[0042] exist Figure 3 In the example of FIG, it is shown that a read instruction issued by CPU 110 in the form of a read instruction to byte 0x0101 causes storage circuit 150 to respond with data stored at byte 0x0101. In this example, the data is 10010011, which is returned to CPU 110 without the need for a device driver.

[0043] Figure 4 An apparatus 300 according to some embodiments is shown. Apparatus 300 also includes a CPU 110 that executes an instruction stream, along with volatile storage circuitry 130 and persistent storage circuitry 150. Circuitry 300 also includes a persistence point 160. However, in this example, the persistence point is located immediately below CPU 110. Physically, volatile storage circuitry 130, comprised of volatile media, is lowered below persistence point 160 and is backed up by a backup battery 175. While backup battery 175 is used in this example, it will be appreciated that in some cases, the capacitance of a failed primary power supply 190 may be sufficient to transfer the necessary data from volatile storage circuitry 130 to persistent storage circuitry 150. In such cases, backup battery 175 may not be required. Deep persistence point 170 is located at the boundary of persistent storage circuitry 150.

[0044] In this example, if and when power supply 190 fails, transfer circuitry 320 is responsible for transferring relevant data from the volatile storage circuitry to the persistent storage circuitry 150. Furthermore, in this example, persistent storage circuitry 150 is accessed via interconnect circuitry 330. Thus, persistent storage circuitry 150 can be a storage circuit accessible by multiple different CPUs, including CPU 110. Additionally, CPU 110 includes a translation lookaside buffer (TLB) 310. TLB 310 is responsible for translating virtual storage addresses into physical storage addresses. TLB 310 may function in conjunction with page walk circuitry to perform translations or store the results of such translations.

[0045] In this example, CPU 110 can construct a descriptor to indicate a subset of data to be transferred from volatile storage circuitry 130. The descriptor may indicate one or more identifiers, such as a virtual machine identifier (VMID), an application space identifier (ASID), a usage mode, and an address. The CPU then invokes offload circuitry 340, which uses the descriptor to manage transfer circuitry 320, thereby transferring the matching data. The subset of data stored in volatile storage circuitry 130 that matches the one or more identifiers in the descriptor is then transferred to persistent storage circuitry 150. In this embodiment, by offloading the task of completing the transfer to offload circuitry 340, which manages transfer circuitry 320, the transfer process occurs asynchronously from CPU 110. Therefore, CPU 110 can continue executing instructions while the transfer occurs. Despite the absence of power loss from main power supply 190, the subset of data stored in volatile storage circuitry 130 is then pushed to deep persistence point 170. Such actions can be taken to better protect the subset of data. Consequently, the data is less likely to be corrupted or lost due to, for example, multiple power failures or hardware errors that cannot be addressed by backup power. Since the subset of data stored in the volatile storage circuit 130 is specified via the identifier, it is not necessary to push all the data in the volatile storage circuit 130 to the deep persistence point 170. Therefore, compared to the case where all the data stored in the volatile storage circuit 130 is transferred to the persistent storage circuit 150 by the transfer circuit 320, this can reduce bandwidth consumption.

[0046] The descriptor indicating the subset of data to be transferred may additionally have an option to communicate whether the lookup or search for the subset of data may be constrained to reside only on volatile storage behind persistence point 160. This option may be used when it is known that the subset of data has been previously pushed to persistence point 160 and is therefore guaranteed or promised to eventually be made persistent (upon power failure).

[0047] In some embodiments, the transfer takes the form of a copy. Thus, the data is preserved in its current form, but by continuing to store it in volatile storage circuitry 130, it can continue to be quickly accessed. This thus preserves a copy of the data while still taking steps to reduce latency. However, future modifications to data stored only in volatile storage circuitry 130 are at increased risk of loss compared to data pushed to persistent storage circuitry 150.

[0048] Note that in these examples, persistence point 160 and deep persistence point 170 are located at the boundaries of a particular memory circuit. However, in other embodiments, persistence point 160 may be located to cover a portion of a memory circuit. For example, only a portion of volatile memory circuit 130 may be backed by backup battery 175.

[0049] Figure 5A An example of a TLB is shown. Figure 5A , each row of the table includes a virtual address, a physical address to which the virtual address is translated, a type indicating whether the memory location is intended to be used in a persistent manner (or, in other embodiments, the location where the memory is to be persisted), a virtual machine identifier associated with the virtual address, and an application space identifier associated with the virtual address. As discussed, the identifier provided in the "clear" instruction or unload command causes data in the volatile storage device associated with the region of memory having its PTE attributes that match the requested identifier to be transferred to the persistent storage circuitry 150. It should be understood that the identifier provided by the CPU 110 in the clear instruction may relate to a virtual address or a physical address.

[0050] Figure 5B 1 shows a table that can be used in the interconnect routing circuit 330 for routing requests between devices. Such a table is used to indicate the specific device to which a request will be sent based on the address of the request. Thus, the columns of the table include an address column, a hardware ID column that identifies a piece of hardware, and a type column as previously described.

[0051] In these examples, a single entry is provided for a specific byte of memory. However, a table entry may alternatively identify a specific address / byte range (virtual or physical).

[0052] Figure 6 A flowchart 500 is shown illustrating how a purge process is performed, according to some embodiments. The process begins at step 510, where the CPU executes an instruction stream. At some point during the execution of those instructions, the CPU 110 issues a purge signal / command / descriptor to the offload circuitry 340 at step 520. In this example, the descriptor specifies a specific VMID. At this point, two operations occur simultaneously. At step 530, the CPU continues to execute instructions in the instruction stream. Simultaneously, at step 540, the offload circuitry 340 causes entries in the volatile storage circuitry 130 that match the VMID specified in the purge signal issued in step 520 to be transferred from the volatile storage circuitry 130 to the persistent storage circuitry 150 by the transfer circuitry 320 (i.e., via a deep persistence point). At step 550, a determination is made as to whether the transfer is complete. If not, steps 530 and 540 continue. If the transfer is complete, the process concludes at step 560 by interrupting the CPU 110 to indicate the transfer is complete. This may result in an interrupt being raised or an acknowledgement signal being sent back to the CPU 110.

[0053] As can be seen from the foregoing description, the CPU 110 is able to execute instructions while transferring data items from the volatile storage circuitry to the persistent storage circuitry 150 using the transfer circuitry 320. Therefore, the CPU 110 does not need to continuously supervise the operation. Furthermore, because a specific identifier can be provided, the CPU 110 does not need to use software to individually issue a large number of addresses to be saved from the volatile storage circuitry 130 to the persistent storage circuitry 150, which would be time-consuming because software is used to supervise the operation and may prevent the CPU 110 from executing other instructions simultaneously.

[0054] Figure 7 A flowchart 600 is shown of a data processing method that may be performed, for example, by the transmission circuit 320, in accordance with some embodiments. The process begins at step 610 where a notification is received. At step 620, a determination is made as to whether a main power failure has occurred. That is, a determination is made as to whether the notification is a notification that the main power supply has become unavailable. If so, the transmission circuit 320 causes the data in the volatile storage circuit 130 that is marked as persistent to be transferred to the persistent storage circuit 150. The process then returns to step 610. If the notification at step 620 does not indicate a main power failure, a determination is made at step 640 as to whether an explicit request to transfer data is being made. If so, a subset of the data indicated in the explicit request is transferred in the persistent storage circuit 150 at step 650. This process may occur without requiring the CPU 110 to indicate each individual address to be transferred, thereby freeing the CPU 110 to indicate as referenced Figure 6 After the transfer is performed, the process then returns to process 610. If no explicit request was issued at step 640, then the appropriate handling of the received notification is performed at step 660, and the process then returns to step 610.

[0055] Thus, in the above paragraphs, we have described how both persistence point 160 and deep persistence point 170 can operate. Transfer circuitry 320 enables data to be transferred from persistence point 160 to deep persistence point 170 in response to a main power failure. CPU 110 can also enable sensitive or highly important data to be pushed to the deep persistence point. This provides greater security for that data and better protection against data loss or corruption. By specifying only a subset of the data to be pushed to deep persistence point 170, bandwidth usage can be reduced that would otherwise be required to transfer all the data.

[0056] In this application, the phrase "configured to..." is used to mean that elements of a device have a configuration capable of performing a defined operation. In this context, "configuration" refers to the arrangement or manner in which hardware or software are interconnected. For example, the device may have dedicated hardware to provide the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device elements need to be modified in any way in order to provide the defined operation.

[0057] Although exemplary embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the present invention is not limited to those precise embodiments and that various changes, additions, and modifications may be implemented therein by those skilled in the art without departing from the scope and spirit of the invention as defined in the appended claims. For example, the features of the dependent claims may be combined in various ways with the features of the independent claims without departing from the scope of the invention.

Claims

1. A data processing device, comprising: a volatile storage circuit for storing data while supplying power; processing circuitry for executing an instruction stream; persistent storage circuitry for storing data in the absence of power; and a transmission circuit configured to transmit data from the volatile storage circuit to the persistent storage circuit, wherein the transfer circuit being adapted to transfer the data from the volatile storage circuit to the persistent storage circuit in response to main power becoming unavailable to the volatile storage circuit; and the transfer circuit being adapted to transfer the subset of the data from the volatile storage circuit to the persistent storage circuit in response to an explicit request including an indication of the subset of the data regardless of whether the primary power source is unavailable; The subset of the data is indicated in a signal by at least one of: The virtual machine identifier, and Application space identifier; and The processing circuitry is adapted to continue executing the instruction stream while the subset of the data is transferred from the volatile storage circuitry to the persistent storage circuitry.

2. The data processing device according to claim 1, comprising: Another volatile storage circuit, wherein the transfer circuit is adapted to search the subset of the data from the volatile storage circuit without searching the further volatile storage circuit.

3. The data processing apparatus according to claim 1 or 2, wherein The subset of the data is indicated by an address identifier.

4. The data processing apparatus according to claim 1 or 2, wherein The volatile storage circuitry and the persistent storage circuitry comprise part of a memory hierarchy.

5. The data processing apparatus according to claim 4, wherein The volatile storage circuit is a last level cache or a higher level cache in the memory hierarchy.

6. The data processing device according to claim 1 or 2, comprising: A backup energy source is provided for supplying power to the volatile storage circuit in response to the primary power source becoming unavailable to the volatile storage circuit.

7. The data processing device according to claim 1 or 2, comprising: processing circuitry for executing an instruction stream, wherein The processing circuit is adapted to transmit a processing circuit signal to the transmitting circuit to indicate the subset of the data.

8. The data processing apparatus according to claim 7, wherein The persistent storage circuit is adapted to receive the processing circuit signal from the processing circuit, the signal indicating a location in the persistent storage circuit at which data is to be accessed.

9. The data processing apparatus according to claim 1 or 2, wherein The persistent storage circuit is adapted to receive a transfer circuit signal from the transfer circuit, the signal indicating a location in the persistent storage circuit at which data is to be accessed.

10. The data processing apparatus according to claim 9, wherein The transfer circuit signal indicates a location in the persistent storage circuit where data is to be written.

11. A data processing method, comprising: transferring data from the volatile storage circuitry to the persistent storage circuitry in response to main power becoming unavailable to the volatile storage circuitry; Execute instruction stream; receiving an explicit request, the explicit request including an indication of a subset of the data in the volatile storage circuit; and in response to the explicit request, transferring the subset of the data from the volatile storage circuitry to the persistent storage circuitry regardless of whether the primary power source is unavailable; The subset of the data is indicated in a signal by at least one of: The virtual machine identifier, and Application space identifier; and The instruction stream is executed while the subset of the data is transferred from the volatile storage circuitry to the persistent storage circuitry.

12. A data processing device, comprising: means for storing data while providing power; means for storing data in the absence of electrical power; means for transferring data from said means for storing data while power is supplied to said means for storing data in the absence of power, and means for executing a stream of instructions; in the means for transferring data being operable to transfer data from the means for storing data while power is supplied to the means for storing data in the absence of power in response to main power becoming unavailable to the means for storing data while power is supplied; and the means for transferring data being further for: in response to an explicit request including an indication of the subset of the data, transferring the subset of the data from the means for storing data while power is provided to the means for storing data in the absence of power regardless of whether the primary power source is unavailable; The subset of the data is indicated in a signal by at least one of: The virtual machine identifier, and Application space identifier; and The instruction stream is executed while the subset of the data is transferred from the means for storing data while power is provided to the means for storing data in the absence of power.

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