Half-bridge with variable deadband control and zero voltage switching

Abstract

An improved method for zero voltage switching (ZVS) of a half-bridge fed by a voltage with a variable deadband is provided. The duration of the deadband is dynamically determined and precisely long enough to ensure the absence of shoot-through events while also minimizing or eliminating switching losses and reverse conduction losses. The method generally comprises: (a) calculating the equivalent capacitance seen by a current source charging the midpoint of the half-bridge; (b) calculating the ZVS charge requirement based on the link voltage and the equivalent capacitance; (c) calculating the charge delivered by the current source over time during the deadband vector, equating the result to the ZVS charge requirement, and solving for the ZVS time requirement at each commutation point over the switching cycle; and (d) updating the deadband for each commutation of each half-bridge in a switched-mode power converter.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 750,896, filed October 26, 2018, the disclosure of which is incorporated by reference in its entirety. Technical Field

[0003] The present invention relates to zero voltage switching of a half-bridge converter for on-board chargers and other applications. Background Art

[0004] Half-bridges are a component of many switch-mode power converter (SMPC) topologies. An example of an isolated dual active bridge (DAB) is an SMPC that uses four half-bridges and a transformer to transfer power from the transformer's primary to the secondary. The DAB has one full-bridge (two half-bridges in parallel) driving the primary winding and one full-bridge driving the secondary winding. Figure 1 The current-fed half-bridge shown in FIG comprises two semiconductor switches connected in series with a current source or storage element, such as an inductor, with a connection to a midpoint node. The node at the end of the series combination is called a linkage. Figure 2 In the case of a voltage-fed half-bridge as shown in Figure 1, this link is called a DC link because its value is not allowed to go negative. A voltage-fed half-bridge can be implemented with any combination of controlled or uncontrolled switches. Examples include a fully controlled half-bridge (e.g., a bidirectional buck-boost DC / DC converter), a semi-controlled half-bridge (e.g., a simple buck DC / DC converter), and an uncontrolled half-bridge (e.g., the front-end rectifier of a totem-pole PFC topology).

[0005] Considering a half-bridge as a type of switching block, both current-fed half-bridges (CFHBs) and voltage-fed half-bridges (VFHBs) can be used to construct an SMPC. A switching block is an active power component and is placed in a configuration with passive power components to create the SMPC power path. A voltage-fed half-bridge can additionally be controlled, semi-controlled, or uncontrolled. Many or most controlled semiconductor switches used in an SMPC are controlled only when current flows in one direction through their primary conduction path and will self-activate (become reverse biased) when current flows in the opposite direction. Despite having an uncontrolled state, two such switches in a half-bridge configuration are considered controlled switching blocks.

[0006] Given a positive cross-join emf , each of the four block states can be commanded by the controller. More specifically, each switch has two states: conducting and non-conducting (blocking). Possible control vectors (drive signals) include the following:

[0007] S1 S2 Control vector open close High side vector close open Low side vector close close No working area vector open open Shoot-Through Vector

[0008] The high side control vector will be connected to the positive rail (rail) V link Applied to the midpoint, the voltage across S1 is limited to and limit the voltage across S2 to The low-side control vector applies the connected negative rail to the midpoint, limiting the voltage across S1 to and limit the voltage across S2 to The deadband control vector releases control of the half-bridge midpoint to the control of the larger topology, which moves v according to the controlled current source hb , making The through control vector shorts both the positive and negative rails to v hb , making .

[0009] In a CFHB, a current source is connected in series with both switches S1 and S2, thereby regulating their currents even when both switches are conducting. Therefore, during normal operation of a CFHB, all four control vectors can be used. However, in a VFHB, a voltage source is connected in series with switches S1 and S2, and therefore a shoot-through control vector would short-circuit the voltage source, resulting in an unregulated current. This condition is potentially catastrophic. To mitigate this, the start of the turn-on signal for one switch is delayed relative to the end of the turn-off signal for the other switch, creating a dead zone (or dead zone time). This technique ensures that one switch is fully off (non-conducting) before the complementary switch is driven on, thereby avoiding unintended shoot-through events. However, the duration of the dead zone is typically predetermined and fixed in length. As a result, existing half-bridge converters experience heat losses due to a dead zone that is longer than strictly required to ensure no shoot-through events. Summary of the Invention

[0010] An improved method for zero-voltage switching (ZVS) of a voltage-fed half-bridge (VFHB) using a variable deadband is provided. The duration of the deadband is dynamically determined by a processor based on a real-time open-loop circuit model and is precisely long enough to ensure the absence of shoot-through events while also minimizing or eliminating switching and reverse conduction losses. Eliminating reverse conduction losses according to this method improves SMPC efficiency, reduces thermal stress on semiconductor devices, and allows for easier cooling scheme design. Any SMPC using a VFHB can be modeled as a controlled current source feeding the midpoint of the half-bridge and a controlled voltage source feeding the half-bridge rails.

[0011] According to one embodiment, the method generally includes: (a) calculating the equivalent capacitance seen by a current source charging the midpoint of a half-bridge; (b) calculating the ZVS charge requirement based on the link voltage and the equivalent capacitance; (c) calculating the charge delivered by the current source over time during the dead zone vector, equating the result to the ZVS charge requirement, and solving for the ZVS time requirement at each commutation point in the switching cycle; and (d) updating the dead zone for each commutation of each half-bridge in the SMPC. The above method is primarily executed in software in conjunction with a microprocessor and control circuit hardware adapted to accommodate real-time updates of the dead zone of the SMPC.

[0012] These and other features of the invention will be more fully appreciated and understood by reference to the description of the embodiments and the accompanying drawings.

[0013] Before explaining the embodiments of the present invention in detail, it should be understood that the present invention is not limited to the details of operation or the details of the construction and arrangement of the parts set forth in the following description or shown in the accompanying drawings. The present invention can be implemented in various other embodiments and can be practiced or executed in alternative ways that are not clearly disclosed herein. In addition, it should be understood that the words and terms used herein are for descriptive purposes and should not be considered as limiting. The use of "include" and "comprising" and their variations means including the items listed thereafter and their equivalents as well as additional items and their equivalents. In addition, enumeration can be used in the description of various embodiments. Unless otherwise expressly stated, the use of enumeration should not be interpreted as limiting the present invention to any specific order or number of parts. The use of enumeration should also not be interpreted as excluding from the scope of the present invention any additional steps or parts that may be combined with or combined into the steps or parts of the enumeration. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is the circuit diagram of a current-fed half-bridge converter.

[0015] Figure 2 is the circuit diagram of a voltage-fed half-bridge converter.

[0016] Figure 3 (a) to 3(f) show the low-to-high commutation state of VFHB under standard ZVS conditions with a fixed deadband.

[0017] Figure 4 A long deadband for control of VFHB is shown, where the deadband is longer than the time required to charge the half-bridge capacitance.

[0018] Figure 5A short deadband for control of VFHB is shown, wherein the deadband is shorter than the time required to charge the half-bridge capacitance.

[0019] Figure 6 A long deadband for control of VFHB is shown, wherein the deadband is exactly long enough to charge the half-bridge capacitance of the half-bridge for ZVS.

[0020] Figure 7 is a flow chart of a method for ZVS of a voltage-fed half-bridge according to one embodiment.

[0021] Figure 8 (a) to 8(e) show the change of Charge Equivalent Capacitance with the corresponding accumulated charge and equivalent static capacitance.

[0022] Figure 9 is a circuit diagram of a single-phase voltage-fed inverter with an ideal dead zone determined by a controller according to the present embodiment. DETAILED DESCRIPTION

[0023] An improved method for zero-voltage switching of a voltage-fed half-bridge using a variable deadband is provided. As discussed herein, the duration of the deadband is dynamically determined to ensure the absence of shoot-through events while also minimizing or eliminating switching losses and reverse conduction losses. As background, Section I below includes known techniques for zero-voltage switching of a voltage-fed half-bridge. Section II below includes a discussion of the present invention's method for zero-voltage switching of a voltage-fed half-bridge using a dynamically calculated variable deadband control vector.

[0024] I. Zero voltage switching of a voltage-fed half-bridge

[0025] Zero Voltage Switching (ZVS) is the commutation of a semiconductor switch from the OFF state to the ON state when there is zero voltage across its primary conduction path. The process by which ZVS commutation occurs can be illustrated by commutating an arbitrary VFHB low to high, as Figure 3 (a)-3(f) As shown in Figure 3. Regarding ZVS, the semiconductor switch can be considered as an ideal MOSFET in parallel with the output capacitor and has a forward voltage V rth Using two such switches in a half-bridge configuration, with S1 being the high-side switch and S2 being the low-side switch, across any DC link V link , referenced as the low side rail, here referred to as GND , with a midpoint voltage supplied by some controlled current source (e.g. a resonant inductor) VHB , so that the current flowing into the midpoint i hb is always positive. Under ZVS conditions, the entire commutation process can be broken down. Figure 3 The low-to-high half-bridge commutation is shown in (a)-3(f). Here, the output capacitance of each switch is abbreviated as and The antiparallel diode is considered ideal and the voltage source is a function of the state of the diode—conducting = 1 and non-conducting = 0—such that and In this way, the behavior of any arbitrary self-activated semiconductor switch can be modeled as an anti-parallel device.

[0026] exist Figure 3 Before commutation in (a), i hb flows freely through S2, and V HB Clamp to GND When S2 is turned off, i hb Starts to migrate from the conduction channel to both S2 and S1 C oss Charging, such as Figure 3 (b) This marks the beginning of the dead zone because the controller is applying the dead zone control vector, driving both S1 and S2 off at the same time. When the channel is collapsing V HB The rate of increase is i hb , the channel resistance of S1 and the resistance of both S1 and S2 C oss control - as the channel collapses, resistance increases, and more i hb Migrate to charge C1 and C2. Once the switch is fully turned off, the channel resistance is high enough that the current through it becomes negligible, and then V HB The change in is dominated by the following relationship (Equation 1):

[0027] (1)

[0028] If the switch has a fast turn-off edge rate, such as in a MOSFET, then C oss The channel stops conducting before it charges to the opposite rail, so the deadband must be long enough to move the midpoint from GND Charge toV link , and thus C1 from V link discharge to 0V. Ideally, S1 will be But in fact V HB Will continue to charge until D1 of S1 becomes reverse biased and V HB Clamp to Once the midpoint voltage is clamped, S1 burns energy in the remaining portion of the deadband. Therefore, it is desirable to keep this region as short as possible. When S1 commutates on, C1 is charged to - V rth After the commutation of S1, some switching loss will be experienced. i hb should still be positive in the bridge, although ideally, i hb It will reach 0 A immediately after commutation of S1 to minimize the resonant current.

[0029] Typically, the deadband is set to a fixed value in the control circuit that generates the pulse width modulation (PWM) of the half-bridge. T ZVS is the minimum time required to control the current source (assuming the current is known) to deliver the charge required for ZVS. ZVS Time Requirement T ZVS is inversely proportional to the current during the deadband and directly proportional to the link voltage. Therefore, a typical control circuit for a ZVS application will be based on the minimum expected I ( T ZVS ) and the maximum link voltage to fix the deadband so that ZVS can be guaranteed for all operating points. However, this means that the ZVS charge requirement will be met faster when the current flowing into the half-bridge is larger, and the midpoint voltage of the half-bridge defined by S1 and S2 v hb The target connection rail will be reached before the end of the dead zone and charging will continue beyond that rail.

[0030] If this charging is allowed to continue, not only will ZVS be lost, but at high switching currents, the voltage rating of the semiconductor switches may be exceeded, leading to lifetime degradation and device failure. For this reason, ZVS topologies (and most SPMC topologies in general) provide a midpoint current i hbThis is achieved by the reverse conduction properties of the anti-parallel body of, for example, a MOSFET and IGBT, or an external diode, or the 2DEG in a HEMT. Since this reverse conduction is uncontrolled, there must be an associated voltage drop equal to the threshold of the anti-parallel devices, and the midpoint will therefore be clamped to the connecting rail plus the reverse threshold voltage. V rth In this clamped conduction state, i hb is forced through the device in the direction of the reverse voltage drop, generating heat losses known as reverse conduction losses. Figure 3 (d) where the low-to-high commutation of the half-bridge takes significantly longer than the time required to transfer enough charge to the equivalent capacitance to change the midpoint voltage by the required amount. As a result, once the midpoint voltage reaches V link (60V in this example), current keeps charging the equivalent capacitor until the midpoint voltage exceeds the high-side rail voltage reverse threshold of the device. Figure 4 (Short deadband depicted) results in hard switching at approximately 20V in this example, while Figure 5 The ideal dead zone avoids switching loss and reverse conduction loss. Figure 4 、 5 and 6 provide a basis for Figure 3 Examples of the general case are presented in (a)-(f), where the current source is provided with an 8 μH inductor with a constant initial current of 2 A and a link voltage of 60 V. The only parameter that varies between the three figures is the deadband time t db .

[0031] Ⅱ. Variable deadband control for voltage switching of a voltage-fed half-bridge

[0032] To eliminate the reverse conduction losses discussed above in Section I, the deadband is dynamically calculated for each commutation point, rather than using predetermined values ​​corresponding to worst-case requirements. Eliminating reverse conduction losses improves the efficiency of the SMPC, reduces thermal stress on semiconductor devices, and allows for easier-to-design cooling schemes.

[0033] refer to Figure 7 A flow chart illustrating a method for zero voltage switching of a voltage-fed half-bridge using a variable deadband control vector is provided. The method generally includes dynamically calculating the deadband for each commutation point, rather than using a predetermined value corresponding to a worst-case requirement. More particularly, the method generally includes the following method steps: (a) calculating the equivalent capacitance seen by a current source charging the midpoint of the half-bridge based on the link voltage, the SMPC topology, and the SMPC circuit state; C eq(Step 10); (b) Calculate the ZVS charge requirement based on the link voltage and equivalent capacitance (Step 12); (c) Calculate the vector in the dead zone Q hb The charge delivered by the current source over time during the switching cycle is equal to the ZVS charge requirement, and the value of T ZVS (step 14); and (d) updating the deadband for each commutation of each half-bridge in the SMPC (step 16).

[0034] Calculate the equivalent capacitance at step 10 C eq This includes determining any capacitance along the return path of the current source. This can include parasitic PCB capacitance, winding capacitance from magnetics, and expected capacitance (such as a resonant tank). Figure 4 、 5 The examples used in 6 assume only switched capacitors C oeq 、PCB capacitors C PCB and winding capacitance C L is connected in parallel along the return path of the inductor. Therefore, This is the case in a single half-bridge commutation in a DAB. This step is also visualized with the example below. A gallium nitride high electron mobility transistor (GaN HEMT) from GaN Stystems Inc., part number GS66516T, is used. Figure 8 Figure 1 shows how capacitance, charge, equivalent capacitance, and energy can vary with the output voltage of a single GaN HEMT. Since the change in output voltage over the deadband of the half-bridge commutation must be equal to the junction, Figure 8 in vds (Drain to Source Voltage) vs. V link Figure 3 (a) Interchangeable. Figure 8 (a) shows the output capacitance change with voltage. Figure 8 (b) shows the charge accumulated across a device as a function of voltage. Figure 8 (c) Plot the voltage at which the C oss The equivalent static capacitance value of the same amount of charge is called "charge equivalent capacitance". Figure 8 (d) shows the accumulated energy versus voltage. Figure 8 (e) shows that at this voltage the C oss The equivalent static capacitance value of the same amount of energy is called "energy equivalent capacitance".

[0035] Based on equivalent capacitance C eq , ZVS charging requirements Q ZVS Then it is calculated according to the following (Equation 2), where C eq is a function of voltage, because the semiconductor C oss Usually with output voltage v oss Not constant:

[0036] (2)

[0037] As mentioned above, Q ZVS The midpoint voltage of S1 and S2 Move from ~0V to V link The required charge, which in turn V oss1 from V link Discharge to ~0 V. Then perform the calculation according to the following (Equation 3-4) ZVS Timing requirements T ZVS :

[0038] (3)

[0039] (4)

[0040] In the above equation 3, Q ZVS is calculated as the average current during the dead zone vector (the inverse ZVS period multiplied by the integral of the current). In Equation 4 above, T ZVS is solved as the charge required for ZVS divided by the average current over time to allow for ZVS or I ( T ZVS ). Therefore, in order to properly set the T ZVS To determine the initial conditions, the initial current at the beginning of each dead zone during the switching cycle must be calculated.

[0041] As an example, Figure 3 The controlled current source in (a) is composed of a resonant inductor L = 8μH Assuming that at time Department, L Charged to , without an initial driving voltage across its terminals, , which means that the current initially flows through the inductor. The capacitance of the inductor winding is , and the parasitic capacitance of the PCB is , which is consistent with both S1 and S2 C oss in parallel, as seen by the inductor. The link voltage is set to , and by T db0 The deadband variations are given to illustrate the effect. Figure 6 shows the low to high commutation of the half bridge, where the dead zone ,from arrive is the precise time required for 2A to deliver enough charge to the equivalent capacitor to change the midpoint voltage by 60V. This is the ideal commutation of the half bridge. The deadband can be larger than the optimal charge by an additional 6.8 V The time required to provide a buffer for real-world sensor errors without incurring reverse conduction losses.

[0042] Method also include At step 16, the deadband is updated for each commutation of each half-bridge in the SMPC. Each step of the aforementioned method can be implemented in digital logic in conjunction with a dual active bridge (DAB) converter having four half-bridges, but the present method can be implemented in other SMPCs as needed. The method does not require any additional hardware and instead calculates the deadband in real time using a mathematical model dependent on the system topology. As described above, eliminating reverse conduction losses according to the present method improves the efficiency of the SMPC, reduces thermal stress on semiconductor devices, and allows for easier design of cooling solutions.

[0043] According to another embodiment, Figure 9 A single-phase voltage-fed inverter for producing a square wave output is shown in FIG. The inverter comprises a half-bridge having two switches S1, S2 connected in series and two freewheeling antiparallel diodes D1, D2. The switches may not be activated simultaneously, which would short-circuit the voltage source. According to one embodiment, the ideal dead zone is calculated in digital logic, the dead zone being the interval between the switch-off and the switch-on of the series connection. In particular, the controller 20, such as an integrated circuit or a digital signal processor, determines the equivalent capacitance at the midpoint 22 of the half-bridge. For a given input current at the midpoint or a given rail voltage across the half-bridge, the equivalent capacitance can be determined empirically and typically includes any switch capacitance, PCB capacitance and winding capacitance. Based on the equivalent capacitance, the controller 20 determines the ZVS charging requirement ( Q ZVS ), which represents the shift of the midpoint voltage from 0V to the rail voltage (V link ) The controller 20 then determines the ideal dead zone according to equation (4) above. T ZVS , where ZVS charging requirements ( Q ZVS ) divided by the average current over time taking into account ZVS ( I (T ZVS ） ), which is obtained by the controller from the initial current at the beginning of each dead zone. The controller 20 then sets the ideal dead zone T ZVS Stored to computer readable memory, potentially updating the existing value of the half-bridge deadband and creating a value at least equal to the ideal deadband T ZVS The interval between turning off and on of the series-connected switches of the half-bridge is 1 / 4 (e.g., with or without a buffer period). The process may be repeated periodically, or in response to an event, such as in response to a change in the input current to the midpoint 22 of the half-bridge, or in response to a change in the DC rail voltage.

[0044] The above description is a description of the current embodiment of the present invention. Various changes and variations can be made without departing from the spirit and broader aspects of the present invention. This disclosure is presented for illustrative purposes and should not be interpreted as an exhaustive description of all embodiments of the present invention or as limiting the scope of the claims to the specific elements shown or described in conjunction with these embodiments. Any reference to a singular element, such as the use of the articles "a," "an," "the," or "said," should not be interpreted as limiting the element to the singular.

Claims

1. A method comprising: Providing a switch-mode power converter comprising a voltage source outputting a DC rail voltage, a half-bridge having first and second switches and a midpoint node, and a controller; Determining, by the controller, a zero voltage switching dead zone in which the first and second switches are open, wherein determining the zero voltage switching dead zone comprises: Calculate the zero voltage switching charge requirement (Q ZVS ), Use the mathematical model to calculate the average current (I(T) at the midpoint node in the maximum dead zone ZVS )), the maximum dead zone is a maximum period of time during which zero voltage switching is allowed to be achieved during deactivation of the first switch and deactivation of the second switch, and Based on the zero voltage switching charge requirement (Q ZVS ) and the calculated average current (I(T ZVS )) to determine the ideal dead zone (T ZVS ); Switching control signals are provided by the controller to the first and second switches for generating an AC output, wherein a time interval between deactivation of the first switch and activation of the second switch is at least equal to the ideal deadband but not greater than the maximum deadband.

2. The method according to claim 1, wherein Determining the ideal deadband is responsive to a detected change in input current to a midpoint node of the half-bridge.

3. The method according to claim 1, wherein An ideal deadband is determined in response to the detected change in the DC rail voltage.

4. The method according to claim 1, wherein Calculate the zero voltage switching charge requirement (Q ZVS ) is based on the equivalent capacitance at the midpoint node, where the input current remains constant or the voltage across the half-bridge remains constant.

5. The method according to claim 4, wherein The equivalent capacitance includes parasitic capacitance, winding capacitance and switch capacitance. The method of claim 1 , further comprising storing the ideal deadband in a non-transitory computer-readable memory.

7. The method according to claim 1, wherein The half-bridge is one of a plurality of half-bridges of a switch-mode power converter, and the method further includes determining, by the controller, an ideal deadband for each of the plurality of half-bridges.

8. The method according to claim 1, wherein The time interval is equal to the ideal dead zone and a buffer period, and the buffer period is between 1% and 10% of the dead zone.

9. A switch-mode power converter comprising: a DC voltage source for providing a DC rail voltage; a half-bridge connected in parallel with the DC voltage source, the half-bridge comprising first and second switches and a midpoint node; as well as A controller operable to provide switching control signals to the first and second switches and operable to adjust a time interval between deactivation of the first switch and activation of the second switch, wherein the controller determines the time interval by: Calculate the zero voltage switching charge requirement (Q ZVS ), Use the mathematical model to calculate the average current (I(T) at the midpoint node in the maximum dead zone ZVS )), the maximum dead zone is a maximum period of time during which zero voltage switching is allowed to be achieved during deactivation of the first switch and deactivation of the second switch, and Based on the zero voltage switching charge requirement (Q ZVS ) and the calculated average current (I(T ZVS )) to determine the ideal dead zone (T ZVS ).

10. The switch mode power converter according to claim 9, wherein The controller determines the time interval in response to a detected change in input current to a midpoint node of the half-bridge.

11. The switch mode power converter according to claim 9, wherein The controller determines the time interval in response to the detected change in the DC rail voltage.

12. The switch mode power converter according to claim 9, wherein Calculate the zero voltage switching charge requirement (Q ZVS ) is based on the equivalent capacitance at the midpoint node, where the input current remains constant or the voltage across the half-bridge remains constant.

13. The switch-mode power converter of claim 9, further comprising a second half-bridge including a third switch and a fourth switch, the controller being operable to adjust a time interval between deactivation of the third switch and activation of the fourth switch.

14. The switch mode power converter according to claim 9, wherein The half bridge forms part of a full bridge DC to AC inverter.

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