Method for manufacturing metal oxide and method for manufacturing semiconductor device

Abstract

A semiconductor device with high reliability is provided. The semiconductor device includes a first step of forming a metal oxide containing indium on a substrate and a second step of performing microwave treatment on the metal oxide, the first step being performed by a sputtering method using an oxide target containing indium, and the second step being performed under reduced pressure using a gas containing oxygen. By the second step, hydrogen enters oxygen vacancies (V O H) in the metal oxide. O ) and hydrogen (H).

Description

Technical Field

[0001] One aspect of the present invention relates to a metal oxide, a transistor, a semiconductor device, and an electronic device. Another aspect relates to a method for manufacturing a metal oxide and a method for manufacturing a semiconductor device. Furthermore, one aspect relates to a semiconductor wafer and module.

[0002] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the properties of semiconductors. Besides semiconductor elements such as transistors, semiconductor circuits, arithmetic processing devices, or storage devices are also types of semiconductor devices. Display devices (liquid crystal displays, light-emitting displays, etc.), projection devices, lighting devices, electro-optical devices, energy storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc., sometimes include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the aforementioned technical fields. One aspect of the invention disclosed in this specification relates to an object, method, or manufacturing method. Additionally, another aspect of the present invention relates to a process, machine, manufacture, or composition of matter. Background Technology

[0004] The technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. However, oxide semiconductors are also attracting attention as other materials.

[0005] In oxide semiconductors, CAAC (c-axis aligned crystalline) and nc (nanocrystalline) structures, which are neither single crystals nor amorphous, have been discovered (see Non-Patent Literature 1 and Non-Patent Literature 2).

[0006] Non-patent documents 1 and 2 disclose a technique for manufacturing transistors using an oxide semiconductor with a CAAC structure.

[0007] [Preliminary Technology Documents]

[0008] [Non-patent literature]

[0009] [Non-Patent Literature 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, pp. 183-186

[0010] [Non-Patent Literature 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, number 4S, p. 04ED18-1-04ED18-10 Summary of the Invention

[0011] The technical problem that the invention aims to solve

[0012] One objective of this invention is to provide a semiconductor device with high reliability. Another objective is to provide a semiconductor device with good electrical characteristics. Another objective is to provide a semiconductor device with a large on-state current. Another objective is to provide a semiconductor device capable of miniaturization or high integration. Furthermore, one objective is to provide a low-power semiconductor device.

[0013] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the invention does not necessarily require achieving all of the above objectives. Note that objectives other than those described above are obvious from the description in the specification, drawings, claims, etc., and can be extracted from the description in the specification, drawings, claims, etc.

[0014] means of solving technical problems

[0015] One aspect of the present invention is a method for manufacturing a metal oxide, comprising: a first step of forming an indium-containing metal oxide on a substrate; and a second step of performing microwave treatment on the metal oxide, wherein the second step is performed under reduced pressure and using an oxygen-containing gas, and hydrogen is introduced into oxygen vacancy defects (V0) in the metal oxide through the second step. O H) is divided into oxygen vacancy (V) O ) and hydrogen (H).

[0016] Additionally, one aspect of the present invention is a method for manufacturing a metal oxide, comprising: a first step of forming an indium-containing metal oxide on a substrate; a second step of microwave processing the metal oxide; and a third step of heat processing the metal oxide, wherein the second step is performed under reduced pressure and using an oxygen-containing gas, the third step is performed under reduced pressure, and hydrogen is introduced into the oxygen vacancy defects (V0) in the metal oxide through the second step. O H) is divided into oxygen vacancy (V) O ) and hydrogen (H), and, through a third process, reduce oxygen vacancies (V) in the metal oxide. O ).

[0017] Additionally, one aspect of the present invention is a method for manufacturing a metal oxide, comprising: a first step of forming an indium-containing metal oxide on a substrate; a second step of forming a first electrical conductor and a second electrical conductor on the metal oxide; a third step of performing microwave treatment on the metal oxide; and a fourth step of performing heat treatment on the metal oxide, wherein the third step is performed under reduced pressure and using an oxygen-containing gas, the fourth step is performed under reduced pressure, and hydrogen is introduced into the oxygen vacancy defects (V0) in the metal oxide through the third step. O H) is divided into oxygen vacancy (V) O ) and hydrogen (H), and, through the fourth process, reduce oxygen vacancies (V) in the metal oxide. O Furthermore, hydrogen (H) in the metal oxide diffuses into the first conductor and the second conductor.

[0018] Additionally, one aspect of the present invention is a method for manufacturing a metal oxide, comprising: a first step of forming an indium-containing metal oxide on a substrate; a second step of forming a first electrical conductor and a second electrical conductor on the metal oxide; a third step of forming an insulating film on the metal oxide; a fourth step of performing microwave treatment on the insulating film; and a fifth step of heat-treating one or both of the metal oxide and the insulating layer, wherein the fourth step is performed under reduced pressure and using an oxygen-containing gas, the fifth step is performed under reduced pressure, and hydrogen is introduced into the oxygen vacancy defects (V0) in the metal oxide through the fourth step. O H) is divided into oxygen vacancy (V) O ) and hydrogen (H), and, through the fifth step, reduce oxygen vacancies (V) in the metal oxide. O Furthermore, hydrogen (H) in the metal oxide diffuses into the first conductor and the second conductor.

[0019] In the above manufacturing method, the heat treatment temperature is preferably above 300°C and below 500°C.

[0020] Furthermore, in the above manufacturing method, the microwave treatment pressure is preferably 133 Pa or higher.

[0021] Furthermore, in the above manufacturing method, it is preferable that the first step is performed by sputtering using an indium-containing oxide target.

[0022] Invention Effects

[0023] According to one aspect of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Additionally, according to one aspect of the present invention, a semiconductor device with a large on-state current can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Moreover, according to one aspect of the present invention, a low-power semiconductor device can be provided.

[0024] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the invention does not necessarily require all of the above-described effects. Note that effects other than those described above are clearly present in the specification, drawings, and claims, and these effects can be obtained from the description in the specification, drawings, and claims.

[0025] Brief description of the attached figures

[0026] Figure 1A This is a top view of a semiconductor device according to one aspect of the present invention. Figures 1B to 1D This is a cross-sectional view of a semiconductor device according to one aspect of the present invention.

[0027] Figure 2A This is a diagram illustrating the behavior of ΔVsh in the +GBT test. Figure 2B This is a diagram illustrating the drain current of a transistor.

[0028] Figure 3A It is a diagram illustrating the energy of metal oxides. Figure 3B and Figure 3C It is a diagram illustrating electron conduction.

[0029] Figure 4A and Figure 4B It's about V O H and V O A schematic diagram of the energy shift in the reaction of H.

[0030] Figure 5A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 5B to 5D This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0031] Figure 6A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 6B to 6D This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0032] Figure 7A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 7B to 7D This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0033] Figure 8A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 8B to 8D This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0034] Figure 9A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 9B to 9D This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0035] Figure 10A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 10B to 10D This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0036] Figure 11A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 11B to 11D This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0037] Figure 12A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 12B to 12D This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0038] Figure 13A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 13B to 13D This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0039] Figure 14A This is a top view of a semiconductor device according to one aspect of the present invention. Figures 14B to 14D This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0040] Figure 15A This is a top view of a semiconductor device according to one aspect of the present invention. Figures 15B to 15DThis is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0041] Figure 16 This is a top view illustrating a microwave processing apparatus according to one aspect of the present invention.

[0042] Figure 17 This is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention.

[0043] Figure 18 This is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention.

[0044] Figure 19 This is a cross-sectional view showing the structure of a storage device according to one aspect of the present invention.

[0045] Figure 20 This is a cross-sectional view showing the structure of a storage device according to one aspect of the present invention.

[0046] Figure 21 This is a cross-sectional view showing the structure of a storage device according to one aspect of the present invention.

[0047] Figure 22A and Figure 22B This is a block diagram illustrating an example of the structure of a storage device according to one aspect of the present invention.

[0048] Figures 23A to 23H This is a circuit diagram illustrating a structural example of a storage device according to one aspect of the present invention.

[0049] Figure 24A and Figure 24B This is a schematic diagram of a semiconductor device according to one aspect of the present invention.

[0050] Figures 25A to 25E This is a schematic diagram of a storage device according to one aspect of the present invention.

[0051] Figures 26A to 26H This is a diagram illustrating an electronic device according to one aspect of the present invention.

[0052] Figure 27 It's a diagram illustrating the market image.

[0053] Methods of implementing the invention

[0054] The embodiments will now be described with reference to the accompanying drawings. However, the embodiments can be implemented in many different ways, and those skilled in the art will readily understand that the methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments shown below.

[0055] In the accompanying drawings, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, the invention is not necessarily limited to the dimensions described above. Furthermore, ideal examples are shown schematically in the drawings, and the invention is not limited to the shapes or values ​​shown. For example, in actual manufacturing processes, layers or resist masks are sometimes unintentionally thinned due to processes such as etching, but this is sometimes not reflected in the drawings for ease of understanding. Additionally, the same reference numerals are sometimes used across different drawings to denote the same parts or parts with the same function, omitting repeated descriptions. Furthermore, the same shading lines are sometimes used when indicating parts with the same function, without additional reference numerals.

[0056] Furthermore, especially in top views (also known as plan views) or perspective views, descriptions of some constituent elements are sometimes omitted to facilitate understanding of the invention. Additionally, descriptions of some hidden lines, etc., are sometimes omitted.

[0057] Furthermore, in this specification and other documents, ordinal numbers such as "first," "second," etc., are added for convenience, but they do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for description. In addition, the ordinal numbers described in this specification and other documents are sometimes inconsistent with the ordinal numbers used to specify one aspect of the present invention.

[0058] In this specification and other materials, for convenience, terms such as "upper" and "lower" are used to indicate configuration, referring to the accompanying drawings to illustrate the positional relationships of the constituent elements. Furthermore, the positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to that described in this specification and may be appropriately replaced as needed.

[0059] For example, in this specification, when it is explicitly stated as "X and Y are connected," it means the following: X and Y are electrically connected; X and Y are functionally connected; X and Y are directly connected. Therefore, the connection relationships specified in the drawings or text are not limited to those shown in the drawings or text; connection relationships other than those shown in the drawings or text are also included in the content disclosed in the drawings or text. Here, X and Y refer to objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films and layers, etc.).

[0060] In this specification and the like, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as the channel-forming region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), through which current can flow between the source and the drain. Note that in this specification and the like, the channel-forming region refers to the region through which current primarily flows.

[0061] Furthermore, in cases where transistors with different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may sometimes be interchanged.

[0062] Note that channel length refers, for example, to the distance between the overlapping region of the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on-state) and the gate electrode in a top view of the transistor, or between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel-forming region. Furthermore, the channel length in a transistor is not necessarily the same in all regions. That is, the channel length of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel length refers to any value, maximum, minimum, or average value in the channel-forming region.

[0063] The channel width, for example, refers to the length of the channel-forming region perpendicular to the channel length direction in the overlapping area of ​​the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on-state) and the gate electrode in a top view of the transistor. Furthermore, the channel width in a transistor is not necessarily the same in all regions. That is, the channel width of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel width refers to any value, maximum value, minimum value, or average value in the channel-forming region.

[0064] In this specification, depending on the transistor structure, the actual channel width (hereinafter referred to as "effective channel width") in the region forming the channel sometimes differs from the channel width shown in the top view of the transistor (hereinafter referred to as "apparent channel width"). For example, when the gate electrode covers the side of the semiconductor, the effect cannot be ignored because the effective channel width is greater than the apparent channel width. For example, in miniature transistors where the gate electrode covers the side of the semiconductor, the proportion of the channel formation region formed on the side of the semiconductor is sometimes increased. In this case, the effective channel width is greater than the apparent channel width.

[0065] In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, estimating the effective channel width from design values ​​requires assuming that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is unclear, it is difficult to accurately measure the effective channel width.

[0066] In this specification, when simply described as "channel width," it sometimes refers to the visual channel width. Alternatively, in this specification, when simply described as "channel width," it sometimes refers to the actual channel width. Note that the values ​​of channel length, channel width, actual channel width, visual channel width, etc., can be determined by analyzing cross-sectional TEM images, etc.

[0067] Note that impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can sometimes lead to an increase in the defect state density or a decrease in crystallinity of the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter its properties include, for example, Group 1, Group 2, Group 13, Group 14, and Group 15 elements, as well as transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water is sometimes also used as an impurity. Furthermore, the incorporation of impurities can sometimes lead to the formation of oxygen vacancies (sometimes denoted as V) in the oxide semiconductor. O ).

[0068] Note that in this specification, silicon oxynitride refers to a substance in which the oxygen content is greater than the nitrogen content. Furthermore, silicon oxynitride refers to a substance in which the nitrogen content is greater than the oxygen content.

[0069] Note that in this specification, etc., "insulator" may be replaced with "insulating film" or "insulating layer". Additionally, "conductor" may be replaced with "conductive film" or "conductive layer". Furthermore, "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer".

[0070] In this specification, "parallel" refers to a state where the angle formed by two straight lines is -10° or more and less than 10°. Therefore, it also includes a state where the angle is -5° or more and less than 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is -30° or more and less than 30°. Furthermore, "perpendicular" refers to a state where the angle between two straight lines is 80° or more and less than 100°. Therefore, it also includes a state where the angle is 85° or more and less than 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is 60° or more and less than 120°.

[0071] In this specification and other materials, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also abbreviated as OS). For example, when a metal oxide is used as the semiconductor layer of a transistor, it is sometimes referred to as an oxide semiconductor. In other words, when denoted as an OS transistor, it means a transistor that contains either a metal oxide or an oxide semiconductor.

[0072] Note that in this specification, "normally off" means that the drain current flowing through the transistor per channel width of 1 μm is 1 × 10⁻⁶ at room temperature when no gate potential is applied or when a ground potential is applied to the gate. -20 Below A, at 85℃, it is 1×10 -18 Below A, or 1×10 at 125℃ -16 Below A.

[0073] (Implementation Method 1)

[0074] In this embodiment, an example of a semiconductor device including a transistor according to one aspect of the present invention will be described.

[0075] <Examples of semiconductor device structures>

[0076] Figures 1A to 1D This is a top view and a cross-sectional view of a semiconductor device including a transistor 200 according to one aspect of the present invention. Figure 1A This is a top view of the semiconductor device. Additionally, Figure 1B , Figure 1C and Figure 1D This is a cross-sectional view of the semiconductor device. Here, Figure 1B It is along Figure 1A The cross-sectional view of the section marked with dotted lines A1-A2 is also a cross-sectional view along the channel length of transistor 200. Additionally, Figure 1C It is along Figure 1A The cross-sectional view of the section marked with dotted lines A3-A4 is also a cross-sectional view of the channel width direction of transistor 200. Additionally, Figure 1D It is along Figure 1A The cross-sectional view of the section marked with dotted lines A5-A6 is also a cross-sectional view of the channel width direction of transistor 200. Note that in Figure 1A In the top view, some constituent elements are omitted for clarity.

[0077] One aspect of the semiconductor device of the present invention includes a transistor 200, an insulator 214, an insulator 216, an insulator 280, an insulator 282, and an insulator 284 used as interlayer films.

[0078] [Transistor 200]

[0079] like Figures 1A to 1D As shown, transistor 200 includes a conductor 205 disposed on a substrate (not shown) and embedded in an insulator 216, an insulator 222 disposed on the insulator 216 and the conductor 205, an insulator 224 disposed on the insulator 222, an oxide 230 (oxide 230a, oxide 230b and oxide 230c) disposed on the insulator 224, an insulator 250 disposed on the oxide 230, a conductor 260 (conductor 260a and conductor 260b) disposed on the insulator 250, a conductor 240a and conductor 240b in contact with a portion of the top surface of the oxide 230b, an insulator 245a on the conductor 240a and an insulator 245b on the conductor 240b.

[0080] In transistor 200, metal oxides (hereinafter also referred to as oxide semiconductors) are preferably used to form oxides 230 (oxides 230a, oxides 230b and oxides 230c) including the region forming the channel (hereinafter also referred to as the channel forming region).

[0081] As the metal oxide used as a semiconductor, it is preferable to use a metal oxide with a band gap of 2 eV or more, and more preferably a metal oxide with a band gap of 2.5 eV or more. In this way, by using a metal oxide with a wider band gap, the off-state current of the transistor can be reduced.

[0082] For example, metal oxides containing In-M-Zn oxides (where element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) are preferably used as oxide 230. In-Ga oxides and In-Zn oxides may also be used as oxide 230.

[0083] Since the transistor 200, which uses metal oxide in the channel formation region, has extremely low leakage current in the non-conducting state, it can provide a low-power semiconductor device. Furthermore, since metal oxide can be formed using methods such as sputtering, it can be used to construct transistors 200 that form highly integrated semiconductor devices.

[0084] On the other hand, the electrical characteristics of transistors using metal oxides vary due to impurities and oxygen vacancies in the metal oxides, and they are prone to always-on characteristics (the characteristic that a channel exists and current flows through the transistor even without applying a voltage to the gate electrode). In addition, when the transistor is driven in a state where the metal oxide contains more than an appropriate amount of excess oxygen, the oxidation state of the excess oxygen atoms sometimes changes, and the electrical characteristics of the transistor change, thereby reducing reliability.

[0085] Furthermore, in one embodiment of the OS transistor of the present invention, a metal oxide with a low carrier concentration is preferably used as the channel formation region. To reduce the carrier concentration of the metal oxide, the impurity concentration in the metal oxide is reduced to lower the defect state density. In this specification, the state of low impurity concentration and low defect state density is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". Note that in this specification, the carrier concentration of the metal oxide in the channel formation region is 1 × 10⁻⁶. 16 cm -3 The following situation is defined as "substantially high purity intrinsic". The details of carrier concentration in metal oxides will be explained later.

[0086] In addition, impurities in metal oxides include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. In particular, hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies in the metal oxide. When oxygen vacancies are present in the channel-forming region of the metal oxide, the transistor sometimes exhibits always-on characteristics. Furthermore, when hydrogen enters an oxygen vacancy in the metal oxide, sometimes hydrogen bonds to the oxygen vacancy to form a V0. O H. Defects where hydrogen enters oxygen vacancies (V) O Hydrogen (H) is used as a donor, sometimes generating electrons as charge carriers. Additionally, some hydrogen atoms sometimes bond with oxygen atoms bonded to metal atoms to generate electrons as charge carriers. Therefore, transistors using metal oxides containing a large amount of hydrogen tend to have always-on characteristics. Furthermore, because hydrogen in metal oxides is easily moved by pressure such as heat and electric fields, a large amount of hydrogen in the metal oxide may lead to a decrease in transistor reliability.

[0087] The defect (V) where hydrogen enters an oxygen vacancy. O H) is used as a donor for metal oxides. However, it is difficult to quantitatively evaluate this defect. Therefore, in metal oxides, the carrier concentration is sometimes used instead of the donor concentration for evaluation. Therefore, in this specification, etc., the carrier concentration, which assumes no electric field is applied, is sometimes used as a parameter for metal oxides instead of the donor concentration. That is to say, the "carrier concentration" described in this specification, etc., can sometimes be referred to as "donor concentration".

[0088] It is preferable to minimize the amount of hydrogen in metal oxides. Specifically, in metal oxides, the hydrogen concentration measured using secondary ion mass spectrometry (SIMS) is set to be below 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 1×10 19 atoms / cm 3 More preferably, less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3 By using metal oxides with sufficiently reduced impurities such as hydrogen in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0089] Furthermore, the carrier concentration of the metal oxide in the channel formation region is preferably 1×10⁻⁶. 18 cm -3 Hereinafter, 1×10 is more preferred. 17 cm -3 Hereinafter, 1×10 is further preferred. 16 cm -3 Below, we further prefer a value less than 1×10 13 cm -3 Especially preferred is less than 1×10 12 cm -3 Note that there is no particular limit to the lower limit of the carrier concentration of the metal oxide in the channel formation region; for example, it can be 1 × 10⁻⁶. -9 cm -3 .

[0090] In one aspect of the invention, it is preferable to minimize V in oxide 230. O H makes oxide 230 "intrinsically high purity" or "substantially high purity". In this way, in order to obtain V... O For metal oxides with sufficiently low H content, it is important to remove impurities such as moisture and hydrogen (sometimes described as dehydration or dehydrogenation) and to supply oxygen to fill oxygen vacancies (sometimes described as oxidation). This is achieved by... O Metal oxides with sufficiently reduced impurities such as hydrogen (H) used in the channel formation region of transistors can impart stable electrical characteristics.

[0091] Here, it is preferable to perform microwave treatment on the oxide 230 under an oxygen-containing atmosphere and under reduced pressure. Particularly preferred is to perform microwave treatment on the channel-forming region of the oxide 230 under an oxygen-containing atmosphere and under reduced pressure. By performing microwave treatment, an electric field generated by the microwaves is applied to the oxide 230, thereby increasing the Vo in the oxide 230. O H separated into V O With hydrogen. At this time, some of the separated hydrogen sometimes bonds to oxygen and is removed from oxide 230 as H2O. Additionally, some hydrogen is sometimes doped by conductors 240a and 240b. Thus, by performing microwave treatment, the hydrogen concentration in oxide 230 can be reduced. Furthermore, by adjusting the V in oxide 230... O H separated into V O V produced after reacting with hydrogen O Supplying oxygen can repair or replenish V O .

[0092] As described above, a device that includes a power source for generating high-density plasma or a device that includes a power source for applying RF (Radio Frequency) to one side of the substrate is preferably used. For example, by using an oxygen-containing gas and high-density plasma, a high density of oxygen free radicals can be generated, and by applying RF to one side of the substrate, the oxygen free radicals generated by the high-density plasma can be efficiently introduced into oxide 230 or an insulator near oxide 230.

[0093] Alternatively, heating treatment can be performed while maintaining a reduced pressure after microwave treatment. This treatment can efficiently remove hydrogen from oxide 230. Furthermore, repeated heating treatment can further efficiently remove hydrogen from oxide 230. Note that the heating treatment temperature is preferably 300°C or higher and 500°C or lower. Note that the step of performing heating treatment while maintaining a reduced pressure after microwave treatment can also be repeated.

[0094] Especially when an indium-containing oxide is used as oxide 230, the oxide 230 is preferably subjected to the above-described microwave treatment. For example, when an In-M-Zn oxide is used as oxide 230, the oxygen in oxide 230 is mainly bonded to one or more of In, element M, and Zn. The bonding between indium and oxygen tends to be weaker than the bonding between element M or zinc and oxygen. Therefore, it can be considered that oxygen bonded to indium is more likely to be lost. In other words, it can be considered that oxygen vacancies are easily formed near indium. Furthermore, hydrogen enters the oxygen vacancy to form V. O H, therefore V tends to form near indium. O H.

[0095] In addition, indium is also a metallic element that improves the conductivity of oxide 230. Therefore, the higher the atomic ratio of indium in oxide 230, the greater the on-state current of transistor 200 tends to be. On the other hand, it can be considered that the higher the atomic ratio of indium in oxide 230, the easier it is to form V. O H. Therefore, when an indium-containing oxide is used as oxide 230, by performing the above-described microwave treatment on oxide 230, the amount of V in oxide 230 can be reduced. O H. Therefore, the on-state current of transistor 200 can be increased and it can be given stable electrical characteristics.

[0096] Furthermore, hydrogen can sometimes diffuse into the metal oxide during subsequent metal oxide film formation processes. For example, when forming an insulator 250, which serves as a gate insulator, in contact with oxide 230, a hydrogen-containing film-forming gas is sometimes used. The possibility of hydrogen in this film-forming gas diffusing into oxide 230 is high.

[0097] For example, the atmosphere in which the insulating film that will become the insulator 250 is formed, or the already formed insulator 250, may contain impurities such as hydrogen, nitrogen, and carbon. In particular, in order to remove impurities bonded to silicon atoms, it is necessary to break the bond between the impurity atoms and the silicon atoms, so it is difficult to remove impurities by heat treatment.

[0098] Therefore, after forming the insulator 250 on the oxide 230, microwave treatment is preferably performed under oxygen-containing gas and reduced pressure. By performing microwave treatment, an electric field generated by the microwaves is applied to the insulator 250 and the oxide 230, thereby causing hydrogen atoms bonded to silicon atoms in the insulator 250 to separate from the silicon atoms, and also causing V in the oxide 230 to be removed. O H is divided into V O And hydrogen. At this time, some of the separated hydrogen sometimes bonds with oxygen and is removed from insulator 250 and oxide 230 as H2O. Additionally, some hydrogen is sometimes doped by conductors 240a and 240b. Thus, by performing microwave treatment, the hydrogen concentration in insulator 250 and oxide 230 can be reduced. Furthermore, by adjusting the V in oxide 230... O H separated into V O V produced after reacting with hydrogen O Supplying oxygen can repair or replenish V O .

[0099] Alternatively, heating treatment can be performed while maintaining a reduced pressure after microwave treatment. This treatment efficiently removes hydrogen from the insulator 250 and oxide 230. Furthermore, the step of performing heating treatment while maintaining a reduced pressure after microwave treatment can be repeated. Alternatively, after microwave treatment for 10 seconds to 300 seconds, preferably 30 seconds to 60 seconds, a reduced pressure can be maintained and heating treatment can be performed for 30 seconds to 3000 seconds, preferably 300 seconds or closer, and this step can be performed 2 to 10 times. Repeated heating treatment allows for more efficient removal of hydrogen from the insulator 250 and oxide 230. Note that the heating treatment temperature is preferably 300°C to 500°C.

[0100] Furthermore, by altering the film quality of the insulator 250 through microwave treatment, the diffusion of hydrogen, water, or impurities can be suppressed. Therefore, the diffusion of hydrogen, water, or impurities from the insulator 250 to the oxide 230 can be suppressed due to subsequent processes such as film formation or heat treatment, which will become the conductive film of the conductor 260.

[0101] For example, in solid silicon oxide, the bond energy between hydrogen and silicon atoms is 3.3 eV, the bond energy between carbon and silicon atoms is 3.4 eV, and the bond energy between nitrogen and silicon atoms is 3.5 eV. Therefore, in order to remove hydrogen atoms bonded to silicon atoms, the bond between hydrogen and silicon atoms can be broken by colliding a free radical or ion with an energy of at least 3.3 eV with the junction of hydrogen and silicon atoms.

[0102] Note that, similarly, as with other impurities such as nitrogen and carbon, the bond between impurity atoms and silicon atoms can be broken by having free radicals or ions with at least bond energies collide with the junction of the impurity atom and silicon atom.

[0103] Here, as examples of free radicals and ions generated by microwave-excited plasma, the ground state O(oxygen radical) can be cited. 3 P), the first excited state of oxygen radical O (P) 1 D) and the monovalent cation O2+ of oxygen molecules, etc. O( 3 The energy of P is 2.42 eV, and the energy of O is... 1 The energy of D) is 4.6 eV. Additionally, due to O 2 + has an electrical charge and is accelerated by the potential distribution and bias voltage in the plasma, so the energy is not limited to a single value, but at least even if only the internal energy is considered, it has a higher energy than O( 1 D) Higher energy.

[0104] In other words, O( 1D) and free radicals and ions such as O2+ can break the bonds between hydrogen, nitrogen, and carbon atoms and silicon atoms in insulator 250 and remove hydrogen, nitrogen, and carbon atoms bonded to silicon atoms. In addition, the thermal energy applied to the substrate by microwave-excited plasma treatment can also reduce impurities such as hydrogen, nitrogen, and carbon.

[0105] On the other hand, due to O( 3 P) has low reactivity, does not react with insulator 250, and diffuses deep into the film. Additionally, O( 3 P) passes through insulator 250 to reach oxide 230 and diffuses into oxide 230. O( 3 When P approaches an oxygen vacancy that has entered hydrogen, the hydrogen in the oxygen vacancy is released from the oxygen vacancy, while O( 3 P) enters and fills the oxygen vacancy. This suppresses the formation of charge carrier electrons in oxide 230.

[0106] Furthermore, when microwave processing is performed under high pressure conditions, the O(n) content relative to the overall free radicals and ionic species... 3 The proportion of P) is increased. To fill oxygen vacancies in oxide 230, O( 3 The proportion of P is high. Therefore, the pressure in microwave processing is 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. In addition, as the gas introduced into the microwave processing apparatus, oxygen and argon are used, and the oxygen flow ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0107] The above steps can reduce the V content in metal oxides that is used as a donor. O H, therefore, can reduce the carrier concentration of the metal oxide used as the channel formation region. Transistors using such metal compounds in the channel formation region can have normally off characteristics, thereby enabling the construction of semiconductor devices with good electrical characteristics and reliability.

[0108] Furthermore, by using the aforementioned metal oxide in the channel formation region of the transistor, the ΔVsh measured by the +GBT (Gate Bias Temperature) stress test can be reduced. This improves the reliability of the transistor. Note that the behavior model of ΔVsh will be explained later.

[0109] Therefore, a highly reliable semiconductor device can be provided. Furthermore, a semiconductor device with good electrical characteristics can be provided. Furthermore, a semiconductor device that can be miniaturized or highly integrated can be provided. Furthermore, a semiconductor device with low power consumption can be provided.

[0110] <Regarding the action of ΔVsh in the +GBT stress test>

[0111] The following section explains the behavior of the off-state current in the OS transistor and ΔVsh during +GBT stress testing. Here, the metal oxide used in the channel formation region is described as an In-Ga-Zn oxide.

[0112] Note that in the following explanation, the drift voltage (Vsh) is defined as: the Vg at which the tangent line at the point of greatest slope on the drain current (Id) vs. gate voltage (Vg) curve of the transistor intersects the straight line where Id = 1 pA. Furthermore, the change in drift voltage is represented by ΔVsh.

[0113] In the +GBT stress test of the OS transistor, ΔVsh sometimes drifts in the negative direction over time. Additionally, ΔVsh sometimes exhibits behavior that varies in both the negative and positive directions, and not just in the - direction (e.g., the negative direction). Note that in this specification, etc., the above behavior is sometimes referred to as a sawtooth behavior in the +GBT stress test.

[0114] Here, Figure 2A This diagram illustrates the action of ΔVsh in the +GBT test. Figure 2A In the diagram, the vertical axis and the horizontal axis represent ΔVsh[mV] and time[hr], respectively.

[0115] like Figure 2A As shown, in the +GBT stress test of the OS transistor, ΔVsh has a positive drift ( Figure 2A Arrow α in the middle) and drift in the negative direction ( Figure 2A The arrow β in the diagram changes simultaneously. Note that, as... Figure 2A As shown, ΔVsh changes in the negative direction overall while exhibiting the drift indicated by arrows α and β.

[0116] It can be assumed that the sawtooth behavior observed in the +GBT stress test is caused by oxygen vacancies (V0.05) in the channel formation region of the metal oxide. O ), hydrogen (H) and oxygen vacancies bonded to hydrogen defects (V) O H). That is, by reducing Vo, H and V in the channel formation region of the metal oxide. O H can reduce jagged movements in the +GBT test.

[0117] <About the basic model>

[0118] Here, the sawtooth behavior of ΔVth in the +GBT stress test can be explained by using the basic model shown below.

[0119] First, refer to Figure 2B The current flowing from the source to the drain in an OS transistor (drain current) is explained. Note that the OS transistor includes a gate electrode, a gate insulating layer, a metal oxide layer with a channel formation region, a source region, and a drain region.

[0120] Figure 2B This is a schematic diagram of the Id-Vg characteristics of an OS transistor. Figure 2B In the graph, the horizontal axis represents the change in the voltage (Vg) [V] applied to the gate electrode, and the vertical axis represents the change in the drain current (Id) [A]. Note that... Figure 2B It is a logarithmic chart with the vertical axis as the logarithmic axis (log).

[0121] Here, the drain current of the OS transistor has two types: one is the current related to the on-state current, and the other is the current related to the off-state current.

[0122] Figure 2B The current A shown by the solid line is the current related to the on-state current. Additionally, Figure 2B The current B, shown by the dashed line, is the current associated with the off-state current. Furthermore, Figure 2B The voltage Vab shown is the gate voltage value that is equal to the values ​​of currents A and B.

[0123] The drain current of the OS transistor was observed to be Figure 2B The sum of currents A and B is shown. When the gate voltage Vg is less than the voltage Vab, the ratio of current B to drain current is higher; when the gate voltage Vg is greater than the voltage Vab, the ratio of current A to drain current is higher.

[0124] In metal oxides, it can be inferred that the s orbitals of heavy metals (e.g., In in In-Ga-Zn oxides) primarily drive the conduction of charge carriers (electrons) associated with the on-state current. In other words, it can be inferred that the on-state current flows mainly due to the conductivity originating from InO. Furthermore, due to the diffusion of the depletion layer throughout the metal oxide, there is sufficient conductivity.

[0125] Furthermore, it can be inferred that the charge carriers associated with the off-state current originate from V. O The electrons of H. Note that V... O H is used as a donor and releases electrons as charge carriers.

[0126] Note that charge carriers are generated by doping silicon with phosphorus (P) or boron (B). These charge carriers are related to the current flowing between the source and drain regions. In other words, a type of charge carrier in silicon can be predicted to determine the on-state current and the off-state current.

[0127] Next, refer to Figure 3A , Figure 3B and Figure 3C Explain the V-channel in the OS transistor O H carrier conduction.

[0128] Figure 3A This is a schematic diagram of the energy diagram of a metal oxide. Figure 3A In the diagram, the vertical axis represents energy. The horizontal axis represents V. O The density of H. Figure 3A E shown CBM It is the energy at the bottom of the conduction band, E VBM It is the energy at the valence band peak, E i This is the energy at the band gap center (also known as the energy at the band gap center). Additionally, E1 and E2 are energies, with E2's value being closer to E than E1's. i The value of E1 is closer to E than the value of E2. CBM .

[0129] Due to V O H was used as a donor, so it can be inferred that the cause was V. O The energy level of H is located near the bottom of the conduction band. Therefore, as Figure 3A As shown, it can be inferred that V O The density distribution of H is located near the bottom of the conduction band. Note that the carriers associated with the off-state current are sometimes caused by V. O The energy level of H or the trapping center (trap center) binds or releases. Alternatively, it can be inferred that the cause is V. O The energy levels or capture centers of H exist in a dispersed manner.

[0130] Here, it is assumed that when the Fermi level is close to the center of the band gap (E i When V O H disappears and V O H decreases. For example, as Figure 3A As shown, assuming that V is closer to the bottom of the conduction band... O The higher the density of H, the closer it is to the center of the band gap (E). i The lower the density.

[0131] As mentioned above, in In-Ga-Zn oxides, V O H readily forms near indium. That is, V O H readily forms in InO.

[0132] In other words, since the conductivity originates from InO carriers, it can be inferred that it originates from V. O The charge carriers of H pass through V O H conducts current through which the off-state current flows. Therefore, by reducing V O H can inhibit the cause of V OH conducts charge carriers and reduces off-state current. Additionally, the number of charge carriers associated with the off-state current can be reduced. By lowering the off-state current, the charge carriers can be brought closer to what is considered naturally occurring charge carriers. This is achieved by reducing V in the metal oxide. O H can make the carrier concentration of metal oxides close to the intrinsic carrier concentration (for example, in the case of a metal compound with a band gap of 3.3 eV, its intrinsic carrier concentration is 1 × 10⁻⁶). -9 cm -3 ).

[0133] When the energy of the Fermi level approaches E1, in other words, when the Fermi level approaches the conduction band, compared to when the energy of the Fermi level approaches E2, V O H is more, or V O H has a higher density. Therefore, as... Figure 3B As shown, the carrier e associated with the off-state current - Via V O As the frequency of H conduction increases, the off-state current becomes larger.

[0134] On the other hand, when the energy of the Fermi level approaches E2, in other words, when the Fermi level approaches the center of the band gap (E2), i When the energy of the Fermi level is close to E1, V O H is less, or V O H has a lower density. Therefore, as... Figure 3C As shown, V O The H interval becomes larger, therefore the carrier e associated with the off-state current - Via V O The frequency of H conduction decreases, and the off-state current becomes smaller.

[0135] In other words, V O The greater the density of H, the greater the off-state current, V O The lower the density of H, the smaller the off-state current. In other words, the generation of V... O H then the off-state current increases, V O When H disappears, the off-state current decreases.

[0136] Furthermore, OS transistors exhibit characteristics such as minimal increase in off-state current at high temperatures and a high ratio of on-state current to off-state current at high temperatures. For example, OS transistors can maintain good switching operation even at temperatures above 125°C and below 150°C. The off-state current at high temperatures primarily originates from the Vo... O When H's charge carriers are conducted, by reducing V O H can further reduce the off-state current at high temperatures.

[0137] Furthermore, the sawtooth behavior of ΔVsh sometimes arises from currents related to the on-state current and sometimes from currents related to the off-state current. In particular, when the sawtooth behavior of ΔVsh arises from currents related to the on-state current, due to V... O Because there is a large amount of H, a sawtooth-shaped behavior of ΔVsh is more likely to occur. For example... Figure 3A As shown, the charge carriers associated with the on-state current are caused by V O The H level is trapped, or the trapped carriers are released into the conduction band. Compared to the Fermi level when the energy is close to E2, when the Fermi level is close to E1, V O H has a higher density because of V. O The energy level density of H is also high. Therefore, the charge carriers associated with the on-state current are generated by V. O The frequency at which H levels trap or trap carriers are released into the conduction band increases. Therefore, fluctuations in the on-state current are more likely to occur, and sawtooth behavior of ΔVsh is more likely to happen.

[0138] <About the application model>

[0139] Next, refer to Figure 4A and Figure 4B This section explains the application model for applying the above basic model to the +GBT stress test of OS transistors.

[0140] Note that in the +GBT stress test of the OS transistor, a positive potential is applied to the gate electrode. When a positive potential is applied to the gate electrode, the electric field generated by the gate electrode is applied to the channel formation region of the metal oxide.

[0141] Figure 4A and Figure 4B It's about V O H and the separated V O And a schematic diagram of the energy shift in the reaction of H. First refer to Figure 4A A detailed description of the application model for +GBT stress testing of OS transistors is provided.

[0142] exist Figure 4A and Figure 4B In the diagram, the vertical axis represents energy. Additionally... Figure 4A and Figure 4B State A in the middle is V O and H as V O The state in which H exists. Figure 4A and Figure 4B State B in the middle is V O The state that is separated from H (denoted as V) O+H). Note that we assume the energy ΔE required for the change from state 1 to state 2 is the difference between the energy of state 1 and the maximum energy located midway through the reaction. In other words, we can say that the larger the energy ΔE required for the reaction, the less likely the reaction is to occur.

[0143] like Figure 4A As shown, with the separated V O Compared to H, V O H is more stable and has lower energy. V is gradually regenerated due to the electric field applied to the metal oxide. O H, sometimes ΔVsh drifts in the negative direction over time. That is, with V O Compared to H being separated, Vo and H are V O It is more stable in the presence of H.

[0144] Figure 4A The dashed line P in the figure represents the energy shift of the above reaction when no electric field is applied to the metal oxide. Figure 4A In the dashed line P shown, ΔE2 represents the change from state A to state B (V O H is divided into V O The energy required to change from state B to state A (V). Additionally, ΔE1 is the energy required to change from state B to state A (V). O It bonds with H to form V O The energy required for H).

[0145] When no electric field is applied to the metal oxide, V O H and the separated V O The reaction with H requires a relatively large amount of energy (ΔE1 and ΔE2). Therefore, the lower the temperature, the greater the energy required for V. O H is divided into V O The lower the frequency of the reaction with H, the higher the temperature, and the higher the frequency. For example, by heat treatment at 400°C for 4 hours, V O H is divided into V O The reaction with H is advanced; furthermore, through oxidation treatment, oxygen vacancies are repaired and hydrogen reacts with oxygen to be removed as H2O, thereby inhibiting V. O The redistribution of H and the reduction of V O H.

[0146] then, Figure 4A The solid line Q shows the energy shift of the above reaction when an electric field is applied to the metal oxide.

[0147] By applying an electric field to the metal oxide, sometimes V O The direction of H changes, or V O H is rearranged. Therefore, regarding V... O H and the separated V OThe energy shift of the reaction with H changes. For example, in V O H and the separated V O The reaction with H involves one or more metastable states. That is, in V... O H is divided into V O The reaction with H and V O It bonds with H to form V O In all reactions involving H, there are multiple energies ΔE required for each reaction.

[0148] Figure 4A V is shown O H and the separated V O The reaction with H involves a metastable state (state C) with an energy shift. Here, state C is the energy shift relative to V. O Metastable states related to H are sometimes used as donors and sometimes not.

[0149] exist Figure 4A In the solid line Q shown, ΔE AC It is determined by state A(V) O The energy required for H to change to state C, ΔE CB The state changes from state C to state B (the separated V) O The energy required for H). Additionally, ΔE BC It is composed of state B (separated V) O The energy required for H to change to state C, ΔE CA The state changes from state C to state A(V). O The energy required for H), ΔE BA It is composed of state B (separated V) O (and H) becomes state A(V) O The energy required for H).

[0150] Notice, Figure 4A Show ΔE CA Ratio ΔE BC A large example, but not limited to this. There is ΔE. CA Ratio ΔE BC Even in small cases, ΔE can still occur. CA and ΔE BC The case where they are equal. Note that we assume ΔE below. CA Ratio ΔE BC The details will be explained.

[0151] like Figure 4A As shown, ΔE AC and ΔE CB It is smaller than ΔE2. Therefore, by applying an electric field to the metal oxide, V in the metal oxide is more easily induced. O H is divided into V OThe reaction with H. Note that even with a weak electric field applied to the metal oxide, V in the metal oxide may still undergo reaction. O H is divided into V O The reaction with H.

[0152] In addition, such as Figure 4A As shown, due to ΔE BC Smaller than ΔE1, state B (the separated V) O (and H) easily transforms into state C. Furthermore, due to ΔE CA Ratio ΔE BC Larger, state C changes to state A(V) O The frequency of H) is low. Therefore, by applying an electric field to the metal oxide, the V in the metal oxide... O H readily transforms into state C. State C is used as a donor, or, when promoting the conduction of carriers associated with the off-state current, the increase in the number of states C causes ΔVsh to shift negatively. Additionally, due to ΔE... CB It is also relatively small, so state C easily returns to state B (the separated V). O (and H). State C returns to state B (the separated V). O The number of states C is reduced by generating states C and B (separated V). Note that reducing the number of states C affects the positive change of ΔVsh but not the negative change. That is, by generating states C and B (separated V), the number of states C is reduced by generating states C and B (separated V). O The reaction with H) makes the energy unstable and produces a sawtooth-shaped behavior of ΔVsh.

[0153] In addition, such as Figure 4A As shown, ΔE BA It is smaller than ΔE1. ​​Furthermore, ΔE BC Ratio ΔE BA Small. Therefore, by applying an electric field to the metal oxide, state B (the separated V) in the metal oxide... O H) can easily become state A(V) O H). V O Increasing the number of H values ​​causes ΔVsh to shift negatively. Additionally, ΔE... AC Smaller than ΔE2 and ΔE CB Ratio ΔE AC Small. Therefore, by applying an electric field to the metal oxide, the V in the metal oxide... O H easily reverts to state B (the separated V). O And H). Through V O H returns to the separated V. O and H, V O The number of H's decreases. Note that this is achieved through V. O As the number of H values ​​decreases, the probability of ΔVsh changing in the positive direction increases. In other words, by generating a cut-off V...O and H and V O The reaction of H becomes energy unstable and produces a sawtooth-shaped behavior of ΔVsh.

[0154] Based on the above explanation, it can be understood that the sawtooth-shaped behavior of ΔVsh in the +GBT stress test is due to V O H occurs.

[0155] As described above, by applying an electric field to the metal oxide, at V O H and V O H is separated from V O The reaction with H involves one or more metastable states. Note that... Figure 4A A schematic diagram illustrating the energy shift when a metastable state exists is shown. Figure 4B A schematic diagram showing the energy shift when multiple metastable states exist. Figure 4B The dashed line P shown is... Figure 4A The same indicates the energy shift of the above reaction when no electric field is applied to the metal oxide. Additionally, Figure 4B The solid line Q shown represents V with respect to the existence of three metastable states (states C, D, and E). O H and the separated V O The energy shift of the reaction with H. Similar to the case where a metastable state exists, V readily produces... O H and the separated V O The reaction with H produces a sawtooth-shaped action of ΔVsh in the +GBT stress test.

[0156] Note that in Figure 4B In the dashed line P shown, ΔE2 is generated by state A(V O H) becomes state B (the separated V) O The energy required for state B (and H), ΔE1 is determined by state B (the separated V). O (and H) becomes state A(V) O The energy required for H).

[0157] In addition, Figure 4B In the solid line Q shown, ΔE AD It is determined by state A(V) O The energy required for state H to change to state D, ΔE AC It is determined by state A(V) O The energy required for H to change to state C, ΔE CE The energy required to change from state C to state E, ΔE EB The state changes from E to B (the separated V) O The energy required for H). Additionally, ΔE BE It is composed of state B (separated V) OThe energy required for state H to change to state E, ΔE BC It is composed of state B (separated V) O The energy required for H to change to state C, ΔE BD It is composed of state B (separated V) O The energy required for state D to change from state H to state D, ΔE DA The state changes from D to A(V) O The energy required for H). Furthermore, ΔE BA It is composed of state B (separated V) O (and H) becomes state A(V) O The energy required for H), ΔE CD It is the energy required to change from state C to state D.

[0158] Figure 4A and Figure 4B This shows the effect of V caused by whether or not an electric field is applied to the metal oxide. O H and the separated V O A schematic diagram of the energy shift of the reaction with H, but the energy shift of this reaction varies depending on the crystallinity of the metal oxide. For example, sometimes it can be... Figure 4A and Figure 4B The dashed line P shown can be interpreted as the energy shift of this reaction in a single-crystal metal oxide, which can be used to... Figure 4A and Figure 4B The solid line Q shown represents the energy shift of this reaction in metal oxides with CAAC or nc structures. That is, metal oxides with CAAC or nc structures sometimes more readily produce V compared to single-crystal metal oxides. O H is divided into V O The reaction with H. Note that the energy shift for this reaction in metal oxides with an nc structure is sometimes greater than that of H. Figure 4A and Figure 4B The solid line Q shown is more complex.

[0159] As mentioned above, the V in metal oxides can be inferred. O H is repeatedly generated and disappears. In other words, in V... O H drifts depending on the electric field, or V O When H repeatedly generates and disappears, a sawtooth-shaped behavior is produced in the +GBT stress test.

[0160] Note that, in addition to the sawtooth behavior of ΔVsh mentioned above, V in metal oxides O The generation and disappearance of H can also be one of the causes of various instabilities. For example, it can be inferred that the change in off-state current each time the OS transistor is measured is also due to V in the metal oxide. OThe generation and disappearance of H.

[0161] On the other hand, in an OS transistor, due to the short-channel effect, the carriers and those from V O The different charge carriers in H suggest that the short-channel effect is less likely to occur. Furthermore, as one example of a short-channel effect, the increase in the S value of the OS transistor can be cited. The S value is related to the on-state current, and the charge carriers related to the on-state current are those originating from V. O The charge carriers in H are different. Therefore, even if V is repeated... O The generation and disappearance of H do not affect, or are unlikely to affect, the short-channel effect. In other words, it can be inferred that the OS transistor is a device structure that is unlikely to produce a short-channel effect.

[0162] In addition, the above V O The disappearance of H can also be described as separation into V. O And H. In the manufacturing process of OS transistors, V O Separation between H and V can be achieved through microwave treatment of metal oxides by applying an electric field, or through heating treatments such as dehydration or dehydrogenation. Therefore, microwave treatment or heating treatment can be considered important processes in the manufacturing of OS transistors. In addition to the aforementioned heating treatments, oxidation treatment is also important. Oxidation treatment refers to the following process: in the manufacturing process of OS transistors, heating treatment is performed under an oxygen atmosphere or in a state where an insulating film with excess oxygen is in contact with the metal oxide, so that V formed in the metal oxide can be repaired by oxygen. O .

[0163] Furthermore, the formulas (1) and (2) shown below can represent the above V. O The disappearance of H and the utilization of oxygen by V O The repair. Formula (1) represents V O The disappearance of H, that is, V O H is divided into V O The state of H, and formula (2) represents the oxygen remediation of V. O The state.

[0164] ·V O H→V O +H (1)

[0165] ·V O +O→null (2)

[0166] V in metal oxides O The probability of H existing >

[0167] Next, we will discuss V in metal oxides. O The probability of the existence of H is explained.

[0168] In an OS transistor, by contacting a conductor used as the source or drain electrode with a metal oxide, oxygen from the metal oxide can diffuse into the conductor, causing it to oxidize. The conductivity of this conductor is highly likely to decrease due to oxidation. Note that the diffusion of oxygen from the metal oxide into the conductor can also be referred to as the conductor absorbing oxygen from the metal oxide.

[0169] Furthermore, by allowing oxygen from the metal oxide to diffuse to the source and drain electrodes, a layer can sometimes be formed between the source electrode and the metal oxide, and between the drain electrode and the metal oxide. Since this layer contains more oxygen than the source or drain electrode, it can be inferred that the layer has insulating properties. In this case, the three-layer structure of the source or drain electrode, the layer, and the metal oxide can be regarded as a three-layer structure formed by metal-insulator-semiconductor, or as a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure dominated by the MIS structure.

[0170] In the above MIS structure, a potential barrier is formed between the source electrode or drain electrode and the aforementioned layer. The bending of the band can be used to infer V. O H accumulates at the interface between the aforementioned layer and the metal oxide. In other words, the V at the interface between the aforementioned layer and the metal oxide can be inferred. O The probability of H's existence increases. In V O When H accumulates at this interface, the energy becomes stable. Furthermore, it can be inferred that through V... O H accumulates at the interface, and the metal oxide near the interface forms a low-resistivity region.

[0171] Note that sometimes it originates from the V that gathers on this interface. O Hydrogen from H diffuses towards the source or drain electrode. In particular, by using tantalum-containing nitrides as both the source and drain electrodes, hydrogen from V deposits accumulated at the interface diffuses towards the source or drain electrode. O Hydrogen readily diffuses towards the source or drain electrode, and sometimes the diffused hydrogen bonds to the nitrogen present at the source or drain electrode. In other words, it sometimes originates from V atoms accumulated at the interface. O The hydrogen in H is absorbed by the source electrode or the drain electrode.

[0172] For example, by heat-treating at 400°C for 4 hours, an oxygen-deficient region is formed in the metal oxide near the aforementioned interface. At this time, the V in the metal oxide... O H can also easily move in regions with low electric fields in the MIS structure, forming low-resistance regions in the metal oxide near the aforementioned interface.

[0173] <Detailed Structure of Semiconductor Devices>

[0174] The detailed structure of a semiconductor device including a transistor 200 according to one aspect of the present invention will now be described.

[0175] The insulator 214 is preferably used as an insulating barrier film to suppress the diffusion of impurities such as water and hydrogen from the substrate side into the transistor 200. Therefore, the insulator 214 is preferably an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. In addition, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0176] In this specification, "the function of inhibiting the diffusion of impurities or oxygen" refers to the function of inhibiting the diffusion of any one or all of the aforementioned impurities or oxygen. Furthermore, membranes with the function of inhibiting the diffusion of hydrogen or oxygen are sometimes referred to as membranes that are not easily permeable to hydrogen or oxygen, membranes with low hydrogen or oxygen permeability, membranes that block hydrogen or oxygen, or barrier membranes for hydrogen or oxygen. Additionally, when the barrier membrane is conductive, it is sometimes referred to as a conductive barrier membrane.

[0177] For example, it is preferable to use aluminum oxide, silicon nitride, or the like as the insulator 214. This suppresses the diffusion of impurities such as water and hydrogen from the side closer to the substrate than the insulator 214 to the transistor 200 side. Furthermore, it suppresses the diffusion of oxygen contained in the insulator 224, etc., to the side closer to the substrate than the insulator 214. Moreover, the insulator 214 may also have a stacked structure of two or more layers. In this case, it is not limited to a stacked structure made of the same material; a stacked structure formed of different materials can also be used. For example, a stack of aluminum oxide and silicon nitride can be used.

[0178] For example, silicon nitride formed by sputtering is preferably used as the insulator 214. This reduces the hydrogen concentration in the insulator 214 and suppresses the diffusion of impurities such as water and hydrogen from the side closer to the substrate than the insulator 214 to the transistor 200 side.

[0179] The dielectric constant of the insulator 216, which is used as the interlayer film, is preferably lower than that of the insulator 214. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen added, and porous silicon oxide are suitable as insulator 216.

[0180] Furthermore, the insulator 216 preferably has a low hydrogen concentration and includes an excess oxygen region or contains oxygen removed by heating (hereinafter also referred to as "excess oxygen"). For example, silicon oxide formed by sputtering is preferably used as the insulator 216. This suppresses hydrogen incorporation into the oxide 230, or supplies oxygen to the oxide 230 to reduce oxygen vacancies. Therefore, a transistor with improved reliability can be provided while maintaining stable electrical characteristics despite variations in electrical properties.

[0181] Furthermore, the insulator 216 may also have a laminated structure. For example, it may be possible to use a structure identical to that of the insulator 214, where at least the portion of the insulator 216 in contact with the side of the conductor 205 is provided. By employing this structure, oxidation of the conductor 205 by the oxygen contained in the insulator 216 can be suppressed. Alternatively, the reduction of the oxygen content contained in the insulator 216 due to the conductor 205 can be suppressed.

[0182] Conductor 205 is sometimes used as a second gate (also called a bottom gate) electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by independently changing the potential supplied to conductor 205 without linking it to the potential supplied to conductor 260. In particular, by supplying a negative potential to conductor 205, the Vth of transistor 200 can be increased and the off-state current can be reduced. Therefore, compared with not applying a negative potential to conductor 205, applying a negative potential to conductor 205 can reduce the drain current when the potential supplied to conductor 260 is 0V.

[0183] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Alternatively, the conductor 205 is preferably disposed within the insulator 214 or the insulator 216.

[0184] In addition, such as Figure 1B As shown, the conductor 205 is preferably larger than the channel formation region of the oxide 230. In particular, as Figure 1C As shown, conductor 205 preferably extends to the region outside the end that intersects with the channel width direction of oxide 230. That is, conductor 205 and conductor 260 preferably overlap with an insulator on the outer side of the side of oxide 230 in the channel width direction. By adopting this structure, a region can be formed around the channel of oxide 230 by the electric field of conductor 260, which is used as the first gate electrode, and the electric field of conductor 205, which is used as the second gate electrode. In this specification, the transistor structure in which the electric fields of the first gate and the second gate form a region around the channel is referred to as a surrounded channel (S-channel) structure.

[0185] In this specification, an S-channel transistor refers to a transistor structure in which the electric field of one of a pair of gate electrodes surrounds the channel forming region. Furthermore, in this specification, the S-channel structure has the following characteristics: Similar to the channel forming region, the sides and peripheries of the oxide 230 in contact with the conductors 240a and 240b, which serve as the source and drain electrodes, are type I. Additionally, since it is in contact with the insulator 280, the sides and peripheries of the oxide 230 in contact with the conductors 240a and 240b may also be type I, similar to the channel forming region. Note that in this specification, type I can be considered the same as the aforementioned high-purity intrinsic structure. Furthermore, the S-channel structure disclosed in this specification differs from Fin-type and planar structures. By employing the S-channel structure, tolerance to short-channel effects can be improved; in other words, a transistor less prone to short-channel effects can be realized.

[0186] Figure 1C This is a cross-sectional view of the region where oxide 230 and conductor 260 overlap. Additionally, Figure 1D This is a cross-sectional view of the region where oxide 230 does not overlap with conductor 260. (Example) Figure 1C As shown, by making the upper end of the oxide 230 into a curved shape, an electric field can be appropriately applied to the oxide 230 from one or both of the conductor 260 used as the first gate electrode and the conductor 205 used as the second gate electrode. On the other hand, as Figure 1D As shown, by making the upper end of the oxide 230 a shape without curvature, the adhesion between the oxide 230 and the conductor 240b can be improved, and the coverage of the insulator 280 can also be improved, so it is preferred.

[0187] In addition, such as Figure 1C As shown, conductor 205 is extended for use as wiring. However, the invention is not limited to this; conductors used for wiring may also be provided under conductor 205. Furthermore, it is not necessary to provide a conductor 205 in each transistor. For example, conductor 205 can be shared among multiple transistors.

[0188] Although a first conductor and a second conductor of conductor 205 are stacked in transistor 200, the present invention is not limited thereto. For example, conductor 205 may also have a single-layer structure or a stacked structure of three or more layers. In addition, when the structure has a stacked structure, ordinal numbers are sometimes assigned according to the order of formation for differentiation.

[0189] Here, as the first conductor of conductor 205, it is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. In addition, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0190] When a conductive material with the function of inhibiting oxygen diffusion is used as the first conductor of conductor 205, the oxidation of the second conductor of conductor 205, which would otherwise lead to a decrease in conductivity, can be prevented. For example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc., are preferably used as the conductive material with the function of inhibiting oxygen diffusion. Therefore, a single layer or a stack of the above-mentioned conductive materials can be used as the first conductor of conductor 205. For example, the first conductor of conductor 205 may also be a stack of tantalum, tantalum nitride, ruthenium, or ruthenium oxide with titanium or titanium nitride.

[0191] Furthermore, as the second conductor of conductor 205, a conductive material with tungsten, copper, or aluminum as its main components is preferably used. In the accompanying drawings, the second conductor of conductor 205 is illustrated as a single layer, but the second conductor of conductor 205 may also have a multilayer structure, for example, it may be a multilayer of titanium or titanium nitride with the aforementioned conductive material.

[0192] Insulators 222 and 224 are used as gate insulators.

[0193] Insulator 222 preferably has the function of inhibiting the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). Furthermore, insulator 222 preferably has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, compared to insulator 224, insulator 222 preferably has the function of inhibiting the diffusion of one or both of hydrogen and oxygen.

[0194] The insulator 222 is preferably an insulator containing an oxide of one or both of aluminum and hafnium as the insulating material. Aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are preferred as this insulator. When this material is used to form the insulator 222, the insulator 222 serves as a layer to suppress the release of oxygen from the oxide 230 to the substrate side or the diffusion of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230. Therefore, by providing the insulator 222, the diffusion of impurities such as hydrogen into the inner side of the transistor 200 can be suppressed, and the generation of oxygen vacancies in the oxide 230 can be suppressed. Furthermore, the reaction between the conductor 205 and the oxygen contained in the insulator 224 or the oxide 230 can be suppressed.

[0195] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Furthermore, the insulator may be nitrided. Additionally, silicon oxide, silicon oxynitride, or silicon nitride may be laminated onto the insulator 222.

[0196] Furthermore, as the insulator 222, insulators comprising so-called high-k materials such as alumina, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST) can be used, either as a single layer or in a stack. When miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0197] The insulator 224 in contact with the oxide 230 is preferably heated to remove oxygen. For example, silicon oxide, silicon oxynitride, etc., can be appropriately used as the insulator 224. By providing an oxygen-containing insulator in a manner that contacts the oxide 230, oxygen vacancies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200.

[0198] Specifically, as the insulator 224, an oxide material that allows a portion of the oxygen to be removed by heating is preferably used; in other words, an insulating material having an excess oxygen region is preferred. An oxide film that allows oxygen to be removed by heating refers to an oxide film in which the amount of oxygen molecules removed by heating is 1.0 × 10⁻⁶ in TDS (Thermal Desorption Spectroscopy) analysis. 18 molecules / cm 3 The preferred value is 1.0 × 10⁴. 19 molecules / cm 3 The above is further preferred to be 2.0×10 19 molecules / cm 3 Above, or 3.0 × 10 20 molecules / cm 3 The above-mentioned oxide film. Furthermore, the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0199] Alternatively, the insulator and oxide 230 with the excess oxygen region described above can be subjected to one or more of the following treatments: heat treatment, microwave treatment, and RF treatment, in a manner that allows them to come into contact with each other. By performing this treatment, water or hydrogen can be removed from the oxide 230. For example, in the oxide 230, a reaction occurs in which the VoH bonds are broken; in other words, a "V" reaction occurs. O H→V O The reaction of +H is used to achieve dehydrogenation. Some of the hydrogen produced here is sometimes bonded to oxygen and removed as H2O from oxide 230 or the insulator near oxide 230. In addition, some hydrogen sometimes diffuses to conductors 240a and 240b or is captured by conductors 240a and 240b (also known as gettering). Note that this microwave processing can be performed using the processing conditions described above.

[0200] Furthermore, in the manufacturing process of transistor 200, the heat treatment is preferably performed with the surface of oxide 230 exposed. This heat treatment can be performed, for example, at a temperature of 100°C or higher and 450°C or lower, more preferably at 350°C or higher and 400°C or lower. Additionally, the heat treatment is performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to oxide 230, thereby reducing oxygen vacancies (V0). O The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in an atmosphere of nitrogen or an inert gas, followed by heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the released oxygen. Alternatively, the heat treatment can be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, followed by continuous heat treatment in an atmosphere of nitrogen or an inert gas.

[0201] By subjecting oxide 230 to oxidation treatment, the supplied oxygen can fill the oxygen vacancies in oxide 230, in other words, it can promote the "V" oxidation process. O The reaction "+O→null" is observed. Furthermore, the hydrogen remaining in oxide 230 reacts with the supplied oxygen to remove the hydrogen as H2O (dehydration). This inhibits the recombination of hydrogen and oxygen vacancies in oxide 230 to form V. O H.

[0202] Additionally, it is preferable that the insulator 224 has a low hydrogen concentration and that the insulator 224 includes or contains excess oxygen regions, for example, it can be formed using the same material as the insulator 216.

[0203] Alternatively, insulators 222 and 224 may also have a multilayer structure with two or more layers. In this case, it is not limited to a multilayer structure made of the same material, but may also be a multilayer structure made of different materials.

[0204] For example, oxide 230 preferably includes oxide 230a disposed on insulator 224, oxide 230b disposed on oxide 230a, and oxide 230c disposed on oxide 230b, at least a portion of which is in contact with the top surface of oxide 230b. When oxide 230a is disposed under oxide 230b, the diffusion of impurities from the structure formed under oxide 230a to oxide 230b can be suppressed. When oxide 230c is disposed on oxide 230b, the diffusion of impurities from the structure formed above oxide 230c to oxide 230b can be suppressed.

[0205] Note that in transistor 200, oxide 230 is stacked with three layers: oxide 230a, oxide 230b, and oxide 230c. However, the present invention is not limited to this. For example, oxide 230 may also have a single-layer structure of oxide 230b, a two-layer structure of oxide 230a and oxide 230b, a two-layer structure of oxide 230b and oxide 230c, or a stacked structure of four or more layers. Each of oxide 230a, oxide 230b, and oxide 230c may also have a stacked structure.

[0206] In transistors using metal oxides, oxygen from the metal oxides is gradually absorbed by the conductors 240a and 240b constituting the transistor. As a result of time-dependent changes, oxygen vacancies may sometimes be generated. Furthermore, during the oxidation of conductors 240a and 240b, the contact resistance between the transistor 200 and the wiring may sometimes increase.

[0207] Therefore, an oxygen-containing insulator is used as the insulator 280, which is in contact with the oxide 230 and serves as an interlayer film. In particular, it is preferable to use an oxide whose oxygen content exceeds the stoichiometric composition as the insulator 280. That is, it is preferable to form a region in the insulator 280 where oxygen is in excess compared to the stoichiometric composition (hereinafter also referred to as "excess oxygen region").

[0208] Furthermore, it is preferable to provide insulators 245a and 245b, which serve as barrier layers, on conductors 240a and 240b, respectively. For example... Figure 1BAs shown, insulators 245a and 245b are preferably in contact with the top surfaces of conductors 240a and 240b, respectively. This structure suppresses the absorption of excess oxygen contained in the insulator 280 by conductors 240a and 240b. Furthermore, by suppressing the oxidation of conductors 240a and 240b, the increase in contact resistance between the transistor 200 and the wiring can be suppressed. Therefore, the transistor 200 can be endowed with good electrical characteristics and reliability.

[0209] Therefore, insulators 245a and 245b preferably have the function of suppressing oxygen diffusion. For example, compared with insulator 280, insulators 245a and 245b preferably have a further function of suppressing oxygen diffusion.

[0210] As insulators 245a and 245b, it is preferable to form an insulator containing an oxide of one or both of aluminum and hafnium. Alternatively, as insulators 245a and 245b, an insulator containing aluminum nitride may be used, for example.

[0211] Here, as Figure 1D As shown, preferably, at least the side surface of oxide 230b, the side surface of conductor 240a, and the side surface of conductor 240b that contact insulator 224 and oxide 230a are substantially perpendicular. Specifically, Figure 1D The angle θ shown is 60° or more and 95° or less, preferably 88° or more and 92° or less.

[0212] Furthermore, the side surface of oxide 230a does not necessarily need to form an angle with insulator 224. For example, a portion of the side surface of oxide 230a may also have a recess (also known as an undercut shape). This undercut shape is sometimes achieved when the side surface of oxide 230b, conductor 240a, and conductor 240b are machined into a shape substantially perpendicular to the surfaces in contact with insulator 224 and oxide 230a. By employing this undercut shape, the contact area of ​​insulator 280 with oxide 230a can sometimes be increased, thus allowing oxygen to be appropriately supplied to oxide 230b by insulator 280.

[0213] Notice, Figure 1D This is a cross-sectional view of the region where oxides 230a and 230b overlap with a conductor (conductor 240b) used as one of the source and drain electrodes in the channel width direction of the transistor.

[0214] In addition, such as Figure 1D As shown, the length of the bottom surface and the length of the top surface of conductor 240b are respectively denoted as L. 1B and L 1TAt that time, the ratio of the length of the bottom surface of conductor 240b to the length of the top surface of conductor 240b (L) 1T / L 1B The preferred value is 0.7 or more and 1.3 or less. For example, when the length (L) of the bottom surface of the conductor 240b is... 1B When the wavelength is 60 nm, the length (L) of the top surface of conductor 240b 1T The preferred nm size is 42 nm or larger and 78 nm or smaller. This is achieved by adjusting the length (L) relative to the bottom surface of the conductor 240b. 1B The length (L) of the top surface of conductor 240b 1T Setting it to the above range can reduce the contact resistance with the wiring formed later.

[0215] Note that when only the contact resistance mentioned above is considered, the length (L) of the top surface of conductor 240b is... 1T The length of the top surface of conductor 240b (L) is greater than the above range, but if the length of the top surface of conductor 240b is greater than the above range, the length of the top surface of conductor 240b (L) is greater than the above range. 1T Beyond the aforementioned range, the coverage (also known as step coverage) of insulator 280 deteriorates. Therefore, the ratio (Lb) of the length of the bottom surface of conductor 240b to the length of the top surface of conductor 240b... 1T / L 1B Preferably, the value is 0.7 or higher and 1.0 or lower, more preferably 0.8 or higher and 0.95 or lower.

[0216] Note that although the above ranges depend on the channel width of the transistor and the thickness of conductor 240a or conductor 240b, in one embodiment of the present invention, there are no particular limitations on the channel width of the transistor and the thickness of conductors 240a and 240b. Preferably, the channel width of the transistor is 5 nm or more and 100 nm or less, more preferably 10 nm or more and 75 nm or less. Similarly, the thickness of conductors 240a and 240b is preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 50 nm or less. As a transistor according to one embodiment of the present invention, significant effects can be expected when the channel width of the transistor and the thickness of conductors 240a and 240b satisfy the above ranges. Furthermore, although there are no particular limitations on the channel length of the transistor, it can be within the same range as the channel width described above.

[0217] Furthermore, although a cross-sectional view of the region where oxide 230 overlaps with another conductor used as both the source and drain electrodes (here, conductor 240a) is not shown, it is consistent with... Figure 1D The cross-sectional views shown are roughly the same.

[0218] Oxide 230 preferably has a stacked structure of oxides with different chemical compositions. Specifically, the atomic ratio of element M relative to the main metal element in the metal oxide used for oxide 230a is preferably greater than that in the metal oxide used for oxide 230b. Furthermore, the atomic ratio of element M relative to In in the metal oxide used for oxide 230a is preferably greater than that in the metal oxide used for oxide 230b. Additionally, the atomic ratio of In relative to element M in the metal oxide used for oxide 230b is preferably greater than that in the metal oxide used for oxide 230a. Furthermore, oxide 230c can use a metal oxide that can be used for either oxide 230a or oxide 230b.

[0219] Furthermore, oxides 230b and 230c preferably have crystallinity. For example, CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferably used. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (oxygen vacancies, etc.). Therefore, the extraction of oxygen from oxide 230b from the source electrode or drain electrode can be suppressed. Thus, even with heat treatment, the extraction of oxygen from oxide 230b can be reduced, and the transistor 200 has stability against the high temperatures (so-called thermal budget) in the manufacturing process.

[0220] Furthermore, CAAC-OS is preferably used as oxide 230c, and the c-axis of the crystals contained in oxide 230c is preferably oriented in a direction substantially perpendicular to the formed surface or top surface of oxide 230c. CAAC-OS has the characteristic of readily moving oxygen in a direction perpendicular to the c-axis. Therefore, the oxygen contained in oxide 230c can be supplied to oxide 230b with high efficiency.

[0221] Preferably, the conduction band bottoms of oxides 230a and 230c are closer to the vacuum level than the conduction band bottom of oxide 230b. In other words, the electron affinity of oxides 230a and 230c is preferably lower than that of oxide 230b. In this case, oxide 230c is preferably a metal oxide that can be used for oxide 230a. At this time, the dominant carrier pathway is oxide 230b.

[0222] Here, at the junction of oxides 230a, 230b, and 230c, the conduction band bottom changes gradually. In other words, the above situation can also be expressed as the conduction band bottom at the junction of oxides 230a, 230b, and 230c changing continuously or continuously joined. For this purpose, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxides 230a and 230b, and at the interface between oxides 230b and 230c.

[0223] Specifically, by including common elements as main components other than oxygen in oxides 230a and 230b, and in oxides 230b and 230c, a mixed layer with low defect state density can be formed. For example, when oxide 230b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, and gallium oxide can be used as oxides 230a and 230c.

[0224] Specifically, for oxide 230a, a metal oxide with an In:Ga:Zn ratio of 1:3:4 or 1:1:0.5 (atomic ratio) can be used. Furthermore, for oxide 230b, a metal oxide with an In:Ga:Zn ratio of 1:1:1 or 4:2:3 (atomic ratio) can be used. Furthermore, for oxide 230c, a metal oxide with an In:Ga:Zn ratio of 1:3:4, 4:2:3, 2:1, or 2:5 (atomic ratio) can be used.

[0225] Note that when metal oxides are formed by sputtering, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide, but can also refer to the atomic ratio of the sputtering target used in the formation of the metal oxide.

[0226] By equipping oxides 230a and 230c with the aforementioned structures, the defect state density at the interfaces between oxides 230a and 230b, and between oxides 230b and 230c, can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, resulting in transistor 200 exhibiting high on-state current and high frequency characteristics.

[0227] Alternatively, oxide 230c may have a stacked structure of two or more layers. For example, it may include a first oxide of oxide 230c and a second oxide of oxide 230c disposed on the first oxide of oxide 230c.

[0228] The first oxide of oxide 230c preferably contains at least one of the metal elements constituting the metal oxide for oxide 230b, and more preferably contains all of the aforementioned metal elements. For example, In-Ga-Zn oxide is preferably used as the first oxide of oxide 230c, and In-Ga-Zn oxide, Ga-Zn oxide, or gallium oxide is used as the second oxide of oxide 230c. This reduces the defect state density at the interface between oxide 230b and the first oxide of oxide 230c. Compared to the first oxide of oxide 230c, the second oxide of oxide 230c is preferably a metal oxide that can suppress oxygen diffusion or permeation. By providing the second oxide of oxide 230c between insulator 250 and the first oxide of oxide 230c, oxygen contained in insulator 280 can be prevented from diffusing to insulator 250. Therefore, oxygen can be readily supplied to oxide 230b through the first oxide of oxide 230c.

[0229] Preferably, the conduction band bottom of the second oxides of oxides 230a and 230c is closer to the vacuum level than the conduction band bottom of the first oxides of oxides 230b and 230c. In other words, the electron affinity of the second oxides of oxides 230a and 230c is preferably less than that of the first oxides of oxides 230b and 230c. In this case, the second oxide of oxide 230c is preferably a metal oxide that can be used for oxide 230a, and the first oxide of oxide 230c is preferably a metal oxide that can be used for oxide 230b. At this time, in addition to oxide 230b, the first oxide of oxide 230c sometimes also becomes the main pathway for charge carriers.

[0230] Specifically, the first oxide of oxide 230c can be a metal oxide with an In:Ga:Zn ratio of 4:2:3 (atomic ratio), and the second oxide can be a metal oxide or gallium oxide with an In:Ga:Zn ratio of 1:3:4 (atomic ratio), Ga:Zn ratio of 2:1 (atomic ratio), or Ga:Zn ratio of 2:5 (atomic ratio). This reduces the defect state density at the interface between the first and second oxides of oxide 230c.

[0231] Furthermore, when the atomic ratio of In to the main metal element in the metal oxide of the second oxide used in oxide 230c is less than the atomic ratio of In to the main metal element in the metal oxide of the first oxide used in oxide 230c, In diffusion to the insulator 250 side can be suppressed. Insulator 250 is used as a gate insulator, so when In mixes into insulator 250, it leads to poor transistor characteristics. Therefore, by employing a stacked structure in oxide 230c, a highly reliable semiconductor device can be provided.

[0232] As conductors 240a and 240b, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, and nitrides containing titanium and aluminum are preferably used. In one embodiment of the invention, nitrides containing tantalum are particularly preferred. Furthermore, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel may also be used, for example. These materials are preferred because they are conductive materials that are not easily oxidized or that maintain conductivity even after absorbing oxygen.

[0233] Insulator 250 is used as a gate insulator. Insulator 250 is preferably disposed in contact with at least a portion of oxide 230c. Insulator 250 may be silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with both carbon and nitrogen, porous silicon oxide, etc. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0234] Similar to insulator 224, insulator 250 is preferably formed using an insulator that releases oxygen upon heating. By providing an insulator that releases oxygen upon heating as insulator 250 in contact with at least a portion of oxide 230c, oxygen can be effectively supplied to the channel formation region of oxide 230b, thereby reducing oxygen vacancies in the channel formation region of oxide 230b. Therefore, a transistor with improved reliability can be provided while suppressing variations in electrical characteristics to achieve stable electrical characteristics. Furthermore, similar to insulator 224, it is preferable to reduce the concentration of impurities such as water and hydrogen in insulator 250. The thickness of insulator 250 is preferably 1 nm or more and 20 nm or less.

[0235] Alternatively, a metal oxide can be disposed between the insulator 250 and the conductor 260. This metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By disposing of a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 can be suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 caused by oxygen in the insulator 250 can be suppressed.

[0236] Furthermore, the aforementioned metal oxide is sometimes used as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, a metal oxide that is a high-k material with a high relative permittivity is preferably used as the aforementioned metal oxide. By making the gate insulator have a stacked structure of insulator 250 and the aforementioned metal oxide, a stacked structure with thermal stability and a high relative permittivity can be formed. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0237] Specifically, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used. In particular, insulators containing oxides of one or both of aluminum and hafnium are preferred.

[0238] Alternatively, the aforementioned metal oxide can also be used as part of the first gate electrode. For example, a metal oxide that can be used as oxide 230 can be used as the aforementioned metal oxide. In this case, by forming the conductor 260 using a sputtering method, the resistance value of the aforementioned metal oxide can be reduced, making it a conductor.

[0239] By incorporating the aforementioned metal oxide, the on-state current of transistor 200 can be increased without reducing the influence of the electric field from conductor 260. Furthermore, by maintaining the distance between conductor 260 and oxide 230 using the physical thickness of insulator 250 and the aforementioned metal oxide, leakage current between conductor 260 and oxide 230 can be suppressed. Additionally, by providing a stacked structure of insulator 250 and the aforementioned metal oxide, the physical distance between conductor 260 and oxide 230, as well as the electric field strength applied from conductor 260 to oxide 230, can be easily adjusted.

[0240] The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed in a manner that surrounds the bottom surface and side surface of the conductor 260b.

[0241] The conductor 260a preferably uses a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Furthermore, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

[0242] Furthermore, when the conductor 260a has the function of inhibiting oxygen diffusion, it can prevent the oxygen contained in the insulator 250 from oxidizing the conductor 260b and causing a decrease in conductivity. As a conductive material with the function of inhibiting oxygen diffusion, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc., are preferably used, for example.

[0243] Furthermore, since conductor 260 is also used for wiring, it is preferable to use a conductor with high conductivity. For example, conductor 260b can be a conductive material with tungsten, copper, or aluminum as the main components. Alternatively, conductor 260b can also adopt a laminated structure, such as a laminated structure of titanium or titanium nitride with the aforementioned conductive material.

[0244] Although Figure 1B and Figure 1C The intermediate conductor 260 has a two-layer structure of conductor 260a and conductor 260b, but it can also have a single-layer structure or a stacked structure of three or more layers.

[0245] Furthermore, in transistor 200, conductor 260 is formed in a self-aligned manner by filling the openings formed in insulator 280, etc. By forming conductor 260 in this way, conductor 260 can be reliably positioned in the region between conductor 240a and conductor 240b without alignment.

[0246] In addition, such as Figure 1B As shown, the top surface of the conductor 260 is roughly the same as the top surface of the insulator 250 and the top surface of the oxide 230c.

[0247] In addition, such as Figure 1C As shown, in the channel width direction of transistor 200, the bottom surface of conductor 260 in the region where conductor 260 does not overlap with oxide 230b is preferably lower than the bottom surface of oxide 230b. By employing a structure in which conductor 260, used as a gate electrode, covers the side and top surfaces of the channel formation region of oxide 230b via insulator 250 or the like, the electric field of conductor 260 can easily act on the entire channel formation region of oxide 230b. This increases the on-state current of transistor 200 and improves frequency characteristics. When the bottom surface of insulator 222 is used as a reference, and the difference between the height of the bottom surface of conductor 260 and the height of the bottom surface of oxide 230b in the region where oxide 230a and oxide 230b do not overlap with conductor 260 is denoted as T1, this T1 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0248] An insulator 280 is disposed on insulator 224, oxide 230, conductor 240a, and conductor 240b. Furthermore, the insulator 280 is disposed in such a way that it is in contact with at least the side surface of oxide 230. Additionally, the top surface of the insulator 280 may be planarized.

[0249] Preferably, the insulator 280 used as the interlayer film has a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between the wirings can be reduced. The insulator 280 is preferably formed, for example, using the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability. Especially, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are preferred because they readily form regions containing oxygen that has been released through heating.

[0250] The concentration of impurities such as water and hydrogen in insulator 280 is preferably reduced. Furthermore, it is preferable that insulator 280 has a low hydrogen concentration and includes or contains excess oxygen regions; for example, it can be formed using the same material as insulator 216. Additionally, insulator 280 may also have a multilayer structure with two or more layers.

[0251] Similar to insulator 214, insulator 282 is preferably used as an insulating barrier film to inhibit the diffusion of impurities such as water and hydrogen from above into insulator 280. Furthermore, similar to insulator 214, it is preferable that insulator 282 has a low hydrogen concentration and that it has the function of inhibiting hydrogen diffusion.

[0252] In addition, such as Figure 1B As shown, insulator 282 preferably contacts the top surfaces of conductor 260, insulator 250, and oxide 230c. Therefore, impurities such as hydrogen contained in insulator 284 can be suppressed from entering insulator 250. This suppresses negative impacts on the electrical characteristics and reliability of the transistor.

[0253] Preferably, an insulator 284, which serves as an interlayer film, is provided on insulator 282. Similar to insulator 216, insulator 284 preferably has a low dielectric constant. Similar to insulator 224, the concentration of impurities such as water and hydrogen in insulator 284 is preferably reduced.

[0254] Furthermore, although not illustrated, it is preferable to set its resistivity to 1.0 × 10⁻⁶ in a manner that covers the aforementioned conductor. 13 Ωcm or more and 1.0×10 15 Below Ωcm, preferably 5.0 × 10 13 Ωcm or more and 5.0×10 14An insulator with a resistivity of Ωcm or less. By providing an insulator with the above resistivity on the conductor, the insulator can not only maintain insulation, but also disperse the charge accumulated between the transistor 200 and the wiring of the conductor, thereby suppressing malfunctions or electrostatic damage to the transistor or electronic device having the transistor caused by the charge, and is therefore preferred.

[0255] <Materials Constituting Semiconductor Devices>

[0256] The following describes the constituent materials that can be used in semiconductor devices.

[0257] Substrate

[0258] For example, insulating substrates, semiconductor substrates, or conductive substrates can be used as substrates for forming the transistor 200. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium-stabilized zirconium oxide substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates can also be used, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples of insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators can also be used. Alternatively, substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements.

[0259] Insulators

[0260] As insulators, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, etc., which have insulating properties.

[0261] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, low voltage can be achieved during transistor operation while maintaining the physical thickness. On the other hand, by using a material with a relatively low permittivity as the insulator used as the interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulator.

[0262] In addition, examples of insulators with relatively high permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0263] In addition, examples of insulators with relatively low permittivity include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide or resin with pores.

[0264] Furthermore, by surrounding a transistor using metal oxides with an insulator (such as insulator 214, insulator 222, insulator 245a, insulator 245b, and insulator 282) that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator that suppresses the permeation of impurities such as hydrogen and oxygen, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used, either as a single layer or in a stack. Specifically, as an insulator that suppresses the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0265] Furthermore, the insulator used as the gate insulator is preferably an insulator having regions containing oxygen that has been removed by heating. For example, by employing a structure in which silicon oxide or silicon oxynitride having regions containing oxygen that has been removed by heating is contacted with oxide 230, oxygen vacancies contained in oxide 230 can be filled.

[0266] Conductors

[0267] As a conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even after absorbing oxygen, and are therefore preferred. Alternatively, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, and silicides such as nickel silicides can also be used.

[0268] Alternatively, multiple conductive layers formed from the above-described materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Alternatively, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Alternatively, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0269] Furthermore, when using oxides in the channel formation region of a transistor, a stacked structure combining a material containing the aforementioned metallic elements and an oxygen-containing conductive material is preferably used as the conductor serving as the gate electrode. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0270] In particular, as the conductor used as the gate electrode, a conductive material containing a metal element and oxygen contained in the metal oxide forming the channel is preferably used. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, nitrogen-containing conductive materials such as titanium nitride and tantalum nitride can also be used. Furthermore, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon can be used. Additionally, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Or, hydrogen entering from external insulators or the like can sometimes be trapped.

[0271] Metal Oxides

[0272] As oxide 230, a metal oxide (oxide semiconductor) that is used as a semiconductor is preferably used. Hereinafter, metal oxides that can be used in oxide 230 according to the present invention will be described.

[0273] The metal oxide preferably contains at least indium or zinc. It is particularly preferred to contain both indium and zinc. In addition, it preferably also contains aluminum, gallium, yttrium, tin, etc. Alternatively, it may contain one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.

[0274] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Note that element M can be aluminum, gallium, yttrium, or tin, etc. Other elements that can be used as element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that multiple of the above elements can sometimes be combined as element M.

[0275] Note that in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Furthermore, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0276] [Structure of metal oxides]

[0277] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0278] CAAC-OS exhibits c-axis orientation, with multiple nanocrystals linked along the ab-plane direction, resulting in a distorted crystal structure. Note that distortion refers to the portion of the lattice orientation that changes between regions with consistent lattice arrangement and other regions with consistent lattice arrangement within the region where multiple nanocrystals are linked.

[0279] Although nanocrystals are primarily hexagonal, they are not limited to regular hexagons and can be non-regular hexagonal. Furthermore, pentagonal, heptagonal, and other lattice arrangements sometimes exist in the distortion. Additionally, in CAAC-OS, clear grain boundaries are difficult to observe even near the distortion. That is, it can be seen that lattice distortion can suppress grain boundary formation. This is because CAAC-OS can accommodate distortion due to the low density of oxygen atoms along the ab plane or changes in interatomic bonding distance caused by the substitution of metal elements.

[0280] Furthermore, CAAC-OS tends to have a layered crystal structure (also called a layered structure) consisting of layers containing indium and oxygen (hereinafter referred to as In layers) and layers containing elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers). Additionally, indium and element M can substitute for each other; when element M in a (M, Zn) layer is replaced by indium, the layer can also be represented as an (In, M, Zn) layer. Similarly, when indium in an In layer is replaced by element M, the layer can also be represented as an (In, M) layer.

[0281] CAAC-OS is a highly crystalline metal oxide. Furthermore, distinct grain boundaries are not readily observed in CAAC-OS, thus reducing the likelihood of decreased electron mobility due to grain boundaries. Additionally, the crystallinity of metal oxides can sometimes decrease due to the introduction of impurities or the formation of defects; therefore, CAAC-OS can be considered a metal oxide with few impurities or defects (such as oxygen vacancies). Consequently, metal oxides containing CAAC-OS exhibit stable physical properties. Therefore, metal oxides containing CAAC-OS possess high heat resistance and high reliability.

[0282] In nc-OS, the atomic arrangement in tiny regions (e.g., regions above 1 nm and below 10 nm, particularly above 1 nm and below 3 nm) exhibits periodicity. Furthermore, no regularity in crystal orientation is observed between different nanocrystals in nc-OS. Therefore, no orientation is observed in the overall film. Thus, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods.

[0283] Furthermore, In-Ga-Zn oxide (hereinafter, IGZO), which is a metal oxide containing indium, gallium, and zinc, may have a stable structure when it is in the form of nanocrystals as described above. In particular, IGZO tends to not readily grow crystals in the atmosphere, so it may be structurally stable when IGZO is in the form of small crystals (e.g., the aforementioned nanocrystals) compared to when IGZO is in the form of large crystals (here, crystals a few mm or a few cm).

[0284] a-like OS is a metal oxide with a structure intermediate between nc-OS and amorphous oxide semiconductors. a-like OS contains voids or low-density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0285] Oxide semiconductors (metal oxides) have various structures and properties. One embodiment of the present invention may also include two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0286] [Impurities]

[0287] Here, we will explain the effects of various impurities in metal oxides.

[0288] When impurities are incorporated into oxide semiconductors, they sometimes form defect levels or oxygen vacancies. Therefore, when impurities are present in the channel formation region of an oxide semiconductor, the electrical characteristics of transistors using oxide semiconductors are prone to change, and sometimes their reliability decreases. Furthermore, when oxygen vacancies are present in the channel formation region, the transistor tends to exhibit always-on characteristics.

[0289] Furthermore, sometimes the aforementioned defect levels include trap levels. The charge trapped in a metal oxide trap level takes a long time to dissipate, sometimes acting like a fixed charge. Therefore, transistors containing metal oxides with high trap state densities in the channel formation region sometimes exhibit unstable electrical characteristics.

[0290] Furthermore, the presence of impurities in the channel formation region of an oxide semiconductor can sometimes reduce the crystallinity of the channel formation region. Additionally, the crystallinity of the oxide in contact with the channel formation region can sometimes decrease. When the crystallinity of the channel formation region is low, there is a tendency for the stability or reliability of the transistor to decrease. Moreover, when the crystallinity of the oxide in contact with the channel formation region is low, interfacial energy levels may sometimes form, leading to a decrease in the stability or reliability of the transistor.

[0291] Therefore, reducing the impurity concentration in and around the channel formation region of an oxide semiconductor is effective in improving the stability or reliability of transistors. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0292] Specifically, in and around the channel formation region of the oxide semiconductor, the concentration of the aforementioned impurities, as measured by SIMS, is 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 Alternatively, in the channel formation region and vicinity of the oxide semiconductor, the concentration of the aforementioned impurities, as measured by elemental analysis using energy dispersive X-ray spectroscopy (EDX), is 1.0 atomic% or less. Furthermore, when an oxide containing element M is used as the oxide semiconductor, the concentration ratio of the aforementioned impurities relative to element M in the channel formation region and vicinity of the oxide semiconductor is less than 0.10, preferably less than 0.05. Here, the concentration of element M used in calculating the aforementioned concentration ratio can be either the concentration in the same region where the impurity concentration is calculated, or the concentration in the oxide semiconductor itself.

[0293] In addition, metal oxides with reduced impurity concentrations have lower defect state densities, so the trap state density sometimes also becomes lower.

[0294] <Methods for Manufacturing Semiconductor Devices>

[0295] Next, refer to Figures 5A to 13D The instructions include Figures 1A to 1D The method for manufacturing a semiconductor device of transistor 200 according to one aspect of the present invention is shown.

[0296] Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A and Figure 13A A top view is shown. Additionally, Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B and Figure 13B They correspond to Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A and Figure 13A The cross-sectional view of the portion indicated by the dotted line A1-A2 in the diagram is also a cross-sectional view along the channel length of transistor 200. Additionally, Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C and Figure 13C They correspond to Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A and Figure 13A The cross-sectional view of the portion indicated by the dotted lines A3-A4 in the diagram is also a cross-sectional view of the channel width direction of transistor 200. Additionally, Figure 5D , Figure 6D , Figure 7D , Figure 8D , Figure 9D , Figure 10D , Figure 11D , Figure 12D and Figure 13D They correspond to Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12Aand Figure 13A The cross-sectional view of the area indicated by the dotted lines A5-A6 in the diagram is also a cross-sectional view of the channel width direction of transistor 200. Note that in Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A and Figure 13A In the top view, some of the constituent elements are omitted for clarity.

[0297] First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The insulator 214 can be formed using methods such as sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or atomic layer deposition (ALD).

[0298] Note that CVD methods can be categorized into plasma-enhanced CVD (PECVD), thermal CVD (TCVD), and photo-CVD. Furthermore, CVD methods can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0299] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because it does not use plasma, thermal CVD is a film formation method that does not cause plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes experience charge buildup due to receiving charge from plasma. This accumulated charge can sometimes damage the wiring, electrodes, and components in the semiconductor device. On the other hand, since thermal CVD, which does not use plasma, does not produce this plasma damage, the yield of semiconductor devices can be improved. Additionally, since thermal CVD does not generate plasma damage during film formation, films with fewer defects can be obtained.

[0300] Furthermore, the ALD method leverages the self-regulating nature of atoms to deposit atoms in each layer, resulting in advantages such as the ability to form extremely thin films, films with high aspect ratios, films with few defects like pinholes, films with excellent coverage, and films formed at low temperatures. In addition, the ALD method includes PEALD (Plasma Enhanced ALD), which utilizes plasma. By using plasma, film deposition can be performed at even lower temperatures, making it sometimes preferred. Note that the precursors used in the ALD method sometimes contain impurities such as carbon. Therefore, films formed using the ALD method sometimes contain more impurities such as carbon compared to films formed using other deposition methods. Furthermore, the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0301] Unlike film formation methods that deposit particles released from a target or similar material, CVD and ALD methods form films based on reactions on the surface of the workpiece. Therefore, films formed by CVD and ALD are less affected by the shape of the workpiece and exhibit good step coverage. In particular, films formed using ALD exhibit excellent step coverage and thickness uniformity, making ALD suitable for applications requiring coverage of surfaces with high aspect ratio openings. Note that ALD has a relatively slow film formation rate, so it is sometimes preferable to combine it with other film formation methods with faster rates, such as CVD.

[0302] CVD and ALD methods allow for control of the film composition by adjusting the source gas flow rate ratio. For example, when using CVD or ALD, films with arbitrary compositions can be formed by adjusting the source gas flow rate ratio. Furthermore, for instance, when using CVD and ALD, films with continuously varying compositions can be formed by changing the source gas flow rate ratio while forming the film. When forming a film while changing the source gas flow rate ratio, the time required for pressure adjustment and transmission is eliminated, thus shortening the film formation time compared to using multiple deposition chambers. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0303] In this embodiment, silicon nitride is formed as the insulator 214 using a sputtering method. The insulator 214 may also have a multilayer structure.

[0304] Next, an insulator 216 is formed on the insulator 214. The insulator 216 can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. In this embodiment, silicon oxynitride is formed as the insulator 216 using CVD.

[0305] Next, an opening leading to insulator 214 is formed in insulator 216. The opening may include, for example, a groove or a slit. Furthermore, the area where the opening is formed is sometimes referred to as the opening portion. Wet etching can be used to form this opening, but dry etching is preferred for microfabrication. As insulator 214, it is preferable to select an insulator that serves as an etch stop film when etching insulator 216 to form a groove. For example, when silicon oxynitride is used as insulator 216 for forming the groove, silicon nitride, aluminum oxide, or hafnium oxide are preferably used as insulator 214.

[0306] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel planar electrodes can be used. The CCP etching apparatus including parallel planar electrodes can also employ a structure in which a high-frequency voltage is applied to one of the parallel planar electrodes. Alternatively, a structure in which multiple different high-frequency voltages are applied to one of the parallel planar electrodes can be used. Alternatively, a structure in which high-frequency voltages of the same frequency are applied to each of the parallel planar electrodes can be used. Alternatively, a structure in which high-frequency voltages of different frequencies are applied to each of the parallel planar electrodes can be used. Alternatively, a dry etching apparatus having a high-density plasma source can also be used. For example, as a dry etching apparatus having a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus can be used.

[0307] After the opening is formed, a conductive film is formed, which will become the first conductor 205. This conductive film preferably contains a conductor that inhibits oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc., can be used. Alternatively, a laminated film of a conductor that inhibits oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. This conductive film can be formed using sputtering, CVD, MBE, PLD, ALD, etc.

[0308] In this embodiment, the conductive film that will serve as the first conductor of the conductor 205 is a tantalum nitride film formed by sputtering or a film formed by laminating titanium nitride on tantalum nitride. By using this metal nitride as the first conductor of the conductor 205, even if a metal that easily diffuses, such as copper, is used as the second conductor of the conductor 205 (described later), the diffusion of this metal from the first conductor of the conductor 205 to the outside can be suppressed.

[0309] Next, a second conductive film, which will also become a conductor 205, is formed on the conductive film that will become the first conductor 205. This conductive film can be formed using methods such as plating, sputtering, CVD, MBE, PLD, and ALD. In this embodiment, a tungsten film is formed as this conductive film.

[0310] Next, by performing CMP (Chemical Mechanical Polishing), the conductive film that will become the first conductor of conductor 205 and a portion of the conductive film that will become the second conductor of conductor 205 are removed, exposing the insulator 216. As a result, only the conductive film that will become the first conductor of conductor 205 and the conductive film that will become the second conductor of conductor 205 remain at the opening. Thus, a conductor 205 comprising the first conductor of conductor 205 and the second conductor of conductor 205, with a flat top surface, can be formed (see reference). Figures 5A to 5C ).

[0311] Alternatively, after forming the conductor 205, the following steps can be performed: removing a portion of the second conductor of the conductor 205, forming a trench in the second conductor of the conductor 205, forming a conductive film on the conductor 205 and the insulator 216 by filling the trench, and performing CMP treatment. This CMP treatment removes a portion of the conductive film, exposing the insulator 216. It is preferable to use a dry etching method or similar technique to remove the portion of the second conductor of the conductor 205.

[0312] Through the above-described process, a conductor 205 comprising the aforementioned conductive film with a flat top surface can be formed. By improving the flatness of the top surfaces of the insulator 216 and the conductor 205, the crystallinity of oxides 230a, 230b, and 230c can be improved. The same material as the first conductor or the second conductor of the conductor 205 can be used as the conductive film.

[0313] The following will describe a method for forming the conductor 205 that differs from the above.

[0314] A conductive film, which will become a conductor 205, is formed on the insulator 214. The conductive film can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. Furthermore, the conductive film can be a multilayer film. For example, a tungsten film can be formed as the conductive film.

[0315] Next, the conductive film that will become the conductor 205 is processed using photolithography to form the conductor 205.

[0316] In photolithography, a photoresist is first exposed through a mask. Then, a developer is used to remove or leave the exposed areas, forming a photoresist mask. Next, etching is performed through this photoresist mask to process conductors, semiconductors, insulators, etc., into the desired shape. For example, a photoresist mask can be formed by exposing the photoresist with KrF stimulated excimer laser, ArF stimulated excimer laser, or EUV (Extreme Ultraviolet) light. Alternatively, immersion lithography can be used, where exposure is performed with liquid (e.g., water) filling the space between the substrate and the projection lens. Electron beams or ion beams can also be used instead of the aforementioned light. Note that a mask is not required when using electron or ion beams. Furthermore, when removing the photoresist mask, dry etching (such as ashing) or wet etching can be performed, or wet etching can be performed after dry etching, or dry etching can be performed after wet etching.

[0317] Alternatively, a hard mask made of an insulator or conductor can be used instead of a photoresist mask. When using a hard mask, an insulating or conductive film that will become the hard mask material can be formed on the conductive film that will become the conductor 205, and a photoresist mask can be formed on it. Then, the hard mask material can be etched to form a hard mask of the desired shape. The etching of the conductive film that will become the conductor 205 can be performed either after removing the photoresist mask or without removing it. In the latter case, the photoresist mask may sometimes disappear during etching. Alternatively, the hard mask can be removed by etching after etching the conductive film that will become the conductor 205. On the other hand, it is not necessary to remove the hard mask if the hard mask material does not affect subsequent processes or can be used in subsequent processes.

[0318] Next, an insulating film, which will become insulator 216, is formed on insulator 214 and conductor 205. This insulating film is formed in contact with the top and side surfaces of conductor 205. The insulating film can be formed using sputtering, CVD, MBE, PLD, ALD, or similar methods.

[0319] Here, the thickness of the insulating film that will become the insulator 216 is preferably greater than or equal to the thickness of the conductor 205. For example, when the thickness of the conductor 205 is 1, the thickness of the insulating film that will become the insulator 216 is 1 or more and 3 or less.

[0320] Next, a portion of the insulating film, which will become the insulator 216, is removed by CMP treatment, exposing the surface of the conductor 205. Thus, a conductor 205 and an insulator 216 with flat top surfaces can be formed. This is another method for forming the conductor 205.

[0321] Next, an insulator 222 is formed on the insulator 216 and the conductor 205. The insulator 222 can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. In this embodiment, hafnium oxide or aluminum oxide is formed as the insulator 222 using the ALD method.

[0322] Next, a heat treatment is preferably performed. The heat treatment is performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the removed oxygen, heat treatment can be performed in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas.

[0323] In this embodiment, as a heat treatment, after the insulator 222 is formed, it is treated at 400°C for 1 hour in a nitrogen atmosphere, followed by continuous treatment at 400°C for 1 hour in an oxygen atmosphere. By performing this heat treatment, impurities such as water and hydrogen contained in the insulator 222 can be removed. Alternatively, the heat treatment can be performed after the insulator 224 is formed, or at other times.

[0324] Next, an insulator 224 is formed on the insulator 222. The insulator 224 can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. In this embodiment, silicon oxynitride is formed as the insulator 224 using CVD.

[0325] To create an excess oxygen region in the insulator 224, an oxygen-containing plasma treatment can be performed under reduced pressure. The oxygen-containing plasma treatment preferably employs a device including a power supply for generating a high-density plasma using microwaves. Alternatively, a power supply applying RF to one side of the substrate may be included. High-density oxygen radicals can be generated using the high-density plasma, and by applying RF to one side of the substrate, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the insulator 224. Alternatively, an oxygen-containing plasma treatment can be performed after a plasma treatment containing an inert gas using such a device to replenish the detached oxygen. Furthermore, by appropriately selecting the conditions of this plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In this case, heating treatment may not be necessary.

[0326] Here, an aluminum oxide film can be formed on the insulator 224, for example, by sputtering, and the aluminum oxide can be subjected to CMP treatment until it reaches the insulator 224. This CMP treatment can planarize and smooth the surface of the insulator 224. By placing the aluminum oxide on the insulator 224 and performing CMP treatment, the endpoint of the CMP treatment can be easily detected. Furthermore, sometimes the thickness of the insulator 224 may become thinner due to polishing of a portion of the insulator 224 through CMP treatment, but this can be corrected by adjusting the thickness during film formation on the insulator 224. Planarizing and smoothing the surface of the insulator 224 can sometimes prevent a decrease in the coverage of the oxide film to be formed underneath and prevent a decrease in the yield of the semiconductor device. Furthermore, it is preferable to add oxygen to the insulator 224 by sputtering an aluminum oxide film on the insulator 224.

[0327] Next, oxide films 230A and 230B are sequentially formed on insulator 224 (refer to...). Figures 5B to 5D Preferably, oxide films 230A and 230B are formed continuously without exposure to the atmospheric environment. By forming the oxide films without exposure to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to oxide films 230A and 230B, thus keeping the area near the interface between oxide films 230A and 230B clean.

[0328] Oxide film 230A and oxide film 230B can be formed by sputtering, CVD, MBE, PLD, ALD and other methods.

[0329] For example, when forming oxide films 230A and 230B using sputtering, oxygen or a mixture of oxygen and rare gases is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the formed oxide film can be increased. Furthermore, when forming the aforementioned oxide films using sputtering, the aforementioned In-M-Zn oxide target can be used, for example.

[0330] In particular, during the formation of the oxide film 230A, a portion of the oxygen contained in the sputtering gas is sometimes supplied to the insulator 224. Therefore, the oxygen content in the sputtering gas can be 70% or more, preferably 80% or more, and more preferably 100%.

[0331] When forming the oxide film 230B using sputtering, an oxygen-excess oxide semiconductor can be formed by forming the film under conditions where the oxygen content in the sputtering gas is more than 30% and less than 100%, preferably more than 70% and less than 100%. Transistors using oxygen-excess oxide semiconductors in the channel formation region can have high reliability. However, the invention is not limited to this. When forming the oxide film 230B using sputtering, an oxygen-deficient oxide semiconductor is formed when the film is formed under conditions where the oxygen content in the sputtering gas is set to more than 1% and less than 30%, preferably more than 5% and less than 20%. Transistors using oxygen-deficient oxide semiconductors in the channel formation region can have high field-effect mobility. Furthermore, by forming the film while heating the substrate, the crystallinity of the oxide film can be improved.

[0332] In this embodiment, an oxide film 230A is formed using an In-Ga-Zn oxide target with an In:Ga:Zn ratio of 1:3:4 (atomic ratio) via sputtering. Additionally, an oxide film 230B is formed using an In-Ga-Zn oxide target with an In:Ga:Zn ratio of 4:2:4.1 (atomic ratio) via sputtering. The deposition conditions and atomic ratios for each oxide film can be appropriately selected based on the desired characteristics of the oxide 230.

[0333] Here, it is preferable to form insulator 222, insulator 224, oxide film 230A, and oxide film 230B in a manner that does not expose them to the atmosphere. For example, a multi-chamber film-forming apparatus is preferred.

[0334] Next, a heat treatment can be performed. This heat treatment can be performed under the conditions described above. By performing this heat treatment, impurities such as water and hydrogen in the oxide films 230A and 230B can be removed. In this embodiment, the treatment is performed at 400°C for 1 hour under a nitrogen atmosphere, followed by a continuous treatment at 400°C for 1 hour under an oxygen atmosphere.

[0335] Next, a conductive film 240A is formed on the oxide film 230B. The conductive film 240A can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD (see reference). Figures 5B to 5D Alternatively, a heat treatment can be performed before forming the conductive film 240A. This heat treatment can be performed under reduced pressure, and the conductive film 240A can be formed continuously without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of the oxide film 230B can be removed, and the moisture and hydrogen concentrations in the oxide films 230A and 230B can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower. In this embodiment, the heat treatment temperature is 200°C.

[0336] Next, an insulating film 245A (see reference) is formed to serve as a barrier layer. Figures 5B to 5D ).

[0337] For example, as the insulating film 245A, it is preferable to form an alumina film by the ALD method. By using the ALD method, a dense film with few defects such as cracks or pinholes or with a uniform thickness can be formed.

[0338] Next, a film 290A, which will become a hard mask, is formed on the insulating film 245A (see reference). Figures 5B to 5D For example, the film 290A, which will become a hard mask, is preferably formed by sputtering a tungsten film or a tantalum nitride film.

[0339] Next, a resist mask 292 is formed on the film 290A, which will become a hard mask, using photolithography (see reference). Figures 5A to 5D Hard mask 290B and insulating layer 245B are formed by selectively removing part of film 290A and insulating film 245A, which will become hard mask, using resist mask 292 (see reference). Figures 6A to 6D ).

[0340] Next, an island-shaped conductive layer 240B is formed by selectively removing a portion of the conductive film 240A using a hard mask 290B and an insulating layer 245B (see reference). Figures 7A to 7D Note that at this point, you can also remove part or all of the hard mask 290B.

[0341] Next, a portion of oxide films 230A and 230B is selectively removed using island conductive layer 240B, insulating layer 245B, and hard mask 290B as masks. Note that in this process, sometimes a portion of insulator 224 is also removed simultaneously. Then, by removing hard mask 290B, a stacked structure of island oxides 230a, 230b, island conductive layer 240B, and island insulating layer 245B can be formed (see reference). Figures 8A to 8D ).

[0342] Here, the side surfaces of oxide 230b and conductive layer 240B are preferably substantially perpendicular to the top surface of insulator 224. Specifically, Figure 1D The angle θ shown is 60° or more and 95° or less, preferably 88° or more and 92° or less. When the side surfaces of the oxide 230b and the conductive layer 240B are substantially perpendicular to the top surface of the insulator 224, a smaller area and higher density can be achieved when multiple transistors 200 are provided. In addition, by adopting the above-described shape, the contact area with the wiring layer subsequently formed by the conductive layer 240B can be increased. Therefore, the increase in contact resistance between the conductive layer 240B and the wiring layer can be suppressed.

[0343] Furthermore, in this process, by using a hard mask 290B to process the conductive film 240A, unnecessary etching (also known as CD loss) in the shape of the conductors 240a and 240b can be suppressed.

[0344] For example, when using a photoresist mask, during etching, sometimes the sides of the mask are etched, resulting in the end surfaces of the workpiece being exposed and the corners becoming rounded. When this defect is large in conductors 240a and 240b, sometimes the volume of conductors 240a and 240b is smaller than the design value, resulting in a smaller on-state current.

[0345] Therefore, by using a material with a high selectivity for the etching rate relative to the hard mask as the workpiece, the shape of the hard mask can be maintained during etching and shape defects of the workpiece can be suppressed. Specifically, the material used as the mask is preferably one in which the etching rate of the material used for the hard mask is 1, and the etching rate of the workpiece is 5 or more, preferably 10 or more.

[0346] Next, an insulating film, which will become the insulator 280, is formed on the stacked structure of island oxide 230a, island oxide 230b, island conductive layer 240B, and island insulating layer 245B. This insulating film can be formed using sputtering, CVD, MBE, PLD, or ALD methods. In this embodiment, a silicon oxide film is formed using CVD or sputtering as the insulating film. Alternatively, a heat treatment can be performed before forming the insulating film. This heat treatment can also be performed under reduced pressure to continuously form the insulating film without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of the insulator 224 can be removed, and the moisture and hydrogen concentrations in oxide 230a, oxide 230b, and the insulator 224 can be reduced. The above-described heat treatment conditions can be used.

[0347] Furthermore, the insulating film that will become the insulator 280 can have a multilayer structure. For example, a silicon oxide film can be formed by sputtering, and a silicon oxide film can be formed on the silicon oxide film by CVD.

[0348] Next, the insulating film that will become insulator 280 is subjected to CMP treatment to form insulator 280 with a flat top surface (see reference). Figures 8B to 8D ).

[0349] Next, a portion of the insulator 280, a portion of the insulating layer 245B, and a portion of the conductive layer 240B are processed to form an opening reaching the oxide 230b. This opening is preferably formed in a manner that overlaps with the conductor 205. By forming this opening, conductors 240a and 240b, insulators 245a and 245b are formed. At this time, sometimes the thickness of the region of oxide 230b overlapping the opening becomes thinner (see reference). Figures 9A to 9C ).

[0350] Furthermore, a portion of the insulator 280, a portion of the insulating layer 245B, and a portion of the conductive layer 240B can be processed under different conditions. For example, a portion of the insulator 280 can be processed by dry etching, a portion of the insulating layer 245B can be processed by wet etching, and a portion of the conductive layer 240B can be processed by dry etching.

[0351] Here, it is preferable to remove impurities adhering to the surface of oxides 230a, oxides 230b, etc., or those diffused into their interior. Examples of such impurities include components contained in the insulator 280, insulating layer 245B, and conductive layer 240B; components contained in the components used in the apparatus for forming the aforementioned opening; components contained in the gas or liquid used for etching; etc. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0352] To remove the aforementioned impurities, washing treatment can also be performed. Washing methods include wet washing using a washing liquid, plasma treatment using plasma, and washing using heat treatment; combinations of these methods are also possible.

[0353] As a wet washing process, washing can be performed using aqueous solutions of ammonia, oxalic acid, phosphoric acid, or hydrofluoric acid diluted with carbonated water or pure water, or pure water or carbonated water. Alternatively, ultrasonic washing can be performed using these aqueous solutions, pure water, or carbonated water. Furthermore, a combination of the above washing methods can be appropriately combined.

[0354] Next, a heat treatment may be performed. This heat treatment is preferably carried out in an oxygen-containing atmosphere. Alternatively, the heat treatment may be carried out under reduced pressure, wherein an oxide film is continuously formed at 230°C (refer to) without exposure to the atmosphere. Figures 10A to 10D This treatment removes moisture and hydrogen adhering to the surface of oxide 230b, and reduces the moisture and hydrogen concentrations in oxides 230a and 230b. The heat treatment temperature is preferably 100°C or higher and 400°C or lower. In this embodiment, the heat treatment temperature is 200°C.

[0355] The oxide film 230C can be formed using sputtering, CVD, MBE, PLD, ALD, and other methods. Depending on the desired properties of the oxide 230C, the oxide film 230C can be formed using the same film formation method as oxide film 230A or oxide film 230B. In this embodiment, the oxide film 230C is formed using an In-Ga-Zn oxide target with an In:Ga:Zn ratio of 1:3:4 or 4:2:4.1 (atomic ratio) via sputtering. Alternatively, as the oxide film 230C, an In-Ga-Zn oxide target with an In:Ga:Zn ratio of 4:2:4.1 (atomic ratio) is used to form a film via sputtering, and an In-Ga-Zn oxide target with an In:Ga:Zn ratio of 1:3:4 (atomic ratio) is used to form a film thereon.

[0356] In particular, during the formation of oxide film 230C, a portion of the oxygen contained in the sputtering gas is sometimes supplied to oxides 230a and 230b. Therefore, the oxygen content in the sputtering gas of oxide film 230C can be 70% or more, preferably 80% or more, and more preferably 100%.

[0357] Next, a heat treatment may be performed. This heat treatment can also be carried out under reduced pressure, during which an insulating film 250A is continuously formed without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of the oxide film 230C can be removed, and the moisture and hydrogen concentrations in the oxides 230a, 230b, and oxide film 230C are reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower.

[0358] The insulating film 250A can be formed using sputtering, CVD, MBE, PLD, ALD, etc. (see reference) Figures 10A to 10D In this embodiment, a silicon oxynitride film is formed using CVD as the insulating film 250A. The film-forming temperature for forming the insulating film 250A is preferably 350°C or higher and lower than 450°C, and particularly preferably around 400°C. By forming the insulating film 250A at a temperature of 400°C, an insulating film with fewer impurities can be formed.

[0359] Alternatively, microwave treatment can be performed under reduced pressure in an oxygen-containing atmosphere after the formation of the insulating film 250A (see [reference]). Figure 11B and Figure 11D By performing microwave treatment, the electric field generated by microwave 291 is applied to insulating film 250A, oxide 230a, oxide 230b, and oxide film 230C, thereby increasing the Vo in oxide 230a, oxide 230b, and oxide film 230C. O H separated into V OWith hydrogen. At this time, some of the separated hydrogen sometimes bonds with oxygen and is removed as H₂O from insulating film 250A, oxide 230a, oxide 230b, and oxide film 230C. Additionally, some hydrogen is sometimes doped by conductors 240a and 240b. Thus, by performing microwave treatment, the hydrogen concentration in insulating film 250A, oxide 230a, oxide 230b, and oxide film 230C can be reduced. Furthermore, by reducing the V in oxide 230a, oxide 230b, and oxide film 230C... O H separated into V O V produced after reacting with hydrogen O Supplying oxygen can repair or replenish V O .

[0360] Alternatively, heating treatment can be performed while maintaining a reduced pressure after microwave treatment. This treatment efficiently removes hydrogen from the insulating film 250A, oxide 230a, oxide 230b, and oxide film 230C. Additionally, some hydrogen may be attracted by the conductors 240a and 240b. Furthermore, the step of performing heating treatment while maintaining a reduced pressure after microwave treatment can be repeated. Repeated heating treatment further efficiently removes hydrogen from the insulating film 250A, oxide 230a, oxide 230b, and oxide film 230C. Note that the heating treatment temperature is preferably 300°C or higher and 500°C or lower.

[0361] Furthermore, by altering the quality of the insulating film 250A through microwave processing, the diffusion of hydrogen, water, impurities, etc., can be suppressed. This prevents the diffusion of hydrogen, water, impurities, etc., through the insulator 250 to the oxide 230 due to subsequent processes such as film formation or heat treatment, which will become the conductor 260. Note that the structure of the microwave processing apparatus will be described later.

[0362] Next, conductive films 260A and 260B are formed sequentially. Conductive films 260A and 260B can be formed using sputtering, CVD, MBE, PLD, ALD, or similar methods. In this embodiment, conductive film 260A is formed using the ALD method, and conductive film 260B is formed using the CVD method (see reference). Figures 12A to 12D ).

[0363] Next, the oxide film 230C, insulating film 250A, conductive film 260A, and conductive film 260B are polished using CMP treatment until the insulator 280 is exposed, forming oxide 230c, insulator 250, and conductor 260 (conductor 260a and conductor 260b) (see reference). Figures 13A to 13CTherefore, oxide 230c is disposed in such a way that it covers the inner wall (side wall and bottom surface) of the opening reaching oxide 230b. Insulator 250 is disposed in such a way that it covers the inner wall of the opening, separated by oxide 230c. In addition, conductor 260 is disposed in such a way that it fills the opening, separated by oxide 230c and insulator 250.

[0364] Next, heat treatment can also be performed. In this embodiment, the treatment is carried out at 400°C for 1 hour under a nitrogen atmosphere. This heat treatment can reduce the moisture concentration and hydrogen concentration in insulators 250 and 280.

[0365] Next, an insulator 282 is formed on oxide 230c, insulator 250, conductor 260, and insulator 280. The insulator 282 can be formed using sputtering, CVD, MBE, PLD, ALD, or similar methods. For example, aluminum oxide or silicon nitride is preferably formed by sputtering as the insulator 282. By forming aluminum oxide or silicon nitride using sputtering, the diffusion of hydrogen contained in the insulator 284 into the oxide 230 can be suppressed. Furthermore, forming the insulator 282 in contact with the conductor 260 can suppress the oxidation of the conductor 260, which is therefore preferred.

[0366] Furthermore, oxygen can be supplied to insulator 280 by sputtering alumina as insulator 282. The oxygen supplied to insulator 280 is sometimes supplied to the channel-forming region of oxide 230b via oxide 230c. Additionally, when oxygen is supplied to insulator 280, the oxygen contained in insulator 280 before the formation of insulator 282 is sometimes supplied to the channel-forming region of oxide 230b via oxide 230c.

[0367] Insulator 282 can also have a multilayer structure. For example, it can be formed by sputtering aluminum oxide and then by sputtering silicon nitride on the aluminum oxide.

[0368] Next, a heat treatment can be performed. This heat treatment can be performed under the conditions described above. This heat treatment can reduce the moisture and hydrogen concentrations in the insulator 280. Furthermore, oxygen contained in the insulator 282 can be injected into the insulator 280.

[0369] Alternatively, before forming the insulator 282, the following steps can be performed: First, an alumina film is formed on the insulator 280 or the like using a sputtering method; then, heat treatment is performed using the aforementioned heat treatment conditions; and finally, the alumina film is removed by CMP treatment. This process allows for the formation of more excess oxygen regions in the insulator 280. Note that in this process, sometimes a portion of the insulator 280, a portion of the conductor 260, a portion of the insulator 250, and a portion of the oxide 230c are removed.

[0370] Alternatively, an insulator can be provided between insulator 280 and insulator 282. For example, silicon oxide formed by sputtering can be used as this insulator. By providing this insulator, an excess oxygen region can be formed in insulator 280.

[0371] Next, insulator 284 can also be formed on insulator 282. Insulator 284 can be formed using sputtering, CVD, MBE, PLD, ALD, etc. (see reference) Figures 1B to 1D ).

[0372] Through the above processes, it is possible to manufacture including Figures 1A to 1D The semiconductor device shown is transistor 200.

[0373] Alternatively, an opening can be formed around the transistor 200 after its formation, and an insulator with high barrier properties against hydrogen or water can be formed around this opening. By enclosing the transistor 200 with this high barrier property insulator, moisture and hydrogen can be prevented from entering from the outside. Alternatively, multiple transistors 200 can be enclosed by an insulator with high barrier properties against hydrogen or water. Furthermore, when an opening is formed around the transistor 200, for example, when forming an opening that reaches insulator 214 or insulator 222 and contacting insulator 214 or insulator 222 to form the high barrier property insulator, this can also be part of the manufacturing process of the transistor 200, and is therefore preferred. In addition, the same material as insulator 222 can be used as the insulator with high barrier properties against hydrogen or water.

[0374] According to one aspect of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high on-state current can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0375] <Examples of variations of semiconductor devices>

[0376] The following reference Figures 14A to 15D This description includes an example of a semiconductor device comprising a transistor 200 according to one aspect of the present invention.

[0377] Here, Figure 14A and Figure 15A A top view is shown. Additionally, Figure 14B and Figure 15B They correspond to Figure 14A and Figure 15A The cross-sectional view of the area indicated by the dotted lines A1-A2. Additionally, Figure 14C and Figure 15C They correspond to Figure 14A and Figure 15A The cross-sectional view of the portion indicated by the dotted lines in A3-A4 format. Additionally, Figure 14D and Figure 15D They correspond to Figure 14A and Figure 15A The cross-sectional view of the portion indicated by the dashed lines in A5-A6 format. Figure 14A and Figure 15A In the top view, some of the constituent elements are omitted for clarity.

[0378] Note that in Figures 14A to 15D In the semiconductor device shown, the same reference numerals are used for components that have the same function as those in the semiconductor device shown in the <Structure Examples of Semiconductor Devices>. Note that the materials used as constituent materials of the semiconductor device in this section may be the materials described in detail in the <Structure Examples of Semiconductor Devices>.

[0379] [Example 1 of a variation of a semiconductor device]

[0380] Figures 14A to 14D The semiconductor device shown is Figures 1A to 1D The semiconductor device shown differs in that: insulators 245a and 245b are not provided; and insulator 254 is provided in such a way that it contacts the top and side surfaces of conductor 240a, the top and side surfaces of conductor 240b, the side surface of oxide 230b, the side surface of oxide 230a, and the top surface of insulator 224.

[0381] Insulator 254 preferably has the function of suppressing the diffusion of one or both of hydrogen and oxygen. For example, compared with insulator 224 and insulator 280, insulator 254 preferably has the function of suppressing the diffusion of one or both of hydrogen and oxygen. Thus, the diffusion of hydrogen contained in insulator 280 to oxides 230a and 230b can be suppressed. Furthermore, by surrounding insulator 224, oxide 230, etc., with insulator 254, the diffusion of impurities such as water and hydrogen from the outside into insulator 224 and oxide 230 can be suppressed. Therefore, transistor 200 can have good electrical characteristics and reliability.

[0382] The insulator 254 is preferably formed by sputtering. By forming the insulator 254 using sputtering in an oxygen-containing atmosphere, oxygen can be added to the vicinity of the region in contact with the insulator 254 in the insulator 224. Oxygen can then be supplied from this region to the oxide 230 through the insulator 224. Here, by making the insulator 254 have the function of suppressing oxygen diffusion upwards, oxygen diffusion from the oxide 230 to the insulator 280 can be prevented. Furthermore, by making the insulator 222 have the function of suppressing oxygen diffusion downwards, oxygen diffusion from the oxide 230 to the substrate side can be prevented. Thus, oxygen is supplied to the channel formation region of the oxide 230. This reduces oxygen vacancies in the oxide 230 and suppresses the constant-on state of the transistor.

[0383] As the insulator 254, an insulator comprising oxides of one or both of aluminum and hafnium can be formed, for example. In this case, it is preferable to form the insulator 254 using the ALD method. Because the ALD method is a film-forming method with good coverage, it can prevent breakage caused by unevenness of the insulator 254.

[0384] Furthermore, an insulator containing aluminum nitride, for example, can be used as the insulator 254. Therefore, a film with high insulation and high thermal conductivity can be formed, thereby improving the heat dissipation generated when driving the transistor 200. Alternatively, silicon nitride or silicon oxynitride can also be used.

[0385] Alternatively, gallium-containing oxides can be used as insulators 254, for example. Gallium-containing oxides are preferred because they sometimes have the function of suppressing the diffusion of one or both of hydrogen and oxygen. Gallium oxide, zinc gallium oxide, indium gallium zinc oxide, etc., can be used as gallium-containing oxides. When indium gallium zinc oxide is used as insulator 254, a large ratio of gallium atoms to indium is preferred. Increasing this ratio improves the insulating properties of the oxide.

[0386] [Example 2 of a variation of a semiconductor device]

[0387] Figures 15A to 15D The semiconductor device shown is Figures 14A to 14DThe semiconductor device shown differs in that: there is no oxide 230c; and the insulator 254 has a stacked structure with insulators 254a and 254b.

[0388] When the insulator 254 has a two-layer laminated structure, the methods described above can be used to form insulators 254a and 254b. Furthermore, the same or different methods can be used to form insulators 254a and 254b. For example, insulator 254a can be formed by sputtering in an oxygen-containing atmosphere, and then insulator 254b can be formed using the ALD method. Because the ALD method is a film-forming method with good coverage, it can prevent breakage due to unevenness in the first layer.

[0389] Furthermore, the aforementioned materials can be used as insulators 254a and 254b, and the materials of insulators 254a and 254b can be the same or different. For example, a laminated structure of silicon oxide, silicon oxynitride, silicon oxynitride, or silicon nitride with an insulator that has the function of suppressing impurities such as hydrogen and oxygen permeation can be used. As an insulator with the function of suppressing impurities such as hydrogen and oxygen permeation, for example, an insulator containing an oxide of one or both of aluminum and hafnium can be used.

[0390] Therefore, a semiconductor device with high reliability can be provided. Furthermore, a semiconductor device with good electrical characteristics can be provided. Furthermore, a semiconductor device capable of miniaturization or high integration can be provided. Furthermore, a semiconductor device with low power consumption can be provided.

[0391] Microwave Processing Device

[0392] The microwave processing apparatus according to one aspect of the present invention will now be described.

[0393] First, refer to Figures 16 to 18 The structure of a manufacturing apparatus with fewer impurities introduced during the manufacture of semiconductor devices is described.

[0394] Figure 16A schematic top view of a monolithic multi-chamber manufacturing apparatus 2700 is shown. The manufacturing apparatus 2700 includes: an atmospheric-side substrate supply chamber 2701 equipped with a cassette port 2761 for receiving substrates and an alignment port 2762 for aligning substrates; an atmospheric-side substrate transfer chamber 2702 for transferring substrates from the atmospheric-side substrate supply chamber 2701; a loading lock chamber 2703a for loading substrates and switching the pressure inside the chamber from atmospheric pressure to depressurization or from depressurization to atmospheric pressure; an unloading lock chamber 2703b for unloading substrates and switching the pressure inside the chamber from depressurization to atmospheric pressure or from atmospheric pressure to depressurization; a transfer chamber 2704 for transferring substrates in a vacuum; and processing chambers 2706a, 2706b, 2706c, and 2706d.

[0395] In addition, the atmospheric side substrate transfer chamber 2702 is connected to the loading lock chamber 2703a and the unloading lock chamber 2703b, the loading lock chamber 2703a and the unloading lock chamber 2703b are connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the processing chambers 2706a, 2706b, 2706c and 2706d.

[0396] A gate valve GV is provided at the connection between the chambers, thereby allowing each chamber, except for the atmospheric substrate supply chamber 2701 and the atmospheric substrate transfer chamber 2702, to be independently maintained in a vacuum state. A transfer robot 2763a is provided in the atmospheric substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. The substrate can be transferred in the manufacturing apparatus 2700 using the transfer robots 2763a and 2763b.

[0397] The back pressure (total pressure) of transfer chamber 2704 and each processing chamber is, for example, 1×10⁻⁶. -4 Pa or less, preferably 3×10 Pa -5 Pa or less, more preferably 1×10 Pa -5 Below Pa. The mass-to-charge ratio (m / z) of the transfer chamber 2704 and each processing chamber is 18, and the partial pressure of gas molecules (atoms) is, for example, 3 × 10⁻⁸. -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 Pa -6 Below Pa. Furthermore, the partial pressure of gas molecules (atoms) with an m / z of 28 in the transfer chamber 2704 and each processing chamber is, for example, 3 × 10⁻⁸. -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 Pa -6Below Pa. The partial pressure of gas molecules (atoms) at m / z 44 in the transfer chamber 2704 and each processing chamber is, for example, 3 × 10⁴. -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 Pa -6 Below Pa.

[0398] The total and partial pressures in transfer chamber 2704 and each processing chamber can be measured using a mass analyzer. For example, a four-pole mass analyzer (also known as a Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. can be used.

[0399] Furthermore, the transfer chamber 2704 and each processing chamber preferably have a structure with minimal external or internal leakage. For example, the leakage rate of the transfer chamber 2704 and each processing chamber is set to 3 × 10⁻⁶. -6 Pa·m 3 For speeds below / s, a setting of 1×10 is preferred. -6 Pa·m 3 / s or less. Furthermore, for example, the leakage rate of gas molecules (atoms) with m / z of 18 is set to 1 × 10⁻⁶. -7 Pa·m 3 For speeds below / s, a setting of 3×10 is preferred. -8 Pa·m 3 / s or less. Furthermore, for example, the leakage rate of gas molecules (atoms) with m / z of 28 is set to 1 × 10⁻⁶. -5 Pa·m 3 For speeds below / s, a setting of 1×10 is preferred. -6 Pa·m 3 / s or less. Furthermore, for example, the leakage rate of gas molecules (atoms) with m / z of 44 is set to 3 × 10⁻⁶. -6 Pa·m 3 For speeds below / s, a setting of 1×10 is preferred. -6 Pa·m 3 / s or less.

[0400] The leakage rate can be calculated based on the total pressure and partial pressure measured using the aforementioned mass analyzer. The leakage rate depends on both external and internal leakage. External leakage refers to the inflow of gas from outside the vacuum system due to small holes or poor sealing. Internal leakage originates from leaks in valves or other baffles within the vacuum system, or from released gas from internal components. To keep the leakage rate below the aforementioned values, measures need to be taken to address both external and internal leakage.

[0401] For example, metal gaskets are preferably used to seal the opening and closing parts of the transfer chamber 2704 and each processing chamber. The metal gaskets are preferably made of metals coated with iron fluoride, alumina, or chromium oxide. Metal gaskets offer higher tightness than O-rings, thus reducing external leakage. By utilizing a passive metal coated with iron fluoride, alumina, or chromium oxide, the release of gases containing impurities from the metal gaskets can be suppressed, thereby reducing internal leakage.

[0402] As components constituting the manufacturing apparatus 2700, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which contain few impurities and release gases, are used. Alternatively, the aforementioned components can be coated with alloys containing iron, chromium, and nickel. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and easy to process. Here, by reducing the surface roughness of the component through polishing or other methods to decrease the surface area, the release of gases can be reduced.

[0403] Alternatively, ferric fluoride, alumina, chromium oxide, etc., can be used to cover the components of the manufacturing apparatus 2700.

[0404] The components of the manufacturing apparatus 2700 are preferably made of metal as much as possible. For example, when a viewing window made of quartz or the like is provided, in order to suppress the release of gas, the surface is preferably covered with a thin layer of iron fluoride, aluminum oxide or chromium oxide.

[0405] Although the deposits present in the transfer chamber 2704 and each processing chamber adhere to the inner walls and do not affect the pressure of the transfer chamber 2704 and each processing chamber, these deposits become the cause of gas release during venting of the transfer chamber 2704 and each processing chamber. Therefore, although the leakage rate is not related to the venting rate, it is very important to pre-vent by using a pump with a high venting capacity to remove the deposits present in the transfer chamber 2704 and each processing chamber as much as possible. To promote the removal of deposits, the transfer chamber 2704 and each processing chamber can also be baked. By baking, the removal rate of adsorbates can be increased by about 10 times. Baking can be carried out at a temperature of 100°C or higher and 450°C or lower. At this time, by introducing inert gas into the transfer chamber 2704 and each processing chamber while removing deposits, the removal rate of water and other substances that are not easily removed by venting alone can be further improved. In addition, by heating the introduced inert gas at a temperature similar to the baking temperature, the removal rate of adsorbates can be further improved. Here, a rare gas is preferably used as the inert gas.

[0406] Furthermore, it is preferable to increase the pressure in the transfer chamber 2704 and each processing chamber by introducing a heated inert gas such as a rare gas or oxygen, and then exhaust the transfer chamber 2704 and each processing chamber again after a certain period of time. The introduction of the heated gas can cause deposits in the transfer chamber 2704 and each processing chamber to detach, thereby reducing impurities present in the transfer chamber 2704 and each processing chamber. Effectively, this process should be repeated at least twice and no more than 30 times, preferably at least five times and no more than 15 times. Specifically, the pressure in the transfer chamber 2704 and each processing chamber is set to 0.1 Pa or more and 10 kPa or less, preferably 1 Pa or more and 1 kPa or less, more preferably 5 Pa or more and 100 Pa or less, by introducing an inert gas or oxygen at a temperature of 40°C or higher and 400°C or lower, preferably 50°C or higher and 200°C, and the pressure is maintained for at least one minute and no more than 300 minutes, preferably 5 minutes or more and 120 minutes or less. Then, exhaust air from the transfer chamber 2704 and each processing chamber for 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0407] Next, refer to Figure 17 The cross-sectional schematic diagram shown illustrates processing chambers 2706b and 2706c.

[0408] Processing chambers 2706b and 2706c are, for example, processing chambers capable of performing microwave processing on the workpiece. Note that the only difference between processing chambers 2706b and 2706c is the atmosphere during microwave processing. Since the other structures of processing chambers 2706b and 2706c are the same, they will be described together below.

[0409] Processing chambers 2706b and 2706c include a slotted antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Furthermore, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are provided externally to processing chambers 2706b and 2706c.

[0410] A high-frequency generator 2803 is connected to a mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slotted antenna plate 2808 via a waveguide 2807. The slotted antenna plate 2808 is grounded in contact with a dielectric plate 2809. Furthermore, a gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is introduced into processing chambers 2706b and 2706c via a gas pipe 2806 passing through the mode converter 2805, waveguide 2807, and dielectric plate 2809. A vacuum pump 2817 is also functional, capable of discharging gas from processing chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. Finally, a high-frequency power supply 2816 is connected to a substrate holder 2812 via a matching adapter 2815.

[0411] The substrate holder 2812 has the function of holding the substrate 2811. For example, the substrate holder 2812 has the function of electrostatically or mechanically chuckling the substrate 2811. In addition, the substrate holder 2812 has the function of serving as an electrode powered by the high-frequency power supply 2816. Furthermore, the substrate holder 2812 includes a heating mechanism 2813 inside and has the function of heating the substrate 2811.

[0412] As the vacuum pump 2817, various types of pumps can be used, such as drying pumps, mechanical booster pumps, ion pumps, titanium sublimation pumps, cryogenic pumps, or turbomolecular pumps. Furthermore, in addition to the vacuum pump 2817, a cryogenic cold trap can also be used. Using both a cryogenic pump and a cryogenic cold trap allows for efficient water removal, which is particularly preferred.

[0413] As the heating mechanism 2813, a heating mechanism that uses a resistance heating element or the like for heating can be used. Alternatively, a heating mechanism that uses heat conduction or heat radiation from a medium such as a gas to be heated can also be used. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA uses a high-temperature gas for heat treatment. An inert gas is used as the gas.

[0414] Furthermore, the gas supply source 2801 can be connected to the purifier via a mass flow controller. Preferably, a gas with a dew point below -80°C, and more preferably below -100°C, is used. For example, oxygen gas, nitrogen gas, and rare gases (such as argon) can be used.

[0415] For example, silicon dioxide (quartz), aluminum oxide, or yttrium oxide can be used as the dielectric plate 2809. Furthermore, other protective layers can be formed on the surface of the dielectric plate 2809. These protective layers can be made of materials such as magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Because the dielectric plate 2809 is exposed to the particularly high-density region of the high-density plasma 2810 (described later), damage can be mitigated by providing a protective layer. As a result, the increase of particles during processing can be suppressed.

[0416] The high-frequency generator 2803 is capable of generating microwaves, for example, at frequencies above 0.3 GHz and below 3.0 GHz, above 0.7 GHz and below 1.1 GHz, or above 2.2 GHz and below 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to a mode converter 2805 via a waveguide 2804. In the mode converter 2805, the transmitted TE-mode microwaves are converted to TEM-mode microwaves. These microwaves are then transmitted to a slotted antenna plate 2808 via a waveguide 2807. Multiple slots are provided in the slotted antenna plate 2808, through which microwaves pass and through a dielectric plate 2809. An electric field is then generated below the dielectric plate 2809, thereby generating a high-density plasma 2810. The high-density plasma 2810 includes ions and free radicals corresponding to the types of gas supplied from the gas supply source 2801. For example, the high-density plasma 2810 includes oxygen free radicals or nitrogen free radicals.

[0417] At this time, the film quality on the substrate 2811 can be improved by utilizing the ions and free radicals generated in the high-density plasma 2810. Furthermore, it is sometimes preferable to apply a bias voltage to one side of the substrate 2811 using a high-frequency power supply 2816. For example, an RF (Radio Frequency) power supply with frequencies such as 13.56 MHz or 27.12 MHz can be used as the high-frequency power supply 2816. By applying a bias voltage to one side of the substrate, ions in the high-density plasma 2810 can be efficiently directed to the depth of the openings in the film on the substrate 2811.

[0418] For example, in processing chamber 2706b, oxygen radical treatment using high-density plasma 2810 can be performed by introducing oxygen from gas supply source 2801, and in processing chamber 2706c, nitrogen radical treatment using high-density plasma 2810 can be performed by introducing nitrogen from gas supply source 2801.

[0419] Next, refer to Figure 18 The cross-sectional schematic diagram shown illustrates processing chambers 2706a and 2706d.

[0420] Processing chambers 2706a and 2706d are, for example, processing chambers capable of irradiating the object being processed with electromagnetic waves. Note that the only difference between processing chambers 2706a and 2706d is the type of electromagnetic wave. Since the other structures of processing chambers 2706a and 2706d are the same, they will be described together below.

[0421] Processing chambers 2706a and 2706d include one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust outlet 2830. Furthermore, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the processing chambers 2706a and 2706d.

[0422] A gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. A vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. A lamp 2820 is configured opposite to a substrate holder 2825. The substrate holder 2825 has the function of holding the substrate 2824. Furthermore, the substrate holder 2825 includes a heating mechanism 2826 inside and has the function of heating the substrate 2824.

[0423] As for lamp 2820, for example, a light source that can emit electromagnetic waves such as visible light or ultraviolet light can be used. For example, a light source that can emit electromagnetic waves with peaks in the wavelength regions of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm can be used.

[0424] For example, as lamp 2820, light sources such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps can be used.

[0425] For example, some or all of the electromagnetic waves emitted from lamp 2820 are absorbed by substrate 2824, thereby improving the quality of films, etc., on substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. At the same time, by heating substrate 2824, defects can be generated or reduced, or impurities can be removed efficiently.

[0426] Alternatively, for example, electromagnetic waves emitted from lamp 2820 can be used to heat substrate holder 2825, thereby heating substrate 2824. In this case, it is not necessary to include heating mechanism 2826 inside substrate holder 2825.

[0427] Vacuum pump 2828 can be found in the description of vacuum pump 2817. Furthermore, heating mechanism 2826 can be found in the description of heating mechanism 2813. Additionally, gas supply source 2821 can be found in the description of gas supply source 2801.

[0428] By using the manufacturing apparatus described above, impurities can be prevented from entering the processed material and the membrane quality can be improved.

[0429] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0430] (Implementation Method 2)

[0431] In this embodiment, refer to Figures 19 to 21 One method of describing a semiconductor device (memory device) is described.

[0432] [Storage Device 1]

[0433] Figure 19 An example of a memory device using a semiconductor device as an embodiment of the present invention is shown. In the memory device according to this embodiment, transistor 200 is disposed above transistor 300, and capacitor 100 is disposed above transistor 200. Preferably, at least a portion of capacitor 100 or transistor 300 overlaps transistor 200. This reduces the area occupied by capacitor 100, transistor 200, and transistor 300 in top view, enabling miniaturization or high integration of the memory device according to this embodiment. The memory device according to this embodiment can be applied, for example, to logic circuits represented by CPU (Central Processing Unit) or GPU (Graphics Processing Unit), or to memory circuits represented by DRAM (Dynamic Random Access Memory) or NVM (Non-Volatile Memory).

[0434] Note that the transistor 200 described in the above embodiments can be used as transistor 200. Therefore, regarding transistor 200 and the layer including transistor 200, please refer to the description of the above embodiments.

[0435] Transistor 200 is a transistor whose channel is formed in a semiconductor layer containing oxide semiconductor. Because transistor 200 has a small off-state current, its use in storage devices allows for long-term retention of stored data. In other words, since refresh operations are unnecessary or occur at extremely low frequencies, the power consumption of the storage device can be significantly reduced. Furthermore, compared to transistors using silicon as the semiconductor layer, transistor 200 exhibits superior electrical characteristics at high temperatures. For example, transistor 200 maintains good electrical characteristics even within a temperature range of 125°C to 150°C. Moreover, within this temperature range, transistor 200 has a conduction-to-cutoff ratio exceeding ten digits. In other words, compared to transistors using silicon as the semiconductor layer, transistor 200 possesses characteristics such as improved on-state current and frequency response at higher temperatures, typical of transistors.

[0436] exist Figure 19 In the semiconductor device shown, wiring 1001 is electrically connected to the source of transistor 300, wiring 1002 is electrically connected to the drain of transistor 300, and wiring 1007 is electrically connected to the gate of transistor 300. Furthermore, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Moreover, the other of the source and drain of transistor 200 is electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100.

[0437] Figure 19 The semiconductor device shown has the characteristic that it can maintain the charge in one electrode of the capacitor 100 by switching the transistor 200 on and off, thus enabling data writing, storage, and reading. Furthermore, the transistor 200 is a device that has a back gate in addition to the source, gate (top gate), and drain. That is, compared to two-terminal devices such as MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistive Random Access Memory), and Phase-change memory, which utilize MTJ (Magnetic Tunnel Junction) characteristics, the four-terminal transistor 200 has the characteristic of easily enabling independent control of input and output. Moreover, sometimes MRAM, ReRAM, and Phase-change memory undergo atomic-level structural changes when rewriting information. On the other hand, Figure 19The semiconductor device shown operates by charging or discharging electrons in transistors and capacitors when rewriting information, thus exhibiting good rewrite durability and minimal structural changes.

[0438] In addition, by Figure 19 The semiconductor devices shown are arranged in a matrix, which can form a memory cell array. In this case, transistors 300 can be used as readout circuits or drive circuits connected to the memory cell array, etc. Figure 19 When the semiconductor device shown is used as a storage element, for example, it can achieve an operating frequency of over 200 MHz under conditions of a driving voltage of 2.5V and an evaluation ambient temperature range of -40°C to 85°C.

[0439] <Transistor 300>

[0440] The transistor 300 is disposed on the substrate 311 and includes: a conductor 316 used as a gate electrode, an insulator 315 used as a gate insulator, a semiconductor region 313 formed by a portion of the substrate 311, and low-resistance regions 314a and 314b used as source or drain regions.

[0441] Here, an insulator 315 is disposed on the semiconductor region 313, and a conductor 316 is disposed on the insulator 315. Furthermore, the transistor 300 formed in the same layer is electrically separated by an insulator 312, which serves as an element separation insulating layer. The same insulator as the insulator 326 described later can be used as the insulator 312. The transistor 300 can be a p-channel or an n-channel type.

[0442] In the substrate 311, the region of the semiconductor region 313 where the channel is formed or the region near it, the low-resistance region 314a and the low-resistance region 314b used as the source or drain region, preferably contain a semiconductor such as silicon, and more preferably contain single-crystal silicon. Alternatively, materials containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc., can also be used. Silicon, by applying stress to the crystal lattice and changing the interplanar spacing to control the effective quality, can be used. Furthermore, the transistor 300 can also be a HEMT (High Electron Mobility Transistor) using GaAs and GaAlAs, etc.

[0443] In the low resistance regions 314a and 314b, in addition to the semiconductor material applied to the semiconductor region 313, elements such as arsenic and phosphorus that impart n-type conductivity or elements such as boron that impart p-type conductivity are also included.

[0444] The conductor 316 used as the gate electrode can be a conductive material such as silicon, a semiconductor material, a metal material, an alloy material, or a metal oxide material, which contains elements that impart n-type conductivity, such as arsenic or phosphorus, or elements that impart p-type conductivity, such as boron.

[0445] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, materials such as titanium nitride or tantalum nitride are preferably used as conductors. In order to combine conductivity and embeddability, a stack of metal materials such as tungsten or aluminum is preferably used as the conductor, especially tungsten, which is preferred in terms of heat resistance.

[0446] Here, in Figure 19 In the transistor 300 shown, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. Furthermore, a conductor 316 is provided such that it covers the side and top surfaces of the semiconductor region 313 with an insulator 315 in between. Because of the convex portion of the semiconductor substrate, this transistor 300 is also called a FIN-type transistor. Alternatively, an insulator serving as a mask for forming the convex portion may be provided in contact with the upper surface of the convex portion. Furthermore, although the case where the convex portion is formed by processing a portion of the semiconductor substrate is shown here, a semiconductor film with convex portions can also be formed by processing an SOI substrate.

[0447] Notice, Figure 19 The structure of transistor 300 shown is just an example and is not limited to the above structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0448] In addition, such as Figure 19 As shown, the semiconductor device is provided with a stack of transistors 300 and 200. For example, transistor 300 can be formed using a silicon-based semiconductor material, and transistor 200 can be formed using an oxide semiconductor material. Thus, Figure 19 The semiconductor device shown can have silicon-based semiconductor materials and oxide semiconductors formed in different layers, respectively. Furthermore, Figure 19 The semiconductor device shown can be manufactured using the same processes as semiconductor devices using silicon-based semiconductor materials, and can achieve high integration.

[0449] <Capacitor>

[0450] The capacitor 100 includes an insulator 114 on an insulator 160, an insulator 140 on an insulator 114, a conductor 110 disposed in an opening formed in the insulator 114 and the insulator 140, an insulator 130 on the conductor 110 and the insulator 140, a conductor 120 on the insulator 130, and an insulator 150 on the conductor 120 and the insulator 130. Here, at least a portion of the conductor 110, the insulator 130, and the conductor 120 are disposed in the opening formed in the insulator 114 and the insulator 140.

[0451] Conductor 110 is used as the lower electrode of capacitor 100, conductor 120 is used as the upper electrode of capacitor 100, and insulator 130 is used as the dielectric of capacitor 100. Capacitor 100 has a structure in which the upper and lower electrodes are opposed to each other by a dielectric material not only on the bottom surface but also on the side surfaces within the openings of insulators 114 and 140, thus increasing the electrostatic capacitance per unit area. Therefore, the deeper the opening, the greater the electrostatic capacitance of capacitor 100. In this way, by increasing the electrostatic capacitance per unit area of ​​capacitor 100, miniaturization or high integration of semiconductor devices can be advanced.

[0452] As insulators 114 and 150, an insulator that can be used as insulator 280 can be used. In addition, insulator 140 is preferably used as an etch stop layer when forming an opening in insulator 114, and an insulator that can be used for insulator 214 can be used.

[0453] Furthermore, the top-view shape of the openings formed in insulators 114 and 140 can be a quadrilateral, a polygon other than a quadrilateral, a polygon with rounded corners, or a circular shape such as an ellipse. Here, it is preferable that the area of ​​the opening overlapping with the transistor 200 is large when viewed from above. By adopting this structure, the area occupied by the semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0454] The conductor 110 is disposed in contact with an opening formed in the insulator 140 and the insulator 114. The top surface of the conductor 110 preferably coincides substantially with the top surface of the insulator 140. Furthermore, the bottom surface of the conductor 110 contacts the conductor 152 disposed on the insulator 160. The conductor 110 is preferably formed by an ALD method or a CVD method, for example, using a conductor suitable for conductor 205.

[0455] The insulator 130 is configured to cover both the conductor 110 and the insulator 140. For example, the insulator 130 is preferably formed by an ALD or CVD method. As the insulator 130, for example, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride, etc., can be used, and a multilayer or single-layer structure can be employed. For example, as the insulator 130, an insulating film sequentially stacked with zirconium oxide, aluminum oxide, and zirconium oxide can be used.

[0456] For example, the insulator 130 is preferably made of a material with high dielectric strength, such as silicon oxynitride, or a material with a high dielectric constant (high-k). Alternatively, a multilayer structure of materials with high dielectric strength or high dielectric constant (high-k) can also be used.

[0457] Note that high-k materials (materials with relatively high dielectric constants) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. By using such a high-k material, even with an increased thickness of the insulator 130, the electrostatic capacitance of the capacitor 100 can be adequately ensured. By increasing the thickness of the insulator 130, leakage current generated between the conductor 110 and the conductor 120 can be suppressed.

[0458] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with both carbon and nitrogen, porous silicon oxide, and resins. For example, silicon nitride (SiN) formed by the ALD method can be used in sequence. x ), silicon dioxide (SiO2) formed by the PEALD method x Silicon nitride (SiN) formed by ALD method x The insulating film of the capacitor 100 is used. By employing this high dielectric strength insulator, the dielectric strength can be increased, thereby suppressing electrostatic damage to the capacitor 100.

[0459] Conductor 120 is disposed in such a way that it fills the openings formed in insulator 140 and insulator 114. Furthermore, conductor 120 is electrically connected to wiring 1005 via conductor 112 and conductor 153. Conductor 120 is preferably formed by ALD or CVD methods, for example, a conductor suitable for conductor 205 can be used.

[0460] Furthermore, the transistor 200 has a structure using oxide semiconductor, thus providing good matching with the capacitor 100. Specifically, the off-state current of the transistor 200 using oxide semiconductor is small, thereby allowing the stored content to be retained for a long period of time by combining the transistor 200 with the capacitor 100.

[0461] <Wiring Layer>

[0462] Wiring layers, including interlayer films, wiring, and plugs, can also be provided between various structures. Furthermore, multiple wiring layers can be provided according to the design. Here, in conductors used as plugs or wiring, multiple structures are sometimes represented by the same reference numeral. Moreover, in this specification, wiring and plugs electrically connected to wiring can also be a single component. That is, a part of a conductor is sometimes used as wiring, and a part of a conductor is sometimes used as a plug.

[0463] For example, in transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductors 328 and 330, which are electrically connected to conductors 153 used as terminals, are embedded within insulators 320, 322, 324, and 326. Additionally, conductors 328 and 330 are used as plugs or wiring.

[0464] Furthermore, the insulator used as an interlayer film can be used as a planarization film covering the uneven shape underneath. For example, in order to improve the flatness of the top surface of insulator 322, its top surface can also be planarized by a planarization process such as chemical mechanical polishing (CMP).

[0465] Furthermore, a wiring layer can also be formed on the insulator 326 and the conductor 330. For example, in Figure 19 In the structure, insulators 350, 352, and 354 are stacked sequentially. Furthermore, a conductor 356 is formed within insulators 350, 352, and 354. The conductor 356 is used as a plug or wiring.

[0466] Insulators 210, 212, 214, and 216 are sequentially stacked on insulators 354 and conductors 356. Furthermore, conductors 218 and conductors constituting transistor 200 (conductor 205) are embedded within insulators 210, 212, 214, and 216. Conductor 218 serves as a plug or wiring for electrical connection with transistor 300.

[0467] Furthermore, conductor 112 and conductors constituting capacitor 100 (conductor 120, conductor 110) are embedded in insulators 114, 140, 130, 150, and 154. Conductor 112 is used as a plug or wiring to electrically connect capacitor 100, transistor 200, or transistor 300 to conductor 153, which is used as a terminal.

[0468] Additionally, a conductor 153 is provided on the insulator 154, and the conductor 153 is covered by the insulator 156. Here, the conductor 153 is in contact with the top surface of the conductor 112 and is used as a terminal of the capacitor 100, transistor 200, or transistor 300.

[0469] Note that insulating materials suitable for use as interlayer films include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides, all possessing insulating properties. For example, by using a material with a low relative permittivity as the insulator for the interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulator.

[0470] For example, insulators 320, 322, 326, 352, 354, 212, 114, 150, and 156 are preferably insulators with a low relative permittivity. For example, the insulator preferably comprises silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen, porous silicon oxide, resin, etc. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen, or porous silicon oxide and resin. Because silicon oxide and silicon oxynitride are thermally stable, a thermally stable laminated structure with a low relative permittivity can be achieved by combining them with resin. Examples of resins include polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, and acrylic resins.

[0471] Additionally, the resistivity of the insulator disposed on or below conductor 152 or conductor 153 is 1.0 × 10⁻⁶. 12 Ωcm or more and 1.0×10 15 Below Ωcm, preferably 5.0 × 10 12 Ωcm or more and 1.0×10 14 Below Ωcm, more preferably 1.0×10 13 Ωcm or more and 5.0×10 13Below Ωcm. By setting the resistivity of the insulator disposed on or below conductor 152 or conductor 153 to the above-mentioned range, the insulator can maintain insulation and disperse the charge accumulated between the wiring of transistor 200, transistor 300, capacitor 100, and conductor 152, etc., thereby suppressing the malfunction or electrostatic damage caused by the charge to the transistor and the semiconductor device including the transistor, and is therefore preferred. Silicon nitride or silicon oxynitride can be used as such an insulator. For example, the resistivity of insulator 160 or insulator 154 can be set to the above-mentioned range.

[0472] By surrounding a transistor using an oxide semiconductor with an insulator that suppresses the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, insulators such as insulator 324, insulator 350, and insulator 210 can be insulators that suppress the permeation of impurities such as hydrogen and oxygen.

[0473] As an insulator that suppresses impurities such as hydrogen and oxygen permeation, single layers or stacks of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. Specifically, as an insulator that suppresses impurities such as hydrogen and oxygen permeation, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, as well as silicon oxynitride or silicon nitride, can be used.

[0474] The preferred conductor for use in wiring and plugs is a material containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. Alternatively, highly conductive semiconductors such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides may also be used.

[0475] For example, conductors 328, 330, 356, 218, 112, 152, and 153 can be conductive materials such as metallic materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above-mentioned materials, either in single layers or in layers. High-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred, with tungsten being particularly preferred. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0476] <Wires or connectors with oxide semiconductor layers>

[0477] Note that when an oxide semiconductor is used in a transistor 200, an insulator with an excess oxygen region is sometimes provided near the oxide semiconductor. In this case, it is preferable to provide a barrier insulator between the insulator with the excess oxygen region and the conductor provided in the insulator with the excess oxygen region.

[0478] For example, in Figure 19 Preferably, an insulator 247 is provided between the insulator 280 containing excess oxygen and the conductor 248. Because the insulator 247 is provided in contact with the insulator 282, a structure in which the conductor 248 and the transistor 200 are sealed by a barrier insulator can be achieved.

[0479] In other words, by providing insulator 247, the absorption of excess oxygen contained in insulator 280 by conductor 248 can be suppressed. Furthermore, by having insulator 247, the diffusion of hydrogen as an impurity through conductor 248 into transistor 200 can be suppressed.

[0480] Here, conductor 248 has the function of a plug or wiring that is electrically connected to transistor 200 or transistor 300.

[0481] Specifically, an insulator 247 is provided in contact with the sidewalls of the openings of insulators 284, 282, and 280, and a conductor 248 is formed in contact with its sidewalls. A conductor 240a or conductor 240b is provided on at least a portion of the bottom of the opening, and the conductor 248 is in contact with the conductor 240a or conductor 240b.

[0482] As the conductor 248, a conductive material with tungsten, copper, or aluminum as the main component is preferably used. Furthermore, the conductor 248 may also have a multilayer structure. Although the conductor 248 in the transistor 200 has a two-layer multilayer structure, the present invention is not limited to this. For example, the conductor 248 may also have a single-layer structure or a multilayer structure with three or more layers.

[0483] When the conductor 248 has a multilayer structure, a conductive material that suppresses the permeation of impurities such as water and hydrogen is preferably used as the conductor that contacts conductor 240a or conductor 240b and contacts insulators 280, 282, and 284 through insulator 247. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc., are preferred. The conductive material that suppresses the permeation of impurities such as water and hydrogen can be used as a single layer or in multilayers. By using this conductive material, oxygen added to insulator 280 can be prevented from being absorbed into conductor 248. Furthermore, impurities such as water and hydrogen contained in the layer above insulator 284 can be prevented from diffusing through conductor 248 to oxide 230.

[0484] As the insulator 247, an insulator suitable for insulator 214 or the like can be used. The insulator 247 can suppress the diffusion of impurities such as water and hydrogen contained in insulator 280 through conductor 248 to oxide 230. In addition, it can prevent oxygen contained in insulator 280 from being absorbed by conductor 248.

[0485] Alternatively, the conductor 152 used for wiring can be configured to contact the top surface of the conductor 248. The conductor used for wiring is preferably a conductive material with tungsten, copper, or aluminum as its main components. Furthermore, the conductor can have a laminated structure, for example, a laminated structure of titanium or titanium nitride with the aforementioned conductive material. Additionally, the conductor can be embedded in an opening provided in an insulator.

[0486] The above is an explanation of the structural examples. By adopting this structure, miniaturization or high integration of semiconductor devices using transistors containing oxide semiconductors can be achieved. Furthermore, in semiconductor devices using transistors containing oxide semiconductors, variations in electrical characteristics can be suppressed and reliability improved. Additionally, a transistor containing oxide semiconductors with a large on-state current can be provided. Furthermore, a transistor containing oxide semiconductors with a small off-state current can be provided. Furthermore, a semiconductor device with low power consumption can be provided.

[0487] [Storage Device 2]

[0488] Figure 20 An example of a semiconductor device (memory device) using one aspect of the present invention is shown. (Compared to...) Figure 19 The semiconductor devices shown are the same. Figure 20 The semiconductor device shown also includes transistor 200, transistor 300, and capacitor 100. However, Figure 20 The semiconductor device shown is Figure 19 The semiconductor device shown differs in that: capacitor 100 is planar; and transistor 200 is electrically connected to transistor 300.

[0489] In one embodiment of the semiconductor device of the present invention, transistor 200 is disposed above transistor 300, and capacitor 100 is disposed above transistors 300 and 200. At least a portion of capacitor 100 or transistor 300 preferably overlaps transistor 200. Therefore, since the area occupied by capacitor 100, transistor 200, and transistor 300 in a top view can be reduced, miniaturization or high integration of the semiconductor device according to this embodiment can be achieved.

[0490] The transistors 200 and 300 described above can be used as transistors 200 and 300. Therefore, the transistors 200, 300 and the layers including them can be referred to the above description.

[0491] exist Figure 20 In the semiconductor device shown, wiring 2001 is electrically connected to the source of transistor 300, and wiring 2002 is electrically connected to the drain of transistor 300. Furthermore, wiring 2003 is electrically connected to one of the source and drain of transistor 200, wiring 2004 is electrically connected to the first gate of transistor 200, and wiring 2006 is electrically connected to the second gate of transistor 200. Additionally, the gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one electrode of capacitor 100, and wiring 2005 is electrically connected to the other electrode of capacitor 100. Note that the node connected to the gate of transistor 300, the other of the source and drain of transistor 200, and one electrode of capacitor 100 is sometimes referred to as node FG.

[0492] Figure 20 The semiconductor device shown has the characteristic that the potential of the gate (node ​​FG) of transistor 300 can be maintained by switching transistor 200, thus enabling data writing, holding and reading.

[0493] In addition, by Figure 20 The semiconductor devices shown are configured in a matrix shape, which can form a memory cell array.

[0494] The layer including transistor 300 has the same Figure 19 The semiconductor device shown has the same structure, so the structure below the insulator 354 can be referred to the above description.

[0495] Insulators 210, 212, 214, and 216 are disposed on insulator 354. Therefore, similar to insulator 350, an insulator 210 that has the function of suppressing the permeation of impurities such as hydrogen and oxygen can be used.

[0496] Conductor 218 is embedded in insulators 210, 212, 214, and 216. Conductor 218 is used as a plug or wiring for electrical connection to capacitor 100, transistor 200, or transistor 300. For example, conductor 218 is electrically connected to conductor 316, which is used as the gate electrode of transistor 300.

[0497] Conductor 248 is used as a plug or wiring for electrical connection with transistor 200 or transistor 300. For example, conductor 248 electrically connects conductor 240b, which is used as another of the source and drain electrodes of transistor 200, to conductor 110, which is used as an electrode of capacitor 100.

[0498] Additionally, a planar capacitor 100 may be disposed above the transistor 200. The capacitor 100 includes a conductor 110 serving as a first electrode, a conductor 120 serving as a second electrode, and an insulator 130 serving as a dielectric. Note that the conductor 110, conductor 120, and insulator 130 may use the constituent elements described in the storage device 1 above.

[0499] Conductors 153 and 110 are disposed in contact with the top surface of conductor 248. Conductor 153 is in contact with the top surface of conductor 248 and is used as a terminal of transistor 200 or transistor 300.

[0500] Conductors 153 and 110 are covered by insulator 130, and conductor 120 is disposed in such a way that it overlaps with conductor 110. Furthermore, insulator 114 is disposed on conductor 120 and insulator 130.

[0501] In addition, although Figure 20 An example of using a planar capacitor as capacitor 100 is shown, but the semiconductor device shown in this embodiment is not limited to this. For example, capacitor 100 can be referred to Figure 19 The cylinder-shaped capacitor 100 is shown.

[0502] [Storage Device 3]

[0503] Figure 21 An example of a memory device using a semiconductor device according to one aspect of the present invention is shown. Figure 21 The storage device shown includes, in addition to Figure 20 In addition to the semiconductor devices shown, transistors 200, 300, and capacitor 100, transistor 400 is also included.

[0504] Transistor 400 can control the second gate voltage of transistor 200. For example, a structure can be adopted in which the first and second gates of transistor 400 are connected to a source diode, and the source of transistor 400 is connected to the second gate of transistor 200. When the second gate of transistor 200 is maintained at a negative potential in this structure, the voltage between the first gate and source of transistor 400 and the voltage between the second gate and source of transistor 400 become 0V. In transistor 400, since the drain current is very small when the second gate voltage and the first gate voltage are 0V, the negative potential of the second gate of transistor 200 can be maintained for a long time even if no power is supplied to transistors 200 and 400. Therefore, a storage device including transistors 200 and 400 can retain stored content for a long period.

[0505] Therefore, in Figure 21 In this configuration, wiring 2001 is electrically connected to the source of transistor 300, and wiring 2002 is electrically connected to the drain of transistor 300. Wiring 2003 is electrically connected to one of the source and drain of transistor 200, wiring 2004 is electrically connected to the gate of transistor 200, and wiring 2006 is electrically connected to the second gate of transistor 200. Furthermore, the gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one electrode of capacitor 100, and wiring 2005 is electrically connected to the other electrode of capacitor 100. Wiring 2007 is electrically connected to the source of transistor 400, wiring 2008 is electrically connected to the first gate of transistor 400, wiring 2009 is electrically connected to the second gate of transistor 400, and wiring 2010 is electrically connected to the drain of transistor 400. Wiring 2006, 2007, 2008, and 2009 are also electrically connected.

[0506] In addition, by Figure 21 The storage device shown is Figure 19 and Figure 20 The illustrated memory device is also configured in a matrix shape, which can form a memory cell array. Note that one transistor 400 can control the second gate voltage of multiple transistors 200. Therefore, it is preferable that the number of transistors 400 is less than the number of transistors 200.

[0507] <Transistor 400>

[0508] Transistor 400 is formed on the same layer as transistor 200, thereby allowing them to be manufactured simultaneously. Transistor 400 includes: conductors 460 (conductors 460a and 460b) serving as a first gate electrode; conductors 405 (conductors 405a and 405b) serving as a second gate electrode; insulators 222, 224, and 450 serving as a gate insulating layer; oxide 430c including a channel forming region; conductors 440a, oxide 431b, and oxide 431a serving as one of the source and drain electrodes; conductors 440b, oxide 432b, and oxide 432a serving as the other of the source and drain electrodes; and insulators 445a and 445b serving as a barrier layer.

[0509] Conductor 405 and conductor 205 are formed in the same layer. Oxides 431a and 432a are formed in the same layer as oxide 230a, and oxides 431b and 432b are formed in the same layer as oxide 230b. Conductors 440a and 440b are formed in the same layer as conductors 240a and 240b. Insulators 445a and 445b are formed in the same layer as insulators 245a and 245b. Oxide 430c and oxide 230c are formed in the same layer. Insulator 450 and insulator 250 are formed in the same layer. Conductor 460 and conductor 260 are formed in the same layer.

[0510] Note that structures formed in the same layer can be formed simultaneously. For example, oxide 430c can be formed by processing an oxide film that will become oxide 230c.

[0511] Similar to oxide 230, the oxide 430c used as the active layer of transistor 400 has fewer oxygen vacancies and impurities such as hydrogen and water. Therefore, the threshold voltage of transistor 400 can be increased, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are both 0V can be made very small.

[0512] This embodiment can be implemented by appropriately combining it with the structures described in other embodiments, etc.

[0513] (Implementation Method 3)

[0514] In this embodiment, refer to Figures 22A to 23HThe following describes a storage device (hereinafter sometimes referred to as an OS storage device) using an oxide-based semiconductor transistor (hereinafter sometimes referred to as an OS transistor) and a capacitor, according to one embodiment of the present invention. An OS storage device is a storage device comprising at least a capacitor and an OS transistor that controls the charging and discharging of the capacitor. Because the off-state current of an OS transistor is extremely small, an OS storage device has excellent retention characteristics and can therefore be used as a non-volatile memory.

[0515] <Example of storage device structure>

[0516] Figure 22A An example of the structure of an OS storage device is shown. Storage device 1400 includes peripheral circuitry 1411 and a storage cell array 1470. Peripheral circuitry 1411 includes row circuitry 1420, column circuitry 1430, output circuitry 1440, and control logic circuitry 1460.

[0517] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit precharges the wiring. The sense amplifier amplifies the data signal read from the memory cell. Note that the wiring described above is the wiring connected to the memory cells included in the memory cell array 1470, and its details are described below. The amplified data signal, as the data signal RDATA, is output to the outside of the memory device 1400 via the output circuit 1440. Furthermore, the row circuit 1420 includes, for example, a row decoder and a word line driver circuit, and can select the row to be accessed.

[0518] The storage device 1400 is supplied with a low power supply voltage (VSS), the peripheral circuit 1411 is supplied with a high power supply voltage (VDD), and the memory cell array 1470 is supplied with a high power supply voltage (VIL). In addition, the storage device 1400 receives external control signals (CE, WE, RE), address signals ADDR, and data signals WDATA. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

[0519] The control logic circuit 1460 processes externally input control signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. Control signal CE is the chip enable signal, control signal WE is the write enable signal, and control signal RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals can be input as needed.

[0520] The memory cell array 1470 includes a plurality of memory cells MCs configured in a row and column configuration and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a column, etc. Furthermore, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a row, etc.

[0521] In addition, although Figure 22A An example is shown where the peripheral circuitry 1411 and the memory cell array 1470 are formed on the same plane, but this embodiment is not limited thereto. For example, as Figure 22B As shown, the memory cell array 1470 can also be arranged overlapping a portion of the peripheral circuitry 1411. For example, the readout amplifier can also be arranged overlapping the memory cell array 1470.

[0522] exist Figures 23A to 23H The text describes a structural example of a memory cell that can be used in the aforementioned memory cell MC.

[0523] [DOSRAM]

[0524] Figures 23A to 23C An example of the circuit structure of a DRAM memory cell is shown. In this specification and other materials, DRAM using a 1000 transistors and 1 capacitor type memory cell is sometimes referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Figure 23A The memory cell 1471 shown includes a transistor M1 and a capacitor CA. Furthermore, the transistor M1 includes a gate (sometimes referred to as the top gate) and a back gate.

[0525] The first terminal of transistor M1 is connected to the first terminal of capacitor CA. The second terminal of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitor CA is connected to wiring CAL.

[0526] Wiring BIL is used as the bit line, and wiring WOL is used as the word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CA. During data writing and reading, it is preferable to apply a low-level potential to wiring CAL. Wiring BGL is used to apply a potential to the back gate of transistor M1. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0527] Here, Figure 23AThe storage cell 1471 shown corresponds to Figure 19 The storage device shown is as follows: That is, transistor M1 corresponds to transistor 200, capacitor CA corresponds to capacitor 100, wiring BIL corresponds to wiring 1003, wiring WOL corresponds to wiring 1004, wiring BGL corresponds to wiring 1006, and wiring CAL corresponds to wiring 1005. Note that... Figure 19 The transistor 300 described corresponds to the one set in Figure 22A and Figure 22B The transistors of the peripheral circuit 1411 of the storage device 1400 shown.

[0528] Furthermore, the memory cell MC is not limited to memory cell 1471, and its circuit structure can be changed. For example, the memory cell MC can also adopt... Figure 23B The transistor M1 in the illustrated memory cell 1472 has a back gate that is not connected to wiring BGL, but to wiring WOL. Furthermore, for example, the memory cell MC can also be as follows: Figure 23C The memory cell shown is a memory cell 1473, which is composed of a single-gate transistor, i.e., a transistor M1 excluding the back gate.

[0529] When the semiconductor device shown in the above embodiment is used in memory cell 1471, transistor 200 can be used as transistor M1, and capacitor 100 can be used as capacitor CA. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be minimized. In other words, since the written data can be held by transistor M1 for a long time, the refresh frequency of the memory cell can be reduced. Furthermore, the memory cell refresh operation can be eliminated. In addition, since the leakage current is minimal, multi-valued data or analog data can be stored in memory cells 1471, 1472, and 1473.

[0530] Furthermore, in DOSRAM, when the read amplifier is arranged in a manner overlapping the memory cell array 1470 as described above, the bit lines can be shortened. This reduces the bit line capacitance, thereby reducing the storage capacitance of the memory cells.

[0531] [NOSRAM]

[0532] Figures 23D to 23G This illustrates an example of a gain-cell type memory cell with two transistors and one capacitor. Figure 23DThe illustrated memory cell 1474 includes transistor M2, transistor M3, and capacitor CB. Furthermore, transistor M2 includes a top gate (sometimes simply referred to as the gate) and a back gate. In this specification and the like, a memory device that includes a gain-cell type memory cell using an OS transistor for transistor M2 is sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0533] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; transistor M2's gate is connected to wiring WOL; and transistor M2's back gate is connected to wiring BGL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0534] Wiring WBL is used as the write bit line, wiring RBL is used as the read bit line, and wiring WOL is used as the word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CB. It is preferable to apply a low-level potential to wiring CAL during data writing, holding, and reading. Wiring BGL is used to apply a potential to the back gate of transistor M2. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0535] Here, Figure 23D The storage cell 1474 shown corresponds to Figure 20 The storage device shown is as follows: transistor M2 corresponds to transistor 200, capacitor CB corresponds to capacitor 100, transistor M3 corresponds to transistor 300, wiring WBL corresponds to wiring 2003, wiring WOL corresponds to wiring 2004, wiring BGL corresponds to wiring 2006, wiring CAL corresponds to wiring 2005, wiring RBL corresponds to wiring 2002, and wiring SL corresponds to wiring 2001.

[0536] Furthermore, the memory cell MC is not limited to memory cell 1474, and its circuit structure can be appropriately modified. For example, the memory cell MC can also adopt... Figure 23E The transistor M2 in the illustrated memory cell 1475 has its back gate connected to the wiring BGL, but not to the wiring WOL. Furthermore, for example, the memory cell MC can also be as follows: Figure 23F The memory cell 1476 shown is a memory cell composed of a single-gate transistor, i.e., a transistor M2 excluding the back gate. Furthermore, for example, the memory cell MC may also have... Figure 23GThe storage cell 1477 shown has a structure that combines wiring WBL and wiring RBL into a wiring BIL.

[0537] When the semiconductor device shown in the above embodiment is used in memory cell 1474, transistor 200 can be used as transistor M2, transistor 300 can be used as transistor M3, and capacitor 100 can be used as capacitor CB. By using an OS transistor as transistor M2, the leakage current of transistor M2 can be minimized. Therefore, since the written data can be held by transistor M2 for a long time, the refresh frequency of the memory cell can be reduced. Furthermore, memory cell refresh operations can be eliminated. Moreover, due to the minimal leakage current, multi-valued data or analog data can be stored in memory cell 1474. The same applies to memory cells 1475 to 1477.

[0538] Furthermore, transistor M3 can also be a transistor containing silicon in the channel formation region (hereinafter sometimes referred to as a Si transistor). The conductivity type of a Si transistor can be n-channel or p-channel. The field-effect mobility of a Si transistor is sometimes higher than that of an OS transistor. Therefore, a Si transistor can also be used as the readout transistor M3. Furthermore, by using a Si transistor in transistor M3, transistor M2 can be stacked on top of transistor M3, thereby reducing the footprint of the memory cell and enabling high integration of the memory device.

[0539] Furthermore, transistor M3 can also be an OS transistor. When OS transistors are used for transistors M2 and M3, only n-type transistors can be used to construct the circuit in the memory cell array 1470.

[0540] also, Figure 23H An example of a gain-cell type memory cell with 3 transistors and 1 capacitor is shown. Figure 23H The illustrated memory cell 1478 includes transistors M4 through M6 and capacitor CC. Capacitor CC can be appropriately configured. Memory cell 1478 is electrically connected to wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. Wiring GNDL is a wiring that supplies a low-level potential. Alternatively, memory cell 1478 can be electrically connected to wiring RBL and wiring WBL without being electrically connected to wiring BIL.

[0541] Transistor M4 is an OS transistor that includes a back gate, which is electrically connected to wiring BGL. Alternatively, the back gate and gate of transistor M4 can be electrically connected to each other. Or, transistor M4 may not include a back gate.

[0542] Furthermore, transistors M5 and M6 can each be either n-channel or p-channel Si transistors. Alternatively, transistors M4 through M6 can all be OS transistors. In this case, only n-type transistors can be used to construct the circuit in the memory cell array 1470.

[0543] When the semiconductor device shown in the above embodiment is used in the memory cell 1478, transistor 200 can be used as transistor M4, transistor 300 can be used as transistors M5 and M6, and capacitor 100 can be used as capacitor CC. By using an OS transistor as transistor M4, the leakage current of transistor M4 can be minimized.

[0544] Note that the structure of the peripheral circuit 1411, the memory cell array 1470, etc., shown in this embodiment is not limited to the structure described above. Furthermore, the configuration or function of these circuits and the wiring and circuit elements connected to them can be changed, removed, or added as needed.

[0545] The structure shown in this embodiment can be used in appropriate combinations with structures shown in other embodiments, etc.

[0546] (Implementation Method 4)

[0547] In this embodiment, refer to Figure 24A and Figure 24B An example of a chip 1200 in which the semiconductor device of the present invention is mounted is described. Multiple circuits (systems) are mounted on the chip 1200. Thus, the technology of integrating multiple circuits (systems) on a single chip is sometimes referred to as a System on Chip (SoC).

[0548] like Figure 24A As shown, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog computing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.

[0549] A bump (not shown) is provided on chip 1200, and the bump is as follows: Figure 24B It is connected to the first side of the printed circuit board (PCB) 1201 as shown. In addition, a plurality of bumps 1202 are provided on the back side of the first side of the PCB 1201, which are connected to the motherboard 1203.

[0550] Alternatively, storage devices such as DRAM 1221 and flash memory 1222 can be provided on the motherboard 1203. For example, the DOSRAM shown in the above embodiment can be applied to the DRAM 1221. Furthermore, for example, the NOSRAM shown in the above embodiment can be applied to the flash memory 1222.

[0551] CPU 1211 preferably has multiple CPU cores. Furthermore, GPU 1212 preferably has multiple GPU cores. Additionally, CPU 1211 and GPU 1212 may each have a memory for temporary data storage. Alternatively, a memory shared by both CPU 1211 and GPU 1212 may be provided on chip 1200. The aforementioned NOSRAM or DOSRAM can be used in this memory. Furthermore, GPU 1212 is suitable for parallel computation of multiple data sets, and can be used for image processing or product operations. By incorporating an image processing circuit or product operation circuit using the oxide semiconductor of the present invention as GPU 1212, image processing and product operations can be performed with low power consumption.

[0552] Furthermore, since the CPU1211 and GPU1212 are located on the same chip, the wiring between the CPU1211 and GPU1212 can be shortened, and data transfer from the CPU1211 to the GPU1212, data transfer between the memory of the CPU1211 and GPU1212, and transfer of the operation result from the GPU1212 to the CPU1211 after the operation in the GPU1212 is completed can be performed at high speed.

[0553] The analog arithmetic unit 1213 includes one or both of an analog-to-digital (A / D) conversion circuit and a digital-to-analog (D / A) conversion circuit. Alternatively, the aforementioned product summation circuit may also be provided in the analog arithmetic unit 1213.

[0554] The storage controller 1214 has circuitry that serves as a controller for the DRAM 1221 and circuitry that serves as an interface for the flash memory 1222.

[0555] Interface 1215 has interface circuitry for connecting to external devices such as display devices, speakers, microphones, imaging devices, and controllers. Controllers include mice, keyboards, and game console controllers. Universal Serial Bus (USB) and High-Definition Multimedia Interface (HDMI) (registered trademark) can be used as the interface.

[0556] Network circuit 1216 includes network circuits such as those for local area networks (LANs). Additionally, it may include network security circuits.

[0557] The aforementioned circuit (system) can be formed on chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, no additional manufacturing process is required, and chip 1200 can be manufactured at low cost.

[0558] The motherboard 1203, which includes a PCB 1201 with a chip 1200 having a GPU 1212, a DRAM 1221, and a flash memory 1222, can be referred to as a GPU module 1204.

[0559] The GPU module 1204 can reduce its size due to the presence of the chip 1200 using SoC technology. Furthermore, the GPU module 1204, with its high image processing capabilities, is suitable for use in portable electronic devices such as smartphones, tablets, laptops, and portable game consoles. Moreover, by utilizing the product-sum operation circuitry of the GPU 1212, deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs) can be executed. Therefore, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0560] The structure shown in this embodiment can be used in appropriate combinations with structures shown in other embodiments, etc.

[0561] (Implementation Method 5)

[0562] In this embodiment, an application example of a storage device using the semiconductor device described in the above embodiments is explained. The semiconductor device described in the above embodiments can be applied, for example, to the storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book reader terminals, digital cameras (including camcorders), video recording devices, navigation systems, etc.). Note that here, "computer" includes tablet computers, notebook computers, desktop computers, and mainframe computers such as server systems. Alternatively, the semiconductor device described in the above embodiments can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB storage devices, and SSDs (solid-state drives). Figures 25A to 25E Several structural examples of removable storage devices are illustrated schematically. For example, the semiconductor devices shown in the above embodiments are fabricated into packaged memory chips and used in various storage devices or removable memories.

[0563] Figure 25AThis is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed within the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device shown in the above embodiment can be assembled onto the memory chip 1105, etc.

[0564] Figure 25B This is a schematic diagram of the SD card's appearance. Figure 25C This is a schematic diagram of the internal structure of an SD card. The SD card 1110 includes a frame 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed within the frame 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Furthermore, a wireless chip with wireless communication capabilities can also be provided on the substrate 1113. Thus, data can be read from and written to the memory chip 1114 via wireless communication between the host device and the SD card 1110. The semiconductor device described in the above embodiment can be assembled onto the memory chip 1114, etc.

[0565] Figure 25D This is a schematic diagram of the SSD's appearance. Figure 25E This is a schematic diagram of the internal structure of an SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed within the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 serves as the working memory for the controller chip 1156; for example, a DOSRAM chip can be used. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the above embodiment can be assembled onto the memory chip 1154, etc.

[0566] This embodiment can be implemented by appropriately combining it with the structures described in other embodiments, etc.

[0567] (Implementation Method 6)

[0568] The semiconductor device according to one aspect of the present invention can be applied to processors or chips such as CPUs and GPUs. Figures 26A to 26H Specific examples of electronic devices having a processor or chip such as a CPU or GPU according to one aspect of the present invention are shown.

[0569] <Electronic Devices and Systems>

[0570] The GPU or chip according to one aspect of the present invention can be installed in a wide variety of electronic devices. Examples of electronic devices include, in addition to television sets, displays for laptop information terminals, digital signage, and large-screen game consoles such as pinball machines, digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices. Furthermore, by incorporating the GPU or chip according to one aspect of the present invention into an electronic device, the electronic device can possess artificial intelligence.

[0571] An electronic device according to one aspect of the present invention may also include an antenna. By receiving signals through the antenna, images or information can be displayed on a display unit. Furthermore, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0572] An electronic device according to one aspect of the present invention may also include a sensor (the sensor having the function of measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation).

[0573] An electronic device according to one aspect of the present invention can have various functions. For example, it can have the following functions: displaying various information (static images, animated images, text images, etc.) on a display unit; a touch panel; displaying a calendar, date, or time; executing various software (programs); performing wireless communication; reading programs or data stored in a storage medium; etc. Figures 26A to 26H Examples of electronic devices are shown.

[0574] [Information Terminal]

[0575] Figure 26A A mobile phone (smartphone) is shown as one of the information terminals. The information terminal 5100 includes a housing 5101 and a display unit 5102. The display unit 5102 has a touch panel as an input interface, and buttons are provided on the housing 5101.

[0576] By applying a chip according to one aspect of the present invention to an information terminal 5100, applications utilizing artificial intelligence can be executed. Examples of such applications utilizing artificial intelligence include applications that identify a session and display the content of that session on a display unit 5102, applications that identify text or graphics input by a user to a touch panel provided with the display unit 5102 and display that text or graphics on the display unit 5102, and applications that perform biometric identification such as fingerprints or voiceprints.

[0577] Figure 26B A notebook-type information terminal 5200 is shown. The notebook-type information terminal 5200 includes an information terminal body 5201, a display unit 5202, and a keyboard 5203.

[0578] Similar to the aforementioned information terminal 5100, by applying a chip according to one aspect of the present invention to the notebook information terminal 5200, applications utilizing artificial intelligence can be executed. Examples of such applications utilizing artificial intelligence include design support software, document proofreading software, and automatic menu generation software. Furthermore, by using the notebook information terminal 5200, novel artificial intelligence technologies can be developed.

[0579] Note that in the example above, Figure 26A and Figure 26B Examples of smartphones and laptops as electronic devices are shown, but other information terminals besides smartphones and laptops can also be applied. Examples of information terminals other than smartphones and laptops include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0580] [Game console]

[0581] Figure 26C A portable game console 5300 is shown as an example of a game console. The portable game console 5300 includes a frame 5301, a frame 5302, a frame 5303, a display unit 5304, a connector 5305, and operation keys 5306. Frames 5302 and 5303 can be detached from frame 5301. By attaching the connector 5305 provided in frame 5301 to another frame (not shown), the image output to display unit 5304 can be output to another video display device (not shown). At this time, frames 5302 and 5303 can each be used as controllers. Thus, multiple players can play games simultaneously. Chips, etc., as shown in the above embodiment, can be embedded in the substrates provided in frames 5301, 5302, and 5303.

[0582] in addition, Figure 26DThe image shows a stationary game console 5400, one of the game consoles. The stationary game console 5400 is connected to a controller 5402 via wireless or wired connection.

[0583] By applying a GPU or chip according to one aspect of the present invention to game consoles such as the portable game console 5300 and the stationary game console 5400, a low-power game console can be achieved. Furthermore, the low power consumption reduces heat generation from the circuitry, thereby minimizing the negative impacts of heat generation on the circuitry itself, peripheral circuits, and modules.

[0584] Furthermore, by applying a GPU or chip according to one aspect of the present invention to a portable game console 5300, a portable game console 5300 with artificial intelligence can be realized.

[0585] The progress of a game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are normally governed by the game's programming. However, by applying artificial intelligence to the portable game console 5300, it is possible to achieve performances that are not limited to the game's programming. For example, it is possible to display the content of the player's questions, the progress of the game, the time elapsed, and changes in the behavior of characters appearing in the game.

[0586] Furthermore, when playing games that require multiple players using the portable game console 5300, artificial intelligence can be used to create human-like game players, allowing one person to play multiplayer games as an opponent.

[0587] Although Figure 26C and Figure 26D Portable and stationary game consoles are shown as examples of game consoles, but game consoles using GPUs or chips according to one aspect of the present invention are not limited to these. Examples of game consoles using GPUs or chips according to one aspect of the present invention include arcade game consoles installed in entertainment facilities (game centers, amusement parks, etc.) and ball-throwing machines installed in sports facilities.

[0588] [Mainframe Computer]

[0589] A GPU or chip based on one aspect of this invention can be applied to large-scale computers.

[0590] Figure 26E The image shows the Supercomputer 5500 as an example of a large computer. Figure 26F The image shows the rack-mount computer 5502 included in the supercomputer 5500.

[0591] The supercomputer 5500 includes a rack 5501 and multiple rack-mounted computers 5502. Note that the multiple computers 5502 are housed in the rack 5501. Additionally, each computer 5502 has multiple substrates 5504 on which the GPU or chip described in the above embodiments can be mounted.

[0592] The Supercomputer 5500 is primarily a large-scale computer suitable for scientific computing. Scientific computing requires massive calculations at high speeds, resulting in high power consumption and significant chip heat generation. By applying a GPU or chip according to one aspect of this invention to the Supercomputer 5500, a low-power supercomputer can be realized. Furthermore, the low power consumption reduces heat generation from the circuitry, thereby minimizing the negative impacts of heat on the circuitry itself, peripheral circuits, and modules.

[0593] exist Figure 26E and Figure 26F The example shown is a supercomputer, but the supercomputer using a GPU or chip according to one aspect of the present invention is not limited to this. Examples of supercomputers using a GPU or chip according to one aspect of the present invention include service-providing computers (servers), large general-purpose computers (hosts), etc.

[0594] [Moving Object]

[0595] One embodiment of the present invention, the GPU or chip, can be applied to a car as a moving body and the area around the driver's seat of the car.

[0596] Figure 26G This is a diagram showing the perimeter of the windshield inside a car interior, illustrating an example of a moving object. Figure 26G Display panels 5701, 5702, and 5703 are shown mounted on the dashboard, and display panel 5704 is mounted on the support column.

[0597] Display panels 5701 to 5703 can provide various other information by displaying speedometer, tachometer, distance traveled, fuel gauge, gear position, air conditioning settings, etc. Furthermore, users can appropriately change the displayed content and layout of the display panels according to their preferences, enhancing design flexibility. Display panels 5701 to 5703 can also be used as lighting devices.

[0598] By displaying images captured by a camera (not shown) installed in the vehicle on display panel 5704, blind spots (obstructions to the view) can be filled. In other words, by displaying images captured by a camera installed on the exterior of the vehicle, blind spots can be filled, thereby improving safety. Furthermore, by displaying images that supplement areas that are not visible, safety can be confirmed more naturally and comfortably. Display panel 5704 can also be used as a lighting device.

[0599] Because the GPU or chip of one aspect of the present invention can be used as a component of artificial intelligence, for example, the chip can be used in an autonomous driving system for automobiles. The chip can also be used in systems for navigation, hazard prediction, etc. Furthermore, navigation, hazard prediction, and other information can be displayed on display panels 5701 to 5704.

[0600] While the automobile was used as an example of a mobile body in the above example, mobile bodies are not limited to automobiles. For example, trams, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles, airplanes, rockets) can also be cited as mobile bodies, and the chip of one aspect of the present invention can be applied to these mobile bodies to provide a system utilizing artificial intelligence.

[0601] [Electrical Products]

[0602] Figure 26H An example of an electrical appliance is shown: an electric refrigerator / freezer 5800. The electric refrigerator / freezer 5800 includes a frame 5801, a refrigerator door 5802, and a freezer door 5803, etc.

[0603] By applying a chip according to one aspect of the present invention to an electric refrigerator / freezer 5800, an electric refrigerator / freezer 5800 equipped with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator / freezer 5800 can have the function of automatically generating a menu based on the food stored in the electric refrigerator / freezer 5800 or the consumption period of the food, and automatically adjusting the temperature of the electric refrigerator / freezer 5800 according to the stored food.

[0604] Electric refrigerators and freezers are one example of electrical appliances, but other electrical appliances that can be cited include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners (including air conditioners with heating and cooling), washing machines, dryers, and audio-visual equipment.

[0605] The electronic device described in this embodiment, its functions, examples of artificial intelligence applications, and their effects can be implemented by appropriately combining them with descriptions of other electronic devices.

[0606] This embodiment can be implemented by appropriately combining it with the structures described in other embodiments, etc.

[0607] (Implementation Method 7)

[0608] In this embodiment, the market image of using OS transistors is explained.

[0609] <Market Image>

[0610] First of all, Figure 27 The image shown illustrates the market potential of using OS transistors. Figure 27 In this diagram, region 701 represents a product region (OS Display) that can be applied to a display using OS transistors; region 702 represents a product region (OS LSI analog) that can be applied to an LSI (Large Scale Integration) using OS transistors for analog processing; and region 703 represents a product region (OS LSI digital) that can be applied to an LSI using OS transistors for digital processing. OS transistors can be preferably applied to... Figure 27 The three regions shown, 701, 702 and 703, can be preferably applied to three large markets.

[0611] In addition, Figure 27 In the diagram, region 704 represents the region where regions 701 and 702 overlap, region 705 represents the region where regions 702 and 703 overlap, region 706 represents the region where regions 701 and 703 overlap, and region 707 represents the region where regions 701, 702, and 703 all overlap.

[0612] In OS displays, FET structures such as bottom-gate OS FETs (BG OSFETs) and top-gate OS FETs (TG OS FETs) can be preferably used. Note that bottom-gate OS FETs include channel-etched FETs and channel-protected FETs. Additionally, top-gate OS FETs include TGSA (Top Gate Self-Aligned) FETs.

[0613] Furthermore, in OS LSI analog and OS LSI digital, a Gate Last type OS FET (GL OS FET) can preferably be used, for example.

[0614] Note that the transistors mentioned above include single-gate transistors with one gate electrode, dual-gate transistors with two gate electrodes, or transistors with three or more gate electrodes. Furthermore, S-channel transistors are particularly preferred among dual-gate transistors.

[0615] Furthermore, products included in the OS Display (area 701) include those that use LCD (liquid crystal display), EL (electro luminescence), and LED (light emission diode) display devices. Additionally, a combination of the aforementioned display device and a Q-Dot (quantum dot) is also preferred.

[0616] Furthermore, in this embodiment, EL includes organic EL and inorganic EL. Additionally, in this embodiment, LED includes Micro LED, Mini LED, and Macro LED. Also, in this specification, the chip area is sometimes described as 10000 μm. 2 The light-emitting diodes described below are referred to as Micro LEDs, with a chip area greater than 10000μm. 2 And 1mm 2 The following light-emitting diodes are referred to as Mini LEDs, with a chip area greater than 1 mm². 2 The light-emitting diode is recorded as a Macro LED.

[0617] In addition, products included in the OS LSI analog (area 702) include sound source localization devices or battery control devices (battery control IC, battery protection IC or battery management system) that correspond to various frequency ranges (e.g., audible sounds with a frequency of 20Hz or higher and lower than 20kHz, or ultrasound with a frequency of 20kHz or higher).

[0618] In addition, products included in OS LSI digital (area 703) include storage devices, CPU (Central Processing Unit) devices, GPU (Graphics Processing Unit) devices, FPGA (field-programmable gate array) devices, power devices, hybrid devices that stack or mix OS LSI and Si LSI, light-emitting devices, etc.

[0619] Furthermore, products included in area 704 can include display devices that include infrared or near-infrared sensors in the display area, signal processing devices equipped with sensors having OS FETs, or embedded biosensor devices. Additionally, products included in area 705 can include processing circuits including A / D (analog-to-digital) conversion circuits, or AI (Artificial Intelligence) devices including such processing circuits. Furthermore, products included in area 706 can include display devices applying Pixel AI technology. In this specification, Pixel AI technology refers to a technology that utilizes memory comprised of OS FETs or similar components installed in the pixel circuitry of a display.

[0620] In addition, as a product included in region 707, a composite product combining all the products included in regions 701 to 706 can be cited.

[0621] As described above, one aspect of the semiconductor device of the present invention is as follows: Figure 27 As shown, it can be applied to various product areas. That is to say, the semiconductor device of one aspect of the present invention can be applied to many markets.

[0622] This embodiment can be implemented by appropriately combining it with the structures described in other embodiments, etc.

[0623] [Symbol Explanation]

[0624] 100: Capacitor, 110: Conductor, 112: Conductor, 114: Insulator, 120: Conductor, 130: Insulator, 140: Insulator, 150: Insulator, 152: Conductor, 153: Conductor, 154: Insulator, 156: Insulator, 160: Insulator, 200: Transistor, 205: Conductor, 210: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 218: Conductor, 222: Insulator, 224: Insulator, 230: Oxide, 230a: Oxide, 230A: Oxide film, 230b: Oxide, 230B: Oxide film, 230c: Oxide, 230C: Oxide film, 240a: Conductor, 2 40A: Conductive film, 240b: Conductor, 240B: Conductive layer, 245a: Insulator, 245A: Insulating film, 245b: Insulator, 245B: Insulator layer, 247: Insulator, 248: Conductor, 250: Insulator, 250A: Insulating film, 254: Insulator, 254a: Insulator, 254b: Insulator, 260: Conductor, 260a: Conductor, 260A: Conductive film, 260b: Conductor, 260B: Conductive film, 280: Insulator, 282: Insulator, 284: Insulator, 290A: Film, 290B: Hard mask, 291: Microwave, 292: Resist mask, 300: Transistor, 311: Substrate, 312: Insulator, 313: Semiconductor Conductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 400: Transistor, 405: Conductor, 405a: Conductor, 405b: Conductor, 430c: Oxide, 431a: Oxide, 431b: Oxide, 432a: Oxide, 432b: Oxide, 440a: Conductor, 440b: Conductor, 445a: Insulator, 445b: Insulator, 450: Insulator, 460 : Conductor, 460a: Conductor, 460b: Conductor, 1001: Wiring, 1002: Wiring, 1003: Wiring, 1004: Wiring, 1005: Wiring, 1006: Wiring, 1007: Wiring, 2001: Wiring, 2002: Wiring, 2003: Wiring, 2004: Wiring, 2005: Wiring, 2006: Wiring, 2007: Wiring, 2008: Wiring, 2009: Wiring, 2010: Wiring, 2700: Manufacturing apparatus, 2701: Atmospheric side substrate supply chamber, 2702: Atmospheric side substrate transfer chamber, 2703a: Loading lock chamber, 2703b: Unloading lock chamber, 2704: Transfer chamber, 2706a: Processing chamber, 2706b: Processing chamber2706c: Processing Chamber; 2706d: Processing Chamber; 2761: Box Interface; 2762: Alignment Interface; 2763a: Transfer Robot; 2763b: Transfer Robot; 2801: Gas Supply Source; 2802: Valve; 2803: High Frequency Generator; 2804: Waveguide; 2805: Mode Converter; 2806: Gas Pipe; 2807: Waveguide; 2808: Slotted Antenna Plate; 2809: Dielectric Plate; 2810: High-Density Plasma Substrate, 2811: Substrate, 2812: Substrate holder, 2813: Heating mechanism, 2815: Matching device, 2816: High-frequency power supply, 2817: Vacuum pump, 2818: Valve, 2819: Exhaust port, 2820: Lamp, 2821: Gas supply source, 2822: Valve, 2823: Gas inlet, 2824: Substrate, 2825: Substrate holder, 2826: Heating mechanism, 2828: Vacuum pump, 2829: Valve, 2830: Exhaust port.

Claims

1. A method for manufacturing a transistor, comprising the following steps: The first step of forming an indium-containing metal oxide on a substrate; The second step of forming a first conductor on the metal oxide; The third step of forming a first insulator on the first conductor; A fourth step involves forming an opening in the first conductor and the first insulator that leads to the metal oxide. The fifth step of forming a second insulator in the opening; The sixth step involves microwave treatment of the second insulator; as well as A seventh step, following the sixth step, involves forming a second conductor in the opening, wherein the second conductor overlaps with the metal oxide via the second insulator. The sixth step is carried out under reduced pressure and using a gas containing oxygen. Furthermore, the sixth step separates the defects of oxygen vacancies in the metal oxide into oxygen vacancies and hydrogen vacancies.

2. A method for manufacturing a transistor, comprising the following steps: The first step of forming an indium-containing metal oxide on a substrate; The second step of forming a first conductor on the metal oxide; The third step of forming a first insulator on the first conductor; A fourth step involves forming an opening in the first conductor and the first insulator that leads to the metal oxide. The fifth step of forming a second insulator in the opening; The sixth step involves microwave treatment of the second insulator; A seventh step involving heat treatment following the sixth step; as well as An eighth step, following the seventh step, involves forming a second conductor in the opening. The second conductor overlaps with the metal oxide through the second insulator. The sixth step is carried out under reduced pressure and using a gas containing oxygen. The seventh process is performed under reduced pressure. The sixth step separates the defects of hydrogen entering oxygen vacancies in the metal oxide into oxygen vacancies and hydrogen. Furthermore, the seventh step reduces oxygen vacancies in the metal oxide.

3. A method for manufacturing a transistor, comprising the following steps: The first step of forming an indium-containing metal oxide on a substrate; The second step of forming a first conductive layer on the metal oxide; The third step of forming a first insulator on the first conductive layer; A fourth step involves forming openings in the first conductive layer and the first insulator to reach the metal oxide in order to form a first conductor and a second conductor on the metal oxide. The fifth step of forming a second insulator in the opening; The sixth step involves microwave treatment of the second insulator; A seventh step involving heat treatment following the sixth step; as well as An eighth step, following the seventh step, involves forming a third conductor in the opening. The third conductor overlaps with the metal oxide through the second insulator. The sixth step is carried out under reduced pressure and using a gas containing oxygen. The seventh process is performed under reduced pressure. The sixth step separates the defects of hydrogen entering oxygen vacancies in the metal oxide into oxygen vacancies and hydrogen. Furthermore, the seventh step reduces oxygen vacancies in the metal oxide and allows hydrogen in the metal oxide to diffuse into the first and second conductors.

4. A method for manufacturing a transistor, comprising the following steps: The first step of forming an indium-containing metal oxide on a substrate; The second step of forming a first conductive layer on the metal oxide; The third step of forming a first insulator on the first conductive layer; A fourth step involves forming openings in the first conductive layer and the first insulator to reach the metal oxide in order to form a first conductor and a second conductor on the metal oxide. The fifth step of forming a second insulator in the opening; The sixth step involves microwave treatment of the second insulator; A seventh step involving heat treatment following the sixth step; An eighth step, following the seventh step, to form a third conductor in the opening; and The ninth step involves chemically and mechanically polishing (CMP) the third conductor and the second insulator until the first insulator is exposed. The third conductor overlaps with the metal oxide through the second insulator. The sixth step is carried out under reduced pressure and using a gas containing oxygen. The seventh process is performed under reduced pressure. The sixth step separates the defects of hydrogen entering oxygen vacancies in the metal oxide into oxygen vacancies and hydrogen. Furthermore, the seventh step reduces oxygen vacancies in the metal oxide and allows hydrogen in the metal oxide to diffuse into the first and second conductors.

5. The method for manufacturing a transistor according to any one of claims 2 to 4, The temperature of the heat treatment is above 300°C and below 500°C.

6. The method for manufacturing a transistor according to any one of claims 1 to 4, The pressure of the microwave treatment is above 133 Pa.

7. The method for manufacturing a transistor according to any one of claims 1 to 4, The first step is performed using an indium-containing oxide target by sputtering.

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