Radar signal modulator with bandwidth compensation and frequency offset sequence

Abstract

The present disclosure relates to a radar signal modulator with bandwidth compensation and a frequency offset sequence. For example, a system, method, and circuit device for generating a frequency-hopping radar signal are provided. In one example, the radar signal modulator includes a frequency offset generator, a phase-locked loop (PLL), and bandwidth compensation circuitry. The frequency offset generator is configured to generate a frequency offset sequence. The bandwidth compensation circuitry is configured to combine a modulated signal with the frequency offset sequence to generate a bandwidth-compensated signal. The PLL is configured to receive the bandwidth compensation signal and generate a frequency-hopping radar signal based on the bandwidth compensation signal.

Description

Technical Field

[0001] The present invention relates to the field of radar circuits, and in particular to a method, a system and a circuit arrangement for generating a radar signal for detecting an object. Background Art

[0002] Radio frequency (RF) transceivers can be found in a variety of applications, particularly in the fields of wireless communications and radar sensors. Within the automotive industry, there is an increasing demand for radar sensors to detect vehicles and other objects in the vicinity of the sensor-equipped vehicle. Frequency-modulated continuous wave (FMCW) radar systems use radar signals whose frequency is modulated by varying the signal frequency up and down in a predetermined pattern. One type of such radar signal is known as a "chirp signal," or simply chirp, where the frequency of the transmitted signal increases in a positive chirp (up-chirp) and decreases in a negative chirp (down-chirp). Summary of the Invention

[0003] According to one aspect of the present disclosure, a radar signal modulator is provided, comprising: a frequency offset generator configured to generate a frequency offset sequence; a phase-locked loop (PLL); and a bandwidth compensation circuit device configured to combine a modulation signal with the frequency offset sequence to generate a bandwidth compensation signal, wherein the PLL is configured to receive the bandwidth compensation signal and generate a frequency-hopping radar signal based on the bandwidth compensation signal.

[0004] In some embodiments, the frequency offset generator is configured to generate a random frequency offset sequence.

[0005] In certain embodiments, the frequency offset generator is configured to generate a frequency offset sequence that encodes frequency shift keying (FSK) or phase shift keying (PSK) information.

[0006] In some embodiments, the bandwidth compensation circuit device includes: a low-pass injection circuit device, configured to: receive the modulated signal; receive the frequency offset sequence; and generate at least one low-pass injection signal based on the frequency offset sequence and the modulated signal; and a high-pass injection circuit device, configured to: receive the modulated signal; receive the frequency offset sequence; and generate at least one high-pass injection signal based on the frequency offset sequence and the modulated signal, so that the bandwidth compensation signal includes the low-pass injection signal and the high-pass injection signal, wherein the PLL is configured to: receive the at least one low-pass injection signal at a low-pass injection point; receive the at least one high-pass injection signal at a high-pass injection point; and generate the frequency hopping radar signal based on the at least one low-pass injection signal and the at least one high-pass injection signal.

[0007] In some embodiments, the high-pass injection circuit device includes: a gain estimation circuit device, configured to determine the gain of the at least one high-pass injection signal based on the sensed phase error of the phase-locked loop; a first combination circuit device, configured to combine the modulation signal with the frequency offset sequence to generate a frequency-hopping modulation signal; and a multiplier, configured to scale the frequency-hopping modulation signal based on the gain to generate the at least one high-pass injection signal.

[0008] In certain embodiments: the low-pass injection circuit device includes a second combination circuit device, which is configured to combine the modulation signal with the frequency offset sequence and the frequency command word for the phase-locked loop to generate an adjusted frequency command word; and the polarity of at least one of the modulation signal or the frequency offset sequence input to the first combination circuit device is reversed relative to the corresponding modulation signal or the corresponding frequency offset sequence input to the second combination circuit device.

[0009] In certain embodiments, the high-pass injection circuit device includes: a modulation path gain estimation circuit device, configured to determine a first gain of the modulation signal based on a sensed phase error of the phase-locked loop; a first multiplier, configured to scale the modulation signal based on the first gain to generate a first high-pass injection signal, and provide the first high-pass injection signal to a first high-pass injection point; an offset path gain estimation circuit device, configured to determine a second gain of the frequency offset sequence based on the sensed phase error of the phase-locked loop; and a second multiplier, configured to scale the frequency offset sequence based on the second gain to generate a second high-pass injection signal, and provide the second high-pass injection signal to a second high-pass injection point.

[0010] In certain embodiments, the first high-pass injection point is coupled to a first capacitor bank in an oscillator circuit of the phase-locked loop, and the second high-pass injection point is coupled to a second capacitor bank in the oscillator circuit.

[0011] In some embodiments, the high-pass injection circuit device includes: a pre-distortion circuit device, configured to determine a first gain of the modulated signal and a second gain of the frequency offset sequence to minimize the phase error of the phase-locked loop; a first multiplier, configured to scale the modulated signal based on the first gain to generate a first high-pass injection signal, and provide the first high-pass injection signal to a first high-pass injection point; and a second multiplier, configured to scale the frequency offset sequence based on the second gain to generate a second high-pass injection signal, and provide the second high-pass injection signal to a second high-pass injection point.

[0012] In certain embodiments, the first high-pass injection point is coupled to a first capacitor bank in an oscillator circuit of the phase-locked loop, and the second high-pass injection point is coupled to a second capacitor bank in the oscillator circuit.

[0013] In some embodiments, the low-pass injection circuit device includes a second combination circuit device, which is configured to: combine the modulated signal with the frequency offset sequence and the frequency command word for the phase-locked loop to generate an adjusted frequency command word; and provide the adjusted frequency command word to a divider circuit device in the phase-locked loop.

[0014] In some embodiments, the bandwidth compensation circuit device includes: a combination circuit device configured to combine the modulated signal with the frequency offset sequence and a frequency command word for the phase-locked loop to generate an adjusted frequency command word; and a pre-emphasis filter to filter the adjusted frequency command word to generate the bandwidth compensation signal.

[0015] In certain embodiments, the bandwidth compensation circuitry includes bandwidth estimation circuitry configured to: estimate a bandwidth of the modulated signal; and control the pre-emphasis filter based on the estimated bandwidth.

[0016] In addition, according to another aspect of the present disclosure, a method for generating a frequency-hopping radar signal is provided, comprising: generating a frequency offset sequence; combining the frequency offset sequence with a modulation signal to generate a bandwidth compensation signal; and providing the bandwidth compensation signal to a phase-locked loop (PLL) so that the PLL generates the frequency-hopping radar signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Some examples of circuits, devices and / or methods are described below by way of example only. In this context, reference will be made to the accompanying drawings.

[0018] Figure 1 An example FMCW radar system that senses target and interfering objects is shown.

[0019] Figure 1A is a diagram showing the frequency and time relationship between transmit and receive signals in an FMCW radar system.

[0020] Figure 1B is a diagram showing a frequency spectrum of a beat frequency including contributions from a target object and contributions from interfering objects.

[0021] Figure 2 An exemplary radar signal modulator in accordance with various aspects described is shown.

[0022] Figure 3 Shown according to various aspects described Figure 2 An exemplary embodiment of a radar signal modulator.

[0023] Figure 3A Shown according to various aspects described Figure 3 Another exemplary embodiment of a radar signal modulator.

[0024] Figure 3B Shown according to various aspects described Figure 3 Another exemplary embodiment of a radar signal modulator.

[0025] Figure 3C Shown according to various aspects described Figure 3 Another exemplary embodiment of a radar signal modulator.

[0026] Figure 4 Shown according to various aspects described Figure 2 An exemplary embodiment of a radar signal modulator.

[0027] Figure 4A Shown according to various aspects described Figure 4 Another exemplary embodiment of a radar signal modulator.

[0028] Figure 5 An example method for generating a frequency hopping radar signal in accordance with various aspects described is shown. DETAILED DESCRIPTION

[0029] Figure 1 An FMCW radar system 100 is shown, which detects target objects traveling at a velocity v. System 100 includes a transmit chain 110 having a modulator circuit 120, which controls an oscillator circuit 130 to generate a chirp signal at the system's operating frequency. The chirp signal is amplified by a power amplifier (PA) 180 and broadcast by an antenna 181. A receive chain 190 includes an antenna 191, which receives a signal including an echo (a reflection of the transmitted chirp signal). The received signal is amplified by a low-noise amplifier (LNA) 192 and combined with the chirp signal by a mixer 193. The mixing process generates a signal (referred to as a beat signal) with a phase equal to the phase difference between the transmitted and received signals. A low-pass filter 194 filters the beat signal, which is then converted to a digital signal by an analog-to-digital converter (ADC) 195. This digital signal is processed by digital signal processing (DSP) circuitry 196 to determine the distance between system 100 and surrounding objects.

[0030] Figure 1AAn example of a transmitted chirp (solid line), a received chirp (dashed line), and an interference signal INT (bold line) is shown. The slope SL of the ramp is known, and the frequency difference (beat frequency f) between the transmitted and received signals is calculated by the DSP 196 based on the measured phase difference between the signals. b The beat frequency and SL are used to derive the time delay τ between the transmitted chirp and the received chirp. This time delay provides an indication of the distance between the system 100 and the object that reflected the echo signal. The beat frequency includes the Doppler component f Dop This Doppler component may be analyzed across multiple chirps to determine the relative velocity between the system 100 and the object.

[0031] Figure 1B An example of a beat frequency spectrum analyzed by the DSP 196 to detect a target object is shown. Frequencies with relatively high amplitudes are identified as indicative of an object. The contribution of the echo from the target object is in the F TAR The first peak is generated at F, while the contribution of the interference source is at F INT It can be seen that ghost targets can cause inaccuracies when the system 100 detects the target object.

[0032] The increasing number of vehicles equipped with FMCW radar systems increases the probability of interference between vehicles. Various methods are used to mitigate the effects of interference in FMCW radar systems. However, many mitigation techniques involve complex signal generators and / or software-based modifications to the chirp. These solutions are inherently slow and involve expensive processing components.

[0033] Described herein are methods, systems, and circuit arrangements for generating a frequency-hopping radar signal that changes frequency. The described methods, systems, and circuit arrangements use bandwidth compensation circuitry to generate the signal, wherein the bandwidth compensation circuitry generates a bandwidth-compensated signal that is input to a phase-locked loop (PLL) without requiring complex waveform generators or software, thereby providing effective interference mitigation with minimal expense.

[0034] Figure 2 An exemplary radar system 200 is shown that utilizes frequency-hopping radar signals to detect objects. Many examples in this specification describe frequency-hopping radar signals as "chirp" signals. However, it should be understood that other FMCW signal frequencies (e.g., triangle, square, step, sinusoidal, or any other FMCW signal) can also be used for interference mitigation using the described methods, systems, and circuit arrangements. Furthermore, the described methods, systems, and circuit arrangements can also be used for phase-modulated radar signals.

[0035] Radar system 200 includes many of the same or similar components as radar system 100, including a receive chain 190, a transmit power amplifier 180, and an antenna 181. For simplicity, the functions of these components will not be repeated here. As with system 100, modulator circuitry 120 generates a modulated signal, which in the illustrated example is a sawtooth signal. The modulated signal is provided to radar signal modulator 140, which includes bandwidth compensation circuitry 150, a PLL 130, and a frequency offset generator 179. Frequency offset generator 179 generates a sequence of offset values and transmits or stores them for access by bandwidth compensation circuitry 150. Frequency offset generator 179 can be a combination of any suitable hardware components and / or software algorithms that generate a sequence of offset values. Frequency offset generator 179 can generate a random sequence of offset values. In some examples, the frequency offset generator can generate a sequence of offset values that encodes frequency shift keying (FSK) or phase shift keying (PSK) information to be exchanged with other radar receivers.

[0036] Bandwidth compensation circuitry 150 combines the modulation signal with the frequency offset sequence to generate a version of the modulation signal with increased bandwidth (hereinafter referred to as the "bandwidth compensation signal"). The bandwidth compensation signal can be characterized as an adaptive modulation signal that, combined with the PLL transfer function, forms an all-pass transfer function from the modulation signal input to the PLL output. In one example, the bandwidth compensation signal has a bandwidth greater than the bandwidth of PLL 130. The use of such a bandwidth compensation signal overcomes the linear frequency modulation speed limitation caused by the narrow bandwidth of the PLL.

[0037] exist Figure 3-3C In one example shown, the bandwidth compensation circuitry is implemented as a high-pass injection circuitry and a low-pass injection circuitry configured to generate bandwidth compensation signals in the form of a low-pass injection signal and a high-pass injection signal for the PLL 130. Figure 4-4A In another example shown, the bandwidth compensation circuitry includes a pre-emphasis filter that operates on the frequency hopping modulated signal to generate a bandwidth compensation signal that is injected into the PLL 130 to compensate for the low-pass transfer function of the PLL.

[0038] Figure 3A radar system 200 is shown in which the bandwidth compensation circuitry is implemented as a high-pass injection circuitry 250a and a low-pass injection circuitry 250b. The radar signal modulator 240 includes a PLL 230, a frequency offset generator 179, and the high-pass injection circuitry 250a and the low-pass injection circuitry 250b. In one example, the high-pass injection circuitry 250a, the low-pass injection circuitry 250b, and the PLL 130 are integrated into the same semiconductor chip. The high-pass injection circuitry 250a generates a high-pass injection signal (solid line), while the low-pass injection circuitry 250b generates a low-pass injection signal (dashed line). The high-pass injection signal is injected into the PLL 230 at a high-pass injection point (HPIP). The low-pass injection signal is injected into the PLL 230 at a low-pass injection point (LPIP). This pair of signals functionally corresponds to Figure 2 The bandwidth compensation signal in is used to compensate for the narrow bandwidth of the PLL 230.

[0039] Figure 3A Shown Figure 2 3. An example of a radar signal modulator 340 for radar system 200. Digital PLL 330 includes a digitally controlled oscillator (DCO) 336, a digital loop filter 334, a phase detector 332, and a divider circuit 337. Phase detector 332 (which in some examples may be a time-to-digital converter (TDC)) receives the (divided) feedback signal from the DCO and a reference signal having some predetermined (e.g., clock) frequency. The phase detector converts the delay between the reference signal and the feedback signal into a digital error signal e[k]. The error signal is the difference between the reference signal (including phase and frequency) and the (divided) feedback signal. Digital loop filter 334 filters noise from the error signal e[k]. In some examples, digital loop filter 334 may include high-pass and low-pass filter functionality.

[0040] Divider circuitry 337 (which in some examples may be a multi-mode divider (MMD)) divides the signal generated by DCO 336 by any one of a plurality of divisors, one of which is selected by a low-pass injection signal n[k]. Divider circuitry 337 (which may be characterized as LPIP for a PLL) performs a frequency divider function on the signal output by the DCO, reducing the signal's frequency to the frequency range of a reference signal. The reference signal, which has a lower frequency than the DCO output signal, can be used to compensate for the frequency capability of phase detection circuitry 332. Divider circuitry 337 receives the selected divisor n in the form of a frequency command word (FCW) specifying n[k]. DCO 336 includes tuning circuitry (not shown), such as a capacitor bank, that adjusts the frequency of the signal generated by the DCO. The tuning circuitry (which may be characterized as HPIP for a PLL) is controlled by a tuning signal m[k]. As can be seen, manipulating the divisor n[k] or the tuning signal m[k] changes the DCO's output signal.

[0041] Radar signal modulator 340 generates a frequency hopping radar signal using two-point injection into PLL 330. In this two-point injection scheme, divisor n[k] corresponds to the low-pass injection signal, while tuning signal m[k] corresponds to the high-pass injection signal. Recall that the low-pass injection signal and the high-pass injection signal together correspond to Figure 2 bandwidth compensation signal. On the low-pass path (shown in dashed lines), the low-pass injection circuit device 350b generates a low-pass injection signal n[k] based on the modulation signal mod[k] and the frequency offset sequence off[k] (which can be random or can also encode FSK or PSK information). The low-pass injection circuit device 350b includes a combination circuit device 362, which adjusts the FCW by combining it with a "negative" modulation signal -mod[k] and a negative frequency offset -off[k]. In other examples, the FCW can be adjusted by combining it with a positive modulation signal mod[k] and / or a positive frequency offset off[k]. The delta-sigma modulator 364 receives the adjusted frequency command word output by the combination circuit device 362 to incrementally adjust the sequence value of the n[k] signal between integers to implement fractional division by the divider circuit device 337 when needed.

[0042] In the high-pass path (shown in bold), high-pass injection circuitry 350a includes combining circuitry 374 that combines the modulation signal mod[k] with the frequency offset sequence off[k] to generate a frequency-hopping modulation signal. High-pass injection circuitry 350a includes gain circuitry, which includes gain estimation circuitry 372 and a multiplier (e.g., mixer) 376. Gain estimation circuitry 372 determines (e.g., using a least mean square (LMS) algorithm) the mismatch between the transfer function of the high-pass path and the transfer function of the low-pass path based on the sensed error signal e[k] and calculates a gain g1 that, when applied to the modulation signal, compensates for the mismatch. In one example, the gain estimation circuitry is configured to determine a gain g1 for at least one high-pass injection signal that minimizes the correlation between the sensed phase error e[k] of the phase-locked loop (determined by the phase detection circuitry 332) and the modulation signal. Multiplier (e.g., mixer) 376 scales the modulated signal by gain g1 and provides the resulting scaled signal as a high-pass injection signal to the tuning circuitry of DCO 336. In this manner, radar signal modulator 340 generates a frequency-hopping radar signal.

[0043] exist Figure 3A In the example shown, the combining circuit means 362 of the low-pass injection circuit means combines the mod[k] signal and the off[k] signal having a first polarity (e.g., “negative”), while the combining circuit means 374 of the high-pass injection circuit means combines the corresponding mod[k] signal and the off[k] signal having an opposite polarity (e.g., “positive”). In other words, in Figure 3A In the example, the polarity of at least one of the modulation signal mod[k] or the frequency offset sequence off[k] input to the combination circuit device 362 is reversed relative to the corresponding modulation signal mod[k] or the frequency offset sequence off[k] input to the combination circuit device 374.

[0044] Figure 3B Shown Figure 2 Another example of a radar signal modulator 440 of the radar system 200 is shown in FIG. The radar signal modulator 440 includes Figure 3A The radar signal modulator 440 includes a PLL 430, which includes a low-pass injection circuit device 350b to generate a low-pass injection signal. Figure 3A 330 , except that the DCO 436 of the PLL 430 has a tuning circuit arrangement including individually controllable capacitor banks.

[0045] Radar signal modulator 440 includes high-pass injection circuitry 450a, which generates high-pass injection signals by generating separate high-pass injection signals for the first and second capacitor banks of DCO 430. Thus, the two different capacitor banks can be characterized as the first and second HPIPs of the PLL. A first high-pass injection signal, m[k], is generated based on the modulated signal, and a second high-pass injection signal, r[k], is generated based on the frequency offset sequence.

[0046] High-pass injection circuitry 450a includes modulation path gain estimation circuitry 474, which determines the mismatch between the transfer function of the high-pass path and the transfer function of the low-pass path of the modulation signal based on the sensed phase error e[k] of the PLL (output by phase detection circuitry 332). Gain estimation circuitry 474 calculates a gain g1 that, when applied to the modulation signal, compensates for the mismatch. In one example, modulation path gain estimation circuitry 474 is configured to determine a gain for the modulation signal that minimizes the correlation between the sensed phase error signal e[k] of the PLL and the modulation signal. The modulation signal is scaled by gain g1 via multiplier (e.g., mixer) 478 and provided to a first high-pass injection point (e.g., a first capacitor bank) of DCO 436.

[0047] High-pass injection circuitry 450a includes offset path gain estimation circuitry 473, which determines the mismatch between the transfer function of the high-pass path and the transfer function of the low-pass path for the frequency offset sequence based on the sensed phase error e[k] of the PLL. Offset path gain estimation circuitry 473 calculates a gain g2, which, when applied to the frequency offset sequence, compensates for the mismatch. In one example, offset path gain estimation circuitry 473 is configured to determine a gain for the frequency offset sequence that minimizes the correlation between the sensed phase error e[k] and the frequency offset sequence. The frequency offset is scaled by gain g2 via multiplier (e.g., mixer) 476 and provided to a second high-pass injection point (e.g., a second capacitor bank) of DCO 436. In this manner, radar signal modulator 440 generates a frequency-hopping radar signal. The segmented tuning circuitry employed by high-pass injection circuitry 450a is advantageous because the granularity and linearity requirements of the capacitor bank (tuned by m[k]) are typically higher than those of the capacitor bank (tuned by r[k]).

[0048] In practical designs, the DCO can exhibit nonlinearity due to the 1 / sqrt(LC) dependence of the oscillation frequency on the tuning capacitance, mismatch, and distributed inductance. Figure 3C Shown Figure 2 Another example of a radar signal modulator 540 of the radar system 200. The radar signal modulator 540 linearizes the DCO using predistortion applied at the high-pass injection point (instead of Figure 3A and Figure 3B The radar signal modulator 540 includes the following: Figure 3A The same or similar low-pass injection circuit device 350b for generating a low-pass injection signal and Figure 3B The same or similar PLL 430. However, the high-pass injection circuitry 550a includes predistortion circuitry 571 that determines predistortion coefficients to be applied to the various frequency components of the frequency offset sequence off[k] and the modulation signal mod[k] by multipliers (e.g., mixers) 576, 578. The predistortion circuitry 571 determines the coefficients to minimize the sensed phase error signal e[k].

[0049] Figure 4 A radar signal modulator 640 is shown, which includes a number of Figure 3A-3C The radar signal modulator 640 has the same layout as the radar signal modulator of FIG330, including PLL 330. Radar signal modulator 640 includes bandwidth compensation circuitry 650 that generates a bandwidth compensation signal that is injected into divider 337 of PLL 330. Bandwidth compensation circuitry 650 generates bandwidth compensation signal n[k] based on the modulation signal mod[k] and the frequency offset sequence off[k] (which may be random or may encode FSK or PSK information).

[0050] Bandwidth compensation circuitry 650 includes combining circuitry 662 that adjusts the FCW by combining it with a "negative" modulation signal, -mod[k], and a negative frequency offset, -off[k]. In other examples, the FCW can be adjusted by combining it with a positive modulation signal, mod[k], and / or a positive frequency offset, off[k]. Pre-emphasis filter 652 acts as a high-pass filter for the adjusted FCW signal to compensate for the low-pass transfer function of PLL 330. In one example, pre-emphasis filter 652 performs filtering based on some predetermined assumptions about the bandwidth of the modulation signal. The pre-emphasized adjusted FCW signal generated by the pre-emphasis filter is input to delta-sigma modulator 664. Delta-sigma modulator 664 incrementally adjusts the value of the pre-emphasized adjusted FCW to generate a bandwidth compensation signal, n[k], which includes a signal between integers to implement fractional division, if necessary, by divider circuit 337.

[0051] Figure 4ARadar signal modulator 740 is shown and includes many of the same components as radar signal modulator 640, including PLL 330, combining circuitry 662, and delta-sigma modulator 664. Radar signal modulator 740 includes bandwidth compensation circuitry 750 that generates a bandwidth compensation signal that is injected into divider 337 of PLL 330. Bandwidth compensation circuitry 750 generates bandwidth compensation signal n[k] based on the modulating signal mod[k] and a frequency offset sequence off[k] (which may be random or may encode FSK or PSK information).

[0052] Bandwidth compensation circuitry 750 includes combining circuitry 662 that adjusts the FCW by combining it with a "negative" modulation signal, -mod[k], and a negative frequency offset, -off[k]. In other examples, the FCW can be adjusted by combining it with a positive modulation signal, mod[k], and / or a positive frequency offset, off[k]. Bandwidth estimation circuitry 754 estimates the bandwidth of the modulation signal based on the sensed phase error, e[k], of PLL 330. Pre-emphasis filter 752 is controlled by bandwidth estimation circuitry 754 based on the estimated bandwidth and acts as a high-pass filter for the adjusted FCW signal to compensate for the low-pass transfer function of PLL 330. Pre-emphasis filter 752 filters according to the bandwidth of the modulation signal estimated by bandwidth estimation circuitry 754. The pre-emphasized, adjusted FCW signal generated by the pre-emphasis filter is input to delta-sigma modulator 664. The delta-sigma modulator 664 incrementally adjusts the value of the pre-emphasized adjusted FCW to generate a bandwidth compensation signal n[k] that includes signals between integers to implement fractional division by the divider circuitry 337 when needed.

[0053] Figure 5 An example method 800 for generating a frequency hopping radar signal is shown. For example, the method 800 may be Figure 2-4A The method includes generating a frequency offset sequence at 810. The operations outlined at 810 may be performed by Figure 2-4A The method includes combining the frequency offset sequence with the modulated signal to generate a bandwidth compensation signal at 820. The operations outlined at 820 may be performed by Figure 2-4A In one example, the bandwidth compensation signal has a higher bandwidth than the bandwidth of the PLL into which the bandwidth compensation signal is injected. The method includes generating a frequency hopping radar signal based on the bandwidth compensation signal at 830. The operations outlined in 830 may be performed, for example, by Figure 2-4A The PLL is used to perform

[0054] As can be seen from the foregoing description, the described systems, circuit arrangements, and methods generate random frequency hopping radar signals for object detection without requiring complex circuit arrangements or software solutions.

[0055] While the present invention has been illustrated and described with respect to one or more embodiments, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components or structures (assemblies, devices, circuits, systems, etc.), unless otherwise indicated, terms used to describe such components (including references to "means") are intended to correspond to any component or structure that performs the specified function of the component (e.g., functional equivalent), even if not structurally equivalent to the disclosed structures that perform the functions illustrated in the exemplary embodiments of the invention herein.

[0056] Examples may include subject matter such as a method for generating a frequency modulated radar signal according to the embodiments and examples described herein, an apparatus for performing the actions or blocks of the method, at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform the actions of the method or apparatus or system.

[0057] Example 1 is a radar signal modulator comprising: a frequency offset generator configured to generate a frequency offset sequence; a phase-locked loop (PLL); and bandwidth compensation circuitry configured to combine a modulated signal with the frequency offset sequence to generate a bandwidth compensation signal. The PLL is configured to receive the bandwidth compensation signal and generate a frequency-hopping radar signal based on the bandwidth compensation signal.

[0058] Example 2 includes the subject matter of Example 1, including or omitting the optional elements, wherein the frequency offset generator is configured to generate a random frequency offset sequence.

[0059] Example 3 includes the subject matter of Example 1, including or omitting the optional elements, wherein the frequency offset generator is configured to generate a frequency offset sequence that encodes frequency shift keying (FSK) or phase shift keying (PSK) information.

[0060] Example 4 includes the subject matter of Example 1, including or omitting optional elements, wherein the bandwidth compensation circuitry includes a low-pass injection circuitry and a high-pass injection circuitry. The low-pass injection circuitry is configured to: receive a modulated signal; receive a frequency offset sequence; and generate at least one low-pass injection signal based on the frequency offset sequence and the modulated signal. The high-pass injection circuitry is configured to: receive a modulated signal; receive a frequency offset sequence; and generate at least one high-pass injection signal based on the frequency offset sequence and the modulated signal, such that the bandwidth compensation signal includes the low-pass injection signal and the high-pass injection signal. The PLL is configured to: receive the at least one low-pass injection signal at a low-pass injection point; receive the at least one high-pass injection signal at a high-pass injection point; and generate the frequency-hopping radar signal based on the at least one low-pass injection signal and the at least one high-pass injection signal.

[0061] Example 5 includes the subject matter of Example 4, including or omitting optional elements, wherein the high-pass injection circuit device comprises: a gain estimation circuit device configured to determine the gain of at least one high-pass injection signal based on a sensed phase error of a phase-locked loop; a first combination circuit device configured to combine the modulation signal with a frequency offset sequence to generate a frequency hopping modulation signal; and a multiplier configured to scale the frequency hopping modulation signal based on the gain to generate at least one high-pass injection signal.

[0062] Example 6 includes the subject matter of Example 5, including or omitting optional elements, wherein the low-pass injection circuit device includes: a second combination circuit device configured to combine the modulation signal with the frequency offset sequence and the frequency command word for the phase-locked loop to generate an adjusted frequency command word, and the polarity of at least one of the modulation signal or the frequency offset sequence input to the first combination circuit device is reversed relative to the corresponding modulation signal or the corresponding frequency offset sequence input to the second combination circuit device.

[0063] Example 7 includes the subject matter of Example 4, including or omitting optional elements, wherein the high-pass injection circuit device includes: a modulation path gain estimation circuit device, configured to determine a first gain of the modulation signal based on a sensed phase error of the phase-locked loop; a first multiplier, configured to scale the modulation signal based on the first gain to generate a first high-pass injection signal, and provide the first high-pass injection signal to a first high-pass injection point; an offset path gain estimation circuit device, configured to determine a second gain of the frequency offset sequence based on the sensed phase error of the phase-locked loop; and a second multiplier, configured to scale the frequency offset sequence based on the second gain to generate a second high-pass injection signal, and provide the second high-pass injection signal to a second high-pass injection point.

[0064] Example 8 includes the subject matter of Example 7, including or omitting the optional element, wherein the first high-pass injection point is coupled to a first capacitor bank in an oscillator circuit of the phase-locked loop, and the second high-pass injection point is coupled to a second capacitor bank in the oscillator circuit.

[0065] Example 9 includes the subject matter of Example 4, including or omitting optional elements, wherein the high-pass injection circuit device comprises: a pre-distortion circuit device, configured to determine a first gain of a modulated signal and a second gain of a frequency offset sequence to minimize a phase error of a phase-locked loop; a first multiplier, configured to scale the modulated signal based on the first gain to generate a first high-pass injection signal, and provide the first high-pass injection signal to a first high-pass injection point; and a second multiplier, configured to scale the frequency offset sequence based on the second gain to generate a second high-pass injection signal, and provide the second high-pass injection signal to a second high-pass injection point.

[0066] Example 10 includes the subject matter of Example 9, including or omitting the optional element, wherein the first high-pass injection point is coupled to a first capacitor bank in an oscillator circuit of the phase-locked loop, and the second high-pass injection point is coupled to a second capacitor bank in the oscillator circuit.

[0067] Example 11 includes the subject matter of Example 4, including or omitting optional elements, wherein the low-pass injection circuit device comprises: a second combination circuit device configured to combine the modulated signal with the frequency offset sequence and the frequency command word for the phase-locked loop to generate an adjusted frequency command word, and provide the adjusted frequency command word to a divider circuit device in the phase-locked loop.

[0068] Example 12 includes the subject matter of Example 1, including or omitting optional elements, wherein the bandwidth compensation circuit device comprises: a combination circuit device configured to combine the modulated signal with the frequency offset sequence and the frequency command word for the phase-locked loop to generate an adjusted frequency command word; and a pre-emphasis filter for filtering the adjusted frequency command word to generate a bandwidth compensation signal.

[0069] Example 13 includes the subject matter of Example 12, including or omitting the optional element, wherein the bandwidth compensation circuitry comprises a bandwidth estimation circuit configured to estimate a bandwidth of the modulated signal and control the pre-emphasis filter based on the estimated bandwidth.

[0070] Example 14 is a method of generating a frequency hopping radar signal, comprising: generating a frequency offset sequence; combining the frequency offset sequence with a modulation signal to generate a bandwidth compensation signal; and providing the bandwidth compensation signal to a phase-locked loop (PLL) to cause the PLL to generate the frequency hopping radar signal.

[0071] Example 15 includes the subject matter of Example 14, including or omitting optional elements, including generating the frequency offset sequence based on random numbers.

[0072] Example 16 includes the subject matter of Example 14, including or omitting optional elements, including generating a frequency offset sequence based on frequency shift keying (FSK) or phase shift keying (PSK) information.

[0073] Example 17 includes the subject matter of Example 14, including or omitting the optional element, wherein the bandwidth of the bandwidth compensation signal is greater than the bandwidth of the PLL.

[0074] Example 18 includes the subject matter of Example 14, including or omitting optional elements, comprising generating a bandwidth compensation signal by combining a modulation signal with a frequency offset sequence and a frequency command word for a phase-locked loop to generate at least one low-pass injection signal; generating at least one high-pass injection signal based on the modulation signal and the frequency offset sequence; determining a gain of the at least one high-pass injection signal based on a sensed phase error of the phase-locked loop; and scaling the high-pass injection signal based on the gain. The bandwidth compensation signal is provided to the PLL by providing the at least one low-pass injection signal to a low-pass injection point of the phase-locked loop and providing the scaled high-pass injection signal to a high-pass injection point of the phase-locked loop.

[0075] Example 19 includes the subject matter of Example 14, including or omitting optional elements, including generating a bandwidth compensation signal by combining a modulated signal with a frequency offset sequence and a frequency command word (FCW) for a phase-locked loop to generate an adjusted FCW, and filtering the adjusted FCW to generate the bandwidth compensation signal.

[0076] Example 20 includes the subject matter of Example 19, including or omitting the optional elements, further comprising determining an estimated bandwidth of the modulated signal based on a sensed phase error of the PLL, and filtering the adjusted FCW based on the estimated bandwidth of the modulated signal.

[0077] The foregoing description of one or more embodiments provides illustration and description, but is not intended to be exhaustive or to limit the scope of the exemplary embodiments to the precise forms disclosed. Modifications and variations may be made in light of the above teachings or may be acquired from practice of various implementations of the exemplary embodiments.

[0078] The various illustrative logics, logical blocks, modules, circuits, and circuits described in connection with the aspects disclosed herein may be implemented or performed by a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine.

[0079] The above description of illustrative embodiments of the disclosed subject matter (including what is described in the Abstract) is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. Although specific embodiments and examples are described herein for illustrative purposes, various modifications are contemplated within the scope of these embodiments and examples, as will be appreciated by those skilled in the relevant art.

[0080] In this regard, although the disclosed subject matter has been described with reference to various embodiments and corresponding drawings (where applicable), it should be understood that other similar embodiments may be used, or modifications and additions may be made to the described embodiments, to perform the same, similar, alternative, or alternative functions of the disclosed subject matter without departing therefrom. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in breadth and scope in accordance with the claims appended hereto.

[0081] In this disclosure, similar reference numerals are used to refer to the same elements, and the structures and devices shown are not necessarily drawn to scale. As used herein, the terms "module," "component," "system," "circuit arrangement," "element," "slice," etc. are used to refer to computer-related entities, hardware, software (e.g., in execution), and / or firmware. For example, a circuit arrangement or similar terms can be a processor, a process running on a processor, a controller, an object, an executable program, a storage device, and / or a computer with a processing device. For example, an application and a server running on a server can also be a circuit arrangement. One or more circuit arrangements can reside within a process, and the circuit arrangement can be located on one computer and / or distributed between two or more computers. A group of elements or a group of other circuit arrangements can be described here, where the term "group" can be interpreted as "one or more."

[0082] As another example, a circuit device or similar term can be a device that provides a specific functionality by mechanical parts operated by electrical or electronic circuitry, where the electrical or electronic circuitry can be operated by a software application or firmware application executed by one or more processors. The one or more processors can be internal or external to the device and can execute at least a portion of the software or firmware application. As yet another example, a circuit device can be a device that provides a specific functionality by electronic components that do not have mechanical parts; the electronic components may include field gates, logic components, hard-coded logic, register transfer logic, where the one or more processors execute software and / or firmware that at least partially negotiates the functionality of the electronic components.

[0083] It should be understood that when an element is referred to as being "electrically connected" or "electrically coupled" to another element, it can be physically connected or coupled to the other element so that electric current and / or electromagnetic radiation can flow along the conductive path formed by these elements. When elements are described as being electrically coupled or connected to each other, there can be intermediate conductive, inductive, or capacitive elements between the element and the other elements. In addition, when electrically coupled or connected to each other, one element can induce a flow of voltage or current or the propagation of electromagnetic waves in another element without physical contact or intermediate components. In addition, when a voltage, current, or signal is referred to as being "applied" to an element, the voltage, current, or signal can be conducted to the element through a physical connection or through capacitive, electromagnetic, or inductive coupling that does not involve a physical connection.

[0084] The use of the word "exemplary" is intended to present concepts in a concrete manner. The terms used herein are intended only to describe specific examples and are not intended to limit the examples. As used herein, the singular forms "a," "an," and "the" also include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprises," when used herein, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

Claims

1. A radar signal modulator, comprising: a frequency offset generator configured to generate a frequency offset sequence; Phase-locked loop (PLL); as well as A bandwidth compensation circuit device, comprising: a combining circuit device configured to combine the modulation signal with the frequency offset sequence and a frequency command word for the phase-locked loop to generate an adjusted frequency command word; as well as a pre-emphasis filter for filtering the adjusted frequency command word to generate a bandwidth compensation signal, The PLL is configured to receive the bandwidth compensation signal and generate a frequency hopping radar signal based on the bandwidth compensation signal. 2 . The radar signal modulator of claim 1 , wherein the frequency offset generator is configured to generate a random frequency offset sequence. 3 . The radar signal modulator according to claim 1 , wherein the frequency offset generator is configured to generate a frequency offset sequence encoding frequency shift keying (FSK) or phase shift keying (PSK) information.

4. The radar signal modulator of claim 1 , wherein the bandwidth compensation circuitry comprises bandwidth estimation circuitry configured to: estimating a bandwidth of the modulated signal; and The pre-emphasis filter is controlled based on the estimated bandwidth.

5. A radar signal modulator, comprising: a frequency offset generator configured to generate a frequency offset sequence; Phase-locked loop (PLL); as well as A bandwidth compensation circuit device, comprising: A low-pass injection circuit arrangement is configured to: receiving a modulated signal; receiving the frequency offset sequence; and generating at least one low-pass injection signal based on the frequency offset sequence and the modulation signal; and The high-pass injection circuit device is configured to: receiving the modulated signal; receiving the frequency offset sequence; and generating at least one high-pass injection signal based on the frequency offset sequence and the modulation signal, Wherein the PLL is configured as: receiving the at least one low-pass injection signal at a low-pass injection point; receiving the at least one high-pass injection signal at a high-pass injection point; and A frequency hopping radar signal is generated based on the at least one low-pass injection signal and the at least one high-pass injection signal.

6. The radar signal modulator according to claim 5, wherein the high-pass injection circuit device comprises: gain estimation circuitry configured to determine a gain of the at least one high-pass injection signal based on a sensed phase error of the phase-locked loop; a first combining circuit device configured to combine the modulated signal with the frequency offset sequence to generate a frequency hopping modulated signal; as well as A multiplier is configured to scale the frequency hopping modulation signal based on the gain to generate the at least one high-pass injection signal.

7. The radar signal modulator according to claim 6, wherein: The low-pass injection circuit device includes a second combination circuit device, the second combination circuit device being configured to combine the modulated signal with the frequency offset sequence and a frequency command word for the phase-locked loop to generate an adjusted frequency command word; and The polarity of at least one of the modulation signal or the frequency offset sequence input to the first combinational circuit means is inverted relative to the corresponding modulation signal or the corresponding frequency offset sequence input to the second combinational circuit means.

8. The radar signal modulator according to claim 5, wherein the high-pass injection circuit device comprises: modulation path gain estimation circuitry configured to determine a first gain of the modulation signal based on a sensed phase error of the phase locked loop; a first multiplier configured to scale the modulated signal based on the first gain to generate a first high-pass injection signal, and provide the first high-pass injection signal to a first high-pass injection point; offset path gain estimation circuitry configured to determine a second gain of the frequency offset sequence based on the sensed phase error of the phase locked loop; as well as A second multiplier is configured to scale the frequency offset sequence based on the second gain to generate a second high-pass injection signal, and provide the second high-pass injection signal to a second high-pass injection point.

9. The radar signal modulator of claim 8, wherein the first high-pass injection point is coupled to a first capacitor bank in an oscillator circuit of the phase-locked loop, and the second high-pass injection point is coupled to a second capacitor bank in the oscillator circuit.

10. The radar signal modulator according to claim 5, wherein the high-pass injection circuit device comprises: a predistortion circuit arrangement configured to determine a first gain of the modulated signal and a second gain of the frequency offset sequence to minimize a phase error of the phase-locked loop; a first multiplier configured to scale the modulated signal based on the first gain to generate a first high-pass injection signal, and provide the first high-pass injection signal to a first high-pass injection point; as well as A second multiplier is configured to scale the frequency offset sequence based on the second gain to generate a second high-pass injection signal, and provide the second high-pass injection signal to a second high-pass injection point.

11. The radar signal modulator of claim 10, wherein the first high-pass injection point is coupled to a first capacitor bank in an oscillator circuit of the phase-locked loop, and the second high-pass injection point is coupled to a second capacitor bank in the oscillator circuit.

12. The radar signal modulator of claim 5, wherein the low-pass injection circuit means comprises a second combination circuit means, the second combination circuit means being configured to: combining the modulation signal with the frequency offset sequence and a frequency command word for the phase-locked loop to generate an adjusted frequency command word; and The adjusted frequency command word is provided to a divider circuit arrangement in the phase locked loop.

13. A method for generating a frequency hopping radar signal, comprising: generating a frequency offset sequence; generating at least one low-pass injection signal by combining a modulation signal with the frequency offset sequence and a frequency command word for a phase-locked loop (PLL); generating at least one high-pass injection signal based on the modulation signal and the frequency offset sequence; providing the at least one low-pass injection signal to a low-pass injection point of the phase-locked loop; as well as providing a high-pass injection signal to a high-pass injection point of the phase-locked loop (PLL) to enable the PLL to generate a frequency-hopping radar signal; sending the frequency hopping radar signal; as well as Received signals corresponding to reflections of the frequency hopping radar signal are processed to detect objects.

14. The method according to claim 13, comprising: The frequency offset sequence is generated based on random numbers.

15. The method according to claim 13, comprising: The frequency offset sequence is generated based on frequency shift keying (FSK) or phase shift keying (PSK) information.

16. The method according to claim 13, wherein The low-pass injection signal and the high-pass injection signal together comprise a bandwidth compensation signal, and The bandwidth of the bandwidth compensation signal is greater than the bandwidth of the PLL.

17. The method according to claim 13, comprising: determining a gain of the at least one high-pass injection signal based on a sensed phase error of the phase-locked loop; as well as scaling the high-pass injection signal based on the gain; and A scaled high-pass injection signal is provided to the high-pass injection point of the phase-locked loop.

18. The method of claim 13, comprising generating the low-pass injection signal by: combining the modulation signal with the frequency offset sequence and a frequency command word FCW for the phase locked loop to generate an adjusted FCW; and The adjusted FCW is filtered to generate the low-pass injection signal.

19. The method according to claim 18, further comprising: An estimated bandwidth of the modulated signal is determined based on a sensed phase error of the PLL, and the adjusted FCW is filtered based on the estimated bandwidth of the modulated signal.

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