Configure the memory subsystem for partitioning different data.

Abstract

This disclosure relates to configuring a memory subsystem for partitioning different data. It receives one or more parameters indicating a request to subdivide a memory device into multiple partitions for use by a host system. In response to receiving the one or more parameters indicating the request to subdivide the memory device into the multiple partitions, a first partition is configured based on the one or more parameters through one or more configuration settings. Configuring the first partition includes determining a memory type from multiple memory types based on the one or more parameters, and configuring the first partition to operate for the determined memory type. The memory type defines the number of bits that a memory cell in the first partition will store.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to a memory subsystem, and more specifically, to the partitioning of a memory subsystem. Background Technology

[0002] The memory subsystem may contain one or more memory components for storing data. Memory components may be, for example, non-volatile memory components and volatile memory components. Generally, a host system can utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the Invention

[0003] One aspect of this disclosure relates to a system comprising: a memory device; and a processing means operatively coupled to the memory device to perform operations including: receiving one or more parameters indicating a request to subdivide the memory device into a plurality of partitions for use by a host system; and, in response to receiving the one or more parameters indicating the request to subdivide the memory device into the plurality of partitions, configuring a first partition among the plurality of partitions based on the one or more parameters via one or more configuration settings, wherein configuring the first partition includes: determining a memory type from a plurality of memory types based on the one or more parameters; and configuring the first partition among the plurality of partitions to operate for the determined memory type, wherein the determined memory type defines the number of bits that memory cells of the first partition will store.

[0004] Another aspect of this disclosure relates to a system comprising: a memory; and a processing means operatively coupled to the memory to perform operations including: receiving one or more parameters indicating a request to subdivide a memory device of a memory subsystem into a plurality of partitions for use by a host system; and, in response to receiving the one or more parameters indicating the request to subdivide the memory device into the plurality of partitions, determining one or more configuration settings for a first partition among the plurality of partitions based on the one or more parameters, wherein determining the one or more configuration settings for the first partition includes: determining a memory type from a plurality of memory types based on the one or more parameters, wherein the determined memory type defines the number of bits that a memory cell in the first partition will store; and sending one or more commands requesting to configure the memory subsystem via the one or more configuration settings, wherein the one or more configuration settings identify that the first partition will be configured as the determined memory type.

[0005] Another aspect of this disclosure relates to a method comprising: receiving, via a processing means, one or more parameters indicating a request to subdivide a memory device into a plurality of partitions for use by a host system; and, in response to receiving the one or more parameters indicating the request to subdivide the memory device into the plurality of partitions, configuring a first partition among the plurality of partitions based on the one or more parameters via one or more configuration settings, wherein configuring the first partition comprises: determining a memory type from a plurality of memory types based on the one or more parameters; and configuring the first partition among the plurality of partitions to operate for the determined memory type, wherein the determined memory type defines the number of bits that memory cells of the first partition will store. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 This describes an instance computing environment including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram illustrating a memory subsystem having multiple partitions according to some embodiments of the present disclosure.

[0009] Figure 3 This is a flowchart of an example method for configuring partitions of a memory subsystem based on one or more parameters according to embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart of an example method for configuring partitions of a memory subsystem based on one or more parameters according to embodiments of the present disclosure.

[0011] Figure 5 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0012] An aspect of the invention is the partitioning of a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of both. Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that contains one or more memory devices for storing data. The host system can provide data to be stored in the memory subsystem and can request retrieval of data from the memory subsystem.

[0013] A memory subsystem can be subdivided into two or more partitions. Partitioning can refer to the process of dividing memory into segments (e.g., partitions) for use by applications, processes, operations, etc. Partitions can be individually addressable and may contain information related to a specific application, process, operation, etc. Partitions can be logically separated areas of a memory subsystem, which appear to the host system as multiple physical memory subsystems.

[0014] Some conventional storage subsystems do not allow individual partitioning. For example, conventional Secure Digital (SD) cards do not allow partitioning of the SD card's memory. Some partitionable conventional storage subsystems partition by default and do not allow users to choose the partitioning feature.

[0015] This disclosure addresses the above and other drawbacks by allowing the user to select one or more parameters indicating a request to subdivide the memory devices of the memory subsystem into partitions for use by the host system. In response to receiving the parameters, configuration settings are determined based on the parameters, and the partitions are configured based on the determined configuration settings. In some embodiments, configuring the partitions includes determining a memory type among a plurality of memory types based on the parameters, and configuring the partitions to operate for the determined memory type. The memory type defines the number of bits that the memory cells of the partition will store. Some examples of memory types include single-level cell (SLC) memory type, multi-level cell (MLC) memory type, three-level cell (TLC) memory type, or four-level cell (QLC) memory type. In some embodiments, configuring the partitions includes determining a refresh rate for the memory cells of the partition based on the determined memory type and parameters. The memory subsystem is configured to refresh the memory cells of the partition at the determined refresh rate. In some embodiments, error correction capabilities to be implemented at the partition are determined based on the parameters. Error detection and error correction code (ECC) operations with the determined error correction capabilities are configured to be performed on data stored at the partition.

[0016] The advantages of this disclosure include, but are not limited to, improved performance of the memory subsystem. Allowing the memory subsystem to be used more efficiently by configuring partitions of the memory subsystem using user-selected parameters, determining configuration settings based on said parameters, and configuring partitions using those configuration settings is beneficial. For example, partitions generated based on user-selected parameters can store important or confidential data more efficiently and securely. In another instance, by determining configuration settings based on user-selected parameters and configuring partitions using those determined configuration settings, the resources of the memory subsystem (e.g., memory resources, power resources, computing resources) can be deployed more efficiently, at least because the configuration settings can be optimized for a specific memory subsystem and the selected parameters. Furthermore, as the characteristics or usage patterns of the memory subsystem change throughout its lifetime, the configuration settings can be adjusted based on these changes, which further enhances the efficient deployment of the memory subsystem's resources.

[0017] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0018] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, secure digital cards (SD cards), universal flash memory (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0019] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car or other means of transport), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or a networked business device), or such a computing device containing memory and processing devices.

[0020] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, and includes connections such as electrical, optical, and magnetic connections.

[0021] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0022] Host system 120 may be a computing device, such as a desktop computer, laptop computer, network server, mobile device, or such computing device containing memory and processing power. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120.

[0023] The memory device may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., memory device 140) may be, but is not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0024] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory allows for in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them.

[0025] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, and a page may refer to a logical cell of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0026] Although a non-volatile memory component, such as a 3D cross-point type memory, is described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0027] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic that performs the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0028] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0029] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0030] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may additionally include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0031] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0032] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 may be a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0033] In an embodiment, memory subsystem 110 includes a partition manager 113B that performs the operations described herein. In some embodiments, partition manager 113A of host system 120 performs the operations described herein. Partition manager 113A and partition manager 113B are generally referred to herein as "partition manager 113". In some embodiments, partition manager 113A of host system 120 and partition manager 113B of memory subsystem 110 work together to perform one or more of the operations described herein. In some embodiments, any component of memory subsystem 110 may include partition manager 113B. For example, partition manager 113 may be part of host system 120, memory subsystem controller 115, memory device 140, memory device 130, an application or operating system (OS) executing at host system 120 (e.g., the OS of host system 120). In another instance, memory subsystem controller 115 may include processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. Further details about Partition Manager 113 are described below.

[0034] Figure 2 This is a block diagram illustrating a memory subsystem having multiple partitions according to some embodiments of the present disclosure. In some embodiments, partition manager 113B is part of memory subsystem controller 115 and is operatively coupled to memory device 210. In some embodiments, partition manager 113A of host system 120 performs some or all of the operations. In some embodiments, partition manager 113B of memory subsystem 110 performs all or some of the operations described herein. In some embodiments, partition manager 113A of host system 120 and partition manager 113B of memory subsystem work together to perform one or more of the operations described herein. In some embodiments, memory device 210 may be Figure 1Examples of one or more memory devices 130 or one or more memory devices 140.

[0035] As will be described in more detail below, the memory subsystem 110, and specifically the memory device 210, can be subdivided into multiple partitions, such as partition 1 and partition 2 as illustrated. In other embodiments, the memory device 210 can be subdivided into any number of partitions, such as three partitions, four partitions, five partitions, etc. In some embodiments, for example, the memory subsystem 110 may include multiple memory devices 210, and partitions may be created such that some of the memory devices 210 are part of one partition and other memory devices 210 are part of another partition. In another embodiment, where multiple memory devices 210 exist, one partition may contain some of the memory cells of one or more memory devices 210, and another partition may contain other memory cells of the same one or more memory devices 210. In some embodiments, the partitioning of the memory subsystem 110 may be based on one or more parameters, such as a memory size parameter, a data retention parameter, a durability parameter, or a priority parameter. The user of the memory subsystem 110 can select the value of each parameter. The parameters can be sent to partition manager 113A or partition manager 113B, and partition manager 113A or partition manager 113B can determine one or more configuration settings based on user-selected parameters. User-selected parameters affect the determination of one or more configuration settings, such as refresh rate, memory type (e.g., SLC, MLC, TLC, etc.), and error correction capability. Different parameters have different trade-offs regarding the one or more configuration settings, and partition manager 113A or partition manager 113B evaluates the trade-offs when selecting the configuration settings.

[0036] In some embodiments, host system 120 sends parameters to storage subsystem 110, and partition manager 113B at storage subsystem 110 determines specific configuration settings for storage subsystem 110. The parameters and the determined configuration settings may be stored at storage subsystem 110.

[0037] In other embodiments, for example, a partition manager 113A executing at host system 120 may receive one or more parameters selected by an administrator. In an illustrative example, host system 120 includes a computer system, such as a desktop computer or server computer coupled to a display device. A user interface (e.g., a graphical user interface (GUI)) may be displayed at the computer system to receive one or more parameters selected by the user. Partition manager 113A at the computer system may determine configuration settings based on the received parameters. Partition manager 112 at the computer system may provide the determined configuration settings for presentation at the computer system. The partitioning of memory subsystem 110 may be an iterative process in which user-selected parameters are received and the resulting configuration settings are provided for presentation at the computer system. Once the user determines that the parameters and configuration settings are appropriate, the user may choose to save the parameters and configuration settings. In response to saving the parameters and configuration settings, the parameters and configuration settings are sent from the computer system to memory subsystem 110, where memory subsystem controller 115 saves the parameters and configuration settings and uses them to configure memory subsystem 110.

[0038] In other embodiments, partition manager 113A at host system 120 and partition manager 113B at memory subsystem 110 may work together to perform one or more operations, or work together to perform different operations of partitioning memory subsystem 110.

[0039] In illustrative embodiments, the memory subsystem 110 may be a Secure Digital (SD) card, a Micro SD card, or a microSD card. The memory subsystem 110 may be implemented in a third-party device, such as a surveillance camera or an Internet Protocol (IP) camera. The surveillance camera may be coupled to the memory subsystem 110. For example, the memory subsystem 110 may be coupled to the surveillance camera locally or via a network. The surveillance camera may be a digital camera of the type that records video data. Typically, a surveillance camera is a fixed camera used for monitoring purposes. An IP camera may be a type of surveillance camera that uses a built-in camera to acquire video data and transmits the video data to a remote server via a network. In some embodiments, the host system 120 may represent a third-party device, such as a surveillance camera.

[0040] In some embodiments, the memory subsystem 110 (e.g., an SD card) may store data associated with a surveillance camera. For example, the surveillance camera may capture video data (e.g., video items) at a specific frame rate (e.g., 30 frames per second) and compress the video data at a specific ratio (e.g., 100:1, 500:1, etc.). The compressed video may be stored at the memory subsystem 110. In addition to the compressed video, video metadata may also be stored at the memory subsystem 110. The video metadata contains information about the video data. For example, the metadata may act as a "journal" indicating the data and the time when the video data was captured. The video data may refer to one or more of the video items (e.g., consecutive video frames) and / or the video metadata.

[0041] In some embodiments, analytical data can be generated from video data. Analytical operations can be performed on video data that produces some output. In some embodiments, the analytical operation uses the content of one or more frames of the video data as input to produce some output. For example, the video data can be used as input to a machine learning model that produces some output, such as probabilities. In another instance, a heuristic model can be used where the video data is processed based on some rules that determine some output. In an illustrative example, the analytical operation may include facial recognition operations to identify people in the video data. In another instance, the analytical operation may identify known or unknown persons in the video data and send a message to the camera owner of the known or unknown person. Data generated by or related to analytical operations on video data can be referred to as analytical data.

[0042] In some embodiments, it may be necessary to store video data and analytics data separately. In some instances, one partition (e.g., partition 1) may be used to store video data, and another partition (e.g., partition 2) may be used to store analytics data. Specifically, analytics data may be considered important or sensitive data and may need to be stored in a partition with higher reliability compared to the partition storing video data. For example, aspects of this disclosure provide the ability to configure a storage subsystem (e.g., an SD card) with multiple partitions, wherein configuration settings are generated based on user-selected parameters, which allows the partitions to be configured for high reliability.

[0043] In some embodiments, a user may select one or more parameters indicating a request to subdivide the memory device 210 into multiple partitions for use by the host system 120. For example, in some embodiments, the host system 120 may represent a computer system implementing an interface such as a graphical user interface (GUI). The user may use the interface to send one or more parameters to the memory subsystem 110. The parameters and corresponding values ​​may be sent via one or more commands. The parameters may include one or more of memory size parameters, data retention parameters, durability parameters, and priority parameters.

[0044] In some embodiments, the memory size parameter may indicate the size of a partition. For example, the memory subsystem may have 1 gigabyte (GB) of user capacity (e.g., full drive capacity). The memory size parameter may indicate that partition 2 of memory device 210 is 256 megabytes (MB) (e.g., the value of the memory size parameter). In the case where two partitions are implemented, the memory size parameter defining the memory capacity of the first partition may also imply the memory capacity of the second partition, since memory capacity not allocated to the first partition is allocated to the second partition by default. For example, for a 1GB memory subsystem 110, the memory size parameter indicates that partition 2 is 256MB. The size of partition 1 is the remaining memory capacity of the 1GB memory subsystem 110.

[0045] In some embodiments, the data retention parameter may indicate the time period for which data stored in a partition will be reliably retained. For example, the data retention parameter may indicate that data stored in partition 2 will be stored for, for example, N minutes, N hours, N days, N weeks, or N months.

[0046] In some embodiments, the durability parameter may indicate the number of write cycles (and / or read cycles) that will be performed at a particular partition during the lifetime of the memory device 210. For example, the durability parameter may indicate that 40,000 write cycles will be performed at a particular partition during the lifetime of the memory device 210. In some embodiments, the number of write cycles may include the actual number of write cycles and / or the number of write cycles attributable to write amplification. For example, if the write amplification factor is 3, then for every 1 actual write, the total write budget attributable to write amplification is 3 write cycles.

[0047] In some embodiments, a priority parameter may indicate the priority of performing memory operations at a particular partition relative to any other partition of the memory subsystem. Memory operations may include, but are not limited to, write operations that write data to memory device 210, and read operations that read data stored at memory device 210. In an example, the priority parameter may indicate that partition 2 has a higher priority than partition 1. Writes to partition 2 will be performed before any writes to partition 1.

[0048] In some embodiments, the memory subsystem controller 115 may be associated with queue 212. For example, queue 212 may be implemented in volatile memory (e.g., SRAM) accessible by the memory subsystem controller 115. Data to be stored at memory device 210 may be received from host system 120. Data may be stored in the queue before being written to memory device 210. In the absence of a priority parameter, default operations (e.g., first-in-first-out (FIFO) or last-in-first-out (LIFO)) may be used to write data in the queue to memory device 210. In embodiments where a priority parameter is implemented, memory operations (e.g., write operations) on the data stored at queue 212 may be performed based on priority. For example, if partition 2 (P2) has a higher priority than partition 1 (P1), then for a memory operation, such as a write operation, partition manager 113B may write all data destined for partition 2 in queue 212 before writing any data destined for partition 1. Similarly, and based on priority, data destined for partition 1 in queue 212 is not written until all data destined for partition 2 in queue 212 has been written to partition 2. As explained, data in the queue can be addressed to a specific partition, such as partition 1 (P1) or partition 2 (P2). Priority decisions can be made based on the partition addresses associated with the data in queue 212.

[0049] In some embodiments, partition manager 113A or partition manager 113B receives the value of a parameter. Partition manager 113A or partition manager 113B may determine appropriate configuration settings based on one or more parameters. In some embodiments, the configuration settings include one or more of refresh rate, memory type, or error correction capability. In embodiments where partition manager 113A is executed at host system 120, one or more commands may be used to send one or more of the configuration settings and / or parameters to memory subsystem 110.

[0050] In some embodiments, the memory type may refer to the number of bits stored in the memory cells of a partition. Examples of memory types may include unit memory types, such as SLC memory types, or multi-bit memory types, such as MLC memory types, TLC memory types, or QLC memory types. In an illustrative example, partition 2 may be configured as a TLC memory type where each memory cell of partition 2 can store 3 bits of information, and partition 1 is configured as an SLC memory type.

[0051] In some embodiments, the refresh rate may refer to the frequency at which refresh operations are performed on memory cells (e.g., once a day, once a month, once a week, etc.). A refresh operation may involve reading information from a memory cell and then rewriting the read information back to the memory cell without modification. A refresh operation can be performed to store information at the memory cell. It can be noted that over time, the charge stored at the memory cell may leak. Without a refresh, the data stored at the memory cell may be lost due to this leakage.

[0052] In some embodiments, error correction capability can refer to the number of errors that an ECC operation can correct. For example, a particular ECC operation may have an error correction capability that corrects two errors. In some embodiments, error correction capability can affect latency and memory space. The higher the error correction capability, the longer the latency. In some cases, the more errors that ECC can correct, the more complex the ECC operation, which takes longer to execute and increases the latency of performing memory operations (e.g., read operations). In some cases, the more errors that ECC can correct (e.g., the greater the error correction capability), the larger the size of the parity data used to correct the errors. For example, the amount of parity data stored with an error correction capability of four errors may be greater than the amount of parity data stored with an error correction capability of one error.

[0053] As described above, the selection of parameters (e.g., the values ​​of the parameters) affects the selection of one or more configuration settings, which are further described below. In some embodiments, each memory type (e.g., SLC, MCL, TLC, etc.) may have a different retention rate. In some cases, fewer bits stored in memory cells of a particular memory type result in a higher retention rate, and vice versa. For example, the SLC memory type has a higher retention rate than the MLC memory type, the MLC memory type has a higher retention rate than the TLC memory type, and the TLC memory type has a higher retention rate than the QLC memory type.

[0054] In some embodiments, each memory type may have different durability. In some cases, the fewer bits stored in a memory cell of a particular memory type, the higher the durability. For example, SLC memory type has higher durability than MCL memory type, MLC memory type has higher durability than TLC memory type, and TLC memory type has higher durability than QLC memory type.

[0055] In some embodiments, the selection of memory type is strongly influenced by durability and / or retention parameters. Each of the memory types may be associated with a durability threshold (e.g., the number of write cycles over the lifetime of the memory device). In illustrative examples, the SLC memory type has the highest durability threshold (e.g., 80k write cycles), the MLC memory type (e.g., 15k write cycles) has the second highest durability threshold, the TLC has the third highest threshold (5k write cycles), and the QLC (2k write cycles) has the fourth highest durability threshold. If the durability parameter has a value of 10k write cycles, then the memory type may be determined to be either an SLC or MLC memory type because the value of the durability parameter satisfies (e.g., less than or equal to) the durability thresholds for both the SLC and MLC memory types.

[0056] In some embodiments, each memory type may be associated with a retention threshold. The SLC memory type may be associated with the highest retention threshold (e.g., 1 year), MLC with the second highest retention threshold (e.g., 2 months), TLC with the third highest retention threshold (e.g., 2 weeks), and QLC with the fourth highest retention threshold (e.g., 5 days). If the retention parameter is 3 months, then the memory type may be the SLC memory type because the value of the retention parameter meets (e.g., is less than or equal to) the retention threshold for the SLC memory type.

[0057] In some embodiments, the refresh rate is strongly influenced by the retention and / or the selected memory type. Refresh operations are performed at different frequencies depending on the memory type. Refresh operations are performed from least frequent to most frequent for the following memory types: SLC, MLC, TLC, and QLC memory types. For example, SLC memory types may be refreshed every 3 months, MLC memory types every 10 days, TLC memory types every 12 hours, and QLC memory types every 3 hours. Refreshing memory cells of a particular memory type consumes power, and the more frequently the memory cells are refreshed, the greater the power consumption. Furthermore, the refresh rate can affect the durability of memory cells because a higher refresh rate results in more read operations within a given time period, leading to lower durability.

[0058] In some embodiments, a threshold scheme can be used to determine the refresh rate. Each memory type can be associated with a refresh threshold. The SLC memory type can be associated with the highest refresh threshold (e.g., 3 months × N factor), the MLC memory type with the second highest refresh threshold (e.g., 10 days × N factor), the TLC memory type with the third highest refresh threshold (e.g., 12 hours × N factor), and the QLC memory type with the fourth highest refresh threshold (e.g., 2 hours × N factor). The N factor can be any number used to normalize the refresh rate based on the hold value. It can be noted that a certain refresh of data is acceptable, but excessive refreshes can be detrimental to the performance of the memory subsystem. The N factor attempts to set the refresh threshold at a value (e.g., a multiple of the refresh rate) that optimizes the performance of the memory subsystem. If the hold parameter is 3 months, then the memory type can be an SLC memory type because the value of the hold parameter satisfies (e.g., greater than or equal to) the refresh thresholds for both the SLC and MLC memory types (where the N factor is 10).

[0059] Continuing with the example above, partition 2 is configured as SLC memory type based on durability and retention parameters. The rated capacity of memory subsystem 110 is 8GB of TLC memory type. The value of the size parameter is 1GB. Partition 2 can be set to have 1GB of memory space configured as SLC memory type. The remaining memory space for partition 1 is 5GB because 1GB of SLC memory type is actually 3GB of TLC memory type minus the 8GB memory subsystem capacity. Since partition 2 is configured as SLC memory type, the corresponding refresh rate for SLC memory type (e.g., 3 months) is determined and the memory subsystem is configured accordingly. It can be noted that in some cases, multiple configuration settings can be determined for a given set of parameters.

[0060] In some embodiments, durability parameters and / or memory type strongly influence error correction capability. A higher value for the durability parameter results in a higher error correction capability, and vice versa. In some instances, the value of the durability parameter may be compared to one or more error thresholds for a specific memory type. For example, for an SLC memory type, a first error threshold may be 30k write cycles, a second error threshold may be 60k write cycles, and a third error threshold may be 80k write cycles. It can be noted that in some cases, the memory type can be determined, and an error threshold corresponding to that specific memory type can be selected. If the value of the durability parameter is less than 30k write cycles, then the lowest error correction capability can be selected. If the value of the durability parameter is between 30k and 60k write cycles, then the second lowest error correction capability can be selected. If the value of the durability parameter is between 60k and 80k write cycles, then the third lowest error correction capability can be selected. If the value of the durability parameter is greater than or equal to 80k write cycles, then the highest error correction capability can be selected, and so on.

[0061] In some embodiments, configuration settings can be dynamically changed based on operational metrics or characteristics during the operation of memory subsystem 110 (e.g., during runtime). For example, partition manager 113B at memory subsystem 110 can compare the number of write cycles to a write cycle threshold. The write cycle threshold can be determined by a durability parameter. For example, suppose the durability parameter indicates 10,000 write cycles over the lifetime of the memory subsystem. At 50% of the lifetime of the memory subsystem, the number of write cycles can be estimated to be approximately 5,000. At half the lifetime of the memory subsystem, two write cycle thresholds can be set based on the expected number of write cycles at half the lifetime of the memory subsystem: a low write cycle threshold (e.g., 3,000 write cycles) and a high write cycle threshold (e.g., 7,000 write cycles). It can be noted that the thresholds can be based on the current position within the lifetime of the memory subsystem and can be adjusted depending on the current position (e.g., 25% lifetime, 30% lifetime, etc.). In the current instance, if the number of write cycles at half the lifespan is between the low write cycle threshold and the high write cycle threshold, the configuration settings remain unchanged. If the current number of write cycles is less than the low write cycle threshold, the partition manager 113B may change one or more configuration settings (e.g., increase the refresh rate or change the memory type, or both). If the current number of write cycles is greater than the high write cycle threshold, the partition manager 113B may change one or more configuration settings (e.g., decrease the refresh rate or change the memory type, or both).

[0062] In another example, partition manager 113B dynamically changes configuration settings during runtime based on other operational metrics (e.g., operational characteristics or changes), such as changes in error rate attributable to wear, changes in durability in memory cells, or changes in average operating temperature. One or more operational metrics can be compared to corresponding thresholds, and if an operational metric meets a corresponding threshold, partition manager 113B can change one or more configuration settings. For example, the initial configuration settings may be set such that the memory type is TLC memory. Partition manager 113B may determine that memory subsystem 110 is operating at an average high temperature (e.g., comparing the average temperature to an average temperature threshold and determining that the average temperature is greater than or equal to the average temperature threshold), which reduces the retention of the TLC memory type. Partition manager 113B may select, for example, a different refresh rate or a different memory type and reconfigure the corresponding partitions.

[0063] In some embodiments, new parameters can be reprogrammed at any given time during the lifetime of the user-storeable subsystem 110. These new parameters can be selected in a manner similar to that described above.

[0064] In some embodiments, memory subsystem 110 may configure a partition (e.g., partition 2) based on received parameters. Another partition (e.g., partition 1) may be configured based on default configuration settings (except for size). For example, suppose the default configuration setting of memory subsystem 110 is a TLC memory type with a TLC refresh rate (e.g., every 12 hours) and error correction capability 1. Memory subsystem 110 may configure partition 1 as a TLC memory type with a TLC refresh rate and error correction capability 1 regardless of the configuration settings of partition 2. In other embodiments, user-selected parameters for both partitions may be received, and configuration settings may be selected as described herein.

[0065] The following sections describe respectively Figure 3 and Figure 4 Methods 300 and 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, special-purpose logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300 or 400 is performed by... Figure 1The partition manager 113 executes the operation. Although shown in a specific order or sequence, the order or sequence of operations may be modified unless otherwise stated. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible. In some embodiments, the same, different, higher, or fewer operations may be performed.

[0066] Figure 3 This is a flowchart of an example method for configuring partitions of a memory subsystem based on one or more parameters according to embodiments of the present disclosure. In some embodiments, method 300 may be performed by a partition manager 113B executing at memory subsystem 110.

[0067] At operation 310, the processing logic receives one or more parameters indicating a request to subdivide the memory device into multiple partitions. In some embodiments, to receive one or more parameters indicating a request to subdivide the memory device into multiple partitions for use by the host system, the processing logic receives an indication of a memory size parameter for the first partition.

[0068] In some embodiments, in order to receive one or more parameters indicating a request to subdivide the memory device into multiple partitions for use by the host system, the processing logic receives an indication of a data retention parameter indicating the time period for which data stored in the first partition will be retained.

[0069] In some embodiments, in order to receive one or more parameters indicating a request to subdivide the memory device into multiple partitions for use by the host system, the processing logic receives an indication of a durability parameter indicating the number of write cycles to be performed at the first partition during the lifetime of the memory device.

[0070] In some embodiments, in order to receive one or more parameters indicating a request to subdivide a memory device into multiple partitions for use by a host system, the processing logic receives an indication of a priority parameter indicating the priority of performing memory operations at a first partition relative to the other partitions among the multiple partitions.

[0071] At operation 320, the processing logic configures a first partition among multiple partitions based on one or more parameters and one or more configuration settings. In some embodiments, in response to receiving one or more parameters indicating a request to subdivide the memory device into multiple partitions, the operation of configuring the first partition among multiple partitions based on one or more parameters and one or more configuration settings is performed.

[0072] In some embodiments of configuring the first partition, the processing logic determines the refresh rate of the memory cells of the first partition based on the determined memory type and one or more parameters. The processing logic configures the memory subsystem to refresh the memory cells of the first partition at the determined refresh rate.

[0073] In some embodiments of configuring the first partition, the processing logic determines the error correction capability to be implemented at the first partition based on one or more parameters. The processing logic determines the error detection and error correction code (ECC) operation with the determined error correction capability to be performed on the data stored at the first partition.

[0074] At operation 330, the processing logic determines the memory type from multiple memory types based on one or more parameters.

[0075] At operation 340, the processing logic configures the first partition of a plurality of partitions to operate on a determined memory type. The memory type defines the number of bits that the memory cells of the first partition will store. In some embodiments, to configure the first partition, the processing logic performs operations 330 and 340.

[0076] At operation 350, the processing logic monitors one or more operational metrics associated with one or more parameters during runtime. At operation 360, the processing logic determines that the one or more operational metrics meet a threshold. The threshold indicates that the first partition is being used in a manner different from that indicated by the one or more parameters. At operation 370, the processing logic adjusts at least one of the configuration settings during runtime. In some embodiments, adjusting at least one of the configuration settings during runtime is a response to determining that the one or more operational metrics meet the threshold.

[0077] In some embodiments, the plurality of partitions includes a first partition and a second partition. The second partition stores video items acquired by the Internet Protocol (IP) camera. The first partition stores analysis data generated by the IP camera using the video items. In some embodiments, the user selects configuration settings for the first partition. In some embodiments, the second partition is configured with default configuration settings.

[0078] Figure 4 This is a flowchart of an example method for configuring partitions of a memory subsystem based on one or more parameters according to embodiments of the present disclosure. In some embodiments, method 300 may be performed by a partition manager 113A executing at host system 120.

[0079] At operation 410, the processing logic receives one or more parameters indicating a request to subdivide the memory device of the memory subsystem into multiple partitions.

[0080] In some embodiments, in order to receive one or more parameters indicating a request to subdivide the memory device into multiple partitions for use by the host system, the processing logic receives an indication of the memory size parameter of the first partition.

[0081] In some embodiments, in order to receive one or more parameters indicating a request to subdivide the memory device into multiple partitions for use by the host system, the processing logic receives an indication of a data retention parameter indicating the time period for which data stored in the first partition will be retained.

[0082] In some embodiments, in order to receive one or more parameters indicating a request to subdivide the memory device into multiple partitions for use by the host system, the processing logic receives an indication of a durability parameter indicating the number of write cycles to be performed at the first partition during the lifetime of the memory device.

[0083] In some embodiments, in order to receive one or more parameters indicating a request to subdivide a memory device into multiple partitions for use by a host system, the processing logic receives an indication of a priority parameter indicating the priority of performing memory operations at a first partition relative to the other partitions among the multiple partitions.

[0084] At operation 420, the processing logic determines one or more configuration settings for the first partition based on one or more parameters. In some embodiments, in response to receiving one or more parameters indicating a request to subdivide the memory device into multiple partitions, the processing logic determines one or more configuration settings for the first partition based on one or more parameters.

[0085] In some embodiments, to determine one or more configuration settings, the processing logic determines the error correction capability to be implemented at the first partition based on one or more parameters. The one or more configuration settings further identify the determined error correction capability at the first partition.

[0086] At operation 430, the processing logic determines the memory type from multiple memory types based on one or more parameters. In some embodiments, the memory type defines the number of bits that will be stored in the memory cells of the first partition.

[0087] At operation 440, the processing logic sends one or more commands to request the configuration of the memory subsystem through one or more configuration settings. In some embodiments, the one or more configuration settings identify the first partition to be configured as a determined memory type. In some embodiments, the processing logic performs operations 430 and 440 to determine one or more configuration settings for the first partition. In some embodiments, to determine the one or more configuration settings, the processing logic determines the refresh rate of the memory cells of the first partition based on the determined memory type and one or more parameters. The one or more configuration settings further identify the determined refresh rate of the memory cells of the first partition.

[0088] In some embodiments, the processing logic sends an indication of one or more determined configuration settings for presentation at a graphical user interface (GUI). The processing logic receives one or more adjusted values ​​of one or more parameters via the GUI. In response to receiving one or more adjusted values ​​of one or more parameters, the processing logic determines a new configuration setting for the first partition based on the adjusted values. The processing logic sends an indication of the new configuration setting for presentation at the GUI.

[0089] Figure 5 This describes an instance machine of computer system 500, within which an instruction set executable for causing the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or uses a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system, thereby executing commands corresponding to...). Figure 1 (Operation of partition manager 113). In alternative embodiments, the machine may be connected (e.g., network connected) to other machines in a LAN, intranet, extranet, or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0090] A machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or bridge, a vehicle, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be considered to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0091] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0092] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 to perform the operations and steps discussed herein. Computer system 500 may additionally include a network interface device 508 for communication on network 520.

[0093] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) on which one or more instruction sets 526 or software embodying any one or more methods or functions described herein are stored. Instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0094] In one embodiment, instruction 526 includes instructions for implementing the corresponding Figure 1 The partition manager 113 provides functional instructions. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0095] Some parts of the previously described description have been presented with respect to the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and are generally considered, a self-consistent sequence of operations that leads to a desired result. An operation is one that requires physical control over physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0096] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0097] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0098] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0099] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0100] The terms “example” and / or “exemplary” are used herein to mean “serving as an example, illustration, or description.” Any aspect or design described herein as “example” or “exemplary” should not necessarily be construed as preferred or advantageous over other aspects or designs. Rather, the use of the terms “example” or “exemplary” is intended to present the concepts in a specific manner. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or clearly apparent from the context, “X comprises A or B” inherently implies any natural inclusion. In other words, “X comprises A” is satisfied if X comprises A; X comprises B; or X comprises both A and B. Additionally, the article “a” as used in this application and the appended claims is generally interpreted as meaning “one or more” unless otherwise specified or clearly apparent from the context to indicate a singular form. Furthermore, the use throughout the document of terms such as “implementation” or “an embodiment” or “an example” or “one embodiment” is not intended to refer to the same embodiment or example unless so described. The one or more embodiments or examples described herein may be combined in a particular embodiment or example. As used herein, the terms “first,” “second,” “third,” “fourth,” etc., are intended as identifiers to distinguish different elements and may not necessarily have ordinal meanings according to their numerical names.

[0101] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: Memory devices; as well as A processing device operatively coupled to the memory device to perform operations including: The system receives, via a graphical user interface (GUI), one or more user selections of parameters indicating a request to subdivide the memory device into multiple partitions for use by the host system, wherein the one or more parameters include a data retention parameter indicating the time period for which data stored in a first partition of the multiple partitions will be retained, and wherein the one or more parameters include a priority parameter, which is a user selection parameter received via the GUI and indicates the priority of performing memory operations at the first partition relative to the other partitions of the multiple partitions; as well as In response to receiving one or more parameters indicating a request to subdivide the memory device into the plurality of partitions, the first partition among the plurality of partitions is configured based on one or more configuration settings using one or more configuration settings, wherein configuring the first partition includes: The memory type is determined from multiple memory types based on one or more parameters; as well as The first partition of the plurality of partitions is configured to operate as the determined memory type, wherein the determined memory type defines the number of bits that the memory cells of the first partition will store.

2. The system of claim 1, wherein configuring the first partition further comprises: The refresh rate of the memory cells in the first partition is determined based on the determined memory type and one or more parameters. as well as Configure the memory subsystem to refresh the memory cells of the first partition at the determined refresh rate.

3. The system of claim 1, wherein configuring the first partition further comprises: The error correction capability to be implemented for the first partition is determined based on one or more parameters; as well as The configuration will perform error detection and error correction code (ECC) operations with the determined error correction capabilities on the data stored in the first partition.

4. The system of claim 1, wherein receiving the one or more parameters indicating the request to subdivide the memory device into the plurality of partitions for use by the host system includes: Receive an indication of the memory size parameter of the first partition.

5. The system of claim 1, wherein receiving the one or more parameters indicating the request to subdivide the memory device into the plurality of partitions for use by the host system includes: Receive an indication of durability parameters, which indicate the number of write cycles to be performed at the first partition during the lifetime of the memory device.

6. The system according to claim 1, further comprising: During the operation of the memory device, monitor one or more operational metrics associated with the one or more parameters; Determine that the one or more operational metrics satisfy a threshold, the threshold indicating that the first partition is being used in a manner different from that indicated by the one or more parameters; as well as In response to determining that one or more operational metrics meet the threshold, at least one of the configuration settings is adjusted during runtime.

7. The system of claim 1, wherein the plurality of partitions includes a first partition and a second partition, wherein the second partition is configured to store video items obtained by an Internet Protocol (IP) camera, wherein the first partition is configured to store analysis data generated by the IP camera using the video items, wherein a user selects the configuration settings of the first partition, and wherein the second partition is configured with default configuration settings.

8. A system comprising: Memory; as well as A processing device, operatively coupled to the memory, performs operations including the following: The system receives, via a graphical user interface (GUI), one or more user selections of parameters indicating a request to subdivide the memory devices of the memory subsystem into multiple partitions for use by the host system. These parameters include a data retention parameter indicating the duration for which data stored in a first partition of the multiple partitions will be retained, and a priority parameter, which is a user selection received via the GUI and indicates the priority of performing memory operations at the first partition relative to the other partitions of the multiple partitions. as well as In response to receiving one or more parameters indicating a request to subdivide the memory device into the plurality of partitions, one or more configuration settings for the first partition among the plurality of partitions are determined based on the one or more parameters, wherein determining the one or more configuration settings for the first partition includes: The memory type is determined from multiple memory types based on one or more parameters, wherein the determined memory type defines the number of bits that the memory cells of the first partition will store; as well as One or more commands are sent to the memory subsystem to request configuration of the memory subsystem through one or more configuration settings, wherein the one or more configuration settings identify that the first partition will be configured as the determined memory type.

9. The system of claim 8, wherein determining the one or more configuration settings further comprises: The refresh rate of the memory cells of the first partition is determined based on the determined memory type and the one or more parameters, wherein the one or more configuration settings further identify the determined refresh rate of the memory cells of the first partition.

10. The system of claim 8, wherein determining the one or more configuration settings further comprises: The error correction capability to be implemented for the data stored in the first partition is determined based on the one or more parameters, wherein the one or more configuration settings further identify the determined error correction capability of the data stored in the first partition.

11. The system of claim 8, wherein receiving the one or more parameters indicating the request to subdivide the memory device into the plurality of partitions for use by the host system includes: Receive an indication of the memory size parameter of the first partition.

12. The system of claim 8, wherein receiving the one or more parameters indicating the request to subdivide the memory device into the plurality of partitions for use by the host system includes: Receive an indication of durability parameters, which indicate the number of write cycles to be performed at the first partition during the lifetime of the memory device.

13. The system of claim 8, further comprising: Send instructions for the determined one or more configuration settings to be presented in the graphical user interface (GUI); Receive one or more adjusted values ​​of the one or more parameters via the GUI; In response to receiving the one or more adjusted values ​​of the one or more parameters, a new configuration setting for the first partition is determined based on the one or more adjusted values; as well as Send instructions for the new configuration settings to be displayed in the GUI.

14. A method comprising: The processor receives, via a graphical user interface (GUI), one or more user selections of parameters indicating a request to subdivide a memory device into multiple partitions for use by a host system. These parameters include a data retention parameter indicating the duration for which data stored in a first partition of the multiple partitions will be retained. The parameters also include a priority parameter, which is a user selection received via the GUI and indicates the priority of performing memory operations at the first partition relative to the other partitions of the multiple partitions. as well as In response to receiving one or more parameters indicating a request to subdivide the memory device into the plurality of partitions, the first partition among the plurality of partitions is configured based on one or more configuration settings using one or more configuration settings, wherein configuring the first partition includes: The memory type is determined from multiple memory types based on one or more parameters; as well as The first partition of the plurality of partitions is configured to operate as the determined memory type, wherein the determined memory type defines the number of bits that the memory cells of the first partition will store.

15. The method of claim 14, wherein configuring the first partition further comprises: The refresh rate of the memory cells in the first partition is determined based on the determined memory type and one or more parameters. as well as Configure the memory subsystem to refresh the memory cells of the first partition at the determined refresh rate.

16. The method of claim 14, wherein configuring the first partition further comprises: The error correction capability to be implemented for the data stored in the first partition is determined based on one or more parameters; as well as The configuration will perform error detection and error correction code (ECC) operations with the determined error correction capabilities on the data in the first partition.

17. The method of claim 14, wherein receiving the one or more parameters indicating the request to subdivide the memory device into the plurality of partitions for use by the host system comprises: Receive an indication of the memory size parameter of the first partition.

18. The method of claim 14, wherein receiving the one or more parameters indicating the request to subdivide the memory device into the plurality of partitions for use by the host system comprises: Receive an indication of durability parameters, which indicate the number of write cycles to be performed at the first partition during the lifetime of the memory device.

19. The method of claim 14, further comprising: During the operation of the memory device, monitor one or more operational metrics associated with the one or more parameters; Determine that the one or more operational metrics satisfy a threshold, the threshold indicating that the first partition is being used in a manner different from that indicated by the one or more parameters; as well as In response to determining that one or more operational metrics meet the threshold, at least one of the configuration settings is adjusted during runtime.

20. The method of claim 14, wherein the plurality of partitions includes a first partition and a second partition, wherein the second partition is configured to store video items acquired by an Internet Protocol (IP) camera, wherein the first partition is configured to store analysis data generated by the IP camera using the video items, wherein a user selects the configuration settings of the first partition, and wherein the second partition is configured with default configuration settings.

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