Memory application verification platform and interaction method

Abstract

The invention discloses a memory application verification platform and an interaction method. The platform comprises a low-speed memory verification system, a high-speed memory verification system and an upper computer, according to the low-speed memory verification system, a daughter board and mother board connection mode is adopted, low-speed memories such as SPIflash and SRAM are tested by replacing a memory test daughter board, and a mother board is responsible for logic control and function read-write control and can monitor current change and test direct-current parameters such as leakage current; the high-speed memory verification system adopts a single mother board mode to perform function and storage verification on high-speed memories such as DDR, SDRAM and the like, and drives and monitors the single event effect through a K7 chip. In the interaction method, the upper computer realizes process control and data interaction based on a Windows system, sends a command and records parameters according to a preset process, and transmits data back to an external field system according to a protocol. The device is compatible with various memory types, the test cost is saved, the reliability of components is guaranteed, and quality control is realized.

Description

Technical Field

[0001] This invention belongs to the field of memory application verification technology, specifically relating to a memory application verification platform and interaction method. Background Technology

[0002] In the field of electronic components, the reliability of memory is crucial for the stable operation of electronic systems, especially in some military applications where quality control is paramount. Currently, there is limited research in China on design methodologies for memory application verification platforms, while practical application verification is needed for various memory types, including Nandflash, MRAM, SPIflash, SRAM, EEPROM, Norflash, configuration PROM, and DDR high-speed memory.

[0003] In existing technologies, different types and specifications of memory often require dedicated verification platforms, resulting in long verification cycles, high costs, and difficulties in unified management and standardized testing processes. This fails to meet the stringent reliability verification requirements of fields such as military applications. Therefore, there is an urgent need for a platform and interaction method that is compatible with multiple memory types, offers flexible configuration, and enables efficient and reliable verification to ensure component reliability and achieve quality control. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a memory application verification platform and interaction method to solve or partially solve the problems mentioned in the background art.

[0005] In view of the above objectives, in a first aspect, the present invention provides a memory application verification platform, including a low-speed memory verification system, a high-speed memory verification system, and a host computer;

[0006] The low-speed memory verification system includes a first external power supply, an oscilloscope, a pattern generator board, a memory test motherboard, a high-speed connector, and a memory test daughterboard. The first external power supply powers the memory test motherboard. The pattern generator board is connected to the memory test motherboard to provide test pattern signals. The oscilloscope is connected to the memory test motherboard to acquire test waveforms. The memory test motherboard is connected to the memory test daughterboard via the high-speed connector. The system allows for testing of specified low-speed memory devices by replacing the memory test daughterboard.

[0007] The high-speed memory verification system includes a second external power supply and an SDRAM test board, wherein the second external power supply supplies power to the SDRAM test board.

[0008] The host computer is communicatively connected to the memory test motherboard of the low-speed memory verification system and the SDRAM test board of the high-speed memory verification system, respectively, to realize the control and data interaction of the low-speed memory verification system and the high-speed memory verification system.

[0009] As a preferred solution for a memory application verification platform, the low-speed memory objects used in the low-speed memory verification system include at least one of SPI flash, SRAM, Nor Flash, NAND Flash, MRAM, and EEPROM.

[0010] The high-speed memory objects used in the high-speed memory verification system include at least one of DDR high-speed memory and SDRAM.

[0011] As a preferred solution for a memory application verification platform, the memory test motherboard of the low-speed memory verification system is a shared control board, which performs logic control and functional read / write control on the memory under test.

[0012] The memory test motherboard is divided into a power module, a control core module, a first host computer communication module, and a daughterboard interface. The memory test motherboard leads the control I / O, monitoring I / O, clock signal, and backup power used by the memory daughterboard to the daughterboard interface.

[0013] As a preferred solution for a memory application verification platform, the memory test sub-board of the low-speed memory verification system is connected to the memory test motherboard, and the pins of the device under test are led out to the connectors on the memory test sub-board. If the IO level of the device under test is inconsistent with that provided by the memory test motherboard, the memory test sub-board is provided with a level conversion circuit, which is powered by the power module of the memory test motherboard.

[0014] As a preferred solution for a memory application verification platform, the memory test motherboard further includes an FPGA, a current monitoring circuit, and a DC parameter measurement circuit. The FPGA, as the control core, is electrically connected to the current monitoring circuit, the DC parameter measurement circuit, the first host computer communication module, and the daughterboard interface, respectively, and is used to generate control timing and coordinate their operation. The current monitoring circuit is used to monitor the current changes of the memory under test, and the DC parameter measurement circuit is used to perform leakage current, VOH, and VOL parameter tests. The first host computer communication module is connected to the host computer via wired communication to realize data interaction between the test motherboard and the host computer.

[0015] As a preferred solution for a memory application verification platform, the SDRAM test board of the high-speed memory verification system is equipped with a DDR chip under test, a DC parameter measurement circuit, a current monitoring circuit, a second host computer communication module, and a control core K7 chip.

[0016] The control core K7 chip is electrically connected to the DDR chip under test, the DC parameter measurement circuit, the current monitoring circuit and the second host computer communication module, respectively, and is used to drive the DDR chip under test to complete the function and storage verification.

[0017] The DC parameter measurement circuit is used for auxiliary monitoring of the chip under abnormal conditions, and the current monitoring circuit is used for auxiliary monitoring of the chip's operating status.

[0018] The second host computer communication module establishes a communication connection with the host computer and transmits the test results of single-event lockout and single-event interruption effect back to the host computer's human-computer interaction platform in real time.

[0019] As a preferred solution for memory application verification platform, for NAND Flash type devices, the memory test motherboard brings out RD, WE, CE, ALE, and CLE, and uses FPGA to simulate the entire timing process to perform bad block identification, read, write, and erase operations on NAND Flash type devices; if the IO power supply of NAND Flash type devices is different, the IO level is converted through a power conversion chip.

[0020] As a preferred solution for the memory application verification platform, when performing single-event experiments on Nor Flash, the memory test motherboard leads out WE, CE, RST, OE, WP, data lines DQ0-DQ7 and address lines A0-A10, and simulates the entire timing process through FPGA to perform read, write and erase operations on Nor Flash; if the I / O power supply of Nor Flash is different, the I / O level is converted through a power conversion chip.

[0021] As a preferred solution for a memory application verification platform, the host computer's software system configuration interface includes menu, login, plan, device, test plan, test program, test, user, and setting function options, as well as test items, test number, test name, test status, and sub-step display areas. It also has parameter display areas for power supply and oscilloscope devices.

[0022] Secondly, the present invention provides an interaction method based on the memory application verification platform of the first aspect, comprising the following steps:

[0023] The host computer software uses the host as a carrier and adopts the Windows operating system to realize the process control and data interaction functions of the low-speed memory verification system and the high-speed memory verification system.

[0024] During the process control, the host computer sends read and write commands to the external power supply, oscilloscope, graphics generation board, memory test motherboard of the low-speed memory verification system, and the second external power supply and SDRAM test board of the high-speed memory verification system according to the preset process, adjusts the output parameters, records the test parameters of the memory under test, and receives the returned results.

[0025] During the data interaction process, the host computer transmits the collected test data back to the field system in accordance with the prescribed protocol format. The test data includes the device number, test package, filling package, and inspection position.

[0026] As a preferred method of interaction, the software system configuration interface of the host computer includes a settings window and a memory selection window; different test programs are selected according to the memory type and model of the single-particle experiment, and after the test is completed, the test results are sent back to the field system.

[0027] As a preferred method of interaction, the host computer establishes communication with the low-speed memory verification system through the first host computer communication module of the memory test motherboard, and establishes communication with the high-speed memory verification system through the second host computer communication module of the SDRAM test board, thereby realizing unified control and data interaction between the low-speed memory verification system and the high-speed memory verification system.

[0028] The beneficial effects of the technical solution provided by this invention are as follows:

[0029] First, it boasts strong compatibility, supporting various memory types, including low-speed memories such as SPI flash, SRAM, Norflash, NANDFlash, MRAM, and EEPROM, as well as high-speed memories such as DDR and SDRAM, making it widely applicable. Its configurable interface design allows it to adapt to different memory specifications, enhancing the platform's flexibility and versatility.

[0030] Secondly, in terms of hardware structure, low-speed memory adopts a mother-daughter board connection method. Different low-speed memory can be tested by replacing different test daughter boards without redesigning the mother board, saving test cycle and test cost. The mother and daughter boards are connected by high-speed flexible flat cables, which facilitates various reliability tests and is easy to operate.

[0031] Third, the test signals for high-speed memory are directly generated by the FPGA, and the frequency meets the minimum 600Mbps rate of DDR devices. It can output accurate and stable high-speed signals, ensuring the accuracy of the verification of high-speed memory functions and storage.

[0032] Fourth, the host computer software is compatible with both high-speed DDR and low-speed memory, enabling process control and data interaction for the verification system of both types of memory. The system configuration interface is also fully functional, allowing users to select test programs according to different experimental needs, thus improving the system's usability.

[0033] Fifth, it can perform comprehensive verification of memory, including functional and DC parameter (leakage current, VOH, VOL, etc.) tests for low-speed memory, as well as functional and storage verification, single-event lockout, and single-event interruption effect verification for high-speed memory, ensuring the reliability of components and helping to achieve quality control. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in this invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the test board structure of the low-speed memory verification system provided in an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of the test board structure of the high-speed memory-like verification system provided in an embodiment of the present invention;

[0037] Figure 3 This is a diagram of a low-speed memory test motherboard architecture provided in an embodiment of the present invention;

[0038] Figure 4 This is a memory test subboard architecture diagram provided in an embodiment of the present invention;

[0039] Figure 5 This is a diagram of the NAND FLASH control structure provided in an embodiment of the present invention;

[0040] Figure 6 This is a diagram of the NOR FLASH control structure provided in an embodiment of the present invention;

[0041] Figure 7 This is a schematic diagram of the high-speed memory test board structure provided in an embodiment of the present invention;

[0042] Figure 8 This is a system configuration interface provided in an embodiment of the present invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0044] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this invention should have the ordinary meaning understood by those skilled in the art to which this invention pertains. The terms "comprising" or "including," or similar words used in the embodiments of this invention, mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0045] In the field of electronic components, memory is the core component for information storage, and its reliability directly affects the stable operation of the entire electronic system. Especially in fields such as military industry where the reliability requirements of components are extremely high, the quality control of memory is even more crucial.

[0046] Currently, there is relatively little research in China on the design methods of memory application verification platforms. However, in practical applications, it is necessary to conduct comprehensive application verification for various types of memory, including Nandflash, MRAM, SPIflash, SRAM, EEPROM, Norflash, configuration PROM, and DDR high-speed memory.

[0047] In existing technologies, dedicated verification platforms are often required for different types and specifications of memory, resulting in long verification cycles, high costs, and difficulties in achieving unified management and standardized testing processes for various types of memory. Furthermore, during the verification process, there is a lack of efficient and compatible solutions for testing DC parameters (such as leakage current, VOH, VOL, etc.) of low-speed memory and verifying the functionality and storage performance of high-speed memory, failing to meet the stringent reliability verification requirements of military and other fields.

[0048] Therefore, there is an urgent need for a platform and corresponding interaction method that is compatible with multiple memory types, has flexible configuration capabilities, and enables efficient and reliable verification, in order to ensure the reliability of components and achieve quality control. The following are the specific details of embodiments of the present invention.

[0049] See Figure 1 and Figure 2 This invention provides a memory application verification platform, including a low-speed memory verification system, a high-speed memory verification system, and a host computer;

[0050] The low-speed memory verification system includes a first external power supply, an oscilloscope, a pattern generator board, a memory test motherboard, a high-speed connector, and a memory test daughterboard. The first external power supply provides power to the memory test motherboard, ensuring power supply to the motherboard and connected daughterboards, and is the basic energy source for the operation of the entire low-speed verification system. The pattern generator board is connected to the memory test motherboard to provide test pattern signals, providing diverse input pattern data for memory functional testing to meet the needs of different functional verification scenarios. The oscilloscope is connected to the memory test motherboard to acquire test waveforms, and waveform analysis allows for intuitive judgment of memory performance in signal transmission, response, etc. The memory test motherboard is connected to the memory test daughterboard via the high-speed connector. By replacing the memory test daughterboard, specific low-speed memory devices can be tested, enabling rapid switching tests of different types of low-speed memory and improving testing efficiency.

[0051] The high-speed memory verification system includes a second external power supply and an SDRAM test board. The second external power supply supplies power to the SDRAM test board to ensure stable power support during the high-speed memory verification process.

[0052] The host computer is communicatively connected to the memory test motherboard of the low-speed memory verification system and the SDRAM test board of the high-speed memory verification system, respectively, to realize the control and data interaction of the two systems. Through a unified control center, the test process of the two systems is coordinated and the test data is centrally processed, thereby improving the overall integrity and ease of operation of the platform.

[0053] In one possible embodiment, the low-speed memory verification system applies at least one of SPI flash, SRAM, NorFlash, NAND flash, MRAM, and EEPROM; the high-speed memory verification system applies at least one of DDR high-speed memory and SDRAM. This design enables the platform to cover a variety of common memory types. Whether low-speed or high-speed memory, application verification can be completed on this platform, broadening its applicability and meeting the needs for verifying different types of memory.

[0054] See Figure 3In one possible embodiment, the memory test motherboard of the low-speed memory verification system is a shared control board that performs logic control and functional read / write control on the memory under test. The memory test motherboard is divided into a power supply module, a control core module, a first host computer communication module, and a daughterboard interface. The power supply module is responsible for supplying power to the relevant circuits of the motherboard and daughterboard to ensure the normal operation of each module. The control core module acts as the control center of the motherboard, issuing logic control and read / write control commands. The first host computer communication module realizes data transmission and command interaction between the motherboard and the host computer. The daughterboard interface is the physical interface connecting the motherboard and the daughterboard. The memory test motherboard leads out control I / O, monitoring I / O, clock signals, and the backup power supply used by the memory daughterboard to the daughterboard interface, enabling the daughterboard to obtain the necessary control signals, monitoring signals, clock signals, and power, ensuring that the memory under test on the daughterboard can be effectively controlled and monitored. At the same time, the lead-out of the backup power supply separates the power supply of the peripheral circuits of the daughterboard from that of the memory under test, making it easier to monitor the current changes of the memory under test more accurately.

[0055] See Figure 3 In one possible embodiment, the memory test motherboard further includes an FPGA, a current monitoring circuit, and a DC parameter measurement circuit. The FPGA, as the control core, is electrically connected to the current monitoring circuit, the DC parameter measurement circuit, the first host computer communication module, and the daughterboard interface, respectively, and is used to generate control timing and coordinate operation. Due to its programmability, the FPGA can accurately generate control timing that meets the requirements of different memories, ensuring the coordinated operation of each module. The current monitoring circuit is used to monitor the current changes of the memory under test. By monitoring the current data in real time, abnormal operating states of the memory under test, such as short circuits and leakage, can be detected in a timely manner. The DC parameter measurement circuit is used to perform leakage current, VOH, and VOL parameter tests. These parameters are key indicators for evaluating the DC characteristics of the memory and directly reflect the electrical performance of the memory. The first host computer communication module is connected to the host computer via wired communication to realize data interaction between the test motherboard and the host computer, enabling the host computer to acquire test data and issue control commands in real time.

[0056] See Figure 4In one possible embodiment, the memory test daughterboard of the low-speed memory verification system is connected to the memory test motherboard. The memory test daughterboard leads the pins of the device under test (DUT) to a connector so that signal transmission can be achieved through the daughterboard interface of the motherboard. If the I / O level of the DUT is inconsistent with that provided by the memory test motherboard, the memory test daughterboard is provided with a level conversion circuit. The level conversion circuit is powered by the power module of the memory test motherboard. The level conversion circuit can convert the I / O level of the motherboard to the level required by the DUT, solve the level mismatch problem, ensure normal communication between the DUT and the motherboard, and avoid test errors or device damage caused by level differences.

[0057] See Figure 5 In one possible embodiment, for NAND Flash devices, the memory test motherboard brings out RD, WE, CE, ALE, and CLE signals. These signals are the core control signals for NAND Flash operation, corresponding to read, write, chip select, address latch, and command latch functions, respectively. The entire timing process is simulated by an FPGA to perform bad block identification, read, write, and erase operations on the NAND Flash device. The timing simulated by the FPGA can accurately match the working timing requirements of the NAND Flash, ensuring that each operation is executed accurately. If the I / O power supply of the NAND Flash is different, the I / O level is converted by a power conversion chip to ensure that the I / O signal level is consistent with the device requirements, thus ensuring the accuracy of the test.

[0058] See Figure 6 In one possible embodiment, when performing a single-event experiment on the NorFlash, the memory test motherboard leads out WE, CE, RST, OE, WP, data lines DQ0-DQ7, and address lines A0-A10. These signals cover the control signals, data signals, and address signals required for NorFlash operation, meeting the comprehensive control requirements of the device in the single-event experiment. The entire timing process is simulated by an FPGA to perform read, write, and erase operations on the NorFlash. The timing generated by the FPGA can be adapted to the operating requirements of the NorFlash, ensuring that the test steps are performed in an orderly manner. If the NorFlash's I / O power supply is different, the I / O level is converted by a power conversion chip to ensure signal level compatibility and the reliability of the test data.

[0059] See Figure 7In one possible embodiment, the SDRAM test board of the high-speed memory verification system is equipped with a DDR chip under test, a DC parameter measurement circuit, a current monitoring circuit, a second host computer communication module, and a control core K7 chip. The control core K7 chip is electrically connected to the DDR chip under test, the DC parameter measurement circuit, the current monitoring circuit, and the second host computer communication module, respectively, and is used to drive the DDR chip under test to complete functional and storage verification. The K7 chip has high-speed processing capabilities and can meet the high-speed data transmission and processing requirements of the DDR chip. The DC parameter measurement circuit is used for auxiliary monitoring of the chip under abnormal conditions, providing DC parameter data when the chip malfunctions, and assisting in the analysis of the cause of the malfunction. The current monitoring circuit is used to assist in monitoring the chip's working status, tracking current changes in real time, and promptly identifying potential problems. The second host computer communication module establishes a communication connection with the host computer, transmitting the test results of single-event lockout and single-event interruption effects back to the host computer's human-machine interaction platform in real time, enabling testers to promptly grasp the performance of the DDR chip in a single-event environment.

[0060] See Figure 8 In one possible embodiment, the host computer's software system configuration interface includes menu, login, plan, device, test scheme, test program, test, user, and setting function options, as well as test items, test number, test name, test status, and sub-step display areas. It also includes parameter display areas for power supplies and oscilloscopes. These function options and display areas provide users with comprehensive operation access and information feedback. After logging in and verifying their entry into the system, users can complete operations such as test plan formulation, device selection, and scheme configuration through the menu functions. During the test, various test information is displayed in real time, allowing users to easily monitor progress. The device parameter display area can display the operating parameters of devices such as power supplies and oscilloscopes in real time, ensuring that the test is conducted with correct parameter settings, thus improving the system's operability and the controllability of the test.

[0061] The method of using the platform of this invention is as follows:

[0062] System setup:

[0063] Assemble a low-speed memory verification system: Connect the first external power supply to the memory test motherboard to power the motherboard; connect the graphics generator board and oscilloscope to the memory test motherboard respectively. The graphics generator board is used to provide test graphics signals, and the oscilloscope is used to acquire test waveforms; connect the memory test motherboard to the corresponding memory test daughterboard through a high-speed connector, and select the corresponding daughterboard according to the type of low-speed memory under test.

[0064] Assemble the high-speed SDRAM verification system: Connect the second external power supply to the SDRAM test board to power it.

[0065] Connecting to the host computer: Establish communication connections between the host computer and the memory test motherboard of the low-speed memory verification system and the SDRAM test board of the high-speed memory verification system to achieve data interaction and control.

[0066] Host computer configuration:

[0067] Launch the host computer software, which uses the host computer as a platform and runs on the Windows operating system. Log in to the system through the login function in the system configuration interface.

[0068] In the configuration interface, select the type (low-speed such as SPI flash, SRAM, etc., high-speed such as DDR, SDRAM, etc.) and specific model of the memory to be tested through the "Device" option.

[0069] Depending on the type and model of the selected memory, choose the corresponding test plan and program in the "Test Plan" and "Test Program" options, or adjust the test parameters through the "Settings" window.

[0070] Low-speed memory testing:

[0071] The memory test motherboard serves as a shared control board, generating control timing sequences through its internal FPGA to perform logic control and functional read / write control on the low-speed memory under test.

[0072] During the test, the current monitoring circuit monitors the current change of the memory under test in real time, and the DC parameter measurement circuit tests DC parameters such as leakage current, VOH and VOL. The test data is transmitted to the host computer through the first host computer communication module.

[0073] If the I / O level of the low-speed memory under test is inconsistent with that provided by the memory test motherboard, the level conversion circuit on the daughterboard will convert the I / O level of the motherboard to the level required by the device under test, ensuring that the test proceeds normally.

[0074] For specific types of low-speed memory such as NAND Flash, the memory test motherboard outputs signals such as RD, WE, and CE, and the timing process is simulated by the FPGA to complete operations such as bad block identification, reading, writing, and erasing; if the IO power supply is different, the IO level is converted by the power conversion chip.

[0075] High-speed memory testing:

[0076] The control core K7 chip on the SDRAM test board drives the DDR chip under test to complete the function and storage verification. During the test, the current monitoring circuit assists in monitoring the chip's working status, and the DC parameter measurement circuit assists in monitoring when the chip is abnormal.

[0077] The test signal for high-speed memory is generated by the FPGA, and the frequency meets the minimum 600Mbps rate of DDR type devices to ensure the accuracy and stability of the test signal.

[0078] Test results such as single-event lockout and single-event interruption effects generated during the test are transmitted back to the host computer's human-computer interaction platform in real time through the second host computer communication module.

[0079] Data interaction and result processing:

[0080] In process control, the host computer sends read and write commands to each device according to the preset process, adjusts the device output, records test parameters, and receives the returned results.

[0081] During the data interaction process, the host computer transmits the collected test data back to the field system in accordance with the specified protocol format (including device number, test package, filler package, inspection position, etc.).

[0082] After the test is completed, the system configuration interface of the host computer will display the test status and results. Users can view detailed results through the "Test" option. These results will also be automatically sent back to the field system for subsequent analysis and quality control.

[0083] Change the test object:

[0084] If other types of low-speed memory need to be tested, only the corresponding memory test daughter board needs to be replaced, without replacing the memory test mother board. This is convenient and saves testing time and costs.

[0085] If you need to test other types of high-speed memory, ensure that the SDRAM test board is compatible, and then select the corresponding test program through the host computer to start the test.

[0086] This invention also provides an interaction method for a memory application verification platform based on the above embodiments, comprising the following steps:

[0087] The host computer software uses the host as a carrier and adopts the Windows operating system to realize the process control and data interaction functions of the low-speed memory verification system and the high-speed memory verification system.

[0088] Specifically, the Windows operating system is used as the carrier because of its good compatibility and user interactivity, which facilitates the development of a graphical user interface, enabling operators to intuitively configure and test the system. The host computer software, as the core control unit, needs to connect to both low-speed and high-speed verification systems. Through a unified software architecture, cross-system process control and data processing are achieved to ensure that the two types of systems can respond to operation commands in a coordinated manner.

[0089] During the process control, the host computer sends read and write commands to the external power supply, oscilloscope, graphics generation board, memory test motherboard of the low-speed memory verification system, and the second external power supply and SDRAM test board of the high-speed memory verification system according to the preset process, adjusts the output parameters, records the test parameters of the memory under test, and receives the returned results.

[0090] Specifically, the preset process is an automated test logic pre-written according to the test standards and requirements of different memories. The host computer achieves precise control of each device by sending read and write commands: for example, sending voltage adjustment commands to the external power supply to match the working voltage of the memory under test, sending trigger and sampling commands to the oscilloscope to capture key test waveforms, and sending graphics data generation commands to the graphics generation board to provide test input signals; by recording test parameters (such as current, voltage, timing signals, etc.) in real time and receiving status information returned by the devices, the test process can be dynamically monitored to see if it meets expectations, and abnormalities can be detected in time to terminate the test or adjust the parameters.

[0091] During the data interaction process, the host computer transmits the collected test data back to the field system in accordance with the specified protocol format. The test data includes the device number, test package, filler package, and inspection position.

[0092] Specifically, the specified protocol format is designed to ensure the integrity and readability of data during transmission. The device number is used to identify the test device, the test packet contains actual test data (such as the functional verification results of the memory, parameter test values, etc.), the padding packet is used to supplement the data length to meet the requirements of the protocol frame format, and the check bit verifies whether there are errors in the data transmission through a check algorithm (such as CRC check). The design of the return field system enables the test data to be centrally stored and analyzed, which facilitates the subsequent tracing of the memory's reliability data and supports quality control decisions.

[0093] In one possible embodiment, the software system configuration interface of the host computer includes a settings window and a memory selection window; different test programs are selected according to the memory type and model of the single-particle experiment, and after the test is completed, the test results are sent back to the field system.

[0094] Specifically, the settings window is used to configure test environment parameters (such as power supply voltage range, oscilloscope sampling rate, etc.), and the memory selection window displays supported memory types and models through drop-down menus or lists. After the operator selects according to the actual test object, the software will automatically associate the corresponding test program (pre-programmed test logic and steps for that memory model). This design realizes automated adaptation of the test process and avoids errors caused by manual configuration. The mechanism for transmitting test results back to the field system ensures the traceability of single-event test data and provides data support for analyzing the performance degradation law of memory under radiation environment.

[0095] In one possible embodiment, the host computer establishes communication with the low-speed memory verification system through the first host computer communication module of the memory test motherboard, and establishes communication with the high-speed memory verification system through the second host computer communication module of the SDRAM test board, thereby realizing unified control and data interaction between the low-speed memory verification system and the high-speed memory verification system.

[0096] The first and second host computer communication modules adopt communication protocols adapted to their respective systems (e.g., UART for low-speed systems and Ethernet for high-speed systems) to ensure that data transmission rate and reliability match system requirements. By distinguishing the addresses or identifiers of the two communication modules, the host computer can simultaneously send instructions to or receive data from both types of systems, realizing a centralized management mode of "one controlling two". This architecture reduces hardware redundancy, simplifies system wiring, and, through software-level priority scheduling, ensures that real-time test data from high-speed memory is transmitted first, avoiding the impact of low-speed data congestion on the timeliness of high-speed testing.

[0097] The embodiments of this invention are intended to cover all such substitutions, modifications, and variations falling within the scope of the claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this invention should be included within the scope of protection of this invention.

Claims

1. A memory application verification platform, characterized in that, This includes a low-speed memory verification system, a high-speed memory verification system, and a host computer; The low-speed memory verification system includes a first external power supply, an oscilloscope, a pattern generator board, a memory test motherboard, a high-speed connector, and a memory test daughterboard. The first external power supply powers the memory test motherboard. The pattern generator board is connected to the memory test motherboard to provide test pattern signals. The oscilloscope is connected to the memory test motherboard to acquire test waveforms. The memory test motherboard is connected to the memory test daughterboard via the high-speed connector. The system allows for testing of specified low-speed memory devices by replacing the memory test daughterboard. The high-speed memory verification system includes a second external power supply and an SDRAM test board, wherein the second external power supply supplies power to the SDRAM test board. The host computer is communicatively connected to the memory test motherboard of the low-speed memory verification system and the SDRAM test board of the high-speed memory verification system, respectively, to realize the control and data interaction of the low-speed memory verification system and the high-speed memory verification system.

2. The memory application verification platform according to claim 1, characterized in that, The low-speed memory verification system applies to at least one of the following low-speed memory objects: SPI flash, SRAM, Nor Flash, NAND Flash, MRAM, and EEPROM. The high-speed memory objects used in the high-speed memory verification system include at least one of DDR high-speed memory and SDRAM.

3. The memory application verification platform according to claim 1, characterized in that, The memory test motherboard of the low-speed memory verification system is a shared control board, which performs logic control and functional read / write control on the memory under test. The memory test motherboard is divided into a power module, a control core module, a first host computer communication module, and a daughterboard interface. The memory test motherboard leads the control I / O, monitoring I / O, clock signal, and backup power used by the memory daughterboard to the daughterboard interface.

4. The memory application verification platform according to claim 3, characterized in that, The memory test sub-board of the low-speed memory verification system is connected to the memory test motherboard. The pins of the device under test are led out to the connectors on the memory test sub-board. If the IO level of the device under test is inconsistent with that provided by the memory test motherboard, the memory test sub-board is provided with a level conversion circuit, which is powered by the power module of the memory test motherboard.

5. The memory application verification platform according to claim 3, characterized in that, The memory test motherboard also includes an FPGA, a current monitoring circuit, and a DC parameter measurement circuit. The FPGA, as the control core, is electrically connected to the current monitoring circuit, the DC parameter measurement circuit, the first host computer communication module, and the daughterboard interface, respectively, and is used to generate control timing and coordinate operation. The current monitoring circuit is used to monitor the current change of the memory under test, and the DC parameter measurement circuit is used to perform leakage current, VOH, and VOL parameter tests. The first host computer communication module is connected to the host computer via wired communication to realize data interaction between the test motherboard and the host computer.

6. The memory application verification platform according to claim 1, characterized in that, The SDRAM test board of the high-speed memory verification system is equipped with a DDR chip under test, a DC parameter measurement circuit, a current monitoring circuit, a second host computer communication module, and a control core K7 chip. The control core K7 chip is electrically connected to the DDR chip under test, the DC parameter measurement circuit, the current monitoring circuit and the second host computer communication module, respectively, and is used to drive the DDR chip under test to complete the function and storage verification. The DC parameter measurement circuit is used for auxiliary monitoring of the chip under abnormal conditions, and the current monitoring circuit is used for auxiliary monitoring of the chip's operating status. The second host computer communication module establishes a communication connection with the host computer and transmits the test results of single-event lockout and single-event interruption effect back to the host computer's human-computer interaction platform in real time.

7. The memory application verification platform according to claim 2, characterized in that, For NAND Flash devices, the memory test motherboard brings out RD, WE, CE, ALE, and CLE, and uses an FPGA to simulate the entire timing process to perform bad block identification, read, write, and erase operations on the NAND Flash devices. If the I / O power supplies of the NAND Flash devices are different, the I / O levels are converted through a power conversion chip.

8. The memory application verification platform according to claim 2, characterized in that, When performing a single-event experiment on Nor Flash, the memory test board leads out WE, CE, RST, OE, WP, data lines DQ0-DQ7 and address lines A0-A10. The entire timing process is simulated by FPGA to perform read, write and erase operations on Nor Flash. If the I / O power supply of Nor Flash is different, the I / O level is converted by a power conversion chip.

9. The memory application verification platform according to claim 1, characterized in that, The host computer's software system configuration interface includes menu, login, plan, device, test plan, test program, test, user, and setting function options, as well as test items, test number, test name, test status, and sub-step display areas. It also has parameter display areas for power supply and oscilloscope devices.

10. An interaction method based on the memory application verification platform according to any one of claims 1-9, characterized in that, Includes the following steps: The host computer software uses the host as a carrier and adopts the Windows operating system to realize the process control and data interaction functions of the low-speed memory verification system and the high-speed memory verification system. During the process control, the host computer sends read and write commands to the external power supply, oscilloscope, graphics generation board, memory test motherboard of the low-speed memory verification system, and the second external power supply and SDRAM test board of the high-speed memory verification system according to the preset process, adjusts the output parameters, records the test parameters of the memory under test, and receives the returned results. During the data interaction process, the host computer transmits the collected test data back to the field system in accordance with the prescribed protocol format. The test data includes the device number, test package, filling package, and inspection position.

11. The interaction method according to claim 10, characterized in that, The host computer's software system configuration interface includes a settings window and a memory selection window; different test programs are selected according to the memory type and model of the single-particle experiment, and after the test is completed, the test results are sent back to the field system.

12. The interaction method according to claim 11, characterized in that, The host computer establishes communication with the low-speed memory verification system through the first host computer communication module of the memory test motherboard, and establishes communication with the high-speed memory verification system through the second host computer communication module of the SDRAM test board, thereby realizing unified control and data interaction between the low-speed memory verification system and the high-speed memory verification system.

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