Doherty amplifier with surface mount package carrier and peaking amplifier

Abstract

Embodiments of a Doherty amplifier include a module substrate, a first surface mount device and a second surface mount device coupled to a top surface of the module substrate, and an impedance translator line assembly. The first and second surface mount devices include first and second amplifier die, respectively. The impedance translator line assembly is electrically connected between outputs of the first and second amplifier die. The impedance translator line assembly includes an impedance translator line coupled to the module substrate, a first lead of the first surface mount device coupled between the first amplifier die output and a proximal end of the impedance translator line, and a second lead of the second surface mount device coupled between the second amplifier die output and a distal end of the impedance translator line. According to further embodiments, the impedance translator line assembly has an electrical length of 90 degrees at a fundamental operating frequency of the Doherty amplifier.

Description

Technical Field

[0001] Embodiments of the subject matter described herein generally relate to radio frequency (RF) amplifiers, and more specifically, to multipath amplifiers (e.g., Doherty amplifiers) and amplifier modules. Background Technology

[0002] Doherty power amplifiers are ubiquitous in cellular base station transmitters because the Doherty power amplifier architecture is known to improve the compensation efficiency of spectrum-efficient modulation compared to other types of amplifiers. The high efficiency of Doherty power amplifiers makes this architecture suitable for current and next-generation wireless systems. However, increasingly higher operating frequencies (e.g., in the gigahertz (GHz) range) and the growing trend towards system miniaturization pose challenges to the traditional Doherty power amplifier architecture, particularly in semiconductor packaging design. With the continued increase in frequency, there is a need for efficient Doherty power amplifier implementations that can achieve high-efficiency operation in low-cost, small-coverage solutions. Summary of the Invention

[0003] According to one aspect of the present invention, a Doherty amplifier is provided, comprising:

[0004] A module substrate, the module substrate having a top substrate surface;

[0005] A first surface mount device coupled to the surface of the top substrate, wherein the first surface mount device includes a first amplifier die;

[0006] A second surface mount device coupled to the surface of the top substrate, wherein the second surface mount device includes a second amplifier die; and

[0007] An impedance converter circuit assembly electrically connected between the outputs of the first amplifier die and the second amplifier die, wherein the impedance converter circuit assembly includes:

[0008] An impedance converter line coupled to the module substrate, wherein the impedance converter line has a near end and a far end.

[0009] The first lead of the first surface mount device has a proximal end electrically coupled to the output of the first amplifier die and a distal end coupled to the proximal end of the impedance converter line, and

[0010] The second lead of the second surface mount device has a proximal end electrically coupled to the output of the second amplifier die and a distal end coupled to the distal end of the impedance converter line.

[0011] According to one or more embodiments, the first lead and the second lead are selected from square flat no-lead (QFN) package leads, gull wing leads, contact grid array (LGA) package leads and ball grid array (BGA) package leads.

[0012] According to one or more embodiments, a first electrical length between the proximal end and the distal end of the first lead is in the range of 2 to 16 degrees, a second electrical length between the proximal end and the distal end of the impedance converter line is in the range of 10 to 80 degrees, a third electrical length between the proximal end and the distal end of the second lead is in the range of 2 to 16 degrees, and the total electrical length between the outputs of the first amplifier die and the second amplifier die includes the first electrical length, the second electrical length, and the third electrical length, and the total electrical length is 90 degrees at the fundamental operating frequency of the Doherty amplifier.

[0013] According to one or more embodiments, the proximal ends of the first lead and the second lead are electrically coupled to the outputs of the first amplifier die and the second amplifier die via bonding wires.

[0014] According to one or more embodiments, the first lead is a first vertical conductor that conducts a first electrical signal between the proximal end and the distal end of the first lead in a direction that is angularly deviated from the main signal conduction direction through the first amplifier die; and the second lead is a second vertical conductor that conducts a second electrical signal between the proximal end and the distal end of the second lead in a direction that is angularly deviated from the main signal conduction direction through the second amplifier die.

[0015] According to a second aspect of the present invention, a Doherty amplifier is provided, comprising:

[0016] A module substrate, the module substrate having a top substrate surface;

[0017] An impedance converter line coupled to the module substrate, wherein the impedance converter line has a proximal end and a distal end, and the impedance converter line is characterized by a first electrical length between the proximal end and the distal end of the impedance converter line.

[0018] A first surface mount device coupled to the surface of the top substrate, wherein the first surface mount device includes a first package, a first vertical lead, and a first amplifier die coupled to the first package, wherein the first vertical lead has a proximal end inside the first package and a distal end outside the first package, wherein the proximal end of the first vertical lead is above the bottom surface of the first surface mount device, wherein the first vertical lead is characterized by a second electrical length between the proximal end and the distal end of the first vertical lead, wherein the proximal end of the first vertical lead is electrically coupled to the output terminal of a first power transistor integrally formed with the first amplifier die, and wherein the distal end of the first vertical lead is coupled to the proximal end of the impedance converter line; and

[0019] A second surface mount device coupled to the surface of the top substrate, wherein the second surface mount device includes a second package, a second vertical lead, and a second amplifier die coupled to the second package, wherein the second vertical lead has a proximal end inside the second package and a distal end outside the second package, wherein the proximal end of the second vertical lead is above the bottom surface of the second surface mount device, wherein the second vertical lead is characterized by a third electrical length between the proximal end and the distal end of the second vertical lead, wherein the proximal end of the second vertical lead is electrically coupled to the output terminal of a second power transistor integrally formed with the second amplifier die, and wherein the distal end of the second vertical lead is coupled to the distal end of the impedance converter line.

[0020] According to one or more embodiments, each of the first surface mount device and the second surface mount device is a square flat no-lead (QFN) package device, and the distal ends of the first vertical lead and the second vertical lead are coplanar with the bottom surfaces of the first surface mount device and the second surface mount device.

[0021] According to one or more embodiments, the first vertical lead and the second vertical lead are gull-wing leads.

[0022] According to one or more embodiments, each of the first package and the second package includes a contact grid array (LGA) at the bottom surface of the first surface mount device and the second surface mount device.

[0023] According to one or more embodiments, each of the first package and the second package includes a ball grid array (BGA), the ball grid array (BGA) comprising an array of balls at the bottom surface of the first surface mount device and the second surface mount device.

[0024] According to one or more embodiments, the first electrical length is in the range of 10 degrees to 80 degrees, the second electrical length is in the range of 2 degrees to 16 degrees, the third electrical length is in the range of 2 degrees to 16 degrees, and the total electrical length between the output terminals of the first power transistor and the second power transistor includes the first electrical length, the second electrical length and the third electrical length, and the total electrical length is 90 degrees at the basic operating frequency of the Doherty amplifier.

[0025] According to one or more embodiments, the total electrical length is affected by the parasitic output capacitance of the first power transistor and the second power transistor.

[0026] According to one or more embodiments, the proximal end of the first vertical lead is electrically coupled to the output terminal of the first power transistor via at least one first bonding line, wherein the at least one first bonding line is characterized by a fourth electrical length; and the proximal end of the second vertical lead is electrically coupled to the output terminal of the second power transistor via at least one second bonding line, wherein the at least one second bonding line is characterized by a fifth electrical length.

[0027] According to one or more embodiments, the first electrical length is in the range of 10 degrees to 80 degrees, the second electrical length is in the range of 2 degrees to 16 degrees, the third electrical length is in the range of 2 degrees to 16 degrees, the fourth electrical length is in the range of 3 degrees to 24 degrees, the fifth electrical length is in the range of 3 degrees to 24 degrees, and the total electrical length between the output terminals of the first power transistor and the second power transistor includes the first electrical length, the second electrical length, the third electrical length, the fourth electrical length, and the fifth electrical length, and the total electrical length is 90 degrees at the fundamental operating frequency of the Doherty amplifier.

[0028] According to one or more embodiments, each of the output terminals of the first amplifier die and the second amplifier die has a side pad, the at least one first bonding line or the at least one second bonding line is coupled to the side pad, and the at least one first bonding line and the at least one second bonding line each extend in a direction orthogonal to the main signal conduction direction through the first amplifier die or the second amplifier die.

[0029] According to one or more embodiments, the first vertical lead is a first vertical conductor that conducts a first electrical signal between the proximal end and the distal end of the first vertical lead in a direction that is angularly deviated from the main signal conduction direction through the first amplifier die; and the second vertical lead is a second vertical conductor that conducts a second electrical signal between the proximal end and the distal end of the second vertical lead in a direction that is angularly deviated from the main signal conduction direction through the second amplifier die.

[0030] According to one or more embodiments, the first surface mount device and the second surface mount device are arranged orthogonally, and the impedance converter line has an L-shape.

[0031] According to one or more embodiments, the first surface mount device and the second surface mount device are arranged in parallel, and the impedance converter line is straight.

[0032] According to one or more embodiments, the first amplifier is a carrier amplifier, and the second amplifier is a peaking amplifier.

[0033] According to one or more embodiments, the first amplifier is a peaking amplifier, and the second amplifier is a carrier amplifier. Attached Figure Description

[0034] A more complete understanding of the subject matter can be obtained by referring to the detailed description and claims when considered in conjunction with the following drawings, wherein similar reference numerals refer to similar elements throughout the drawings.

[0035] Figure 1 This is a schematic diagram of a Doherty amplifier according to an exemplary embodiment;

[0036] Figure 2 This is a schematic diagram illustrating a carrier device, a peaking device, and a series of inductor components forming a converter line assembly between the output of the carrier device and the combination node, according to an exemplary embodiment.

[0037] Figure 3 This is a Smith chart illustrating impedance transformation that can be performed using exemplary embodiments of converter line components;

[0038] Figure 4 This is a top view of a leadless packaged amplifier device according to an exemplary embodiment;

[0039] Figure 5 This is according to an exemplary embodiment. Figure 4 A cross-sectional side view of a leadless packaged amplifier device along line 5-5, the amplifier device being further coupled to an amplifier module substrate;

[0040] Figure 6 This is according to an exemplary embodiment. Figure 5 Isometric view of the leadless packaged amplifier device and amplifier module substrate;

[0041] Figure 7 This is a top view of a Doherty amplifier module having leadless carrier and peaking amplifier devices in an orthogonal arrangement according to an exemplary embodiment; and

[0042] Figure 8 This is a top view of a Doherty amplifier module having leadless carrier and peaking amplifier devices in a parallel arrangement, according to an exemplary embodiment. Detailed Implementation

[0043] An embodiment of the Doherty amplifier includes a module substrate having a top substrate surface, a first surface mount device coupled to the top substrate surface, a second surface mount device coupled to the top substrate surface, and an impedance converter circuit assembly. The first surface mount device includes a first amplifier die, the second surface mount device includes a second amplifier die, and the impedance converter circuit assembly is electrically connected between the outputs of the first and second amplifier dies. The impedance converter circuit assembly includes an impedance converter line, a first lead of the first surface mount device, and a second lead of the second surface mount device. The impedance converter line is coupled to the module substrate and has a proximal end and a distal end. The first lead has a proximal end electrically coupled to the output of the first amplifier die and a distal end coupled to the proximal end of the impedance converter line. The second lead has a proximal end electrically coupled to the output of the second amplifier die and a distal end coupled to the distal end of the impedance converter line.

[0044] In another embodiment, the first and second leads are selected from Quad Flat No-Lead (QFN) package leads, gull-wing leads, LGA (Large Grid Array) package leads, and BGA (Ball Grid Array) package leads. In yet another embodiment, the first electrical length between the near and far ends of the first lead is in the range of 2 to 16 degrees, the second electrical length between the near and far ends of the impedance converter line is in the range of 10 to 80 degrees, the third electrical length between the near and far ends of the second lead is in the range of 2 to 16 degrees, and the total electrical length between the outputs of the first and second amplifier dies includes the first, second, and third electrical lengths, wherein the total electrical length is 90 degrees at the fundamental operating frequency of the Doherty amplifier. In yet another embodiment, the near ends of the first and second leads are electrically coupled to the outputs of the first and second amplifier dies via bonding wires. In yet another embodiment, the first lead is a first vertical conductor that conducts a first electrical signal between the proximal and distal ends of the first lead at an angle deviating from the main signal conduction direction through the first amplifier die, and the second lead is a second vertical conductor that conducts a second electrical signal between the proximal and distal ends of the second lead at an angle deviating from the main signal conduction direction through the second amplifier die.

[0045] Another embodiment of the Doherty amplifier includes a module substrate having a top substrate surface, an impedance converter line coupled to the module substrate, a first surface mount device coupled to the top substrate surface, and a second surface mount device coupled to the top substrate surface. The impedance converter line has a proximal end and a distal end, and is characterized by a first electrical length between the proximal and distal ends of the impedance converter line. The first surface mount device includes a first package, a first vertical lead, and a first amplifier die coupled to the first package. The first vertical lead has a proximal end inside the first package and a distal end outside the first package. The proximal end of the first vertical lead is above the bottom surface of the first surface mount device, and is characterized by a second electrical length between the proximal and distal ends of the first vertical lead. The proximal end of the first vertical lead is electrically coupled to the output of a first power transistor integrally formed with the first amplifier die, and the distal end of the first vertical lead is coupled to the proximal end of the impedance converter line. The second surface mount device includes a second package, a second vertical lead, and a second amplifier die coupled to the second package. The second vertical lead has a proximal end inside the second package and a distal end outside the second package. The proximal end of the second vertical lead is above the bottom surface of the second surface mount device, and the second vertical lead is characterized by a third electrical length between its proximal and distal ends. The proximal end of the second vertical lead is electrically coupled to the output terminal of the second power transistor integrally formed with the second amplifier die, and the distal end of the second vertical lead is coupled to the distal end of the impedance converter circuit.

[0046] In another embodiment, each of the first and second surface mount devices is a square flat no-lead (QFN) package, and the distal ends of the first and second vertical leads are coplanar with the bottom surfaces of the first and second surface mount devices. In yet another embodiment, the first and second vertical leads are gull-wing leads. In yet another embodiment, each of the first and second packages includes a contact grid array (LGA) comprising a contact array on the bottom surfaces of the first and second surface mount devices. In yet another embodiment, each of the first and second packages includes a ball grid array (BGA) comprising a ball array on the bottom surfaces of the first and second surface mount devices. In yet another embodiment, the first electrical length is in the range of 10 to 80 degrees, the second electrical length is in the range of 2 to 16 degrees, the third electrical length is in the range of 2 to 16 degrees, and the total electrical length between the output terminals of the first power transistor and the second power transistor includes the first electrical length, the second electrical length, and the third electrical length, and the total electrical length is 90 degrees. In yet another embodiment, the total electrical length is affected by the parasitic output capacitance of the first power transistor and the second power transistor. In yet another embodiment, the proximal end of the first vertical lead is electrically coupled to the output terminal of the first power transistor through at least one first bonding wire, characterized by a fourth electrical length; the proximal end of the second vertical lead is electrically coupled to the output terminal of the second power transistor through at least one second bonding wire, characterized by a fifth electrical length. In yet another embodiment, the first electrical length is in the range of 10 to 80 degrees, the second electrical length is in the range of 2 to 16 degrees, the third electrical length is in the range of 2 to 16 degrees, the fourth electrical length is in the range of 3 to 24 degrees, and the fifth electrical length is in the range of 3 to 24 degrees. The total electrical length between the output terminals of the first power transistor and the second power transistor includes the first, second, third, fourth, and fifth electrical lengths, and the total electrical length is 90 degrees. In yet another embodiment, each of the output terminals of the first amplifier die and the second amplifier die has a side pad, to which at least one first bonding line or at least one second bonding line is coupled, and the at least one first bonding line and the at least one second bonding line each extend in a direction orthogonal to the main signal conduction direction through the first amplifier die or the second amplifier die.In yet another embodiment, the first vertical lead is a first vertical conductor that conducts a first electrical signal between its proximal and distal ends at an angle deviating from the main signal conduction direction through the first amplifier die, and the second vertical lead is a second vertical conductor that conducts a second electrical signal between its proximal and distal ends at an angle deviating from the main signal conduction direction through the second amplifier die. In yet another embodiment, the first surface mount device and the second surface mount device are arranged orthogonally, and the impedance converter line has an L-shape. In yet another embodiment, the first surface mount device and the second surface mount device are arranged in parallel, and the impedance converter line is straight. In yet another embodiment, the first amplifier is a carrier amplifier, and the second amplifier is a peaking amplifier. In yet another embodiment, the first amplifier is a peaking amplifier, and the second amplifier is a carrier amplifier.

[0047] A conventional bidirectional Doherty power amplifier includes a signal distributor with an input and two outputs, where each distributor output is connected to the input of a carrier amplifier or a peaking amplifier. The outputs of the carrier and peaking amplifiers are electrically connected to a combination node configured to combine (in-phase) the amplified output signals from the carrier and peaking amplifiers. More specifically, in a “0-90” Doherty power amplifier, the output of one of the amplifiers is directly connected to the combination node, where this direct connection ideally features a phase shift of approximately 0 degrees. Conversely, the output of the other amplifier is coupled to the combination node via an impedance converter, characterized by a phase shift of approximately 90 degrees. Typically, the impedance converter consists of a series of conductive structures, including impedance converter lines (e.g., transmission lines on a printed circuit board (PCB)), which occupy a large portion of the area used for the impedance converter. Doherty power amplifiers implemented in an integrated package typically have tight size constraints that dictate the potential physical length of the impedance converter lines. Generally, from a loss perspective, it is desirable to make the impedance converter lines as compact as possible. However, there is an inherent trade-off between the compactness of the impedance converter lines and the ease of designing a Doherty power amplifier with optimized performance.

[0048] According to various Doherty power amplifier embodiments, each of the carrier and peaking amplifiers is implemented as one or more amplifier dies (i.e., integrated circuits (ICs) or semiconductor dies carrying power transistors) packaged in a surface-mount package, wherein the "vertical" nature of the package leads enables the use of very compact impedance converter lines. More specifically, in this embodiment, vertical package leads are employed as part of a minimum 90-degree phase converter between the carrier and peaking amplifier outputs, and vertical package leads facilitate optimal combination at combination nodes (e.g., the peaking amplifier drain (current source)).

[0049] An impedance converter essentially comprises a series-coupled assembly of conductive components connected between a carrier and the output of a peaking amplifier die. According to one embodiment, the series-coupled assembly includes an electrical connection (e.g., a bonding wire) between the carrier and the peaking amplifier die output (e.g., the drain terminal), a vertical package lead, and an impedance converter line. This “assembly” may herein be referred to as an impedance converter and Doherty load modulation assembly, or more simply as an “impedance converter line assembly.”

[0050] The carrier amplifier and peaking amplifier can each be implemented using a single-stage or multi-stage power amplifier comprising one or more transistor integrated circuit (IC) dies. A single-stage power amplifier comprises a single power transistor, and a multi-stage power amplifier comprises at least a driver transistor connected in series with the final-stage transistor. As used herein, when the power amplifier (e.g., a carrier or peaking amplifier) ​​is a single-stage power amplifier, a single transistor stage can be considered a “final-stage” transistor. Using terminology generally applied to field-effect transistors (FETs), on the input side, the carrier amplifier and peaking amplifier can each comprise a transistor (e.g., a driver transistor and / or a final-stage transistor) having an input / control terminal (e.g., a gate) configured to receive an RF input signal, and on the output side, the carrier amplifier and peaking amplifier can each comprise a final-stage transistor having two current-conducting terminals (e.g., a drain terminal and a source terminal). In some configurations, each source terminal is coupled to a ground reference voltage node, and amplified carrier and peaking signals are provided at the drain terminal (or output) of the final-stage carrier amplifier transistor and the final-stage peaking amplifier transistor, respectively.

[0051] In a “non-inverting” Doherty power amplifier embodiment (also known as a “classical” Doherty, a “90-0” Doherty, or a “0-90” Doherty), a phase shift (multiple) is applied to the input RF signal such that the phase of the RF signal supplied to the peaking amplifier lags by approximately 90 degrees compared to the phase of the RF signal supplied to the carrier amplifier. According to the embodiment shown and described in detail here, the drain terminal of the peaking amplifier serves as a combination node for the amplified RF signal generated by the carrier and the peaking amplifier. More specifically, the accompanying drawings and the following description illustrate and discuss an embodiment of a bidirectional non-inverting Doherty power amplifier comprising a carrier amplifier and a single peaking amplifier, wherein the RF signal supplied to the input of the peaking amplifier lags by approximately 90 degrees compared to the RF signal supplied to the input of the carrier amplifier. In other words, the input RF signal of the peaking amplifier has a phase lag of approximately 90 degrees for the input RF signal of the carrier amplifier. In such an embodiment, the converter circuitry is configured to apply a phase shift (and impedance reversal) of approximately 90 degrees to the amplified carrier signal before the amplified carrier signal and the amplified peaked signal are combined at the combining node, while no substantial phase shift is applied to the amplified peaked signal before it reaches the combining node.

[0052] To provide a 90-degree phase shift and impedance reversal between the drain of the carrier amplifier and the combination node (e.g., at the drain of the final stage transistor of the peaking amplifier), the drain of the final stage carrier amplifier transistor is electrically coupled to a first end of an embodiment of the impedance converter line assembly, and a second end of the impedance converter line assembly is electrically coupled to the drain of the final stage peaking amplifier transistor (i.e., the combination node). The electrical length of the impedance converter line assembly between the drains of the carrier and final stage transistors is determined by the following: the parasitic drain-source capacitances of the carrier and peaking amplifier transistors, the electrical length of the impedance converter line (e.g., a transmission line) extending between the drains of the carrier and peaking amplifier transistors, and the electrical length of any additional series conductive structures between the drain and the ends of the impedance converter line.

[0053] In a 90-0 Doherty amplifier, the drain-source capacitance and electrical length of the additional series conductive structure are significant, so the electrical length of the impedance converter line in the impedance converter line assembly will have a value less than 90 degrees. In various embodiments, depending on the fundamental frequency f0 of the Doherty amplifier and the characteristics of the connection to the end of the impedance converter line, the electrical length of the impedance converter line can have a value ranging from approximately 10 degrees to approximately 70 degrees, although the electrical length of the impedance converter line can also be smaller or larger. At higher fundamental operating frequencies, the electrical length translates to a very short physical length of the impedance converter line, which can be difficult to achieve in a compact package arrangement. This difficulty becomes more pronounced when the dielectric constant of the substrate (e.g., PCB) to which the impedance converter line is coupled is relatively high.

[0054] Various embodiments of the subject matter of this invention overcome some or all of these challenges by utilizing a unique surface-mount package arrangement for carrier amplifiers and peaking amplifiers, which makes impedance converter components between amplifiers physically more feasible, even for Doherty amplifiers configured to operate at relatively high fundamental operating frequencies, and / or for Doherty amplifiers constrained to be mounted in a relatively compact coverage area.

[0055] It should be noted that although the figures and the following description focus on a non-inverting Doherty amplifier embodiment, other embodiments may include an "inverting" Doherty amplifier, wherein the RF signal provided to the carrier amplifier lags by approximately 90 degrees compared to the RF signal provided to the peaking amplifier, and a phase shift sufficient to phase align the amplified carrier and peaking signals is applied between the outputs of the carrier and peaking amplifiers and the combination node. Therefore, in the claims, references to "first amplifier" and "first amplifier transistor" may correspond to either a carrier amplifier (and carrier amplifier transistor) or a peaking amplifier (and peaking amplifier transistor), while references to "second amplifier" and "second amplifier transistor" may correspond to other types of amplifiers or transistors from the first type. Additionally, although the figures and the following description focus on a bidirectional Doherty amplifier, embodiments of the converter line assembly may also include other n-directional Doherty amplifiers comprising a carrier amplifier and n-1 peaking amplifiers (where n has two or more integer values, e.g., values ​​from 3 to 5).

[0056] Figure 1 This is a schematic diagram of the Doherty amplifier 100 according to an exemplary embodiment; as shown Figure 1 As shown in box 110, some or all of the components of the Doherty amplifier 100 can be implemented in a single amplifier module (e.g., some or all of the components are coupled to a single amplifier module substrate). As will be explained in detail later, and according to various embodiments, the configuration of the various amplifier components allows for a significant reduction in module size compared to conventional packaging techniques using conventional components. These miniaturization benefits can be achieved while still meeting performance standards for gain, lineability, stability, and efficiency.

[0057] In one embodiment, the Doherty amplifier 100 includes an RF input node 112, an RF output node 114, a power divider 120, a carrier amplifier path 130, a peaking amplifier path 150, an impedance converter line assembly 172, and a combination node 180. As will be discussed in more detail below, embodiments of the impedance converter line assembly 172 include a transmission line 176, leads 164, 166, and additional series components 161, 162 (e.g., bonding wires) that establish the electrical length of the impedance converter line assembly 172. Figure 2 In more detail, the parasitic output capacitance of the carrier amplifier and peaking amplifier also affects the electrical length of the impedance converter line assembly 172.

[0058] When integrated into a larger RF system, RF input node 112 is coupled to an RF signal source (not shown), and RF output node 114 is coupled to a load 190 (e.g., an antenna or other load). The RF signal source provides the RF input signal, which is an analog signal comprising spectral energy generally centered at one or more carrier frequencies. Essentially, the Doherty amplifier 100 is configured to amplify the RF input signal and produce an amplified RF signal at RF output node 114.

[0059] In one embodiment, power divider 120 has an input 122 and two outputs 124, 126. Power divider input 122 is coupled to RF input node 112 to receive an RF input signal. Power divider 120 is configured to split the RF input signal received at input 122 into a first RF signal and a second RF signal (or carrier and peaking signal), which are provided to carrier amplifier path 130 and peaking amplifier path 150, respectively, through outputs 124, 126. According to an embodiment, power divider 120 includes a first phase shift element configured to impart one or more phase shifts to the first and second RF signals to establish a phase difference (e.g., approximately 90 degrees) between the signals at outputs 124, 126. In a non-inverting Doherty amplifier, a phase shift is applied such that the phase of the RF signal provided to the peaking amplifier lags by approximately 90 degrees compared to the phase of the RF signal provided to the carrier amplifier. Therefore, at outputs 124 and 126, the carrier signal and the peaking signal can be approximately 90 degrees out of phase with each other.

[0060] When the Doherty amplifier 100 has a symmetrical configuration (i.e., where the carrier amplifier power transistor and the peaking amplifier power transistor are substantially the same size), the power divider 120 can split or distribute the RF input signal received at input 122 into two signals with substantially equal power. Conversely, when the Doherty amplifier 100 has an asymmetrical configuration (i.e., where one of the amplifier power transistors, typically the peaking amplifier transistor, is significantly larger), the power divider 120 can output signals with unequal power. For example, in one embodiment, the peaking amplifier transistor may be approximately twice the size of the carrier amplifier transistor, and the power divider 120 can provide a peaked signal with approximately twice the power of the carrier signal. In some embodiments, the power divider 120 can be implemented with passive components of a fixed value. In other embodiments, the power divider 120 can be implemented with one or more controllable variable attenuators and / or variable phase shifters, which allows the power divider 120 to attenuate the carrier and peaked signals and / or phase shift the carrier and peaked signals based on externally provided control signals.

[0061] Outputs 124 and 126 of power divider 120 are connected to carrier amplifier path 130 and peaking amplifier path 150, respectively. Carrier amplifier path 130 is configured to amplify the carrier signal from power divider 120 and provide the amplified carrier signal to power combining node 180. Similarly, peaking amplifier path 150 is configured to amplify the peaked signal from power divider 120 and provide the amplified peaked signal to power combining node 180, wherein paths 130 and 150 are designed such that the amplified carrier and peaked signals arrive substantially in phase at power combining node 180.

[0062] According to an embodiment, the carrier amplifier path 130 includes an input circuit 170 (e.g., including impedance matching circuitry), a carrier amplifier device 132, and an impedance converter line assembly 172. The peaking amplifier path 150 includes an input circuit 171 (e.g., including impedance matching circuitry) and a peaking amplifier device 152. The carrier amplifier device 132 and the peaking amplifier device 152 correspond to the carrier and peaking amplifiers of the Doherty amplifier 100, respectively, and are implemented using packaged carrier amplifier devices 132 and peaking amplifier devices 152. According to one embodiment, and as will be described in more detail later, each of the carrier amplifier device 132 and the peaking amplifier device 152 is packaged as a surface mount device, such as a rectangular leadless package (e.g., a square flat leadless (QFN) package) or other types of surface mount devices. Thus, each device 132, 152 includes a plurality of leads (e.g., leads 423 to 426, ...). Figure 4 ), thermal pads or flanges (e.g., flange 411, Figure 4 A package that holds the leads and flanges in a fixed orientation relative to each other (e.g., lower package 412). Figure 4 One or more power transistor dies (e.g., die 432) are attached to the flange. Figure 4 ), and electrical conductors that electrically couple the die to the leads (e.g., bonding wires 455, 465, 462, 463, Figure 4 ).

[0063] In various embodiments, the carrier amplifier device 132 includes an RF input lead 134, an RF input terminal 135 electrically connected to the RF input lead 134, an RF output terminal 138, an RF output lead 164 electrically connected to the RF output terminal 138, and one or more amplification stages 136, 137 coupled between the input terminal 135 and the output terminal 138. The RF input lead 134 is coupled to a first output 124 of the power divider 120 via an input circuit 170, and thus receives the carrier signal generated by the power divider 120. One or more bias voltage terminals (e.g., drain bias voltage lead 116) may be coupled to one or more external bias circuits (e.g., via terminal 117) for providing DC bias voltages to the amplification stages 136, 137.

[0064] Each amplification stage 136, 137 of the carrier amplifier device 132 includes a power transistor. More specifically, each power transistor includes a control terminal (e.g., a gate terminal) and a first current-carrying terminal and a second current-carrying terminal (e.g., a drain terminal and a source terminal). In a single-stage device that includes a single power transistor (e.g., stage 137 instead of stage 136), the control terminal of the single power transistor corresponds to an RF input terminal 135, which is electrically connected to an RF input lead 134. One of the current-carrying terminals (e.g., a drain terminal or a source terminal) corresponds to an RF output terminal 138, which is electrically connected to an RF output lead 164. The other current-carrying terminal (e.g., a source terminal or a drain terminal) is electrically connected to a ground reference (e.g., a package flange to which the transistor die is coupled). Conversely, a two-stage device will include two power transistors coupled in series (e.g., two stages 136, 137), where the first transistor serves as a drive amplifier transistor with relatively low gain, and the second transistor serves as an output stage (or final stage) amplifier transistor with relatively high gain. In this embodiment, the control terminal of the drive amplifier transistor corresponds to RF input 135, which is electrically connected to RF input lead 134. One of the current-carrying terminals of the drive amplifier transistor (e.g., the drain or source terminal) is electrically connected to the control terminal of the final-stage amplifier transistor, and the other current-carrying terminal of the drive amplifier transistor (e.g., the source or drain terminal) is electrically connected to a ground reference. Furthermore, one of the current-carrying terminals of the final-stage amplifier transistor (e.g., the drain or source terminal) corresponds to RF output 138, which is electrically connected to RF output lead 164. The other current-carrying terminal of the final-stage amplifier transistor (e.g., the source or drain terminal) is electrically connected to a ground reference.

[0065] In addition to power transistors, it may also include input and output impedance matching networks and bias circuitry. Figure 1 (Not shown in the image) is electrically coupled to the carrier amplifier device 132 as part of the carrier amplifier device 132 and / or part of the input and output impedance matching network and bias circuit system. Additionally, in embodiments where the carrier amplifier device 132 is a two-stage device, an inter-stage matching network (…) may also be included. Figure 1 (Not shown in the image) is part of the carrier amplifier device 132.

[0066] Referring now to peaking amplifier path 150, in one embodiment, it includes input circuitry 171 (e.g., including impedance matching circuitry) and peaking amplifier device 152. In various embodiments, peaking amplifier device 152 includes an RF input lead 154, a first RF input terminal 155 electrically connected to the RF input lead 154, an RF output terminal 158, an RF output lead 160 electrically connected to the RF output terminal 158, a second RF input lead 166 electrically connected to the RF output terminal 158, and one or more amplification stages 156, 157 coupled between the input terminal 155 and the output terminal 158. RF input lead 154 is coupled to a second output 126 of power divider 120 via input circuitry 171, and therefore receives the peaking signal generated by power divider 120. One or more bias voltage terminals (e.g., drain bias voltage lead 119) may be coupled to one or more external bias circuits (e.g., through terminal 118) for providing DC bias voltage to amplification stages 156, 157.

[0067] Similar to carrier amplifier device 132, each amplification stage 156, 157 of peaking amplifier device 152 includes a power transistor. More specifically, each power transistor includes a control terminal (e.g., a gate terminal) and a first current-carrying terminal and a second current-carrying terminal (e.g., a drain terminal and a source terminal). In a single-stage device that includes a single power transistor (e.g., stage 157 instead of stage 156), the control terminal of the single power transistor corresponds to an RF input terminal 155, which is electrically connected to an RF input lead 154. One of the current-carrying terminals (e.g., a drain terminal or a source terminal) corresponds to an RF output terminal 158, which is electrically connected to a second RF input lead 166 and an RF output lead 160. The other current-carrying terminal (e.g., a source terminal or a drain terminal) is electrically connected to a ground reference (e.g., a package flange to which the transistor die is coupled). Conversely, a two-stage device would comprise two series-coupled power transistors (e.g., two stages 156, 157), where the first transistor functions as a drive amplifier transistor with relatively low gain, and the second transistor functions as an output stage (or final stage) amplifier transistor with relatively high gain. In such an embodiment, the control terminal of the drive amplifier transistor corresponds to RF input 155, which is electrically connected to RF input lead 154. One of the current-carrying terminals of the drive amplifier transistor (e.g., drain or source) is electrically connected to the control terminal of the final stage amplifier transistor, and the other current-carrying terminal (e.g., source or drain) is electrically connected to a ground reference. Furthermore, one of the current-carrying terminals of the final stage amplifier transistor (e.g., drain or source) corresponds to RF output 158, which is electrically connected to RF input lead 166 and RF output lead 160. The other current-carrying terminal (e.g., source or drain) of the final stage amplifier transistor is electrically connected to a ground reference.

[0068] In addition to power transistors, it may also include input and output impedance matching networks and bias circuitry. Figure 1 (Not shown in the image) is electrically coupled to the peaking amplifier device 152 as part of the peaking amplifier device 152 and / or part of the input and output impedance matching network and bias circuit system. Additionally, in embodiments where the peaking amplifier device 152 is a two-stage device, an inter-stage matching network (…) may also be included. Figure 1 (Not shown in the image) is part of the peaking amplifier device 152.

[0069] The RF output 158 ​​of the peaking amplifier device 152 is coupled to the power combination node 180 and the impedance converter line assembly 172. According to an embodiment, the RF output 158 ​​of the peaking amplifier device 152 and the combination node 180 are implemented using common components. More specifically, in an embodiment, the RF output 158 ​​of the peaking amplifier device 152 is configured to serve as the output 158 ​​of both the combination node 180 and the peaking amplifier device 152.

[0070] The RF outputs 138 of the carrier amplifier device 132 and 158 of the peaking amplifier device 152 are coupled together via an impedance converter line assembly 172. Alternatively, in other words, the RF output of the carrier amplifier device 132 is electrically coupled to the combination node 180 via the impedance converter line assembly 172, and the RF output of the peaking amplifier device 152 is directly coupled to the combination node 180. As will be discussed in detail below, embodiments of the impedance converter line assembly 172 include an RF output lead 164 of the carrier amplifier device 132, a transmission line 176 (e.g., a microstrip or stripline transmission line), an RF input lead 166 of the peaking amplifier device 152, and additional electrical connections 161, 163 (e.g., bonding wires) between the carrier amplifier 138 and the peaking amplifier output 158 ​​and the leads 164, 166.

[0071] According to an embodiment, the impedance converter line assembly 172 is a λ / 4 phase shift circuit that imparts a relative phase shift of approximately 90 degrees to the carrier signal at its fundamental operating frequency f0 after the carrier signal has been amplified by the carrier amplifier device 132. A first or "proximal" end of the impedance converter line assembly 172 is coupled to the RF output 138 of the carrier amplifier device 132, and a second or "far" end of the impedance converter line assembly 172 is coupled to the power combination node 180.

[0072] Amplifier 100 is designed such that, during operation, the amplified carrier and peaked RF signals are combined substantially in phase (or coherently) at combination node 180. Combination node 180 is electrically coupled to RF output node 114 via RF output lead 160 and output impedance matching network 184. Thus, the amplified and combined RF output signal is provided to RF output node 114 via lead 160 and network 184. In one embodiment, the output impedance matching network 184 between combination node 180 and RF output node 114 provides an appropriate load impedance to each of carrier amplifier device 132 and peaked amplifier device 152. A finally amplified RF output signal is generated at RF output node 114, to which output load 190 (e.g., an antenna) is connected.

[0073] Amplifier 100 is configured such that carrier amplifier path 130 amplifies a relatively low-level input signal, and the two amplifier paths 130 and 150 are combined to amplify a relatively high-level input signal. This can be achieved, for example, by biasing carrier amplifier device 132 to operate in Class AB mode and biasing peaking amplifier device 152 to operate in Class C mode.

[0074] According to an embodiment, the carrier amplifier device 132 and the peaking amplifier device 152 are oriented relative to each other such that corresponding portions of the carrier amplifier path 130 and the peaking amplifier path 150 extend in substantially different directions from each other. As used herein, the term "signal path" refers to the path followed by the RF signal through the circuit. For example, a portion of a first signal path through the carrier amplifier device 132 extends between the RF input 135 and the RF output 138 in a first direction (indicated by arrow 130). Similarly, a portion of a second signal path through the peaking amplifier device 152 extends between the RF input 155 and the RF output 158 ​​in a second direction (indicated by arrow 150), wherein the first and second directions are substantially different from each other. In the illustrated embodiment, the first and second directions are perpendicular to each other (i.e., separated by an angle of 90 degrees). In other embodiments, the first and second directions may be separated by an angle of less than or greater than 90 degrees. For example, in other embodiments, the first and second directions may be separated by an angle between 45 degrees and 315 degrees. In other embodiments, the first direction and the second direction may be parallel (e.g., the carrier amplifier device 132 and the peaking amplifier device 152 may be oriented in the same direction).

[0075] As described above, embodiments of the impedance converter line assembly 172 include a transmission line 176, leads 164, 166, and (optionally) additional series assemblies 161, 162 (e.g., bonding wires). Now, in conjunction with... Figure 2 The electrical characteristics of the impedance converter line assembly 172 are discussed in more detail. More specifically, Figure 2 This indicates that the output stage 237 of the carrier device (e.g., output stage 137) is a carrier device. Figure 1 The output terminal 238 of the peaking device and the output stage 257 of the peaking device (e.g., output stage 157, Figure 1 The output terminals 258 of the impedance converter line assembly 272 are connected via an embodiment (e.g., assembly 172, ...). Figure 1 A schematic diagram of the interconnection.

[0076] exist Figure 2 In the diagram, node 238 represents the drain of the output stage 237 of the carrier device (e.g., node 138 of carrier device 132). Figure 1 ), and node 258 represents the drain of the output stage 257 of the peaking device (e.g., node 258 of the peaking device 152, Figure 1 As described above, node 258 also corresponds to composite node 280 (e.g., composite node 180, Figure 1 Capacitor 234 represents the parasitic drain-source shunt capacitance of the carrier output stage 237, and capacitor 254 represents the parasitic drain-source shunt capacitance of the peaking output stage 257. Bracket 272 includes impedance converter line components (e.g., component 172). Figure 1 The impedance converter line assembly interconnects the drains of the carrier output stage 237 and the peaking output stage 257 (nodes 238, 258).

[0077] Impedance converter line assembly 272 includes multiple components coupled in series. According to an embodiment, the series-coupled components of impedance converter line assembly 272 include:

[0078] - The first inductor 265 (e.g., connected to connection 161) coupled to the output terminal 238 (e.g., the drain terminal) of the carrier output stage 237. Figure 1 Or join line array 465, Figure 4 It has an inductance value ranging from about 0.5 nanohenries (nH) to about 1.0 nH, although the inductance value can be lower or higher;

[0079] - A second inductor 264 coupled to the first inductor 265 at node 273 (e.g., corresponding to RF output lead 164, Figure 1 Or lead 764, Figure 7 , 8 (The inductance), which has an inductance value in the range of about 0.25nH to about 0.75nH, although the inductance value can be lower or higher;

[0080] - A transmission line 276 coupled to the second inductor 265 at node 275 (e.g., transmission line 176, Figure 1 Or transmission lines 774, 774', or 874. Figure 7 , 8 It has an electrical length ranging from approximately 10 degrees to approximately 80 degrees, depending on the basic operating frequency and other factors (discussed below);

[0081] - A third inductor 266 coupled to transmission line 276 at node 277 (e.g., corresponding to RF input lead 166, Figure 1 Or lead wire 766, Figure 7 , 8 (The inductance), which has an inductance value in the range of about 0.25nH to about 0.75nH, although the inductance value can be lower or higher;

[0082] - Fourth inductor 262 (e.g., Figure 1 The connection 162 or the bonding line array 462 in the middle, Figure 4 It is coupled between node 279 and the output terminal 258 (e.g., the drain terminal) of peaking output stage 257, and thus coupled to combination node 280, which has an inductance value in the range of about 0.5nH to about 1.0nH, although the inductance value may be lower or higher.

[0083] supply Figure 3 The Smith chart 300 is used to illustrate the impedance shift caused by parasitic shunt capacitors 234, 254 and various series elements in the impedance converter line assembly 272. More specifically, the Smith chart 300 is used to illustrate how the overall Zmod transformation occurs at the drain 258 of the peaking device 257 (or combination node 280 (e.g., combination node 180)). Figure 1 The impedance occurs between the drain 238 of the carrier device 237 and the peaking device 237 via the impedance converter line assembly 272. The exemplary Smith chart 300 assumes an impedance of approximately 25 ohms at the drain 238 of the carrier device 237 and approximately 100 ohms at the combination node 280 (i.e., the drain 258 of the peaking device 257). Based on the description herein, those skilled in the art will understand how the Smith chart can be modified for systems with different characteristic impedances. Essentially, the impedance at the combination node (e.g., the drain 258 of the peaking device 257) is significantly lower (e.g., 50 to 100 ohms lower) than the impedance at the drain 238 of the carrier device 237. For example, in some embodiments, the impedance at the drain 258 of the peaking device 257 can range from approximately 10 ohms to approximately 30 ohms, and the impedance at the drain 238 of the carrier device 237 can range from approximately 75 ohms to approximately 125 ohms, although this impedance can also be lower or higher than these ranges.

[0084] Point 301 on the Smith chart 300 corresponds to the impedance (e.g., 25 ohms) at the drain 258 of the peaking device 257, which corresponds to the combination node (e.g., combination node 180). Figure 1 By moving from point 301 and from the drain 258 of peaking device 257 to the drain 238 of carrier device 237, the parasitic drain-source shunt capacitance 254 of peaking device 257 causes it to move downwards along a constant conductance circle to point 302. The shunt inductor circuit (e.g., the inductor portion of shunt circuit 791) Figure 7 This can be coupled to the drain of peaking device 257 to cause a slight upward shift to point 303. First inductor 262 then causes a normal upward shift along the constant impedance circle to point 304 (e.g., corresponding to node 279). Second inductor 266 (e.g., RF output lead 166, Figure 1 This causes the impedance change to shift additionally upwards along the constant impedance circle to point 305 (e.g., corresponding to node 277). As used herein, “usually along” the constant conductance or impedance circle means that the impedance change occurs substantially along the circle, but there may be slight deviations from that circle on the Smith chart.

[0085] Transmission line 276 causes an additional upward movement along the constant impedance circle to point 306 (e.g., corresponding to node 275). From there, a third inductor 264 (e.g., RF input lead 164)... Figure 1 This causes the carrier device 237 to move upwards along the constant impedance circle to point 307 (e.g., corresponding to node 273). Next, the fourth inductor 265 causes it to move upwards along the constant impedance circle to point 308 (e.g., corresponding to node 238). Finally, the parasitic drain-source shunt capacitance 234 causes the carrier device 237 to move downwards along the constant conductance circle to point 309. Similarly, the shunt inductor circuit (e.g., the inductor portion of the shunt circuit 790)... Figure 7 It can be coupled to the drain of the carrier device 237 to cause a slight upward shift to point 310, which corresponds to the impedance (e.g., 100 ohms) at the drain 238 of the carrier device 237.

[0086] In summary, to ensure that the amplified RF signal generated by carrier amplifier 237 and the amplified RF signal generated by peaking amplifier 257 are combined in phase at the combination node (e.g., sharing a ground with the drain 258 of peaking device 257), the total electrical length between drain nodes 238 and 258 should be approximately 90 degrees. Additionally, the impedance transformation provided by impedance converter line assembly 272 should be designed to appropriately match the output impedances of carrier device 237 and peaking device 257. Since the inductance / impedance transformation of components 264, 266, 265, and 262 may be relatively non-adjustable, therefore... Figure 3 It is clearly shown that the electrical length / impedance of the transmission line 276 can be selected to achieve the desired impedance transformation between the carrier device 237 and the peaking device 257.

[0087] In a symmetrical Doherty amplifier where the carrier amplifier 237 and the peaking amplifier 257 are of the same size, the drain-source capacitors 234 and 254 can have approximately the same capacitance value. However, in an asymmetrical Doherty amplifier where the peaking amplifier 257 is significantly larger than the carrier amplifier 237, the drain-source capacitor 254 of the peaking amplifier 257 can be significantly larger than the drain-source capacitor 234 of the carrier amplifier 237. In either case, the drain-source capacitor can significantly reduce the permissible electrical and physical length of the impedance transducer.

[0088] It should be noted that in actual circuit implementations, the electrical length of transmission line 276 (e.g., transmission line 176, ...) Figure 1 The dielectric constant is a essentially fixed value that can be significantly less than ninety degrees, for example, in the range of approximately 10 degrees to approximately 70 degrees. At higher frequencies, this fixed electrical length can translate into a very short physical length. This is especially true when the dielectric constant of the amplifier module substrate is high, which can be typical of printed circuit board (PCB) type substrates (e.g., amplifier module substrate 710). Figure 7 , 8 (This is the situation.) Please refer to it again. Figure 1 The relatively long physical and electrical length of transmission line 176 can therefore be adapted for relatively low operating frequencies. Furthermore, the transmission line 176 shown has an "L" shape with the carrier device 132 and peaking device 152 orthogonally arranged, which allows for a compact amplifier configuration of the carrier device 132 and peaking device 152 orthogonally arranged (e.g., as shown in...). Figure 7 (As shown). In alternative embodiments, such as transmission line 176', a relatively short, straight transmission line can be implemented. In such embodiments, the carrier device 132 and the peaking device 152 can be arranged side by side (e.g., as shown). Figure 8 (as shown, arranged in parallel) rather than orthogonal.

[0089] Now refer to Figure 4-6 Detailed description of embodiments of surface-mount amplifier devices, variations of which are suitable for use as carrier amplifier device 132 and peaking amplifier device 152 in a Doherty amplifier module (e.g., Doherty amplifier 100, Figure 1 More specifically, Figure 4 This is a top view of a surface-mount packaged amplifier device 400 according to an exemplary embodiment, and Figure 5 yes Figure 4 The device 400 is shown in a cross-sectional side view along line 5-5. Similarly, as... Figure 6 As shown in the isometric view, the surface-mount packaged amplifier device 400 can be coupled to the amplifier module substrate 510 to assemble the device into an amplifier module (e.g., a Doherty amplifier module). To enhance... Figures 4 to 6 The description of the relative orientation and direction of various components. Figures 4 to 6 Each of these includes a depiction of a three-dimensional Cartesian coordinate system 490, in which orthogonal x-axis, y-axis, and z-axis are depicted.

[0090] Amplifier device 400 essentially includes a surface mount package 410, an amplifier die 432, and a plurality of bonding wires 455, 465, 462, 463 for electrically coupling the amplifier die 432 to the surface mount package 410 via leads 434, 460, 464, 466, 471, 474. As will be explained in detail below, amplifier device 400 is configured to function as a carrier amplifier (e.g., carrier amplifier 132). Figure 1 The first variant of the amplifier device 400 is used as a peaking amplifier (e.g., peaking amplifier 152). Figure 1 The second variant can be substantially the same, except for different bonding wire connections within the package. Of course, for asymmetric Doherty amplifiers, the relative dimensions and / or current carrying capacity of the amplifier die 432 can also differ between amplifier devices 400 used as carrier or peaking amplifiers.

[0091] The surface mount package 410 has a rectangular (e.g., square) perimeter defined by a first side 413, a second side 414, a third side 415, and a fourth side 416, the four sides being on the top surface 520. Figure 5 The surface mount package 410 extends between a central thermal pad or flange 411 and an opposing bottom surface (or substrate-facing surface) 521. The surface mount package 410 includes a lead frame having a central thermal pad or flange 411 and a plurality of leads (e.g., leads 434, 460, 464, 466, 471, 474) electrically isolated from each other and held in a fixed orientation relative to each other by a lower package body 412. The lower package body 412 has opposing top surfaces 522 and bottom surfaces 523, wherein the top surface 522 of the lower package body 412 is inside the package 410, and the bottom surface 523 of the lower package body 412 also corresponds to the bottom surface 521 of the entire package 410. According to an embodiment, the lower package body 412 may be formed of a molded plastic sealing material, although in other embodiments, the package body 412 may be formed of ceramic or other high-dielectric materials.

[0092] Flange 411 is a conductive and thermally conductive solid structure located at the center of lower package 412 and extending between the top surface 522 and bottom surface 523 of lower package 412. More specifically, the top surface 524 of flange 411 is coplanar with the top surface 522 of lower package 412, and the bottom surface 525 of flange 411 is coplanar with the bottom surface 523 of lower package 412 (and with the bottom surface 521 of package 410). Flange 411 may be formed, for example, of a bulk conductive material (e.g., copper), which may or may not be plated. Alternatively, flange 411 may be formed of a composite (e.g., layered or multi-part) conductive structure. The perimeter of flange 411 (e.g., from...) Figure 4 The circumference of the amplifier die 432 (as seen in the top view) is generally equal to or greater than that of the circumference of the amplifier die 432 connected to the flange 411. As will be discussed in more detail later, the bottom surface 529 of the amplifier die 432 is physically and electrically connected (e.g., by solder, conductive adhesive, brazing, sintering or other materials) to the top surface 524 of the flange 411, and the bottom surface 525 of the flange 411 is physically and electrically connected (e.g., by solder 530, conductive adhesive or other materials) to the top surface 512 of the amplifier module substrate 510.

[0093] Multiple sets of leads 423, 424, 425, and 426 are located at or near each of the four sides 413 to 416 of the lower package 412. Specifically, in Figure 4 In the lower package 412, six aligned leads 423 to 426 are located at each of the four sides 413 to 416. Alternatively, more or fewer leads 423 to 426 may be located at or near each of the four sides 413 to 416. Each of the leads 423 to 426 is sometimes alternatively referred to as a “contact” or “pin”, and they are also formed of a bulk conductive material (e.g., copper), which may or may not be plated. Alternatively, the leads may be formed of a composite (e.g., layered or multipart) conductive structure. Essentially, each lead 423 to 426 is a generally cubic structure having a top surface 526 (or “inner end” or “proximal end”), a bottom surface 527 (or “outer end” or “far end”), and four sides. The top surface 526 is exposed at and / or coplanar with the top surface 522 of the lower package 412, the bottom surface 527 is coplanar with the bottom surface 523 of the lower package 412 (and the bottom surface 521 of the device 400), and the four sides extend between the top surface 526 and the bottom surface 527. The inner end of each lead 423 to 426 (e.g., the top surface 526) is located at a height above the bottom surface 521 of the device (and therefore at a height 512 above the module substrate 510). According to embodiments, this height, which substantially corresponds to the thickness of leads 423 to 426 (i.e., the distance between the top surface 526 and the bottom surface 527 of each lead), is in the range of approximately 0.2 mm to approximately 0.5 mm in embodiments, or in the range of approximately 0.3 mm to approximately 0.4 mm in more specific embodiments. The bottom surface 527 of each lead is exposed at the bottom surface 523 of the lower package 412 (and at the bottom surface 521 of the device 400), and one of the side surfaces of each lead 423 to 426 may be exposed at the side surfaces 413 to 416 of the lower package 412. In other embodiments, the side surfaces of the leads may not be exposed at the side surfaces 413 to 416 of the lower package 412 (e.g., a sealing material for the lower package 412 may be present between the leads 423 to 426 and the side surfaces 413 to 416 of the lower package 412). Regardless of the approach, the lead configuration ultimately facilitates a robust connection between the leads and conductive structures (e.g., traces 514, 515) located on the top surface 512 of the amplifier module substrate 510 (e.g., solder joint 532 or connection to a socket). Furthermore, the vertically packaged leads 423 to 426 help provide a 90-degree impedance transducer while allowing for the use of peaked amplifiers (e.g., peaked amplifier 752). Figure 7 , 8 The optimal combination is achieved at the drain (or current source) of the circuit. The 4-sided (square) lead arrangement also allows for a vertically and symmetrically balanced supply of drain bias voltage.

[0094] Given that the top surfaces 520, 528, and 512 of the device package 410, the planes of the amplifier die 432 and the amplifier module substrate 510 are “horizontal,” each of the leads 423 to 426 can be considered a “vertical” conductor (or vertical inductor). As used herein, a “vertical conductor” or “vertical lead” is a conductive structure that transmits electrical signals in a vertical direction from an internal or near end (e.g., the top surface 526 of leads 423 to 426) to an external or distant end (e.g., the lower surface 527 of leads 423 to 426), which is significantly raised above the top surface 512 of the amplifier module substrate 510, and the external or distant end is substantially at the top surface 512 of the amplifier module substrate 510. Between its proximal and distal ends, a "vertical conductor" (or vertical lead) can transmit a conductive signal in a direction orthogonal to (i.e., deviated from about 90 degrees) or angularly deviated from (e.g., deviated from 30 to 90 degrees) the main signal conduction direction, which is conducted through the amplifier die 432, the plane of the top surface 528 of the amplifier die 432 and / or the plane of the top surface 512 of the amplifier module substrate 510.

[0095] As will be discussed in more detail below, each of leads 423 to 426 (or each "vertical conductor" or "vertical lead") has a non-negligible inductance between its near and far ends (e.g., inductances 264 or 266). Figure 2 This results in a non-negligible phase shift and impedance transformation being applied to the signal conducted between the near and far ends of leads 423 to 426. Therefore, each vertical conductor (or vertical lead) can also be referred to as a "vertical inductor." Furthermore, because each lead 423 to 426 is angled (including orthogonal to) from the direction of signal conduction through amplifier die 432 (and also from the direction of signal conduction through transmission lines 176, 176' of the converter line assembly), the electromagnetic coupling between the signal conducted through amplifier die 432 and the signal conducted through leads 423 to 426 or the transmission lines is likely minimal.

[0096] Although leads 423 to 426 are described as a generally cubic structure forming the lead frame portion, each lead 423 to 426 may alternatively have more or fewer four sides, or may have a shape different from a cube. For example, in an alternative embodiment, instead of utilizing a QFN package (e.g., QFN package 410), the amplifier die 432 is packaged in a square flat package (QFP). Essentially, the difference between a QFP and a QFN package 410 is that a QFP includes gull-wing leads (e.g., in...). Figure 5The gull-wing lead 464' shown in the upper left corner (not the body conductive leads 423 to 426 of the lead frame) provides electrical coupling between the amplifier die 432 and the amplifier module substrate 510. Like the QFN package, the QFP package includes thermal pads or flanges (e.g., flange 411). Figure 4 ), multiple leads (in this case, gull-wing leads, for example in Figure 5 The upper left corner shows the gull-wing lead 464', and the package body that holds the flange and lead in a fixed orientation relative to each other. Each gull-wing lead 464' includes an inner end 526' (similar to the top surface 526 or inner or proximal end of leads 423 to 426) and an outer end 527' (similar to the bottom surface 527 or outer or distal end of leads 423 to 426), the inner end 526' being embedded in the package body and rising above the bottom surface 523 of the lower package body 412, and the outer end 527' being outside the lower package body 412 and coplanar with the bottom surface 523 of the lower package body 412. As will be explained in more detail below, in the QFP embodiment with gull-wing leads, the bonding wires (e.g., bonding wires 455, 465, 462, 463, ... Figure 4 The distal end of the gull-wing lead 464′ is connected to the raised inner end 526′ of each gull-wing lead 464′, and the outer distal end 527′ of the gull-wing lead 464′ is connected to a conductive structure (e.g., one of traces 514, 515 or other conductive structures) on the top surface 512 of the amplifier module substrate 510. Therefore, such a gull-wing lead 464′ can also be considered as a vertical conductor (i.e., a conductor that is angled away from or approximately orthogonal to the direction of signal conduction through the amplifier die 432 (i.e., a direction parallel to the y-axis of coordinate system 490) to the top surface 528 of the amplifier die 432, or to the top surface 512 of the amplifier module substrate 510).

[0097] In yet another alternative embodiment, the lower package 412 may include a contact grid array (LGA) or ball grid array (BGA) comprising a contact array, ball array, or pin array at the bottom surface 523 of the lower package 412. Figure 5 The lower left and lower right corners show two embodiments of LGA leads 464″ and 464″′, respectively. LGA lead 464″ is inserted from the side of the lower package 412 and extends between a top or proximal end 526″ at the top surface 522 of the lower package 412 and a bottom or distal end 527″ at the bottom surface of the lower package 412. The bottom end 527″ serves as a contact point that can be soldered to a corresponding contact on the top surface of the PCB, or can be contacted via a conductive pin protruding from the PCB. In some embodiments, such conductive leads may protrude into lead 464″ (i.e., each lead 464″ effectively serves as a single-pin socket).

[0098] The LGA lead 464″′ also inserts from the side of the lower package 412 and has a portion extending between a top or proximal end 526″′ at the top surface 522 of the lower package 412 and the bottom surface 523 of the lower package 412. However, the LGA lead 464″′ also includes a pin 550 that protrudes from the bottom surface 523 of the lower package 412, and an end 527″′ of the pin 550 corresponds to the bottom or distal end of the lead 464″′. The pin 550 is configured to be received by a socket coupled to the PCB.

[0099] Amplifier die 432 includes the main amplification circuitry of amplifier assembly 400 (e.g., amplification stages 136, 137 or 156, 157). Figure 1 As described above, amplifier die 432 is physically and electrically connected to the top surface 524 of flange 411 (e.g., using solder, conductive adhesive, brazing, sintering, or other materials). After being connected to flange 411, an electrical connection is formed between a conductive end (or pad) and some of the leads 423 to 426, which are exposed at the top surface 528 of amplifier die 432. More specifically, when package 410 is a QFN package, a first end of a bonding wire (e.g., bonding wires 455, 465, 462, 463) is connected to the conductive end at the top surface 528 of amplifier die 432, and a second end of the bonding wire is connected to the top surface 526 of some of the leads 423 to 426 (e.g., connected to leads 434, 460, 464, 466, 471, 474) (or connected to the interior or near end). In other embodiments, as previously described, the surface mount package may be a QFP, LGA, or BGA package, and the second end of the bonding wires is connected to the proximal ends 526', 526', 526'' of the corresponding leads 464', 464'', 464'''. In some embodiments, the amplifier die 432, the bonding wires (e.g., bonding wires 455, 465, 462, 463), the top surface 522 of the lower package 412, and the top surface 526 (or interior or proximal end) of the leads 423 to 426 may then be overmolded with a sealing material 540. Alternatively, a protective cap may be attached to the top surface 522 of the lower package 412 to create a sealed internal cavity containing the amplifier die 432 and the bonding wires (e.g., bonding wires 455, 465, 462, 463). In other words, the surface mount package 410 may also be a cavity QFN package (or other types of surface mount cavity packages).

[0100] Amplifier die 432 has a rectangular perimeter defined by a first side 483, a second side 484, a third side 485, and a fourth side 486, which extend between a top surface 528 and an opposing bottom surface 529 of amplifier die 432. Sides 483, 484, 485, and 486 of amplifier die 432 are parallel to device sides 413, 414, 415, and 416, respectively.

[0101] The illustrated embodiment of amplifier die 432 includes two amplifier stages, and each amplification stage (e.g., amplification stages 136, 137 or 156, 157) Figure 1 The amplifier die 432 includes power transistors 436 and 437. More specifically, the electrical components of the amplifier die 432 include, in series coupled RF input 435, integrated input matching network 456, driver transistor 436, integrated inter-stage matching network 457, final stage transistor 437, and RF output 438. Driver transistor 436 is configured to apply a relatively low gain to the RF input signal, and final stage transistor 437 is configured to apply a relatively high gain to the RF signal after the initial amplification by driver transistor 436. In other embodiments, amplifier die 432 may embody a single-stage amplifier or may include more than two amplification stages.

[0102] An RF input terminal 435, configured to receive an amplified RF signal, is electrically coupled to the gate terminal of transistor 436 via an input matching network 456, and the drain terminal of transistor 436 is electrically coupled to the gate terminal of transistor 437 via an interstage matching network 457. According to an embodiment, the drain terminal of transistor 437 is electrically coupled to an output terminal 438. The source terminals of transistors 436 and 437 are coupled to a ground reference. The signal path through amplifier die 432 extends from RF input terminal 435 to RF output terminal 438, corresponding to the x-axis of coordinate system 490. The amplified RF carrier signal is generated by amplifier die 432 at RF output terminal 438.

[0103] RF input 435 and RF output 438 each include conductive contacts exposed at the top surface 528 of amplifier die 432. In addition to the conductive contacts for RF input 435 and RF output 438, amplifier die 432 also includes multiple conductive contacts for providing gate and drain DC bias voltages to driver transistor 436 and final-stage transistor 437. Figure 4As shown, for example, a first conductive bias contact (lower left corner of amplifier die 432) is electrically coupled to the gate of power transistor 436, and a gate bias voltage can be provided to the gate via lead 471 and the junction line coupled between lead 471 and the first conductive bias contact. Similarly, a second conductive bias contact (center right side of amplifier die 432) is electrically coupled to the drain of power transistor 436, and a drain bias voltage can be provided to the drain via lead 472 and the junction line coupled between lead 472 and the second conductive bias contact. Finally, a third conductive bias contact (center left side of amplifier die 432) is electrically coupled to the gate 433 of power transistor 437, and a gate bias voltage can be provided to the gate 433 via lead 473 and the junction line coupled between lead 473 and the third conductive bias contact.

[0104] Each of transistors 436 and 437 may be a field-effect transistor (FET) (e.g., a metal-oxide-semiconductor FET (MOSFET), a laterally diffused MOSFET (LDMOS FET), a high electron mobility transistor (HEMT), etc.). Therefore, each power transistor 436 and 437 includes a control terminal (e.g., a gate terminal) and a first current-carrying terminal and a second current-carrying terminal (e.g., a drain terminal and a source terminal). Alternatively, each of transistors 436 and 437 may be a bipolar junction transistor (BJT). The references to “gate,” “drain,” and “source” commonly used herein to describe FETs are not intended to be limiting, as each of these names has similar characteristics for BJT implementations.

[0105] In some embodiments, the semiconductor technology for the power transistors 436 and 437 in the amplifier die 432 may include silicon (e.g., transistors 436 and 437 may be silicon LDMOS FETs built on silicon, silicon carbide, or other silicon-containing substrates), while in other embodiments, the semiconductor technology for the power FETs in the amplifier die 432 may include gallium nitride (GaN) (e.g., transistors 436 and 437 may be GaN FETs formed from GaN-containing layers built on silicon, GaN, or other substrates). In other embodiments, the driver transistor 436 may be included in a first IC, and the final stage transistor 437 may be included in a different second IC. In such embodiments, both the driver and final stage amplifier dies are coupled to the top surface 524 of the flange 511, and additional bonding wires may be used to electrically connect the drain of the driver transistor 436 to the gate of the final stage transistor 437. In such embodiments, the driver and final stage amplifier dies can be formed using the same semiconductor technology (e.g., silicon or GaN), or the driver and final stage amplifier dies can be formed using different semiconductor technologies (e.g., the driver stage amplifier die can be formed using silicon technology and the final stage amplifier die can be formed using GaN technology, or vice versa).

[0106] The connection between leads 423 to 426 of package 410 and amplifier die 432 will now be described in more detail. On the input side of device 400, corresponding to the RF input of device 400 (e.g., input 134 or 154), Figure 1 One or more package leads 434 are electrically coupled to conductive contacts corresponding to the RF input terminal 435 of the amplifier die 432 using bonding wires 455. On the output side of the device 400, the connection between the package leads and the RF output terminal 438 depends on whether the device 400 is configured as a carrier amplifier or a peaking amplifier. Furthermore, the connection between the package leads and the RF output terminal 438 depends on the configuration of the Doherty amplifier module (e.g., modules 700, 800). Figure 7 , 8 Is the carrier amplifier device located to the left or right of the peaking amplifier device? The following description assumes that the carrier amplifier device is typically located to the right of the peaking amplifier device. Based on this description, those skilled in the art will understand how to modify the connection between the package leads and the RF output terminal 438 of the carrier and peaking devices in an alternative configuration where the carrier amplifier device is typically located to the left of the peaking amplifier device.

[0107] According to the embodiments, and with reference to Figure 4An enlarged version of transistor 437 on the right, the RF output terminal 438 is shaped such that two sets of bonding lines (for a carrier amplifier) ​​or three sets of bonding lines (for a peaking amplifier) ​​can extend from die 432 in directions that are angularly offset from each other. More specifically, the RF output terminal 438 includes a conductive first-side pad 446, an elongated center pad 445, and a conductive second-side pad 447. The conductive first-side pad 446 is adjacent to the second side 414 of amplifier die 432, the elongated center pad 445 is adjacent to the third side 415 of amplifier die 432, and the conductive second-side pad 447 is adjacent to the fourth side 416 of amplifier die 432.

[0108] exist Figure 7 and Figure 8 This will be better understood in the discussion, when device 400 is configured to be located to the right of the peaking amplifier (e.g., carrier amplifiers 132, 732, 832, ...). Figure 1 , 7 When , , 8), it corresponds to the RF output of the device (e.g., output 164, Figure 1 One or more package leads 464 can be electrically coupled to the second-side pad 447 of the RF output terminal 438 via bonding wire 465, and an amplified carrier signal can be transmitted through the second-side pad 447, bonding wire 465, and lead 464. Figure 4 As shown, bonding wire 465 extends in a direction orthogonal to the main signal path direction through amplifier die 432. In other words, although the main signal path direction through amplifier die 432 is between terminals 435 and 438 (i.e., parallel to the x-axis of coordinate system 490), bonding wire 465 extends in an orthogonal direction (i.e., parallel to the y-axis of coordinate system 490). As will be explained in more detail below, when device 400 is used as a carrier amplifier in a Doherty power amplifier, package lead 464 and bonding wire 465 each form part of the converter line assembly between the output and combination node of the carrier amplifier. One or more other package leads 460 are electrically coupled to an elongated center pad 445 of RF output terminal 438 via bonding wire 463, such that a drain bias voltage can be provided to the drain of power transistor 437 through leads 460, bonding wire 463, and the elongated center pad 445 of RF output terminal 438.

[0109] When device 400 is configured as a peaking amplifier located to the left of the carrier amplifier (e.g., peaking amplifiers 152, 752, 852), Figure 1 , 7 When , , 8), it corresponds to the RF output of the device (e.g., output 160, Figure 1 The package lead 460 is electrically coupled to the elongated center pad 445 of the RF output terminal 438 via bonding wire 463. (The last sentence appears to be incomplete and possibly refers to a different package.) Figure 7 and8 To explain in more detail, the RF output 438 of the peaking amplifier also corresponds to the combination node of the Doherty amplifier, including device 400 (e.g., combination node 180). Figure 1 Furthermore, the combined, amplified carrier and peaked signals can be transmitted via the elongated center pad 445, bonding wire 463, and lead 460. Conversely, the package lead 464 is electrically coupled to the second-side pad 447 of the RF output terminal 438 via the bonding wire 465, allowing the drain bias voltage to be supplied to the drain of the power transistor 437 via the lead 464, bonding wire 465, and RF output terminal 438.

[0110] Because the combination node is used to combine the RF signals generated by both the peaking amplifier and the carrier amplifier, when device 400 is configured as a peaking amplifier, device 400 also includes a connection configured to receive an amplified carrier signal from the carrier amplifier. More specifically, when device 400 is configured as a peaking amplifier, one or more package leads 466 coupled to the first-side pad 446 of the RF output terminal 438 via bonding wire 462 may correspond to additional inputs of device 432, which is configured to transmit the amplified carrier signal to the RF output terminal 438 (and thus to the combination node). Figure 4 As shown, junction line 462 extends in a direction orthogonal to the direction of the main signal path through amplifier die 432. Again, although the direction of the main signal path through amplifier die 432 is between ends 435 and 438 (i.e., parallel to the x-axis of coordinate system 490), junction line 462 extends in an orthogonal direction (i.e., parallel to the y-axis of coordinate system 490). As will be explained in more detail below, when device 400 is used as a peaking amplifier in a Doherty power amplifier, package lead 466 and junction line 462 each form part of the converter line assembly between the output of the carrier amplifier and the combination node. Junction line 462 in Figure 4 They are shown in dashed lines because they are included only when device 400 is configured as a peaking amplifier, and excluded when device 400 is configured as a carrier amplifier.

[0111] The first side pad 446 and the second side pad 447 each have a length (along the x-axis of coordinate system 490) that extends parallel to the second side 484 or the fourth side 486 of the amplifier die 432, respectively. According to an embodiment, the length of each of the side pads 445, 447 is large enough that multiple bonding lines (e.g., from 2 to 10 or more) can be connected in parallel to each other along the length of the first side pad 445 or the second side pad 447. Figure 4As shown, the lengths of the side pads 445 and 447 are large enough to allow multiple bonding lines 465 and 462 to be connected, so that they can extend vertically from the sides 486 and 484 respectively.

[0112] Figure 4 Two bonding lines 465 are shown connected in parallel to side pad 447, and two bonding lines 462 are shown connected in parallel to side pad 446. In alternative embodiments, the lengths of side pads 446, 447 may be sufficient to allow fewer (e.g., as few as one) or more (e.g., 10 or more) bonding lines to be connected in parallel along the length of side pads 446, 447. For example, the length may range from about 200 micrometers to about 400 micrometers, although this length may also be smaller or larger. Side pads 446, 447 each also have sufficient width (dimension along the y-axis of coordinate system 490) to allow at least one row of bonding lines 465, 462 to be coupled to each of side pads 446, 447. For example, the width may range from about 100 micrometers to about 150 micrometers, although this width may also be smaller or larger.

[0113] An elongated center pad 445 of the RF output terminal 438 is electrically coupled to elongated side pads 446, 447. More specifically, a first end of the center pad 445 is electrically coupled to a first side pad 446, and a second end of the center pad 445 is electrically coupled to a second side pad 447. In an embodiment, the elongated center pad 445 is located near a third side surface 485 of the amplifier die 432, and the elongated center pad 445 has a length extending parallel to the third side surface 485 (along the y-axis dimension of coordinate system 490). According to an embodiment, the side pads 446, 447 and the center pad 445 have lengths perpendicular to each other. The length of the center pad 445 is large enough to allow a third plurality of bonding lines 463 to be connected in parallel along the length of the center pad 445. Figure 4 As shown, the length of the center pad 445 is large enough to allow multiple bonding lines 463 to be connected, so that they can extend vertically from the side 485. Figure 4 Four bonding lines 463 are shown connected in parallel to each other. In an alternative embodiment, the length of the center pad 445 may be sufficient to allow more (e.g., 20 or more) bonding lines to be connected in parallel along the length of the center pad 445. According to embodiments, the length may be in the range of approximately 800 micrometers to approximately 1800 micrometers, or more ideally in the range of approximately 1500 micrometers to approximately 1800 micrometers, although this length may also be smaller or larger.

[0114] In one embodiment, side pads 446, 447, and center pad 445 are integrally formed as part of the same conductive layer (e.g., a metal-5 (M5) layer in a 5-layer device). In an alternative embodiment, side pads 446, 447, and center pad 445 may be formed from different portions of a single conductive layer and electrically connected together via conductive vias, portions of other conductive layers, bonding wires, or other types of electrical conductors. Alternatively, side pads 446, 447, and center pad 445 may be formed from electrically connected portions of multiple conductive layers.

[0115] exist Figure 4 In the illustrated embodiment, terminals 435 and 438 of amplifier die 432 are electrically coupled to leads 434, 460, 464, and 466 via bonding wires (e.g., bonding wires 455, 463, 464, and 466). In other embodiments, amplifier die 432 may be a flip-chip die, and the top surface of die 432 may be directly connected to the top surface of lower package 412. In such an embodiment, terminals 435 and 438 may be replaced with contact terminals, and bonding wires 455, 463, 464, and 466 may be replaced with traces on the top surface of lower package 412 to interconnect the contact terminals with leads 434, 460, 464, and 466.

[0116] As previously described, two instances of amplifier device 400 can be surface-mounted to an amplifier module substrate to utilize the amplifier device as a carrier amplifier (e.g., carrier amplifier 132) of a Doherty amplifier module. Figure 1 ) and peaking amplifiers (e.g., peaking amplifier 152, Figure 1 ). In combination Figure 7 and Figure 8 Before describing in detail embodiments of the Doherty amplifier module, the following are provided: Figure 6 This illustrates details of how the amplifier device 400 is coupled to the top surface 512 of the amplifier module substrate 510 (without overlay molding), and details of how electrical connections are formed between device leads and conductive traces (e.g., transmission lines) on the top surface 512 of the amplifier module substrate 510. Figure 6In this configuration, RF input lead 434 is electrically connected to a first conductive trace 634 on the top surface 512 of module substrate 510, and RF output lead 460 is electrically connected to a second conductive trace 660 on the top surface 512 of module substrate 510. Additionally, final-stage gate bias lead 464 is electrically connected to a third conductive trace 514 on the top surface 512 of module substrate 510. An additional input lead 466 (for receiving amplified carrier signals) is electrically connected to a fourth conductive trace 515 on the top surface 512 of module substrate 510. Gate and drain bias leads 471 to 473 are electrically connected to additional conductive traces (not shown) on the top surface 512 of module substrate 510, which are configured to deliver DC gate and drain bias voltages to amplifier die 432 via leads 471 to 473. Figure 6 As shown, according to an embodiment, flange 411 can also be coupled to one or more leads (e.g., lead 620) via additional bonding lines (not numbered), and lead 620 can in turn be electrically coupled to additional conductive traces 630, providing an electrical connection between flange 411 and a ground reference disposed at the bottom surface 513 of module substrate 510 via substrate via 640 (i.e., a conductive via extending between the top surface 512 and the bottom surface 513 of the substrate). Alternatively, module substrate 510 may include a ground / heat dissipation structure (e.g., a conductive coin, conductive via, or other heat dissipation structure) in contact with and beneath flange 411. Solder (e.g., solder 532) can be used. Figure 5 ) or conductive adhesive, or having pins (e.g., pin 550, Figure 5 In the case of an LGA type package (where the pins can be received by a socket coupled to the PCB), physical attachment and electrical connection are formed between leads 434, 460, 464, 464′, 464″, 464″′, 466, 471 to 473, 620 and conductive traces 514, 515, 630, 634, 660.

[0117] Now we will combine Figure 7 and 8 Two embodiments of the Doherty amplifier module are described. For the sake of brevity, they will be discussed together. Figure 7 and 8 Common or similar components. More specifically, according to two exemplary embodiments, Figure 7 This is a top view of the Doherty amplifier module 700, in which the surface-mount carrier amplifier device 732 and the peaking amplifier device 752 are arranged at an angular offset (e.g., perpendicular, orthogonal), and Figure 8 This is a top view of the Doherty amplifier module 800, in which the surface-mounted carrier amplifier device 732 and peaking amplifier device 752 are arranged in parallel orientation.

[0118] Doherty amplifier modules 700 and 800 each include an amplifier module substrate 710, an RF input connector 712 and an RF output connector 714, and a power divider 720 (e.g., power divider 120). Figure 1 ), carrier amplifier device 732 (e.g., carrier amplifier device 132, 400, Figure 1 4) Peaking amplifier device 752 (e.g., peaking amplifier device 152, 400, Figure 1 , 4 ), phase shift line assembly 772 and impedance converter line assembly 872 (e.g., impedance converter line assemblies 172, 272, Figure 1 , 2 And various other circuit elements, which will be discussed in more detail below.

[0119] The amplifier module substrate 710 may be, for example, a printed circuit board (PCB) or other type of substrate. The substrate 710 has a top substrate surface 711 (or component mounting surface) and an opposing bottom substrate surface. In some embodiments, the substrate 710 may be a multilayer organic substrate (e.g., formed of PCB material) with multiple metal layers, wherein adjacent metal layers are separated by a dielectric material. According to embodiments, when the Doherty amplifier modules 700, 800 are integrated into a larger electrical system, the metal layers on the bottom substrate surface may be coupled to an external ground voltage reference. Therefore, system grounding can be established via an electrical connection (e.g., conductive vias through the substrate) between system components at or on the top substrate surface 711 and the metal layers on the bottom substrate surface.

[0120] A metal layer formed on the top substrate surface 711 is patterned to provide a plurality of conductive traces and contacts (or pads) on the top substrate surface 711. These traces and contacts enable the RF input connector 712 and RF output connector 714, input splitter 720, carrier amplifier device 732, and peaking amplifier device 752 to be electrically connected to other components that can be coupled to the top substrate surface 711. Furthermore, one or more portions of the impedance converter line assemblies 772, 872, as described in more detail below, may be formed from one or more portions of the patterned metal layer on the top substrate surface 711. In a particular embodiment, for example, the transmission lines 774 (or 774'), 874 of the impedance converter line assemblies 772, 872 may be formed from a portion of the patterned top metal layer. Conductive vias (e.g., via 640, Figure 6 It provides electrical connectivity between metal layers of substrate 710, including electrical connectivity between a patterned metal layer on the top substrate surface 711 and a metal layer on the bottom substrate surface.

[0121] Each of the carrier amplifier device 732 and the peaking amplifier device 752 is a surface-mount device (e.g., a variant of amplifier device 400). Figures 4 to 6 The surface mount device is physically coupled to the top substrate surface 711 and has leads (e.g., leads 716, 734, 754, 760, 764, 766, 765) with conductive pads and traces that are physically and electrically connected to the top surface of the substrate 710 (e.g., formed by the top metal layer of the substrate 710). Because each of the carrier amplifier device 732 and the peaking amplifier device 752 requires proximity to a ground reference, the substrate 710 may include embedded conductive coin or conductive substrate vias located beneath each device 732, 752 and extending between the top substrate surface 711 and the bottom substrate surface. Alternatively, one or more device leads (e.g., lead 620, ...) may be used. Figure 6 Access the grounding reference.

[0122] RF input connector 712 and RF output connector 714 are coupled to the side of substrate 710. RF input connector 712 corresponds to the RF input for modules 700 and 800 (e.g., RF input 112). Figure 1 ), and is therefore configured to receive an RF input signal for amplification when the RF input connector 712 is coupled to an external RF signal source. The RF output connector 714 corresponds to the RF output for modules 700, 800 (e.g., RF output 114, Figure 1 ), and is therefore configured to provide an amplified RF signal to a load (e.g., an antenna) coupled to the RF output connector 714.

[0123] RF input connector 712 is electrically coupled to input 722 (or a first port) of power divider 720. In one embodiment, power divider 720 may be a discrete packaged component mounted to top substrate surface 711, or it may be implemented using lumped components and / or conductive traces on top substrate surface 711. Either way, power divider 720 is configured to split the power of the RF input signal into carrier and peaked portions of the input signal (i.e., the carrier RF input signal and the peaked RF input signal). Furthermore, power divider 720 may include one or more phase-shifting elements configured to impart approximately 90 degrees of phase shift difference between the RF signals provided at outputs 724, 726. In an embodiment, conductive trace 781 or a transmission line on top substrate surface 711 electrically connects RF input connector 712 to input 722 (e.g., input 122) of power divider 720. Figure 1The power divider 720 is configured to receive RF input signals from RF input connector 712. The second port 723 of the power divider 720 can be coupled to ground (e.g., via a 50-ohm clock terminal). The carrier RF input signal is output at the power divider output 724 (or the third port, e.g., divider output 124). Figure 1 The signal is supplied to the carrier amplifier path at point 726 (or the fourth port, such as divider output 126), and the peaked RF input signal is output at the power divider output 726 (or the fourth port, such as divider output 126). Figure 1 The peak signal is provided to the peaking amplifier path. As mentioned earlier, the carrier and peak RF signals can have equal or unequal power.

[0124] The carrier RF signal generated at the power divider output 724 passes through the carrier amplifier path (e.g., path 130). Figure 1 The peaked RF signal generated at the power divider output 726 is amplified and then passed through the peaking amplifier path (e.g., path 150). Figure 1 The carrier amplifier path includes conductive trace 782, carrier amplifier device 732, and impedance converter line assemblies 772 and 872. The carrier RF signal generated at the power divider output 724 is transmitted through conductive trace 782 to carrier amplifier device 732 to provide the carrier amplifier device 732 with an RF carrier signal for amplification. Input impedance matching circuit (e.g., circuit 170, Figure 1 , Figure 7 , 8 (Not shown) can be coupled (e.g., along trace 782) between the power divider output 724 and the carrier amplifier device 732. The input impedance matching circuitry may include multiple discrete and / or integrated components (e.g., inductors and capacitors) configured to provide appropriate impedance matching between the first power divider output 724 and the input of the carrier amplifier device 732.

[0125] As in Figure 4 As discussed herein, the carrier amplifier device 730 has a lower package (e.g., lower package 412, Figure 4 , 5 The lower package has a first side 713, a second side 714, a third side 715, and a fourth side 716 (e.g., sides 413 to 416). Figure 4 The carrier amplifier device 730 further includes multiple leads 734, 760, 764, an amplifier die 732, and electrical connections between the amplifier die 732 and the leads 734, 760, 764.

[0126] According to an embodiment, one or more first package leads 734 (e.g., package lead 434) are located on the first side 713 of the device 730. Figure 4The bottom surface (or distal end) of the first package lead 734 is connected (e.g., using solder or conductive adhesive, or via a socket) to trace 782, and the top surface (or proximal end) of the first package lead 734 is electrically coupled (e.g., via bonding wire 455). Figure 4 ) to the RF input terminal corresponding to amplifier die 732 (e.g., RF input terminal 435, Figure 4 The conductive contacts of the lead 734 are then connected to the carrier RF signal received via lead 734. The signal is then transmitted through one or more power transistors (e.g., transistors 436, 437). Figure 4 The amplified carrier RF signal is amplified, and the amplified carrier RF signal is output at the RF output terminal (e.g., RF output terminal 438). Figure 4 It is produced at ) location. Figure 7 and Figure 8 In both embodiments, the RF output is electrically coupled (e.g., via junction line 461, Figure 4 One or more second package leads 764 (e.g., package lead 464) are connected to the top surface (or proximal end) of the fourth side 716 of the device 730. Figure 4 In a more specific embodiment, the RF output terminal has an elongated portion (e.g., elongated portion 445, Figure 4 ) and side pads (e.g., side pad 447, Figure 4 The elongated portion extends parallel to the third side 715 of the device 730, and the side pad is integrally formed with or electrically coupled to the elongated portion. The side pad has a length that extends parallel to the fourth side 716 of the device 730, and the length is sufficient to allow multiple bonding lines to be connected between the side pad and the package lead 764.

[0127] The bottom surface (or distal end) of the second package lead 764 is connected (e.g., with solder or conductive adhesive, or via a socket) to the proximal end of converter lines 774 (or 774'), 874. As will be described in more detail later, the bonding wire coupled to lead 764, lead 764 itself, and converter lines 774 (or 774'), 874 form the portion of converter line assemblies 772, 872 between carrier device 730 and peaking device 750, and more specifically, between the output of the carrier amplifier and combination node 780 (e.g., combination node 180). Figure 1 (part of)

[0128] Converter lines 774 (or 774') and 874 have a proximal end connected to a lead 764 of the carrier amplifier device 730 and a distal end connected to a lead 766 of the peaking amplifier device 750. According to an embodiment, converter lines 774 (or 774') and 874 (e.g., traces 176, 176')... Figure 1 , or trace 276, Figure 2The transmission line 774, in an embodiment, includes a conductor (on the ground plane) formed by a portion of a patterned metal layer on the surface 711 of the top substrate. In module 700, where the carrier amplifier device 730 and the peaking amplifier device 750 are orthogonally oriented to each other, one embodiment of the converter line 774 is "L-shaped," wherein a first branch extends orthogonally to the fourth side 716 of the carrier amplifier device 730, and a second branch (attached to the first branch) extends orthogonally to the second side 774 of the peaking amplifier device 750. In an alternative embodiment, the converter line 774' of module 700 may extend linearly from the fourth side 716 (and lead 764) of the carrier amplifier device 730 to the second side 774 (and lead 766) of the peaking amplifier device 750. In module 800, where carrier amplifier device 730 and peaking amplifier device 750 are oriented parallel to each other, converter line 874 may also extend linearly from the fourth side 716 (and lead 764) of carrier amplifier device 730 to the second side 774 (and lead 766) of peaking amplifier device 750. Whether in the orthogonal orientation embodiment of module 700 or the parallel orientation embodiment of module 800, the converter line may also have other shapes to achieve a desired electrical length between its proximal and distal ends, as will be discussed below.

[0129] Returning to the power divider 720, the peaking amplifier path includes conductive trace 785 and peaking amplifier device 752. The peaked RF signal generated at the power divider output 726 is transmitted via conductive trace 785 to the peaking amplifier device 752 to provide the peaking amplifier device 752 with an RF peaked signal for amplification. Input impedance matching circuitry (e.g., circuit 171) Figure 1 , Figure 7 , 8 (Not shown) can be coupled (e.g., along trace 785) between the power divider output 726 and the peaking amplifier device 752. The input impedance matching circuitry may include multiple discrete and / or integrated components (e.g., inductors and capacitors) configured to provide appropriate impedance matching between the second power divider output 726 and the input of the peaking amplifier device 752.

[0130] Like the carrier amplifier device 730, the peaking amplifier device 750 has a lower package (e.g., lower package 412, Figure 4 , 5 The lower package has a first side 773, a second side 774, a third side 775, and a fourth side 776 (e.g., sides 413 to 416). Figure 4The outer perimeter is defined by the peaking amplifier device 750. The peaking amplifier device 750 also has multiple leads 754, 761, 765, 766, an amplifier die 752, and electrical connections between the amplifier die 752 and the leads 754, 761, 765, 766.

[0131] According to an embodiment, one or more first package leads 754 (e.g., package lead 434) are located at a first side 773 of the device 750. Figure 4 The bottom surface (or distal end) of the first package lead 754 is connected (e.g., using solder or conductive adhesive, or via a socket) to trace 785, and the top surface (or proximal end) of the first package lead 754 is electrically coupled (e.g., via bonding wire 455). Figure 4 ) to the RF input terminal corresponding to amplifier die 752 (e.g., RF input terminal 435, Figure 4 The conductive contacts of the lead 754 are then used to receive the peaked RF signal via lead 754. The signal is then passed through one or more power transistors (e.g., transistors 436, 437). Figure 4 The amplified peaked RF signal is amplified at the RF output (e.g., RF output 438). Figure 4 It is generated at ) location.

[0132] As discussed earlier, the RF output of the peaking amplifier die 752 (e.g., RF output 438) Figure 4 This also corresponds to the combination node of the Doherty amplifier modules 700 and 800 (e.g., combination node 180). Figure 1 At this combination node, the amplified carrier and peaked RF signals are combined. To receive the amplified carrier signal, the bottom surface (or distal end) of the second package lead 766 is connected (e.g., with solder or conductive adhesive, or via a socket) to the distal end of converter lines 774 (or 774'), 874. The top surface (or proximal end) of the second package lead 766 is electrically coupled (e.g., via bonding wire 462), Figure 4 This leads to the RF output of the peaking amplifier die 752. In a more specific embodiment, the RF output has an elongated portion (e.g., elongated portion 445). Figure 4 ) and side pads (e.g., side pad 446, Figure 4The elongated portion extends parallel to the third side 775 of the device 750, and the side pad is integrally formed with or electrically coupled to the elongated portion. The side pad has a length extending parallel to the second side 774 of the device 750, and this length is sufficient to allow multiple bonding wires to be connected between the side pad and the package lead 766. As will be described in more detail later, the bonding wires coupled to the lead 766, together with the lead 766 itself, also form the portion of the converter line assemblies 772, 872 between the carrier device 750 and the peaking device 750, and more specifically, at the output of the peaking amplifier and the combination node 780 (e.g., combination node 180). Figure 1 The part between ).

[0133] In summary, the impedance converter line assemblies 772 and 872 include multiple components coupled in series. This includes the drain-source capacitances (e.g., capacitances 234 and 254) at the final stage transistors of the carrier die 732 and the peaking die 752. Figure 2 Each of the series-coupled components contributes to an approximately 90-degree phase shift of the RF signal transmitted between the drain of the carrier and the peaked final stage transistor (or between the drain of the carrier final stage transistor and the combination node 780). Assuming the basic operating frequency f0 of modules 700, 800 is in the range of approximately 800 MHz to approximately 5.2 GHz, the phase shift of the RF output signal between the near and far ends of each series-coupled component (due to their electrical length and impedance) is listed below. Of course, the basic operating frequency can also be lower or higher. According to an embodiment, the series-coupled components (and their associated phase shifts) of the impedance converter line assemblies 772, 872 include:

[0134] - The first interconnect (e.g., junction line 465) between the output terminal (e.g., drain terminal) of the carrier final stage transistor and lead 764. Figure 4 Between its proximal and distal ends, the first interconnection is characterized by a first electrical length (providing a first phase shift) in the range of about 3 degrees to about 24 degrees and an inductance value in the range of about 0.5 nH to about 1.0 nH (e.g., about 0.75 nH), although this first electrical length / phase shift / inductance value may also be smaller or larger;

[0135] - One or more first "vertical" leads 764. Between the proximal and distal ends of the leads 764 (e.g., between the proximal ends 526, 526′, 526″′ and the distal ends 527, 527′, 527″′), the leads 764 are characterized by a second electrical length (providing a second phase shift) in the range of about 2 degrees to about 16 degrees, and an inductance value in the range of about 0.25 nH to about 0.75 nH (e.g., about 0.5 nH), although this second electrical length / phase shift / inductance value may also be smaller or larger;

[0136] Impedance converter lines 774 (or 774') and 874 have a near end connected to vertical lead 764 and a far end connected to vertical lead 766. Between their near and far ends, impedance converter lines 774 (or 774') and 874 are characterized by a third electrical length (providing a third phase shift) in the range of approximately 10 degrees to approximately 80 degrees (i.e., whatever electrical length results in a total electrical length of 90 degrees between the carrier and peaked drain ends, taking into account the drain-source capacitance of the carrier amplifier and the peaked amplifier), although this third electrical length / phase shift can also be smaller or larger;

[0137] - One or more second "vertical" leads 766. Between the proximal and distal ends of the leads 766 (e.g., between the proximal ends 526, 526′, 526″′ and the distal ends 527, 527′, 527″′), the leads 766 are characterized by a fourth electrical length (providing a fourth phase shift) in the range of approximately 2 degrees to approximately 16 degrees, and an inductance value in the range of approximately 0.25 nH to approximately 0.75 nH (e.g., approximately 0.5 nH), although this fourth electrical length / phase shift / inductance value may also be smaller or larger; and

[0138] - A second interconnect (e.g., junction line 462) between lead 766 and the output terminal (e.g., drain terminal) (or combination node 780) of the peaked final stage transistor. Figure 4 Between its proximal and distal ends, the second interconnect is characterized by a fifth electrical length (providing a fifth phase shift) in the range of about 3 degrees to about 24 degrees and an inductance value in the range of about 0.5 nH to about 1.0 nH (e.g., about 0.75 nH), although this fifth electrical length / phase shift / inductance value may also be smaller or larger;

[0139] Based on the description herein, those skilled in the art will understand that the ability to change the first electrical length / phase shift, the second electrical length / phase shift, the fourth electrical length / phase shift, and the fifth electrical length / phase shift is somewhat limited. However, the physical and electrical lengths of the impedance converter lines (i.e., the third electrical length / phase shift above) can be readily adjusted to ensure that the total electrical length / phase shift of the impedance converter line assemblies 772, 872 (including the drain-source capacitances at the final stage transistors of the carrier die 732 and the peaking die 752, e.g., capacitances 234, 254) is adjusted. Figure 2 The effect of ) is approximately 90 degrees.

[0140] According to an embodiment, the physical and electrical lengths of the impedance converter circuitry (i.e., the third electrical length / phase shift mentioned above) can also be affected by coupling the RF outputs (or drain terminals of the final stage transistors) of the carrier amplifier die 732 and the peaking amplifier die 752 to the bias circuit 790 and the shunt circuit 791. The bias circuit 790 and the shunt circuit 791 can have two functions: providing a DC bias voltage to the RF output and resonating at least some of the drain-source capacitances (e.g., capacitors 234, 254) of the final stage transistors of the carrier amplifier die 732 and the peaking amplifier die 752. Figure 2 More specifically, the RF output can be connected via bonding wires (e.g., respectively). Figure 4 The bonding wires 463 or 465 and leads 760, 765 are coupled to traces 783, 786. According to an embodiment, traces 783, 786 each correspond to an RF cold spot node, and therefore traces 783, 786 can be used to provide DC bias to the drain terminals of the final stage transistors of the carrier amplifier die 732 and the peaking amplifier die 752. To receive DC bias, traces 783, 786 are coupled to drain bias connections 717, 718. Drain bias connections 717, 718 can in turn be connected to an external bias source. Although not explicitly stated... Figure 7 and 8 As shown, however, additional traces and connectors may be included in each module 700, 800 to provide gate bias voltages to the driver and final stage transistors, as well as to the drain of the driver transistor (if included).

[0141] Bonding wires (e.g., bonding wires 463 or 465), Figure 4 ), leads 760, 765 (e.g., leads 460 or 464, Figure 4 The inductance of the junction wires 760, 765 and traces 783, 786 can form the inductor portion of the shunt circuits 790, 791. According to an embodiment, the junction wires 760, 765 and traces 783, 786 are configured to provide inductance sufficient to resonate at least some of the drain-source capacitances of the final-stage transistors of the carrier amplifier die 732 and the peaking amplifier die 752. This allows the electrical and physical lengths of the impedance converter lines 774 (or 774'), 874 to be increased compared to the electrical and physical lengths selectable if the shunt circuits 790, 791 are excluded from modules 700, 800. For example, the series combination of the junction wires 760, 765 and traces 783, 786 can be configured to have an inductance value in the range of approximately 0.25H to approximately 0.75H, although this series inductance can also be smaller or larger.

[0142] Shunt circuits 790 and 791 each further include capacitors 793 and 795 (e.g., chip capacitors), with a first end coupled to traces 783 and 786 and a second end coupled to additional traces 784 and 787, which in turn can be connected to a ground reference voltage. The capacitance value of each shunt capacitor 793 and 795 is selected to provide a virtual ground reference voltage to the conductive traces 783 and 786, such that the junction wires, leads 760 and 765, and traces 783 and 786 act as shunt inductors for the RF ground voltage. Ideally, the shunt capacitors 793 and 795 are in series resonant within the band. For example, the capacitance value of each shunt capacitor 793 and 795 can range from approximately 5.6 picofarads (pF) to approximately 33.0 pF, or more specifically, from approximately 8.0 pF to approximately 12.0 pF, although this capacitance value can also be smaller or larger.

[0143] exist Figure 7 and Figure 8 In both embodiments, the RF output (or combination node 780) of the peaking amplifier die 752 is electrically coupled (e.g., via junction line 463). Figure 4 One or more third package leads 761 (e.g., package lead 460) are located at the third side 775 of the device 750. Figure 4 The top surface (or proximal end) of the RF output terminal. In a more specific embodiment, the RF output terminal has an elongated portion (e.g., elongated portion 445, Figure 4 ), which extends parallel to the third side 775 of the device 750, and the bonding wire (e.g., bonding wire 463) between the RF output terminal and the lead 761. Figure 4 It is coupled between the slender portion at the RF output and lead 761.

[0144] Lead 761 is electrically coupled (via solder or conductive adhesive, or via a socket) to conductive output traces 788, 789 on the top surface 711 of the module substrate 710, and trace 789 is in turn coupled to RF output connector 714. In an embodiment, an output impedance matching network (not shown) and / or decoupling capacitor 792 may be coupled along output traces 788, 789. The output impedance matching network is used to provide appropriate load impedance to the combination node 780. Although in Figure 7 , 8 Although not shown, the output impedance matching network may include a variety of discrete and / or integrated components (e.g., capacitors, inductors, and / or resistors) to provide the desired impedance matching.

[0145] The foregoing detailed description is illustrative in nature and is not intended to limit the embodiments of this subject matter or the application and use of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any embodiment described herein as exemplary is not necessarily to be construed as superior to or better than other embodiments. Furthermore, it is intended to be bound by any express or implied theory presented in the preceding art, background, and detailed embodiments.

[0146] The connecting lines shown in the various figures included herein are intended to illustrate exemplary functional relationships and / or physical couplings between various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in embodiments of this subject matter. Furthermore, certain terms may be used herein for reference only and are therefore not intended to be limiting, and the terms “first,” “second,” and other such numerical terms referring to structures do not imply order or sequence unless the context clearly indicates otherwise.

[0147] As used herein, a “node” refers to any internal or external reference point, connection point, junction, signal line, conductive element, etc., in which a given signal, logic level, voltage, data pattern, current, or quantity exists. Furthermore, two or more nodes can be implemented by a single physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished, although received or output at a common node).

[0148] The above description refers to elements, nodes, or features that are “connected” or “coupled” together. As used herein, unless otherwise expressly stated, “connected” means that one element is directly engaged to (or directly connected to) another element, and not necessarily mechanically. As used herein, unless otherwise expressly stated, “coupled” means that one element is directly or indirectly engaged to (or directly or indirectly electrically connected to, or otherwise connected to) another element, and not necessarily mechanically. Therefore, although the schematic diagrams shown in the figures depict an exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in embodiments of the depicted subject matter.

[0149] While at least one exemplary embodiment has been given in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments or examples described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide convenient guidance to those skilled in the art for implementing the one or more embodiments described above. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, including equivalents known or foreseeable at the time of filing this patent application.

Claims

1. A Doherty amplifier characterized by, comprising: a module substrate having a top substrate surface; a first surface mount device coupled to the top substrate surface, wherein the first surface mount device includes a first amplifier die; a second surface mount device coupled to the top substrate surface, wherein the second surface mount device includes a second amplifier die; and an impedance translator line assembly electrically connected between outputs of the first amplifier die and the second amplifier die, wherein the impedance translator line assembly includes: an impedance translator line coupled to the module substrate, wherein the impedance translator line has a proximal end and a distal end, a first lead of the first surface mount device having a proximal end electrically coupled to an output of the first amplifier die and a distal end coupled to the proximal end of the impedance translator line, and a second lead of the second surface mount device having a proximal end electrically coupled to an output of the second amplifier die and a distal end coupled to the distal end of the impedance translator line, wherein a first electrical length between the proximal end and the distal end of the first lead is in a range of 2 degrees to 16 degrees, a second electrical length between the proximal end and the distal end of the impedance translator line is in a range of 10 degrees to 80 degrees, a third electrical length between the proximal end and the distal end of the second lead is in a range of 2 degrees to 16 degrees, and a total electrical length between the outputs of the first amplifier die and the second amplifier die includes the first electrical length, the second electrical length, and the third electrical length, and the total electrical length is 90 degrees at a fundamental operating frequency of the Doherty amplifier. the first lead and the second lead are selected from a group consisting of a quad flat no-lead (QFN) package lead, a gull wing lead, a land grid array (LGA) package lead, and a ball grid array (BGA) package lead.

2. The Doherty amplifier of claim 1, wherein the proximal ends of the first lead and the second lead are electrically coupled to the outputs of the first amplifier die and the second amplifier die by wirebonds.

3. The Doherty amplifier of claim 1, wherein, 4. The Doherty amplifier of claim 1, wherein: the first lead is a first vertical conductor that conducts a first electrical signal between the proximal end and the distal end of the first lead in a direction that is angularly offset from a primary signal conduction direction through the first amplifier die; and the second lead is a second vertical conductor that conducts a second electrical signal between the proximal end and the distal end of the second lead in a direction that is angularly offset from a primary signal conduction direction through the second amplifier die. comprising:

5. A Doherty amplifier characterized by, a module substrate having a top substrate surface; an impedance translator line coupled to the module substrate, wherein the impedance translator line has a proximal end and a distal end, and the impedance translator line is characterized by a first electrical length between the proximal end and the distal end of the impedance translator line; ​ a first surface mount device coupled to the top substrate surface, wherein the first surface mount device includes a first package, a first vertical lead, and a first amplifier die coupled to the first package, wherein the first vertical lead has a proximal end inside the first package and a distal end outside the first package, wherein the proximal end of the first vertical lead is above a bottom surface of the first surface mount device, wherein the first vertical lead is characterized by a second electrical length between the proximal end and the distal end of the first vertical lead, wherein the proximal end of the first vertical lead is electrically coupled to an output of a first power transistor integrally formed with the first amplifier die, and wherein the distal end of the first vertical lead is coupled to the proximal end of the impedance converter line; and a second surface mount device coupled to the top substrate surface, wherein the second surface mount device includes a second package, a second vertical lead, and a second amplifier die coupled to the second package, wherein the second vertical lead has a proximal end inside the second package and a distal end outside the second package, wherein the proximal end of the second vertical lead is above a bottom surface of the second surface mount device, wherein the second vertical lead is characterized by a third electrical length between the proximal end and the distal end of the second vertical lead, wherein the proximal end of the second vertical lead is electrically coupled to an output of a second power transistor integrally formed with the second amplifier die, and wherein the distal end of the second vertical lead is coupled to the distal end of the impedance converter line, wherein the first electrical length is in a range of 10 degrees to 80 degrees, the second electrical length is in a range of 2 degrees to 16 degrees, the third electrical length is in a range of 2 degrees to 16 degrees, and a total electrical length between the outputs of the first and second power transistors includes the first, second, and third electrical lengths, and the total electrical length is 90 degrees at a fundamental operating frequency of the Doherty amplifier. each of the first and second surface mount devices is a square flat no-lead (QFN) package device, and the distal ends of the first and second vertical leads are coplanar with the bottom surfaces of the first and second surface mount devices.

6. The Doherty amplifier of claim 5, wherein, the first and second vertical leads are gull wing leads.

7. The Doherty amplifier of claim 5, wherein, each of the first and second packages includes a land grid array (LGA) including an array of lands at the bottom surfaces of the first and second surface mount devices.

8. The Doherty amplifier of claim 5, wherein, each of the first and second packages includes a ball grid array (BGA) including an array of balls at the bottom surfaces of the first and second surface mount devices.

9. The Doherty amplifier of claim 5, wherein, ​

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