Chirp sequence synthesis in dynamic distribution networks

Abstract

The present disclosure relates to chirp sequence synthesis in a dynamic distribution network. An array of one or more integrated circuits is disclosed that includes at least one local input port to receive a chirp signal from a local generator, one or more primary input ports to each receive a respective chirp signal from a remote source, a primary switch arrangement operable to switch between the chirp signal from the at least one local input port and the chirp signals from the one or more primary input ports to produce a composite signal having a chirp sequence with at least one chirp that starts during a stable period of a preceding chirp, and one or more primary output ports to provide a local oscillator signal to a transmitter and a receiver based on the composite signal. The roles of the master and follower circuits can change during operation of the array.

Description

TECHNICAL FIELD

[0001] The present application relates generally to frequency modulated continuous wave (FMCW) radar systems, and more particularly to systems employing multiple chirp generators in generating a chirp sequence. BACKGROUND

[0002] In the quest for safer and more convenient transportation options, many automobile manufacturers are developing self-driving cars, which require an impressive number and variety of sensors, often including arrays of acoustic and / or electromagnetic sensors, to monitor the distance between the car and any nearby people, pets, vehicles, or obstacles. Attempts to synchronize chirp signals across arrays have not been entirely satisfactory. Accordingly, there is room for improvement in the art. SUMMARY

[0003] According to one aspect of the disclosure, an integrated circuit is provided, characterized in that it comprises: at least one local input port for receiving a chirp signal from a local generator; one or more primary input ports for each receiving a respective chirp signal from a remote source; a primary switch arrangement operable to switch between the chirp signal from the at least one local input port and the chirp signal from the one or more primary input ports to produce a composite signal having a chirp sequence with at least one chirp starting during a stable period of a preceding chirp; and one or more primary output ports for providing a local oscillator signal to a transmitter and a receiver based on the composite signal.

[0004] In one embodiment, the integrated circuit is characterized in that it further comprises: a plurality of repeater ports to produce a plurality of copies of the amplified chirp signal.

[0005] In one embodiment, the integrated circuit is characterized in that it further comprises: one or more secondary input ports for each receiving a respective chirp signal from a remote source; and a secondary switch arrangement operable to switch between the chirp signal from the at least one local input port and the chirp signal from the one or more secondary input ports to provide the amplified chirp signal to the plurality of repeater ports, the amplified chirp signal having a chirp sequence with at least one chirp starting during a stable period of a preceding chirp.

[0006] In one embodiment, the integrated circuit is characterized in that it further comprises at least one frequency multiplier to multiply up a frequency of the composite signal to produce the local oscillator signal.

[0007] According to another aspect of the disclosure, there is provided an integrated circuit, characterized in that it comprises: at least one primary input port for receiving an amplified chirp signal; one or more primary output ports for providing a local oscillator signal to a transmitter and a receiver based at least in part on the amplified chirp signal; a plurality of secondary input ports for each receiving a respective chirp signal from a remote source; a plurality of repeater ports for producing a plurality of copies of the amplified chirp signal; and a secondary switch arrangement operable to switch between the chirp signals from the plurality of secondary input ports to provide the plurality of repeater ports with an amplified signal having a chirp sequence with at least one chirp that starts during a stable period of a previous chirp.

[0008] In one embodiment, the integrated circuit is further characterized in that it comprises: at least one local input port for receiving a local chirp signal from a local generator, wherein the second switch arrangement is further operable to include a chirp from the local chirp signal in the chirp sequence.

[0009] In one embodiment, the integrated circuit is further characterized in that it comprises a frequency multiplier that multiplies a frequency of the amplified signal to produce the local oscillator signal.

[0010] In one embodiment, the integrated circuit is characterized in that the previous chirp corresponds to the amplified chirp signal.

[0011] In one embodiment, the integrated circuit is characterized in that the previous chirp corresponds to the respective chirp signal from the remote source.

[0012] According to another aspect of the disclosure, there is provided a radar system interface, characterized in that it comprises a first plurality of integrated circuits, each integrated circuit of the first plurality of integrated circuits having: a local generator that provides a chirp signal; at least one input port that receives a chirp signal from a remote source; one or more repeater ports operable to provide a plurality of copies of an amplified chirp signal; a primary output port that provides a local oscillator signal to a transmitter or a receiver; at least one switch arrangement operable to combine a plurality of chirp signals to produce a composite signal having a chirp sequence with at least one chirp that starts during a stable period of a previous chirp; and a wiring configuration that enables the first plurality of integrated circuits to collectively produce at least one composite signal, to convert the at least one composite signal into a plurality of copies of an amplified chirp signal, and to each provide a copy of the amplified chirp signal as a local oscillator signal to a transmitter or a receiver. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a top view of an example vehicle equipped with sensors.

[0014] Figure 2 is a block diagram of a driver assistance system according to an example of the present disclosure.

[0015] Figure 3 is a schematic of a reconfigurable multiple-input multiple-output radar system according to an example of the present disclosure.

[0016] Figure 4 is a radar transceiver circuit according to an example of the present disclosure shown in block diagram form.

[0017] Figure 5 is a radar interface according to an example of the present disclosure.

[0018] Figure 6A is an ideal chirp signal sequence according to an example of the present disclosure.

[0019] Figure 6B is an actual chirp signal sequence according to an example of the present disclosure.

[0020] Figure 6C is a chirp signal superimposed on another chirp signal according to an example of the present disclosure.

[0021] Figure 7 is another radar interface according to an example of the present disclosure.

[0022] Figure 8 is another radar interface according to an example of the present disclosure.

[0023] Figure 9 is another radar interface according to an example of the present disclosure.

[0024] Figures 10A-10B is the operation of a first radar array shown.

[0025] Figures 11A-11B is the operation of a second radar array shown.

[0026] Figures 12A-12D is the operation of a third radar array shown. DETAILED DESCRIPTION

[0027] The accompanying drawings and following detailed description are not intended to limit the present disclosure to the specific configurations, parameters, and operation examples provided therein, but are intended to provide a basis for understanding all modifications, equivalents, and alternatives falling within the scope of the appended claims. The specific configurations, parameter values, and operation examples are provided for explanatory purposes, and are not intended to limit the scope of the present disclosure in any way.

[0028] Figure 1 An exemplary vehicle 102 is shown equipped with a radar antenna array including antennas 104 for short range sensing (e.g., for parking assist), antennas 106 for mid-range sensing (e.g., for monitoring for parking and driving and passing events), antennas 108 for long range sensing (e.g., for adaptive cruise control and collision warning), each of which can be placed behind the front bumper cover. Antennas 110 for short range sensing (e.g., for back-up assist) and antennas 112 for mid-range sensing (e.g., for rear collision warning) can be placed behind the rear bumper cover. Antennas 114 for short range sensing (e.g., for blind spot monitoring and side obstacle detection) can be placed behind the car fenders. Each antenna and each group of antennas can be grouped into one or more arrays. Each array can be controlled by a radar array controller (205). Each group of antennas can perform multiple input multiple output (MIMO) radar sensing. The types, number, and configuration of sensors in a sensor arrangement vary for vehicles with driver assist and autonomous driving capabilities. The vehicle can employ the sensor arrangement to detect and measure the distance / direction to objects in various detection zones to enable the vehicle to navigate while avoiding other vehicles and obstacles.

[0029] Figure 2 An electronic control unit (ECU) 202 is shown as the center of a star topology coupled to various ultrasonic sensors 204 and a radar array controller 205. Other topologies including serial, parallel, and hierarchical (tree) topologies are also suitable and are contemplated for use in accordance with the principles disclosed herein. The radar array controller 205 is coupled to transmit and receive antennas in the radar antenna array 106 to transmit electromagnetic waves, receive reflections, and determine the spatial relationship of the vehicle to its surroundings. The radar array controller 205 is coupled to a carrier signal generator (404). In at least one example, the radar array controller 205 controls the timing and sequence of actuation of multiple carrier signal generators (404).

[0030] To provide automatic parking assist, the ECU 202 can be further connected to a set of actuators such as turn signal actuators 208, steering actuators 210, brake actuators 212, and throttle actuators 214. The ECU 202 can be further coupled to a user interactive interface 216 to accept user input and provide displays of various measurements and system status.

[0031] Using interfaces, sensors, and actuators, the ECUs 202 can provide automatic parking, assist parking, lane change assist, obstacle and blind spot detection, autonomous driving, and other desired functionality. In an automobile, various sensor measurements are collected by one or more ECUs 202 and can be used by the ECUs 202 to determine the state of the automobile. The ECUs 202 can further act on the state and incoming information to actuate various signaling and control transducers to regulate and maintain operation of the automobile. The operations provided by the ECUs 202 are various driver assist functions, including automatic parking, lane following, automatic braking, and autonomous driving.

[0032] To collect the necessary measurements, the ECUs 202 can employ a MIMO radar system. A radar system operates by transmitting electromagnetic waves that travel outward from a transmitting antenna before reflecting back to a receiving antenna. Reflectors can be any suitably reflective object in the path of the transmitted electromagnetic waves. By measuring the travel time of the electromagnetic waves from the transmitting antenna to the reflector and back to the receiving antenna, the radar system can determine the distance to the reflector and its velocity relative to the vehicle. If multiple transmitting or receiving antennas are used, or if multiple measurements are made at different locations, the radar system can determine the direction of the reflector and thus track the location of the reflector relative to the vehicle. With more complex processing, multiple reflectors can be tracked. At least some radar systems employ array processing to“scan” a directional electromagnetic beam and construct an image of the surroundings of the vehicle. Both pulsed and continuous wave implementations of radar systems can be implemented.

[0033] Figure 3 An exemplary system with a MIMO configuration is shown, in which J transmitters are collectively coupled to M transmitting antennas to transmit a transmitting signal. The M possible signals can reflect off one or more targets in various ways so as to be received via N receiving antennas coupled to P receivers. Each receiver can extract the amplitude and phase or travel delay associated with each of the M transmitting signals, thereby enabling the system to obtain N*M measurements (although only J*P of the measurements can be obtained at a time). The processing requirements associated with each receiver extracting J measurements can be reduced via the use of time division multiplexing and / or orthogonal encoding. The available antennas can be multiplexed to the available transmitters and receivers in a systematic manner to collect a complete set of measurements for radar imaging.

[0034] Figure 4 A radar transceiver circuit 402 according to an example of the present disclosure is shown in block diagram form. In at least one example, the radar transceiver circuit 402 is implemented as an integrated circuit in a packaged chip. The radar transceiver circuit 402 includes a carrier signal generator 404, a splitter 420, a receiver 408, a transmitter 406, and a local oscillation (LO) circuit 410.

[0035] In examples of the present disclosure, the carrier signal generator 404 is coupled to the radar array controller 205. The carrier signal generator 404 includes a chirp generator to produce a frequency modulated continuous wave (FMCW) signal. The chip rate of the carrier signal generator 404 can be controlled by the radar array controller 205. In at least one example, the carrier signal generator 404 can be disabled by the radar array controller 205 to provide an unmodulated carrier signal. The carrier signal generator 404 can be implemented as a local oscillator (LO) signal generator, as a fractional-N phase-locked loop (PLL) with a sigma-delta modulator, or as a direct digital synthesizer (DDS) generator.

[0036] The carrier signal generator 404 is connected to the transmitter (Tx) 406 and the receiver (Rx) 408 through an LO distribution circuit 410 and a splitter 420. The carrier signal generator 404 generates a signal (e.g., a chirp signal). The LO distribution circuit 410 receives the signal from the carrier signal generator 404 at an amplifier (AMP) 412. (Additionally, the LO distribution circuit 410 has two input ports (primary input port 442 and secondary input port 424), through which the LO distribution circuit 410 can receive a signal from an external source of the radar transceiver circuit 402. The external source can include other radar transceiver circuits 402. The AMP 412 amplifies the signal from the carrier signal generator 404. The LO distribution circuit 410 includes a primary switch arrangement and a secondary switch arrangement, the primary switch arrangement including a switch SI and a switch S2, the secondary switch arrangement including a switch S3. The AMP 412 is connected to the switch SI. The switch SI alternately couples the signal to the switch S2 and the switch S3. The switch S2 selects either a line 417 carrying the oscillating signal from SI or an input signal received at the primary input port 442. In examples of the present disclosure, the switches SI-S3 can be implemented as single-pole double-throw (SPDT) integrated transistor switches.

[0037] The switch S2 passes the signal received by the switch S2 to an AMP 418. The signal is amplified by the AMP 418 and passed to the splitter 420. The splitter 420 passes one copy of the signal from the AMP 418 to the transmitter 406 and one copy to the receiver 408.

[0038] Switch S3 selects either the signal from SI at line 415 or the input signal received at secondary input port 424. The signal selected by switch S3 is passed to AMP 428. The passed signal is amplified by AMP 428. A copy of the amplified signal is passed to AMP 434 and AMP 436 by splitter 430. AMP 434 amplifies the copy of the signal and passes the amplified copy of the signal to repeater output 438. AMP 436 amplifies the copy of the signal and passes it to repeater output port 440. Thus, repeater output port 438 and repeater output port 440 will propagate either the electromagnetic waves originating from generator 404 or received at secondary input port 424, depending on the selection position of S3. Likewise, transmitter 406 will propagate either the electromagnetic waves originating from generator 404 or received at primary input port 442, depending on the selection position of S2. In at least one example, radar transceiver circuit 402 includes one or more frequency multipliers and one or more mixers (not shown). For example, a frequency multiplier positioned between amplifier 412 and switch SI can increase the chirp signal carrier frequency. As another example, a frequency multiplier can be positioned between amplifier 418 and splitter 420.

[0039] Figure 5 A radar transceiver circuit 600 according to an example of the present disclosure is shown. In at least one example, radar transceiver circuit 600 includes some or all of the same or similar components as transceiver circuit 402. Some of these components are not shown in FIG. 6 in order to facilitate understanding of some of the working principles that follow. Radar transceiver circuit 600 includes a signal generator 404 (e.g., PLL1) connected to a frequency multiplier circuit 502. Depending on the switch positions of switch SI and switch S2, either the chirp signal generated by PLL1 or a chirp signal received at primary input port 602 will be fed to frequency multiplier circuit 502. Frequency multiplier circuit 502 increases the frequency of the received signal by a factor of four. A copy of the chirp signal is passed to transmitter 406 and receiver 408. As will be explained in more detail, a chirp signal received at primary input port 602 can originate from PLL1 and be returned to primary input port 602 through a return path that includes one or more transceiver circuits 600. For reasons of convenient understanding, transceiver circuit 600 will also be referred to as interface-A within this disclosure. Figure 5

[0040] Radar transceiver circuit 600 can be used as an FMCW radar device, (as can transceiver circuit 402). FMCW radars transmit a chirp sequence in order to detect the range and relative velocity of targets. A chirp is a frequency-modulated radio frequency (RF) signal whose frequency increases or decreases linearly over a period of time. A single chirp signal is characterized by its carrier frequency f0, chirp bandwidth BW = f1-f0, and chirp duration T c .​c A chirp sequence is defined by the number of chirps N and the chirp period T p = T c + T d where T d is the delay period between the end of a chirp and the start of the next chirp. The relationship between these parameters under ideal conditions is shown in Figure 6A A chirp profile includes parameters that define a chirp sequence. A chirp profile for a chirp sequence includes information about the chirp duration, the chirp bandwidth, the delay between individual chirps, and the delay at the start and end of the chirp sequence. The chirp profile is pre-loaded into the radar module memory by an external controller.

[0041] During operation, signals reflected from different objects (targets) are received by the radar and mixed with the transmitted signal to generate an intermediate frequency (IF) signal, the frequency of which depends on the target range and relative velocity. IF refers to the frequency to which the carrier is shifted as an intermediate step during transmission or reception. The IF signal is sampled by an analog-to-digital converter (ADC) (not shown) at a sampling frequency f s and processed by a digital signal processor (DSP) (e.g., ECU 202). The maximum detectable range R max , the maximum velocity v d，max and the range and velocity resolutions AR and Av are given by the following equations:

[0042]

[0043]

[0044]

[0045]

[0046] To maximize the maximum velocity (equation 3), the radar (e.g., 402) must transmit a chirp sequence with a high chirp repetition frequency (short chirp duration) T c ). In at least one example of the present disclosure, the chirp bandwidth BW is high in order to produce an appropriate maximum range resolution (equation 2) when transmitting short duration chirps (with low T c ) (see Figure 6A ).

[0047] In at least one example of this disclosure, the FMCW chirp is generated by the PLL (e.g., 404) because the PLL is capable of synthesizing a linear chirp with a high signal-to-noise ratio (SNR). At least one example is a vehicle radar application where the PLL generates the chirp at a small integer fraction (e.g., 1 / 4) of the transmitted chirp frequency to optimize phase noise. The frequency of the PLL output is then multiplied (e.g., by a factor of 4, see 502) before the output is transmitted by the radar transmitter (e.g., 408).

[0048] Figure 6B The chirped sequence generated by PLL 404 is shown. The chirped period T... p From the effective period T v (The chirp is emitted during this period) and the steady-state period constitute T. s . Figure 6B The stable period T in s Must be smaller than Figure 6A Delay period T d If the minimum delay between chirps is required, then T s Mapping to T p When one chirp ends and another begins, the PLL divider modulus suddenly changes, and the PLL output frequency experiences a transient overshoot until the PLL output frequency stabilizes within a time T. s After stabilization, the chirp cannot be used for radar detection during this stabilization period. The entire chirp period T can be... p Divided into steady time T s And the effective time T for radar operation v When the radar emits rapid, dense chirps (e.g., to sense fast-moving objects), the settling time T... s Occupy the chirping period T p A large percentage. (The phrase "fast chirped sequence" can be used to refer to a sequence derived from one or more chirped generators having an effective slope time T.) v Equivalent to and / or greater than the chirping period T p 20% settling time T s .).For example, Figure 6B The chirping sequence in the transceiver circuit 600 can be generated by PLL1.

[0049] If the desired chirping period T p，synth If the (synthetic chirp period) is comparable to or shorter than the settling time of a single chirp, then two or more PLLs (e.g., 404) are used to synthesize a linear chirp sequence (e.g., T). s，synth →0, where T s，synth The settling time T of the synthesized chirped sequence s It may be advantageous for T. s. According to examples of the present disclosure, a fast chirp sequence is constructed with T p，synth = T v and T s，synth = 0. The minimum number (N) of PLLs required to construct a fast chirp sequence with T s / T v (Eq: 5)

[0050] N≥ 1 + T s / T v (Eq: 5)

[0051] Examples of the present disclosure include apparatuses and methods of synthesizing fast chirp sequences that minimize the impact on the settling time of a chirp generator (e.g., 404). In at least one example, a fast chirp sequence with negligible (or even zero) settling time can be synthesized by superimposing the chopped time-shifted chirp portions from multiple PLLs (e.g., 404). This concept is illustrated in Figure 6C .

[0052] Figure 6C The chirp signal of PLL1 of transceiver circuit 600 and the chirp signal of a different PLL (e.g., PLL2) of a different transceiver circuit (e.g., a second copy of the transceiver circuit) are shown on the same graph. When the reset times of PLL1 and PLL2 are excluded, and the chirp signal of PLL2 is superimposed on the chirp signal of PLL1 (e.g., by switching between the PLL signals), a digital sawtooth wave is produced. The principles discussed so far will become clearer when explained with reference to an array containing multiple transceiver circuits. Exemplary transceiver circuits include interface-B (400), interface-C (500), and interface-D (600). Figure 7 . Figure 8 . Figure 9 .

[0053] Figure 7 A transceiver circuit 800 (interface-B) according to examples of the present disclosure is shown. Transceiver circuit 800 includes a primary switch arrangement including switch S1 and switches S2 and S4, and a secondary switch arrangement including switch S3. Interface-B is identical to interface-A, except that interface-B includes switch S4 and an additional primary input port 802. Switch S4 selects the signal received at secondary input port 602 or the signal received at primary input port 802 and passes the selected signal to switch S2. Switch S2 of interface-B operates in the same manner as switch S2 of interface-A (and switch S2 of LO distribution circuit 410). Switches S2 and S4 enable clean switching between multiple chirp signals without limiting one of these signals to be on-chip.

[0054] Figure 8A transceiver circuit 900 (interface-C) is shown in accordance with examples of the present disclosure. The transceiver circuit 900 includes a primary switch arrangement including switch SI and switch S2, and a secondary switch arrangement including switch S3 and switch S5. Interface-C is the same as interface-A, except that interface-C includes switch S5 and an additional secondary input port 902. Switch S5 selects either the signal received at secondary input port 604 or the signal received at secondary input port 902, and passes the selected signal to switch S3. Switch S3 of interface-B operates in the same manner as switch S3 of interface-A (and interface-B and transceiver circuit 402).

[0055] Figure 9 A transceiver circuit 1000 (interface-D) is shown in accordance with examples of the present disclosure. The transceiver circuit 1000 includes a primary switch arrangement including switch SI, and switch S2 and switch S4, and a secondary switch arrangement including switch S3 and switch S5. Interface-D includes all of the same components as interface-A. Additionally, (as with interface-B), interface-D includes switch S4 and an additional primary input port 802. Switch S4 selects either the signal received at secondary input port 602 or the signal received at primary input port 802, and passes the selected signal to switch S2. Switch S2 of interface-D operates in the same manner as switch S2 of interface-A. Additionally, (as with interface-C), interface-D includes switch S5 and an additional secondary input port 902. Switch S5 selects either the signal received at secondary input port 604 or the signal received at secondary input port 902, and passes the selected signal to switch S3. Switch S3 of interface-D operates in the same manner as switch S3 of interface-A, interface-B, and interface-C. Interface-D also includes two additional switches S6 and S7, and two additional ports: repeater output port 1002 and repeater output port 1004. With respect to Figure 4 As described above, amplifier 434 receives a signal. In interface-D, switch S6 couples amplifier 434 to either repeater output port 606 or repeater output port 1002. Likewise, with respect to Figure 4 As described above, amplifier 436 receives a copy of the signal received by amplifier 434. In interface-D, switch S7 couples amplifier 436 to either repeater output port 608 or repeater output port 1004.

[0056] Figure 10A A dual-PLL radar system 1100 at a first time is shown in accordance with examples of the present disclosure. The radar system 1100 includes a first copy of interface-B (“B1”) connected to a second copy of interface-B (“B2”). Figure 10BA dual-PLL radar system 1100 is shown at a second time. The system 1100 includes a first PLL (404) (such as a first copy of PLL1 from the transceiver circuit 402, 600), and a second PLL (such as a second copy of PLL2 from the transceiver circuit 402, 600). In FIG. 10A, the radar system 1100 transmits a first active chirp portion T v Thereafter, in Figure 10B , the radar system 1100 transmits T v generated by PLL2 during the settling time of PLL1 s The second active segment. Then, during the settling time of PLL2, the chirp from PLL1 (e.g., 404) is transmitted Figure 10A , etc. Figure 6C An overlay of two chirp signals such as generated by the system 1100 is shown, where the settling time of PLL1 overlaps the active chirp segment T v of PLL2, and vice versa. At a first time Figure 10A , a signal from amplifier 434 of interface-B1 reaches switch S4 of interface-B1. Also, at the first time, a signal from amplifier 436 of interface-B1 reaches switch S4 of interface-B2. At a second time, a signal from amplifier 434 of interface-B2 is passed to switch S4 of interface-B2, and a signal from amplifier 436 of interface-B2 is passed to switch S4 of interface-B1. Thus, in Figure 10A , interface-B1 is the initiator or “master,” while in Figure 10B , interface-B1 is the master. During the time in which one copy is the master, the other copy is the follower. In at least one example of the present disclosure, the rate at which the roles of master and follower are switched is controlled by the array controller 205. It should be appreciated that for the configuration shown in Figures 10A-10B , either interface can be designated to always be the master, while the other interface is always the follower. It should be appreciated that for the configuration shown in Figures 10A-10B , either interface can be cascaded with one or more additional interfaces (e.g., 402, 600, 800, 900, 1000).

[0057] In one or more examples of the disclosure, in order to operate several radar modules as a single array (e.g., 1100), the chirp generators (PLLs) and receiver ADC clocks of all modules must be synchronized. To this end, each module has a chirp sequence start signal output attenuator and an ADC clock output attenuator (not shown). The array of modules (e.g., 1200) can be configured such that one module provides these two signals to all other modules (e.g., in a tree topology). In at least one example, while each module can be dynamically configured to be the master in the sense that the module provides the chirp sequence to all other modules, only one module is predefined to provide the chirp sequence start signal and the ADC clock.

[0058] In examples of the disclosure, the chirp start signal is distributed to all modules simultaneously, and the delay between chirps of different modules (which is applied to achieve a fast chirp sequence by superimposing several chirp sequences from several modules, see Figure 6C ) is defined in a chirp configuration file and preloaded to each module.

[0059] Figure 11A The array 1200 is shown to include two copies of interface-A and two copies of interface-C at a first time. At the first time, copy 1 of interface-A drives the array. The oscillating signal (e.g., chirp) from copy 1 of interface-A is passed to switch S5 of interface-C (copy 1) and switch S5 of interface-C (copy 2). As shown, the oscillating signal from copy 1 of interface-A is passed by interface-C (copy 1) to interface-A (copy 1) through return path 1202. The oscillating signal from copy 1 of interface-A is passed by interface-C (copy 2) to interface-A (copy 2) through return path 1204.

[0060] Figure 11BThe array 1200 at a second time is shown. At the second time, copy 2 of interface-A drives the array. The oscillating signal from copy 2 of interface-A is passed to switch S5 of interface-C (copy 1) and switch S5 of interface-C (copy 2). As shown, the oscillating signal from copy 1 of interface-A is passed by interface-C (copy 1) to interface-A (copy 1) through return path 1202. The oscillating signal from copy 2 of interface-A is passed by interface-C (copy 2) to interface-A (copy 2) through return path 1204. Thus, during operation of the array 1200, the role of master alternates between copy 1 of interface-A and copy 2 of interface-A. During the period when copy 1 of interface-A is master, copy 2 of interface-A and both copies of interface-C are slaves. During the period when copy 2 of interface-A is master, copy 1 of interface-A and both copies of interface-C are slaves. In at least one example of the disclosure, the rate at which the roles of master and slave are switched is controlled by the array controller 205. It will be appreciated that for Figures 11A-11B For the configuration shown, either copy 1 or copy 2 of interface-A can be designated to always be master, and the other to always be slave. It will be appreciated that for Figures 11A-11B For the configuration shown, either interface can be cascaded with one or more additional interfaces (e.g., 402, 600, 800, 900, 1000).

[0061] Figure 12A The array 1300 at a first time including four copies of interface-D is shown. At the first time, copy 1 of interface-D drives the array. The oscillating signal from copy 1 of interface-D is passed to switch S5 of interface-D (copy 3) and switch S5 of interface-D (copy 4). As shown, the oscillating signal from copy 1 of interface-D is passed by interface-D (copy 3) to interface-D (copy 1) through return path 1302. The oscillating signal from copy 1 of interface-D is passed by interface-D (copy 4) to interface-D (copy 2) through return path 1304.

[0062] Figure 12B The array 1300 at a second time is shown. At the second time, copy 2 of interface-D drives the array 1300. The oscillating signal from copy 2 of interface-D is passed to switch S5 of interface-D (copy 3) and switch S5 of interface-D (copy 4). As shown, the oscillating signal from copy 2 of interface-D is passed by interface-D (copy 3) to interface-D (copy 1) through return path 1302. The oscillating signal from copy 2 of interface-D is passed by interface-D (copy 4) to interface-D (copy 2) through return path 1304.

[0063] Figure 12CThe array 1300 is shown at a third time. At the third time, copy 3 of interface D drives the array 1300. The oscillating signal from copy 3 of interface-D is passed through line 1306 to switch S5 of interface-D (copy 1) and through line 1308 to switch S5 of interface-D (copy 2). The oscillating signal from copy 3 of interface-D is passed by interface-D (copy 2) through line 1310 to interface-D (copy 4). The oscillating signal from copy 3 of interface-D is returned from interface-D (copy 1) to copy 3 of interface-D through return path 1312.

[0064] Figure 12D The array 1300 is shown at a fourth time. At the fourth time, copy 4 of interface D drives the array 1300. The oscillating signal from copy 4 of interface-D is passed through line 1309 to switch S5 of interface-D (copy 1) and through line 1316 to switch S5 of interface-D (copy 2). The oscillating signal from copy 4 of interface-D is passed by interface-D (copy 1) through line 1312 to interface-D (copy 3). The oscillating signal from copy 4 of interface-D is returned from interface-D (copy 2) to copy 4 of interface-D through return path 1310. It should be understood that for the configuration shown, any copy of interface-D can be designated to always be the master, while the others are always followers. It should be understood that for the configuration shown, each copy of interface-D of any interface can be cascaded with one or more additional interfaces (e.g., 402, 600, 800, 900, 1000). Figures 12A-12D The array 1300 is shown at a fourth time. At the fourth time, copy 4 of interface D drives the array 1300. The oscillating signal from copy 4 of interface-D is passed through line 1309 to switch S5 of interface-D (copy 1) and through line 1316 to switch S5 of interface-D (copy 2). The oscillating signal from copy 4 of interface-D is passed by interface-D (copy 1) through line 1312 to interface-D (copy 3). The oscillating signal from copy 4 of interface-D is returned from interface-D (copy 2) to copy 4 of interface-D through return path 1310. It should be understood that for the configuration shown, any copy of interface-D can be designated to always be the master, while the others are always followers. It should be understood that for the configuration shown, each copy of interface-D of any interface can be cascaded with one or more additional interfaces (e.g., 402, 600, 800, 900, 1000). Figures 12A-12D The array 1300 is shown at a fourth time. At the fourth time, copy 4 of interface D drives the array 1300. The oscillating signal from copy 4 of interface-D is passed through line 1309 to switch S5 of interface-D (copy 1) and through line 1316 to switch S5 of interface-D (copy 2). The oscillating signal from copy 4 of interface-D is passed by interface-D (copy 1) through line 1312 to interface-D (copy 3). The oscillating signal from copy 4 of interface-D is returned from interface-D (copy 2) to copy 4 of interface-D through return path 1310. It should be understood that for the configuration shown, any copy of interface-D can be designated to always be the master, while the others are always followers. It should be understood that for the configuration shown, each copy of interface-D of any interface can be cascaded with one or more additional interfaces (e.g., 402, 600, 800, 900, 1000).

[0065] Embodiments of the present disclosure further include:

[0066] Example 1. An electronic circuit comprising: an oscillation circuit (e.g., 410) comprising: a first amplifier (e.g., 412) configured to amplify a first signal; a first switch (e.g., SI) configured to receive the first signal from the first amplifier and alternately couple the first signal to a second switch (e.g., S2) and a third switch (e.g., S3), wherein the second switch is configured to alternately select a first signal from a first input port (e.g., 442) and a second signal, and pass the signal selected by the second switch to a second amplifier (e.g., 418), and wherein the second amplifier is configured to amplify the signal received from the second switch; the third switch (e.g., S3) configured to alternately select the first signal from the first switch and a third signal from a second input port (e.g., 424), and pass the signal selected by the third switch to a third amplifier (e.g., S3), wherein the third amplifier is configured to amplify the signal received from the third switch; and a splitter (e.g., 430) configured to receive the signal from the third amplifier, and pass a first copy of the signal received from the third amplifier to a fourth amplifier (e.g., 434), and pass a second copy (e.g., 436) of the signal received from the third amplifier to a fifth amplifier; wherein the fourth amplifier is configured to amplify the first copy of the signal from the splitter, and the fifth amplifier is configured to amplify the second copy of the signal from the splitter.

[0067] Example 2. The electronic circuit of Example 1, further comprising: a first transceiver circuit (e.g., 402) comprising: an oscillation signal generator (e.g., 404) configured to generate a first oscillation signal, the first oscillation signal corresponding to the first signal, the oscillation signal generator connected to the first amplifier (e.g., 412) of the oscillation circuit (e.g., 410) and configured to pass the first signal to the first amplifier; and a second splitter (e.g., 420) connected to the second amplifier of the oscillation circuit and configured to receive the amplified signal from the second amplifier (e.g., 418) of the oscillation circuit and pass a first copy of the signal from the second amplifier to a transmitter (e.g., 406), and further configured to pass a second copy of the signal from the second amplifier of the oscillation circuit to a receiver (e.g., 408).

[0068] Example 3. The electronic circuit of Example 2, further comprising: a second transceiver circuit (e.g., 800), wherein the second transceiver circuit (see, e.g., Interface-B, Copy 2, Figure 10A) is a duplicate of the first transceiver circuit (e.g., 402), the oscillator signal generator of the second transceiver circuit is configured to generate a second oscillator signal; a fourth switch (e.g., S4) configured to alternately select a signal from a fifth amplifier (e.g., 436) of the first transceiver circuit and a signal from a fourth amplifier (e.g., 434) of the second transceiver circuit, and to pass the signal selected by the fourth switch to the second switch of the first transceiver circuit; and a fifth switch configured to alternately select a signal from the fifth amplifier of the first transceiver circuit and a signal from the fourth amplifier of the second transceiver circuit, and to pass the signal selected by the fifth switch to the second switch of the second transceiver circuit, wherein the oscillator signal generator of the first transceiver circuit is configured to generate the first oscillator signal during a settling time of the oscillator signal generator of the second transceiver circuit, and the oscillator signal generator of the second transceiver circuit is configured to generate the second oscillator signal during a settling time of the oscillator signal generator of the first transceiver circuit.

[0069] Embodiment 4. The electronic circuit of embodiment 2, further comprising: a second transceiver circuit, wherein the second transceiver circuit is a duplicate of the first transceiver circuit, the oscillator signal generator of the second transceiver circuit is configured to generate a second oscillator signal; a third transceiver circuit, wherein the third transceiver circuit includes duplicates of components of the first transceiver circuit, and further includes an additional switch configured to alternately select an output signal from the fourth amplifier of the first transceiver circuit and an output signal from the fourth amplifier of the second transceiver circuit; and a fourth transceiver circuit, wherein the third transceiver circuit includes duplicates of components of the first transceiver circuit, and further includes an additional switch configured to alternately select an output signal from the fifth amplifier of the first transceiver circuit and an output signal from the fifth amplifier of the second transceiver circuit, wherein the oscillator signal generator of the first transceiver circuit is configured to generate the first oscillator signal during a settling time of the oscillator signal generator of the second transceiver circuit, and the oscillator signal generator of the second transceiver circuit is configured to generate the second oscillator signal during a settling time of the oscillator signal generator of the first transceiver circuit.

[0070] Example 5. The electronic circuit of Example 2, wherein the first transceiver circuit further comprises: a fourth switch configured to alternately select a signal from the first input port and a signal from the third input port, and to pass the signal selected by the fourth switch to the second switch; a fifth switch configured to alternately select a signal from the second input port and a signal from the fourth input port, and to pass the signal selected by the fifth switch to the third switch; a sixth switch configured to alternately couple the fourth amplifier to the first output port and the third output port; and a seventh switch configured to alternately couple the fifth amplifier to the second output port and the fourth output port.

[0071] Example 6. The electronic circuit of Example 5, further comprising: a second transceiver circuit, wherein the second transceiver is a same copy of the first transceiver circuit; a third transceiver circuit, wherein the third transceiver is a same copy of the first transceiver circuit; and a fourth transceiver circuit, wherein the fourth transceiver is a same copy of the first transceiver circuit, wherein the first input port of the first transceiver circuit is connected to the second output port of the third transceiver circuit, the second input port of the first transceiver circuit is connected to the third output port of the third transceiver circuit, the third input port of the first transceiver circuit is connected to the first output port of the first transceiver circuit, the fourth input port of the first transceiver circuit is connected to the second output port of the fourth transceiver circuit, the second output port of the first transceiver circuit is connected to the first input port of the third transceiver circuit, and the third output port of the first transceiver circuit is connected to the second input port of the third transceiver circuit, the first input port of the second transceiver circuit is connected to the second output port of the fourth transceiver circuit, the second input port of the second transceiver circuit is connected to the fourth output port of the third transceiver circuit, the third input port of the second transceiver circuit is connected to the first output port of the second transceiver circuit, the fourth input port of the second transceiver circuit is connected to the fourth output port of the fourth transceiver circuit, and the oscillator signal generator of the second transceiver circuit is configured to generate a second oscillator signal during a settling time of the oscillator signal generator of the first transceiver circuit.

[0072] Example 7. The electronic circuit of Example 6, wherein the oscillator signal generator of the third transceiver circuit is configured to generate a third oscillator signal during a settling time of the oscillator signal generator of the second transceiver circuit.

[0073] Example 8. The electronic circuit of Example 7, wherein the oscillator signal generator of the fourth transceiver circuit is configured to generate a fourth oscillator signal during a settling time of the oscillator signal generator of the third transceiver circuit.

[0074] Example 9. The electronic circuit of Example 8, wherein the oscillator signal generator of the first transceiver circuit is configured to generate the first oscillating signal during a settling time of the oscillator signal generator of the fourth transceiver circuit.

[0075] Example 10. The electronic circuit of Example 9, wherein the transmitter of each of the transceiver circuits is configured to transmit each of the oscillating signals generated by the oscillator signal generator of each of the other transceiver circuits.

[0076] Example 11. The electronic circuit of Example 10, wherein the oscillator signal generator of each of the transceivers is connected to the radar array control circuit.

[0077] Example 12. The electronic circuit of Example 10, wherein the oscillating signal is a chirp signal.

[0078] Example 13. The electronic circuit of Example 10, wherein the periodicity of each of the oscillating signals is the same as the periodicity of each of the other signals.

[0079] Example 14. A method of manufacturing a radar unit, comprising: providing a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, and a fifth amplifier; providing a first switch, a second switch, and a third switch, providing a first splitter; constructing an oscillator circuit, wherein constructing the oscillator circuit comprises: configuring the first amplifier to amplify a first signal; connecting the first amplifier to the first switch; configuring the first switch to receive the first signal from the first amplifier and to alternately couple the first signal to the second switch and to the third switch; configuring the second switch to alternately select the first signal from the first switch and a second signal from a first input port and to pass the signal selected by the second switch to the second amplifier; configuring the third switch to alternately select the first signal from the first switch and a third signal from a second input port and to pass the signal selected by the third switch to the third amplifier; connecting the first splitter to the third amplifier, the fourth amplifier, and the fifth amplifier; configuring the first splitter to receive a signal from the third amplifier and to pass a first copy of the signal received from the third amplifier to the fourth amplifier and to pass a second copy of the signal received from the third amplifier to the fifth amplifier.

[0080] Example 15. The method of manufacturing a radar unit of Example 14, further comprising: providing an oscillator signal generator, a second splitter, a transmitter, and a receiver; constructing the first transceiver circuit, wherein constructing the first transceiver circuit comprises: connecting the oscillator signal generator to the first amplifier; configuring the oscillator signal generator to generate a first oscillating signal, the first oscillating signal corresponding to the first signal, and pass the first signal to the first amplifier; and connecting the second splitter to the second amplifier, the transmitter, and the receiver; configuring the second splitter to receive the amplified signal from the second amplifier, and pass a first copy of the signal from the second amplifier to the transmitter, and pass a second copy of the signal from the second amplifier to the receiver.

[0081] Example 16. The method of manufacturing a radar unit of Example 15, further comprising: providing a second transceiver circuit, wherein the second transceiver circuit is an identical copy of the first transceiver circuit; providing a fourth switch configured to alternately select a signal from a fourth amplifier of the first transceiver circuit and a signal from a fifth amplifier of the second transceiver circuit, and pass the signal selected by the fourth switch to the second switch of the first transceiver circuit; providing a fifth switch configured to alternately select a signal from the fifth amplifier of the first transceiver circuit and a signal from the fourth amplifier of the second transceiver circuit, and pass the signal selected by the fifth switch to the second switch of the second transceiver circuit; configuring the oscillator signal generator of the first transceiver circuit to generate the first oscillating signal during a settling time of the oscillator signal generator of the second transceiver circuit; and configuring the oscillator signal generator of the second transceiver circuit to generate the second oscillating signal during a settling time of the oscillator signal generator of the first transceiver circuit.

[0082] Example 17. The method of manufacturing a radar unit of Example 15, further comprising: providing a second transceiver circuit, wherein the second transceiver circuit is a same copy of the first transceiver circuit, and configuring the oscillator signal generator of the second transceiver circuit to generate a second oscillating signal; providing a third transceiver circuit, wherein the third transceiver circuit includes a same copy of components of the first transceiver circuit, and further includes an additional switch, and configuring the additional switch to alternately select an output signal from the fourth amplifier of the first transceiver circuit and an output signal from the fourth amplifier of the second transceiver circuit; providing a fourth transceiver circuit, wherein the third transceiver circuit includes a same copy of components of the first transceiver circuit, and further includes an additional switch, and configuring the additional switch to alternately select an output signal from the fifth amplifier of the first transceiver circuit and an output signal from the fifth amplifier of the second transceiver circuit; configuring the oscillator signal generator of the first transceiver circuit to generate the first oscillating signal during a settling time of the oscillator signal generator of the second transceiver circuit; and configuring the oscillator signal generator of the second transceiver circuit to generate the second oscillating signal during a settling time of the oscillator signal generator of the first transceiver circuit.

[0083] Example 18. The method of manufacturing a radar unit of Example 15, further comprising: providing a fourth switch, and configuring the fourth switch to alternately select a signal from the first input port and a signal from the third input port, and pass the signal selected by the fourth switch to the second switch; providing a fifth switch, and configuring the fifth switch to alternately select a signal from the second input port and a signal from the fourth input port, and pass the signal selected by the fifth switch to the third switch; providing a sixth switch, the sixth switch configuring the fifth switch to alternately couple the fourth amplifier to the first output port and the third output port; and providing a seventh switch, and configuring the seventh switch to alternately couple the fifth amplifier to the second output port and the fourth output port.

[0084] Example 19. A method of operating an electronic circuit, comprising: amplifying a first signal using a first amplifier; receiving the first signal using a first switch, wherein the first switch is configured to receive the first signal from the first amplifier and alternately couple the first signal to a second switch and a third switch, wherein the second switch is configured to alternately select a first signal from a first input port and a second signal, and pass the signal selected by the second switch to a second amplifier, and wherein the second amplifier is configured to amplify the signal received from the second switch; receiving the first signal using the third switch, wherein the third switch is configured to alternately select the first signal from the first switch and a third signal from a second input port; passing the signal selected by the third switch to a third amplifier; amplifying the signal selected by the third switch using the third amplifier; receiving the signal from the third amplifier at a first splitter; passing a first copy of the signal received from the third amplifier to a fourth amplifier using the first splitter, and passing a second copy of the signal received from the third amplifier to a fifth amplifier using a second splitter.

[0085] Example 20. The method of operating an electronic circuit of Example 19, further comprising: generating the first signal using an oscillator signal generator; receiving the first signal at the first amplifier; receiving a second signal corresponding to the first signal at the second switch through the first input port; receiving the second signal at the second amplifier through the second switch; receiving the second signal from the second amplifier at a second splitter; passing a first copy of the signal from the second amplifier to a transmitter using the second splitter; and passing a second copy of the signal from the second amplifier of the oscillator circuit to a receiver using the second splitter.

[0086] While the operations described herein can be listed sequentially for purposes of explanation, in practice the method can be performed with multiple components operating concurrently and even speculatively to enable out-of-order operations. The sequential discussion described is not intended to constitute a limitation. Moreover, the focus of the foregoing discussion has been on radar sensors, but these principles apply to any pulsed return or continuous wave travel time measurement system. These and numerous other modifications, equivalents, and alternatives will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be construed to include all such modifications, equivalents, and alternatives as fall within the scope of the claims.

Claims

1. An integrated circuit, characterized in that... The integrated circuit includes: At least one local input port, the at least one local input port being used to receive a first chirp signal from a local generator; One or more primary input ports, each of which is used to receive a corresponding second chirp signal from a remote source; A primary switching arrangement operable to switch between a first chirped signal from the at least one local input port and a corresponding second chirped signal from the one or more primary input ports to generate a composite signal having a chirped sequence with at least one chirped chirp that begins during the settling period of a previous chirp, wherein the switching excludes the settling period of the first chirped signal and the corresponding second chirped signal; and One or more primary output ports, the one or more primary output ports being used to provide a local oscillator signal to the transmitter and receiver based on the composite signal.

2. The integrated circuit according to claim 1, characterized in that... The integrated circuit also includes: Multiple repeater ports are used to generate multiple copies of an amplified chirped signal.

3. The integrated circuit according to claim 2, characterized in that... The integrated circuit also includes: One or more secondary input ports, each of which is used to receive a corresponding chirped signal from a remote source; and A secondary switch arrangement operable to switch between a first chirp signal from the at least one local input port and corresponding chirp signals from the one or more secondary input ports to provide the amplified chirp signal to the plurality of repeater ports, the amplified chirp signal having a chirp sequence with at least one chirp that begins during a stable period of a previous chirp.

4. The integrated circuit according to claim 1, characterized in that... The integrated circuit also includes at least one frequency multiplier, which multiplies the frequency of the composite signal to generate the local oscillator signal.

5. An integrated circuit, characterized in that... The integrated circuit includes: At least one primary input port, the at least one primary input port being used to receive an amplified first chirped signal; One or more primary output ports, the one or more primary output ports being used to provide a local oscillator signal to the transmitter and receiver, at least in part, based on the amplified first chirp signal; Multiple secondary input ports, each of which is used to receive a corresponding second chirp signal from a remote source; Multiple repeater ports, said multiple repeater ports being used to generate multiple copies of the amplified first chirped signal; and A secondary switching arrangement operable to switch between corresponding second chirp signals from the plurality of secondary input ports to provide the amplified chirp signal to the plurality of repeater ports. The amplified chirp signal has a chirp sequence with at least one chirp that begins during the stabilization period of a previous chirp, wherein the switching excludes the stabilization period of the amplified first chirp signal and the corresponding second chirp signal.

6. The integrated circuit according to claim 5, characterized in that... The integrated circuit also includes: At least one local input port is provided for receiving a local chirp signal from a local generator, wherein the secondary switch arrangement is also operable to include a chirp from the local chirp signal in the chirp sequence.

7. The integrated circuit according to claim 5, characterized in that... The integrated circuit also includes a frequency multiplier that multiplies the frequency of the amplified chirped signal to generate the local oscillator signal.

8. The integrated circuit according to claim 5, characterized in that... The preceding chirp corresponds to the amplified first chirp signal.

9. The integrated circuit according to claim 5, characterized in that... The preceding chirp corresponds to the corresponding chirp signal from the remote source.

10. A radar system interface, characterized in that... The radar system interface includes a first plurality of integrated circuits, each of the first plurality of integrated circuits having: A local generator that provides a first chirp signal; At least one input port, said at least one input port receiving a second chirp signal from a remote source; One or more repeater ports, the one or more repeater ports being operable to provide multiple copies of an amplified chirped signal; A primary output port that provides a local oscillator signal to a transmitter or receiver; At least one switch arrangement operable to combine the first chirped signal and the second chirped signal to generate a composite signal having a chirped sequence, the chirped sequence having at least one chirped chirped during the stable period of a previous chirped chirped signal, wherein the composite signal excludes the stable period of the first chirped signal and the second chirped signal. and The wiring configuration enables the first plurality of integrated circuits to jointly generate at least one composite signal, to convert the at least one composite signal into multiple copies of an amplified chirped signal, and to provide each copy of the amplified chirped signal as a local oscillator signal to a transmitter or receiver.

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